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[brcm63xx] resync kernel configuration
[openwrt.git] / target / linux / s3c24xx / patches-2.6.26 / 1146-uplevel-samsung-camera-unit.patch.patch
1 From 0bd2a8e00d4a1814d0a9d8206d52717e3f538b68 Mon Sep 17 00:00:00 2001
2 From: Andy Green <andy@opennoko.com>
3 Date: Fri, 25 Jul 2008 23:06:10 +0100
4 Subject: [PATCH] uplevel-samsung-camera-unit.patch
5
6 Update this old code to clk API, I2C changes, official GPIO API
7 various struct changes, explicit readl() writel(), DMA API changes.
8 Still not ready for actual use (eg, I2C) but a LOT closer.
9
10 Compiles on 2.6.24 without errors or warnings now.
11
12 Use CONFIG_S3C2440_CAMERA=y in .config
13
14 Signed-off-by: Andy Green <andy@openmoko.com>
15 ---
16 arch/arm/mach-s3c2440/Kconfig | 5 +-
17 arch/arm/mach-s3c2440/Makefile | 9 +-
18 arch/arm/mach-s3c2440/camera/Makefile | 1 -
19 arch/arm/mach-s3c2440/camera/cam_reg.h | 92 +++--
20 arch/arm/mach-s3c2440/camera/camif.c | 633 +++++++++++++++------------
21 arch/arm/mach-s3c2440/camera/camif_fsm.c | 5 +
22 arch/arm/mach-s3c2440/camera/imgsensor.c | 43 +-
23 arch/arm/mach-s3c2440/camera/qt-driver.c | 5 +-
24 arch/arm/mach-s3c2440/camera/video-driver.c | 87 +++--
25 arch/arm/mach-s3c2440/camera/videodev.c | 24 +-
26 arch/arm/mach-s3c2440/camera/videodev.h | 16 +-
27 11 files changed, 516 insertions(+), 404 deletions(-)
28
29 diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
30 index e042965..20dd2c5 100644
31 --- a/arch/arm/mach-s3c2440/Kconfig
32 +++ b/arch/arm/mach-s3c2440/Kconfig
33 @@ -30,9 +30,6 @@ config S3C2440_C_FIQ
34 Support for S3C2440 FIQ support in C -- see
35 ./arch/arm/macs3c2440/fiq_c_isr.c
36
37 -source "arch/arm/mach-s3c2440/camera/Kconfig"
38 -
39 -
40 menu "S3C2440 Machines"
41
42 config MACH_ANUBIS
43 @@ -96,3 +93,5 @@ config NEO1973_GTA02_2440
44 of the FIC/Openmoko Neo1973 GTA02 GSM Phone.
45
46 endmenu
47 +
48 +#source "arch/arm/mach-s3c2440/camera/Kconfig"
49 diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile
50 index e9c6334..964e50b 100644
51 --- a/arch/arm/mach-s3c2440/Makefile
52 +++ b/arch/arm/mach-s3c2440/Makefile
53 @@ -1,4 +1,10 @@
54 -obj-y += camera/
55 +# arch/arm/mach-s3c2440/Makefile
56 +#
57 +# Copyright 2007 Simtec Electronics
58 +#
59 +# Licensed under GPLv2
60 +
61 +obj-y :=
62 obj-m :=
63 obj-n :=
64 obj- :=
65 @@ -17,5 +23,6 @@ obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o
66 obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o
67 obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
68 obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
69 +obj-$(CONFIG_MACH_HXD8) += mach-hxd8.o
70 obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o
71
72 diff --git a/arch/arm/mach-s3c2440/camera/Makefile b/arch/arm/mach-s3c2440/camera/Makefile
73 index a46d3be..9cd6d79 100644
74 --- a/arch/arm/mach-s3c2440/camera/Makefile
75 +++ b/arch/arm/mach-s3c2440/camera/Makefile
76 @@ -1,7 +1,6 @@
77 obj-$(CONFIG_S3C2440_CAMERA) += \
78 videodev.o \
79 imgsensor.o \
80 - videodrv.o \
81 video-driver.o \
82 camif.o \
83 camif_fsm.o \
84 diff --git a/arch/arm/mach-s3c2440/camera/cam_reg.h b/arch/arm/mach-s3c2440/camera/cam_reg.h
85 index 7247a4e..93d59b8 100644
86 --- a/arch/arm/mach-s3c2440/camera/cam_reg.h
87 +++ b/arch/arm/mach-s3c2440/camera/cam_reg.h
88 @@ -7,6 +7,7 @@
89 #ifndef __FIMC20_CAMERA_H__
90 #define __FIMC20_CAMERA_H__
91
92 +extern u32 * camregs;
93
94 #ifdef CONFIG_ARCH_S3C24A0
95 #define CAM_BASE_ADD 0x48000000
96 @@ -14,10 +15,23 @@
97 #define CAM_BASE_ADD 0x4F000000
98 #endif
99
100 +#if ! defined(FExtr)
101 +#define UData(Data) ((unsigned long) (Data))
102 +#define FExtr(Data, Field) \
103 + ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
104 +#define FInsrt(Value, Field) \
105 + (UData (Value) << FShft (Field))
106 +#define FSize(Field) ((Field) >> 16)
107 +#define FShft(Field) ((Field) & 0x0000FFFF)
108 +#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
109 +#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
110 +#define F1stBit(Field) (UData (1) << FShft (Field))
111 +#define Fld(Size, Shft) (((Size) << 16) + (Shft))
112 +#endif
113
114 /*
115 * CAMERA IP
116 - * P-port is used as RGB Capturing device which including scale and crop
117 + * P-port is used as RGB Capturing device which including scale and crop
118 * those who want to see(preview ) the image on display needs RGB image.
119 *
120 * C-port is used as YCbCr(4:2:0, 4:2:2) Capturing device which including the scale and crop
121 @@ -25,45 +39,45 @@
122 YCBCB format not RGB
123 */
124
125 -#define CISRCFMT __REG(CAM_BASE_ADD+0x00) // RW Input Source Format
126 -#define CIWDOFST __REG(CAM_BASE_ADD+0x04) // Window offset register
127 -#define CIGCTRL __REG(CAM_BASE_ADD+0x08) // Global control register
128 -#define CICOYSA0 __REG(CAM_BASE_ADD+0x18) // Y 1 st frame start address
129 -#define CICOYSA1 __REG(CAM_BASE_ADD+0x1C) // Y 2 nd frame start address
130 -#define CICOYSA2 __REG(CAM_BASE_ADD+0x20) // Y 3 rd frame start address
131 -#define CICOYSA3 __REG(CAM_BASE_ADD+0x24) // Y 4 th frame start address
132 -#define CICOCBSA0 __REG(CAM_BASE_ADD+0x28) // Cb 1 st frame start address
133 -#define CICOCBSA1 __REG(CAM_BASE_ADD+0x2C) // Cb 2 nd frame start address
134 -#define CICOCBSA2 __REG(CAM_BASE_ADD+0x30) // Cb 3 rd frame start address
135 -#define CICOCBSA3 __REG(CAM_BASE_ADD+0x34) // Cb 4 th frame start address
136 -#define CICOCRSA0 __REG(CAM_BASE_ADD+0x38) // Cr 1 st frame start address
137 -#define CICOCRSA1 __REG(CAM_BASE_ADD+0x3C) // Cr 2 nd frame start address
138 -#define CICOCRSA2 __REG(CAM_BASE_ADD+0x40) // Cr 3 rd frame start address
139 -#define CICOCRSA3 __REG(CAM_BASE_ADD+0x44) // Cr 4 th frame start address
140 -#define CICOTRGFMT __REG(CAM_BASE_ADD+0x48) // Target image format of codec
141 -#define CICOCTRL __REG(CAM_BASE_ADD+0x4C) // Codec DMA control related
142 -#define CICOSCPRERATIO __REG(CAM_BASE_ADD+0x50) // Codec pre-scaler ratio control
143 -#define CICOSCPREDST __REG(CAM_BASE_ADD+0x54) // Codec pre-scaler destination
144 -#define CICOSCCTRL __REG(CAM_BASE_ADD+0x58) // Codec main-scaler control
145 -#define CICOTAREA __REG(CAM_BASE_ADD+0x5C) // Codec pre-scaler destination
146 -#define CICOSTATUS __REG(CAM_BASE_ADD+0x64) // Codec path status
147 -#define CIPRCLRSA0 __REG(CAM_BASE_ADD+0x6C) // RGB 1 st frame start address
148 -#define CIPRCLRSA1 __REG(CAM_BASE_ADD+0x70) // RGB 2 nd frame start address
149 -#define CIPRCLRSA2 __REG(CAM_BASE_ADD+0x74) // RGB 3 rd frame start address
150 -#define CIPRCLRSA3 __REG(CAM_BASE_ADD+0x78) // RGB 4 th frame start address
151 -#define CIPRTRGFMT __REG(CAM_BASE_ADD+0x7C) // Target image format of preview
152 -#define CIPRCTRL __REG(CAM_BASE_ADD+0x80) // Preview DMA control related
153 -#define CIPRSCPRERATIO __REG(CAM_BASE_ADD+0x84) // Preview pre-scaler ratio control
154 -#define CIPRSCPREDST __REG(CAM_BASE_ADD+0x88) // Preview pre-scaler destination
155 -#define CIPRSCCTRL __REG(CAM_BASE_ADD+0x8C) // Preview main-scaler control
156 -#define CIPRTAREA __REG(CAM_BASE_ADD+0x90) // Preview pre-scaler destination
157 -#define CIPRSTATUS __REG(CAM_BASE_ADD+0x98) // Preview path status
158 -#define CIIMGCPT __REG(CAM_BASE_ADD+0xA0) // Image capture enable command
159 -
160 -#define CICOYSA(__x) __REG(CAM_BASE_ADD+0x18 + (__x)*4 )
161 -#define CICOCBSA(__x) __REG(CAM_BASE_ADD+0x28 + (__x)*4 )
162 -#define CICOCRSA(__x) __REG(CAM_BASE_ADD+0x38 + (__x)*4 )
163 -#define CIPRCLRSA(__x) __REG(CAM_BASE_ADD+0x6C + (__x)*4 )
164 +#define S3C2440_CAM_REG_CISRCFMT (0x00) // RW Input Source Format
165 +#define S3C2440_CAM_REG_CIWDOFST (0x04) // Window offset register
166 +#define S3C2440_CAM_REG_CIGCTRL (0x08) // Global control register
167 +#define S3C2440_CAM_REG_CICOYSA0 (0x18) // Y 1 st frame start ads
168 +#define S3C2440_CAM_REG_CICOYSA1 (0x1C) // Y 2 nd frame start ads
169 +#define S3C2440_CAM_REG_CICOYSA2 (0x20) // Y 3 rd frame start ads
170 +#define S3C2440_CAM_REG_CICOYSA3 (0x24) // Y 4 th frame start ads
171 +#define S3C2440_CAM_REG_CICOCBSA0 (0x28) // Cb 1 st frame start ads
172 +#define S3C2440_CAM_REG_CICOCBSA1 (0x2C) // Cb 2 nd frame start ads
173 +#define S3C2440_CAM_REG_CICOCBSA2 (0x30) // Cb 3 rd frame start ads
174 +#define S3C2440_CAM_REG_CICOCBSA3 (0x34) // Cb 4 th frame start ads
175 +#define S3C2440_CAM_REG_CICOCRSA0 (0x38) // Cr 1 st frame start ads
176 +#define S3C2440_CAM_REG_CICOCRSA1 (0x3C) // Cr 2 nd frame start ads
177 +#define S3C2440_CAM_REG_CICOCRSA2 (0x40) // Cr 3 rd frame start ads
178 +#define S3C2440_CAM_REG_CICOCRSA3 (0x44) // Cr 4 th frame start ads
179 +#define S3C2440_CAM_REG_CICOTRGFMT (0x48) // Target img format of codec
180 +#define S3C2440_CAM_REG_CICOCTRL (0x4C) // Codec DMA control related
181 +#define S3C2440_CAM_REG_CICOSCPRERATIO (0x50) // Codec pre-scaler ratio
182 +#define S3C2440_CAM_REG_CICOSCPREDST (0x54) // Codec pre-scaler dest
183 +#define S3C2440_CAM_REG_CICOSCCTRL (0x58) // Codec main-scaler control
184 +#define S3C2440_CAM_REG_CICOTAREA (0x5C) // Codec pre-scaler dest
185 +#define S3C2440_CAM_REG_CICOSTATUS (0x64) // Codec path status
186 +#define S3C2440_CAM_REG_CIPRCLRSA0 (0x6C) // RGB 1 st frame start ads
187 +#define S3C2440_CAM_REG_CIPRCLRSA1 (0x70) // RGB 2 nd frame start ads
188 +#define S3C2440_CAM_REG_CIPRCLRSA2 (0x74) // RGB 3 rd frame start ads
189 +#define S3C2440_CAM_REG_CIPRCLRSA3 (0x78) // RGB 4 th frame start ads
190 +#define S3C2440_CAM_REG_CIPRTRGFMT (0x7C) // Target img fmt of preview
191 +#define S3C2440_CAM_REG_CIPRCTRL (0x80) // Preview DMA ctl related
192 +#define S3C2440_CAM_REG_CIPRSCPRERATIO (0x84) // Preview pre-scaler ratio
193 +#define S3C2440_CAM_REG_CIPRSCPREDST (0x88) // Preview pre-scaler dest
194 +#define S3C2440_CAM_REG_CIPRSCCTRL (0x8C) // Preview main-scaler ctl
195 +#define S3C2440_CAM_REG_CIPRTAREA (0x90) // Preview pre-scaler dest
196 +#define S3C2440_CAM_REG_CIPRSTATUS (0x98) // Preview path status
197 +#define S3C2440_CAM_REG_CIIMGCPT (0xA0) // Image capture enable cmd
198 +
199 +#define S3C2440_CAM_REG_CICOYSA(__x) (0x18 + (__x)*4 )
200 +#define S3C2440_CAM_REG_CICOCBSA(__x) (0x28 + (__x)*4 )
201 +#define S3C2440_CAM_REG_CICOCRSA(__x) (0x38 + (__x)*4 )
202 +#define S3C2440_CAM_REG_CIPRCLRSA(__x) (0x6C + (__x)*4 )
203
204 /* CISRCFMT BitField */
205 #define SRCFMT_ITU601 BIT31
206 diff --git a/arch/arm/mach-s3c2440/camera/camif.c b/arch/arm/mach-s3c2440/camera/camif.c
207 index 36d4ccc..2e97e21 100644
208 --- a/arch/arm/mach-s3c2440/camera/camif.c
209 +++ b/arch/arm/mach-s3c2440/camera/camif.c
210 @@ -7,14 +7,11 @@
211 * for more details.
212 */
213
214 -#include <linux/config.h>
215 #include <linux/module.h>
216 #include <linux/kernel.h>
217 #include <linux/init.h>
218 #include <linux/sched.h>
219 #include <linux/irq.h>
220 -#include <linux/tqueue.h>
221 -#include <linux/locks.h>
222 #include <linux/completion.h>
223 #include <linux/delay.h>
224 #include <linux/slab.h>
225 @@ -26,28 +23,29 @@
226 #include <asm/semaphore.h>
227 #include <asm/hardware.h>
228 #include <asm/uaccess.h>
229 +#include <linux/device.h>
230 +#include <linux/dma-mapping.h>
231 +#include <linux/clk.h>
232
233 #ifdef CONFIG_ARCH_S3C24A0A
234 #include <asm/arch/S3C24A0.h>
235 #include <asm/arch/clocks.h>
236 #else
237 -#include <asm/arch/S3C2440.h>
238 -#include <asm/arch/clocks.h>
239 +#include <asm/arch/regs-gpio.h>
240 +#include <asm/arch/regs-gpioj.h>
241 +#include <asm/arch/regs-irq.h>
242 #endif
243
244 #include "cam_reg.h"
245 //#define SW_DEBUG
246 +#define CONFIG_VIDEO_V4L1_COMPAT
247 +#include <linux/videodev.h>
248 #include "camif.h"
249 -#include "videodev.h"
250 #include "miscdevice.h"
251
252 -
253 static int camif_dma_burst(camif_cfg_t *);
254 static int camif_scaler(camif_cfg_t *);
255
256 -static const char *camif_version =
257 - "$Id: camif.c,v 1.10 2004/06/04 04:24:14 swlee Exp $";
258 -
259 /* For SXGA Image */
260 #define RESERVE_MEM 15*1024*1024
261 #define YUV_MEM 10*1024*1024
262 @@ -66,11 +64,13 @@ static int camif_malloc(camif_cfg_t *cfg)
263 t_size = t_size *cfg->pp_num;
264
265 #ifndef SAMSUNG_SXGA_CAM
266 - cfg->pp_virt_buf = consistent_alloc(GFP_KERNEL, t_size, &cfg->pp_phys_buf);
267 + cfg->pp_virt_buf = dma_alloc_coherent(cfg->v->dev,
268 + t_size, &cfg->pp_phys_buf,
269 + GFP_KERNEL);
270 #else
271 printk(KERN_INFO "Reserving High RAM Addresses \n");
272 cfg->pp_phys_buf = PHYS_OFFSET + (MEM_SIZE - RESERVE_MEM);
273 - cfg->pp_virt_buf = ioremap_nocache(cfg->pp_phys_buf,YUV_MEM);
274 + cfg->pp_virt_buf = ioremap_nocache(cfg->pp_phys_buf, YUV_MEM);
275 #endif
276
277 if ( !cfg->pp_virt_buf ) {
278 @@ -90,7 +90,9 @@ static int camif_malloc(camif_cfg_t *cfg)
279 }
280 t_size = t_size * cfg->pp_num;
281 #ifndef SAMSUNG_SXGA_CAM
282 - cfg->pp_virt_buf = consistent_alloc(GFP_KERNEL, t_size, &cfg->pp_phys_buf);
283 + cfg->pp_virt_buf = dma_alloc_coherent(cfg->v->dev,
284 + t_size, &cfg->pp_phys_buf,
285 + GFP_KERNEL);
286 #else
287 printk(KERN_INFO "Reserving High RAM Addresses \n");
288 cfg->pp_phys_buf = PHYS_OFFSET + (MEM_SIZE - RESERVE_MEM ) + YUV_MEM;
289 @@ -112,7 +114,8 @@ static int camif_demalloc(camif_cfg_t *cfg)
290 {
291 #ifndef SAMSUNG_SXGA_CAM
292 if ( cfg->pp_virt_buf ) {
293 - consistent_free(cfg->pp_virt_buf,cfg->pp_totalsize,cfg->pp_phys_buf);
294 + dma_free_coherent(cfg->v->dev, cfg->pp_totalsize,
295 + cfg->pp_virt_buf, cfg->pp_phys_buf);
296 cfg->pp_virt_buf = 0;
297 }
298 #else
299 @@ -131,13 +134,14 @@ int camif_g_frame_num(camif_cfg_t *cfg)
300 int index = 0;
301
302 if (cfg->dma_type & CAMIF_CODEC ) {
303 - index = FRAME_CNT(CICOSTATUS);
304 + index = FRAME_CNT(readl(camregs + S3C2440_CAM_REG_CICOSTATUS));
305 DPRINTK("CAMIF_CODEC frame %d \n", index);
306 }
307 else {
308 assert(cfg->dma_type & CAMIF_PREVIEW );
309 - index = FRAME_CNT(CIPRSTATUS);
310 - DPRINTK("CAMIF_PREVIEW frame %d 0x%08X \n", index, CIPRSTATUS);
311 + index = FRAME_CNT(readl(camregs + S3C2440_CAM_REG_CIPRSTATUS));
312 + DPRINTK("CAMIF_PREVIEW frame %d 0x%08X \n", index,
313 + readl(camregs + S3C2440_CAM_REG_CIPRSTATUS));
314 }
315 cfg->now_frame_num = (index + 2) % 4; /* When 4 PingPong */
316 return index; /* meaningless */
317 @@ -148,60 +152,59 @@ static int camif_pp_codec(camif_cfg_t *cfg)
318 u32 i, c_size; /* Cb,Cr size */
319 u32 one_p_size;
320 u32 daon = cfg->target_x * cfg->target_y;
321 - if (cfg->fmt & CAMIF_OUT_YCBCR420) {
322 - c_size = daon /4;
323 - }
324 + if (cfg->fmt & CAMIF_OUT_YCBCR420)
325 + c_size = daon / 4;
326 else {
327 assert(cfg->fmt & CAMIF_OUT_YCBCR422);
328 - c_size = daon /2;
329 + c_size = daon / 2;
330 }
331 switch ( cfg->pp_num ) {
332 - case 1 :
333 - for ( i =0 ; i < 4; i=i+1) {
334 - cfg->img_buf[i].virt_y = cfg->pp_virt_buf;
335 - cfg->img_buf[i].phys_y = cfg->pp_phys_buf;
336 - cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon;
337 - cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon;
338 - cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size;
339 - cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size;
340 - CICOYSA(i) = cfg->img_buf[i].phys_y;
341 - CICOCBSA(i) = cfg->img_buf[i].phys_cb;
342 - CICOCRSA(i) = cfg->img_buf[i].phys_cr;
343 - }
344 - break;
345 - case 2:
346 + case 1 :
347 + for (i =0 ; i < 4; i++) {
348 + cfg->img_buf[i].virt_y = cfg->pp_virt_buf;
349 + cfg->img_buf[i].phys_y = cfg->pp_phys_buf;
350 + cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon;
351 + cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon;
352 + cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size;
353 + cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size;
354 + writel(cfg->img_buf[i].phys_y, camregs + S3C2440_CAM_REG_CICOYSA(i));
355 + writel(cfg->img_buf[i].phys_cb, camregs + S3C2440_CAM_REG_CICOCBSA(i));
356 + writel(cfg->img_buf[i].phys_cr, camregs + S3C2440_CAM_REG_CICOCRSA(i));
357 + }
358 + break;
359 + case 2:
360 #define TRY (( i%2 ) ? 1 :0)
361 - one_p_size = daon + 2*c_size;
362 - for (i = 0; i < 4 ; i++) {
363 - cfg->img_buf[i].virt_y = cfg->pp_virt_buf + TRY * one_p_size;
364 - cfg->img_buf[i].phys_y = cfg->pp_phys_buf + TRY * one_p_size;
365 - cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon + TRY * one_p_size;
366 - cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon + TRY * one_p_size;
367 - cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size + TRY * one_p_size;
368 - cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size + TRY * one_p_size;
369 - CICOYSA(i) = cfg->img_buf[i].phys_y;
370 - CICOCBSA(i) = cfg->img_buf[i].phys_cb;
371 - CICOCRSA(i) = cfg->img_buf[i].phys_cr;
372 - }
373 - break;
374 - case 4:
375 - one_p_size = daon + 2*c_size;
376 - for (i = 0; i < 4 ; i++) {
377 - cfg->img_buf[i].virt_y = cfg->pp_virt_buf + i * one_p_size;
378 - cfg->img_buf[i].phys_y = cfg->pp_phys_buf + i * one_p_size;
379 - cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon + i * one_p_size;
380 - cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon + i * one_p_size;
381 - cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size + i * one_p_size;
382 - cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size + i * one_p_size;
383 - CICOYSA(i) = cfg->img_buf[i].phys_y;
384 - CICOCBSA(i) = cfg->img_buf[i].phys_cb;
385 - CICOCRSA(i) = cfg->img_buf[i].phys_cr;
386 - }
387 - break;
388 - default:
389 - printk("Invalid PingPong Number %d \n",cfg->pp_num);
390 - panic("halt\n");
391 - }
392 + one_p_size = daon + 2*c_size;
393 + for (i = 0; i < 4 ; i++) {
394 + cfg->img_buf[i].virt_y = cfg->pp_virt_buf + TRY * one_p_size;
395 + cfg->img_buf[i].phys_y = cfg->pp_phys_buf + TRY * one_p_size;
396 + cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon + TRY * one_p_size;
397 + cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon + TRY * one_p_size;
398 + cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size + TRY * one_p_size;
399 + cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size + TRY * one_p_size;
400 + writel(cfg->img_buf[i].phys_y, camregs + S3C2440_CAM_REG_CICOYSA(i));
401 + writel(cfg->img_buf[i].phys_cb, camregs + S3C2440_CAM_REG_CICOCBSA(i));
402 + writel(cfg->img_buf[i].phys_cr, camregs + S3C2440_CAM_REG_CICOCRSA(i));
403 + }
404 + break;
405 + case 4:
406 + one_p_size = daon + 2*c_size;
407 + for (i = 0; i < 4 ; i++) {
408 + cfg->img_buf[i].virt_y = cfg->pp_virt_buf + i * one_p_size;
409 + cfg->img_buf[i].phys_y = cfg->pp_phys_buf + i * one_p_size;
410 + cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon + i * one_p_size;
411 + cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon + i * one_p_size;
412 + cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size + i * one_p_size;
413 + cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size + i * one_p_size;
414 + writel(cfg->img_buf[i].phys_y, camregs + S3C2440_CAM_REG_CICOYSA(i));
415 + writel(cfg->img_buf[i].phys_cb, camregs + S3C2440_CAM_REG_CICOCBSA(i));
416 + writel(cfg->img_buf[i].phys_cr, camregs + S3C2440_CAM_REG_CICOCRSA(i));
417 + }
418 + break;
419 + default:
420 + printk("Invalid PingPong Number %d \n",cfg->pp_num);
421 + panic("halt\n");
422 +}
423 return 0;
424 }
425
426 @@ -222,21 +225,21 @@ static int camif_pp_preview(camif_cfg_t *cfg)
427 for ( i = 0; i < 4 ; i++ ) {
428 cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf ;
429 cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf ;
430 - CIPRCLRSA(i) = cfg->img_buf[i].phys_rgb;
431 + writel(cfg->img_buf[i].phys_rgb, camregs + S3C2440_CAM_REG_CICOCRSA(i));
432 }
433 break;
434 case 2:
435 for ( i = 0; i < 4 ; i++) {
436 cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf + TRY * daon;
437 cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf + TRY * daon;
438 - CIPRCLRSA(i) = cfg->img_buf[i].phys_rgb;
439 + writel(cfg->img_buf[i].phys_rgb, camregs + S3C2440_CAM_REG_CICOCRSA(i));
440 }
441 break;
442 case 4:
443 for ( i = 0; i < 4 ; i++) {
444 cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf + i * daon;
445 cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf + i * daon;
446 - CIPRCLRSA(i) = cfg->img_buf[i].phys_rgb;
447 + writel(cfg->img_buf[i].phys_rgb, camregs + S3C2440_CAM_REG_CICOCRSA(i));
448 }
449 break;
450 default:
451 @@ -308,7 +311,7 @@ static int camif_source_fmt(camif_gc_t *gc)
452 cmd |= SOURCE_HSIZE(gc->source_x)| SOURCE_VSIZE(gc->source_y);
453 /* Order422 */
454 cmd |= gc->order422;
455 - CISRCFMT = cmd;
456 + writel(cmd, camregs + S3C2440_CAM_REG_CISRCFMT);
457
458 return 0 ;
459 }
460 @@ -331,33 +334,24 @@ static int camif_target_fmt(camif_cfg_t *cfg)
461 assert(cfg->fmt & CAMIF_OUT_YCBCR422);
462 cmd |= OUT_YCBCR422|IN_YCBCR422;
463 }
464 - CICOTRGFMT = cmd | cfg->flip;
465 - }
466 - else {
467 + writel(cmd | cfg->flip, camregs + S3C2440_CAM_REG_CICOTRGFMT);
468 +
469 + } else {
470 assert(cfg->dma_type & CAMIF_PREVIEW);
471 - CIPRTRGFMT =
472 - TARGET_HSIZE(cfg->target_x)|TARGET_VSIZE(cfg->target_y)|cfg->flip;
473 + writel(TARGET_HSIZE(cfg->target_x)|TARGET_VSIZE(cfg->target_y)|cfg->flip,
474 + camregs + S3C2440_CAM_REG_CIPRTRGFMT);
475 }
476 return 0;
477 }
478
479 void camif_change_flip(camif_cfg_t *cfg)
480 {
481 - u32 cmd = 0;
482 + u32 cmd = readl(camregs + S3C2440_CAM_REG_CICOTRGFMT);
483
484 - if (cfg->dma_type & CAMIF_CODEC ) {
485 - /* YCBCR setting */
486 - cmd = CICOTRGFMT;
487 - cmd &= ~(BIT14|BIT15); /* Clear FLIP Mode */
488 - cmd |= cfg->flip;
489 - CICOTRGFMT = cmd;
490 - }
491 - else {
492 - cmd = CIPRTRGFMT;
493 - cmd &= ~(BIT14|BIT15);
494 - cmd |= cfg->flip;
495 - CICOTRGFMT = cmd;
496 - }
497 + cmd &= ~(BIT14|BIT15);
498 + cmd |= cfg->flip;
499 +
500 + writel(cmd, camregs + S3C2440_CAM_REG_CICOTRGFMT);
501 }
502
503
504 @@ -373,70 +367,81 @@ int camif_capture_start(camif_cfg_t *cfg)
505 u32 n_cmd = 0; /* Next Command */
506
507 switch(cfg->exec) {
508 - case CAMIF_BOTH_DMA_ON:
509 - camif_reset(CAMIF_RESET,0); /* Flush Camera Core Buffer */
510 - CIPRSCCTRL |= SCALERSTART;
511 - CICOSCCTRL |= SCALERSTART;
512 - n_cmd = CAMIF_CAP_PREVIEW_ON|CAMIF_CAP_CODEC_ON;
513 - break;
514 - case CAMIF_DMA_ON:
515 - camif_reset(CAMIF_RESET,0); /* Flush Camera Core Buffer */
516 - if (cfg->dma_type&CAMIF_CODEC) {
517 - CICOSCCTRL |= SCALERSTART;
518 - n_cmd = CAMIF_CAP_CODEC_ON;
519 - }else {
520 - CIPRSCCTRL |= SCALERSTART;
521 - n_cmd = CAMIF_CAP_PREVIEW_ON;
522 - }
523 + case CAMIF_BOTH_DMA_ON:
524 + camif_reset(CAMIF_RESET, 0); /* Flush Camera Core Buffer */
525 + writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) |
526 + SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
527 + writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) |
528 + SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
529 + n_cmd = CAMIF_CAP_PREVIEW_ON | CAMIF_CAP_CODEC_ON;
530 + break;
531 + case CAMIF_DMA_ON:
532 + camif_reset(CAMIF_RESET, 0); /* Flush Camera Core Buffer */
533 + if (cfg->dma_type&CAMIF_CODEC) {
534 + writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) |
535 + SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
536 + n_cmd = CAMIF_CAP_CODEC_ON;
537 + } else {
538 + writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) |
539 + SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
540 + n_cmd = CAMIF_CAP_PREVIEW_ON;
541 + }
542
543 - /* wait until Sync Time expires */
544 - /* First settting, to wait VSYNC fall */
545 - /* By VESA spec,in 640x480 @60Hz
546 - MAX Delay Time is around 64us which "while" has.*/
547 - while(VSYNC & CICOSTATUS);
548 - break;
549 - default:
550 - break;
551 - }
552 - CIIMGCPT = n_cmd|CAMIF_CAP_ON;
553 + /* wait until Sync Time expires */
554 + /* First settting, to wait VSYNC fall */
555 + /* By VESA spec,in 640x480 @60Hz
556 + MAX Delay Time is around 64us which "while" has.*/
557 + while(VSYNC & readl(camregs + S3C2440_CAM_REG_CICOSTATUS));
558 + break;
559 + default:
560 + break;
561 +}
562 + writel(n_cmd | CAMIF_CAP_ON, camregs + S3C2440_CAM_REG_CIIMGCPT);
563 return 0;
564 }
565
566
567 int camif_capture_stop(camif_cfg_t *cfg)
568 {
569 - u32 n_cmd = CIIMGCPT; /* Next Command */
570 + u32 n_cmd = readl(camregs + S3C2440_CAM_REG_CIIMGCPT); /* Next Command */
571
572 switch(cfg->exec) {
573 - case CAMIF_BOTH_DMA_OFF:
574 - CIPRSCCTRL &= ~SCALERSTART;
575 - CICOSCCTRL &= ~SCALERSTART;
576 - n_cmd = 0;
577 - break;
578 - case CAMIF_DMA_OFF_L_IRQ: /* fall thru */
579 - case CAMIF_DMA_OFF:
580 - if (cfg->dma_type&CAMIF_CODEC) {
581 - CICOSCCTRL &= ~SCALERSTART;
582 - n_cmd &= ~CAMIF_CAP_CODEC_ON;
583 - if (!(n_cmd & CAMIF_CAP_PREVIEW_ON))
584 - n_cmd = 0;
585 - }else {
586 - CIPRSCCTRL &= ~SCALERSTART;
587 - n_cmd &= ~CAMIF_CAP_PREVIEW_ON;
588 - if (!(n_cmd & CAMIF_CAP_CODEC_ON))
589 - n_cmd = 0;
590 - }
591 - break;
592 - default:
593 - panic("Unexpected \n");
594 - }
595 - CIIMGCPT = n_cmd;
596 - if(cfg->exec == CAMIF_DMA_OFF_L_IRQ) { /* Last IRQ */
597 - if (cfg->dma_type & CAMIF_CODEC)
598 - CICOCTRL |= LAST_IRQ_EN;
599 - else
600 - CIPRCTRL |= LAST_IRQ_EN;
601 - }
602 + case CAMIF_BOTH_DMA_OFF:
603 + writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) &
604 + ~SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
605 + writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) &
606 + ~SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
607 + n_cmd = 0;
608 + break;
609 + case CAMIF_DMA_OFF_L_IRQ: /* fall thru */
610 + case CAMIF_DMA_OFF:
611 + if (cfg->dma_type&CAMIF_CODEC) {
612 + writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) &
613 + ~SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
614 + n_cmd &= ~CAMIF_CAP_CODEC_ON;
615 + if (!(n_cmd & CAMIF_CAP_PREVIEW_ON))
616 + n_cmd = 0;
617 + } else {
618 + writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) &
619 + ~SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
620 + n_cmd &= ~CAMIF_CAP_PREVIEW_ON;
621 + if (!(n_cmd & CAMIF_CAP_CODEC_ON))
622 + n_cmd = 0;
623 + }
624 + break;
625 + default:
626 + panic("Unexpected \n");
627 + }
628 + writel(n_cmd, camregs + S3C2440_CAM_REG_CIIMGCPT);
629 +
630 + if (cfg->exec == CAMIF_DMA_OFF_L_IRQ) { /* Last IRQ */
631 + if (cfg->dma_type & CAMIF_CODEC)
632 + writel(readl(camregs + S3C2440_CAM_REG_CICOCTRL) |
633 + LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CICOCTRL);
634 + else
635 + writel(readl(camregs + S3C2440_CAM_REG_CIPRCTRL) |
636 + LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CIPRCTRL);
637 + }
638 #if 0
639 else { /* to make internal state machine of CAMERA stop */
640 camif_reset(CAMIF_RESET, 0);
641 @@ -449,16 +454,13 @@ int camif_capture_stop(camif_cfg_t *cfg)
642 /* LastIRQEn is autoclear */
643 void camif_last_irq_en(camif_cfg_t *cfg)
644 {
645 - if(cfg->exec == CAMIF_BOTH_DMA_ON) {
646 - CIPRCTRL |= LAST_IRQ_EN;
647 - CICOCTRL |= LAST_IRQ_EN;
648 - }
649 - else {
650 - if (cfg->dma_type & CAMIF_CODEC)
651 - CICOCTRL |= LAST_IRQ_EN;
652 - else
653 - CIPRCTRL |= LAST_IRQ_EN;
654 - }
655 + if ((cfg->exec == CAMIF_BOTH_DMA_ON) || (cfg->dma_type & CAMIF_CODEC))
656 + writel(readl(camregs + S3C2440_CAM_REG_CICOCTRL) |
657 + LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CICOCTRL);
658 +
659 + if ((cfg->exec == CAMIF_BOTH_DMA_ON) || !(cfg->dma_type & CAMIF_CODEC))
660 + writel(readl(camregs + S3C2440_CAM_REG_CIPRCTRL) |
661 + LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CIPRCTRL);
662 }
663
664 static int
665 @@ -502,23 +504,33 @@ int camif_g_fifo_status(camif_cfg_t *cfg)
666 u32 reg;
667
668 if (cfg->dma_type & CAMIF_CODEC) {
669 - u32 flag = CO_OVERFLOW_Y|CO_OVERFLOW_CB|CO_OVERFLOW_CR;
670 - reg = CICOSTATUS;
671 + u32 flag = CO_OVERFLOW_Y | CO_OVERFLOW_CB | CO_OVERFLOW_CR;
672 + reg = readl(camregs + S3C2440_CAM_REG_CICOSTATUS);
673 if (reg & flag) {
674 printk("CODEC: FIFO error(0x%08x) and corrected\n",reg);
675 /* FIFO Error Count ++ */
676 - CIWDOFST |= CO_FIFO_Y|CO_FIFO_CB|CO_FIFO_CR;
677 - CIWDOFST &= ~(CO_FIFO_Y|CO_FIFO_CB|CO_FIFO_CR);
678 + writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) |
679 + CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR,
680 + camregs + S3C2440_CAM_REG_CIWDOFST);
681 +
682 + writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) &
683 + ~(CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR),
684 + camregs + S3C2440_CAM_REG_CIWDOFST);
685 return 1; /* Error */
686 }
687 }
688 if (cfg->dma_type & CAMIF_PREVIEW) {
689 - u32 flag = PR_OVERFLOW_CB|PR_OVERFLOW_CR;
690 - reg = CIPRSTATUS;
691 + u32 flag = PR_OVERFLOW_CB | PR_OVERFLOW_CR;
692 + reg = readl(camregs + S3C2440_CAM_REG_CIPRSTATUS);
693 if (reg & flag) {
694 printk("PREVIEW:FIFO error(0x%08x) and corrected\n",reg);
695 - CIWDOFST |= PR_FIFO_CB|PR_FIFO_CR;
696 - CIWDOFST &= ~(CO_FIFO_Y|CO_FIFO_CB|CO_FIFO_CR);
697 + writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) |
698 + CO_FIFO_CB | CO_FIFO_CR,
699 + camregs + S3C2440_CAM_REG_CIWDOFST);
700 +
701 + writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) &
702 + ~(CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR),
703 + camregs + S3C2440_CAM_REG_CIWDOFST);
704 /* FIFO Error Count ++ */
705 return 1; /* Error */
706 }
707 @@ -537,13 +549,16 @@ int camif_win_offset(camif_gc_t *gc )
708 u32 v = gc->win_ver_ofst;
709
710 /*Clear Overflow */
711 - CIWDOFST = CO_FIFO_Y|CO_FIFO_CB|CO_FIFO_CR|PR_FIFO_CB|PR_FIFO_CB;
712 - CIWDOFST = 0; /* ? Dummy */
713 + writel(CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR | PR_FIFO_CB | PR_FIFO_CB,
714 + camregs + S3C2440_CAM_REG_CIWDOFST);
715 + writel(0, camregs + S3C2440_CAM_REG_CIWDOFST);
716 +
717 if (!h && !v) {
718 - CIWDOFST = 0;
719 + writel(0, camregs + S3C2440_CAM_REG_CIWDOFST);
720 return 0;
721 }
722 - CIWDOFST = WINOFEN | WINHOROFST(h) | WINVEROFST(v);
723 +
724 + writel(WINOFEN | WINHOROFST(h) | WINVEROFST(v), camregs + S3C2440_CAM_REG_CIWDOFST);
725 return 0;
726 }
727
728 @@ -554,7 +569,7 @@ int camif_win_offset(camif_gc_t *gc )
729 */
730 static void camif_polarity(camif_gc_t *gc)
731 {
732 - u32 cmd = CIGCTRL;
733 + u32 cmd = readl(camregs + S3C2440_CAM_REG_CIGCTRL);;
734
735 cmd = cmd & ~(BIT26|BIT25|BIT24); /* clear polarity */
736 if (gc->polarity_pclk)
737 @@ -563,7 +578,8 @@ static void camif_polarity(camif_gc_t *gc)
738 cmd |= GC_INVPOLVSYNC;
739 if (gc->polarity_href)
740 cmd |= GC_INVPOLHREF;
741 - CIGCTRL |= cmd;
742 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
743 + cmd, camregs + S3C2440_CAM_REG_CIGCTRL);
744 }
745
746
747 @@ -599,12 +615,13 @@ int camif_dynamic_close(camif_cfg_t *cfg)
748 static int camif_target_area(camif_cfg_t *cfg)
749 {
750 u32 rect = cfg->target_x * cfg->target_y;
751 - if (cfg->dma_type & CAMIF_CODEC ) {
752 - CICOTAREA = rect;
753 - }
754 - if (cfg->dma_type & CAMIF_PREVIEW) {
755 - CIPRTAREA = rect;
756 - }
757 +
758 + if (cfg->dma_type & CAMIF_CODEC)
759 + writel(rect, camregs + S3C2440_CAM_REG_CICOTAREA);
760 +
761 + if (cfg->dma_type & CAMIF_PREVIEW)
762 + writel(rect, camregs + S3C2440_CAM_REG_CIPRTAREA);
763 +
764 return 0;
765 }
766
767 @@ -613,40 +630,44 @@ static int inline camif_hw_reg(camif_cfg_t *cfg)
768 u32 cmd = 0;
769
770 if (cfg->dma_type & CAMIF_CODEC) {
771 - CICOSCPRERATIO = PRE_SHIFT(cfg->sc.shfactor)
772 - |PRE_HRATIO(cfg->sc.prehratio)|PRE_VRATIO(cfg->sc.prevratio);
773 - CICOSCPREDST =
774 - PRE_DST_WIDTH(cfg->sc.predst_x)|PRE_DST_HEIGHT(cfg->sc.predst_y);
775 + writel(PRE_SHIFT(cfg->sc.shfactor) |
776 + PRE_HRATIO(cfg->sc.prehratio) |
777 + PRE_VRATIO(cfg->sc.prevratio),
778 + camregs + S3C2440_CAM_REG_CICOSCPRERATIO);
779 + writel(PRE_DST_WIDTH(cfg->sc.predst_x) |
780 + PRE_DST_HEIGHT(cfg->sc.predst_y),
781 + camregs + S3C2440_CAM_REG_CICOSCPREDST);
782
783 /* Differ from Preview */
784 if (cfg->sc.scalerbypass)
785 cmd |= SCALERBYPASS;
786 if (cfg->sc.scaleup_h & cfg->sc.scaleup_v)
787 cmd |= BIT30|BIT29;
788 - CICOSCCTRL = cmd | MAIN_HRATIO(cfg->sc.mainhratio)
789 - |MAIN_VRATIO(cfg->sc.mainvratio);
790 + writel(cmd | MAIN_HRATIO(cfg->sc.mainhratio) |
791 + MAIN_VRATIO(cfg->sc.mainvratio),
792 + camregs + S3C2440_CAM_REG_CICOSCCTRL);
793 return 0;
794 }
795 - else if (cfg->dma_type & CAMIF_PREVIEW) {
796 - CIPRSCPRERATIO = PRE_SHIFT(cfg->sc.shfactor)
797 - |PRE_HRATIO(cfg->sc.prehratio)|PRE_VRATIO(cfg->sc.prevratio);
798 - CIPRSCPREDST =
799 - PRE_DST_WIDTH(cfg->sc.predst_x)|PRE_DST_HEIGHT(cfg->sc.predst_y);
800 + if (cfg->dma_type & CAMIF_PREVIEW) {
801 + writel(PRE_SHIFT(cfg->sc.shfactor) |
802 + PRE_HRATIO(cfg->sc.prehratio) |
803 + PRE_VRATIO(cfg->sc.prevratio),
804 + camregs + S3C2440_CAM_REG_CIPRSCPRERATIO);
805 + writel(PRE_DST_WIDTH(cfg->sc.predst_x) |
806 + PRE_DST_HEIGHT(cfg->sc.predst_y),
807 + camregs + S3C2440_CAM_REG_CIPRSCPREDST);
808 /* Differ from Codec */
809 - if (cfg->fmt & CAMIF_RGB24) {
810 + if (cfg->fmt & CAMIF_RGB24)
811 cmd |= RGB_FMT24;
812 - }
813 - else {
814 - /* RGB16 */;
815 - }
816 if (cfg->sc.scaleup_h & cfg->sc.scaleup_v)
817 - cmd |= BIT29|BIT28;
818 - CIPRSCCTRL = cmd |MAIN_HRATIO(cfg->sc.mainhratio)|S_METHOD
819 - |MAIN_VRATIO(cfg->sc.mainvratio);
820 - }else {
821 - panic("CAMERA:DMA_TYPE Wrong \n");
822 + cmd |= BIT29 | BIT28;
823 + writel(cmd | MAIN_HRATIO(cfg->sc.mainhratio) | S_METHOD |
824 + MAIN_VRATIO(cfg->sc.mainvratio),
825 + camregs + S3C2440_CAM_REG_CIPRSCCTRL);
826 + return 0;
827 }
828
829 + panic("CAMERA:DMA_TYPE Wrong \n");
830 return 0;
831 }
832
833 @@ -654,46 +675,50 @@ static int inline camif_hw_reg(camif_cfg_t *cfg)
834 /* Configure Pre-scaler control & main scaler control register */
835 static int camif_scaler(camif_cfg_t *cfg)
836 {
837 - int tx = cfg->target_x,ty=cfg->target_y;
838 + int tx = cfg->target_x, ty = cfg->target_y;
839 int sx, sy;
840
841 - if (tx <= 0 || ty<= 0) panic("CAMERA: Invalid target size \n");
842 + if (tx <= 0 || ty <= 0)
843 + panic("CAMERA: Invalid target size \n");
844 +
845 + sx = cfg->gc->source_x - 2 * cfg->gc->win_hor_ofst;
846 + sy = cfg->gc->source_y - 2 * cfg->gc->win_ver_ofst;
847 + if (sx <= 0 || sy <= 0)
848 + panic("CAMERA: Invalid source size \n");
849
850 - sx = cfg->gc->source_x - 2*cfg->gc->win_hor_ofst;
851 - sy = cfg->gc->source_y - 2*cfg->gc->win_ver_ofst;
852 - if (sx <= 0 || sy<= 0) panic("CAMERA: Invalid source size \n");
853 cfg->sc.modified_src_x = sx;
854 cfg->sc.modified_src_y = sy;
855
856 /* Pre-scaler control register 1 */
857 - camif_scaler_internal(sx,tx,&cfg->sc.prehratio,&cfg->sc.hfactor);
858 - camif_scaler_internal(sy,ty,&cfg->sc.prevratio,&cfg->sc.vfactor);
859 + camif_scaler_internal(sx, tx, &cfg->sc.prehratio, &cfg->sc.hfactor);
860 + camif_scaler_internal(sy, ty, &cfg->sc.prevratio, &cfg->sc.vfactor);
861
862 - if (cfg->dma_type & CAMIF_PREVIEW) {
863 - if ( (sx /cfg->sc.prehratio) <= 640 ) {}
864 - else {
865 - printk(KERN_INFO "CAMERA: Internal Preview line buffer is 640 pixels\n");
866 + if (cfg->dma_type & CAMIF_PREVIEW)
867 + if ((sx / cfg->sc.prehratio) > 640) {
868 + printk(KERN_INFO "CAMERA: Internal Preview line "
869 + "buffer is 640 pixels\n");
870 return 1; /* Error */
871 }
872 - }
873
874 - cfg->sc.shfactor = 10-(cfg->sc.hfactor+cfg->sc.vfactor);
875 + cfg->sc.shfactor = 10 - (cfg->sc.hfactor + cfg->sc.vfactor);
876 /* Pre-scaler control register 2 */
877 cfg->sc.predst_x = sx / cfg->sc.prehratio;
878 cfg->sc.predst_y = sy / cfg->sc.prevratio;
879
880 /* Main-scaler control register */
881 - cfg->sc.mainhratio = (sx << 8)/(tx << cfg->sc.hfactor);
882 - cfg->sc.mainvratio = (sy << 8)/(ty << cfg->sc.vfactor);
883 - DPRINTK(" sx %d, sy %d tx %d ty %d \n",sx,sy,tx,ty);
884 - DPRINTK(" hfactor %d vfactor %d \n",cfg->sc.hfactor,cfg->sc.vfactor);
885 + cfg->sc.mainhratio = (sx << 8) / (tx << cfg->sc.hfactor);
886 + cfg->sc.mainvratio = (sy << 8) / (ty << cfg->sc.vfactor);
887 + DPRINTK(" sx %d, sy %d tx %d ty %d \n", sx, sy, tx, ty);
888 + DPRINTK(" hfactor %d vfactor %d \n",cfg->sc.hfactor, cfg->sc.vfactor);
889
890 cfg->sc.scaleup_h = (sx <= tx) ? 1: 0;
891 cfg->sc.scaleup_v = (sy <= ty) ? 1: 0;
892 - if ( cfg->sc.scaleup_h != cfg->sc.scaleup_v)
893 + if (cfg->sc.scaleup_h != cfg->sc.scaleup_v)
894 printk(KERN_ERR "scaleup_h must be same to scaleup_v \n");
895 +
896 camif_hw_reg(cfg);
897 camif_target_area(cfg);
898 +
899 return 0;
900 }
901
902 @@ -706,38 +731,38 @@ static void camif_g_bsize(u32 hsize, u32 *mburst, u32 *rburst)
903 {
904 u32 tmp;
905
906 - tmp = (hsize/4) % 16;
907 + tmp = (hsize / 4) % 16;
908 switch(tmp) {
909 + case 0:
910 + *mburst=16;
911 + *rburst=16;
912 + break;
913 + case 4:
914 + *mburst=16;
915 + *rburst=4;
916 + break;
917 + case 8:
918 + *mburst=16;
919 + *rburst=8;
920 + break;
921 + default:
922 + tmp=(hsize / 4) % 8;
923 + switch(tmp) {
924 case 0:
925 - *mburst=16;
926 - *rburst=16;
927 + *mburst = 8;
928 + *rburst = 8;
929 break;
930 case 4:
931 - *mburst=16;
932 - *rburst=4;
933 - break;
934 - case 8:
935 - *mburst=16;
936 - *rburst=8;
937 - break;
938 + *mburst = 8;
939 + *rburst = 4;
940 default:
941 - tmp=(hsize/4)%8;
942 - switch(tmp) {
943 - case 0:
944 - *mburst=8;
945 - *rburst=8;
946 - break;
947 - case 4:
948 - *mburst=8;
949 - *rburst=4;
950 - default:
951 - *mburst=4;
952 - tmp=(hsize/4)%4;
953 - *rburst= (tmp) ? tmp: 4;
954 - break;
955 - }
956 + *mburst = 4;
957 + tmp = (hsize / 4) % 4;
958 + *rburst= (tmp) ? tmp: 4;
959 break;
960 }
961 + break;
962 + }
963 }
964
965 /* SXGA 1028x1024*/
966 @@ -759,24 +784,30 @@ static int camif_dma_burst(camif_cfg_t *cfg)
967 u32 yburst_m, yburst_r;
968 u32 cburst_m, cburst_r;
969 /* CODEC DMA WIDHT is multiple of 16 */
970 - if (width %16 != 0 ) return BURST_ERR; /* DMA Burst Length Error */
971 - camif_g_bsize(width,&yburst_m,&yburst_r);
972 - camif_g_bsize(width/2,&cburst_m,&cburst_r);
973 - CICOCTRL =YBURST_M(yburst_m)|CBURST_M(cburst_m)
974 - |YBURST_R(yburst_r)|CBURST_R(cburst_r);
975 + if (width % 16)
976 + return BURST_ERR; /* DMA Burst Length Error */
977 + camif_g_bsize(width, &yburst_m, &yburst_r);
978 + camif_g_bsize(width / 2, &cburst_m, &cburst_r);
979 +
980 + writel(YBURST_M(yburst_m) | CBURST_M(cburst_m) |
981 + YBURST_R(yburst_r) | CBURST_R(cburst_r),
982 + camregs + S3C2440_CAM_REG_CICOCTRL);
983 }
984
985 if (cfg->dma_type & CAMIF_PREVIEW) {
986 u32 rgburst_m, rgburst_r;
987 if(cfg->fmt == CAMIF_RGB24) {
988 - if (width %2 != 0 ) return BURST_ERR; /* DMA Burst Length Error */
989 + if (width % 2)
990 + return BURST_ERR; /* DMA Burst Length Error */
991 camif_g_bsize(width*4,&rgburst_m,&rgburst_r);
992 - }
993 - else { /* CAMIF_RGB16 */
994 - if ((width/2) %2 != 0 ) return BURST_ERR; /* DMA Burst Length Error */
995 + } else { /* CAMIF_RGB16 */
996 + if ((width / 2) %2)
997 + return BURST_ERR; /* DMA Burst Length Error */
998 camif_g_bsize(width*2,&rgburst_m,&rgburst_r);
999 }
1000 - CIPRCTRL = RGBURST_M(rgburst_m) | RGBURST_R(rgburst_r);
1001 +
1002 + writel(RGBURST_M(rgburst_m) | RGBURST_R(rgburst_r),
1003 + camregs + S3C2440_CAM_REG_CIPRCTRL);
1004 }
1005 return 0;
1006 }
1007 @@ -786,19 +817,20 @@ static int camif_gpio_init(void)
1008 #ifdef CONFIG_ARCH_S3C24A0A
1009 /* S3C24A0A has the dedicated signal pins for Camera */
1010 #else
1011 - set_gpio_ctrl(GPIO_CAMDATA0);
1012 - set_gpio_ctrl(GPIO_CAMDATA1);
1013 - set_gpio_ctrl(GPIO_CAMDATA2);
1014 - set_gpio_ctrl(GPIO_CAMDATA3);
1015 - set_gpio_ctrl(GPIO_CAMDATA4);
1016 - set_gpio_ctrl(GPIO_CAMDATA5);
1017 - set_gpio_ctrl(GPIO_CAMDATA6);
1018 - set_gpio_ctrl(GPIO_CAMDATA7);
1019 - set_gpio_ctrl(GPIO_CAMPCLKIN);
1020 - set_gpio_ctrl(GPIO_CAMVSYNC);
1021 - set_gpio_ctrl(GPIO_CAMHREF);
1022 - set_gpio_ctrl(GPIO_CAMPCLKOUT);
1023 - set_gpio_ctrl(GPIO_CAMRESET);
1024 + s3c2410_gpio_cfgpin(S3C2440_GPJ0, S3C2440_GPJ0_CAMDATA0);
1025 + s3c2410_gpio_cfgpin(S3C2440_GPJ1, S3C2440_GPJ1_CAMDATA1);
1026 + s3c2410_gpio_cfgpin(S3C2440_GPJ2, S3C2440_GPJ2_CAMDATA2);
1027 + s3c2410_gpio_cfgpin(S3C2440_GPJ3, S3C2440_GPJ3_CAMDATA3);
1028 + s3c2410_gpio_cfgpin(S3C2440_GPJ4, S3C2440_GPJ4_CAMDATA4);
1029 + s3c2410_gpio_cfgpin(S3C2440_GPJ5, S3C2440_GPJ5_CAMDATA5);
1030 + s3c2410_gpio_cfgpin(S3C2440_GPJ6, S3C2440_GPJ6_CAMDATA6);
1031 + s3c2410_gpio_cfgpin(S3C2440_GPJ7, S3C2440_GPJ7_CAMDATA7);
1032 +
1033 + s3c2410_gpio_cfgpin(S3C2440_GPJ8, S3C2440_GPJ8_CAMPCLK);
1034 + s3c2410_gpio_cfgpin(S3C2440_GPJ9, S3C2440_GPJ9_CAMVSYNC);
1035 + s3c2410_gpio_cfgpin(S3C2440_GPJ10, S3C2440_GPJ10_CAMHREF);
1036 + s3c2410_gpio_cfgpin(S3C2440_GPJ11, S3C2440_GPJ11_CAMCLKOUT);
1037 + s3c2410_gpio_cfgpin(S3C2440_GPJ12, S3C2440_GPJ12_CAMRESET);
1038 #endif
1039 return 0;
1040 }
1041 @@ -827,21 +859,33 @@ int camif_clock_init(camif_gc_t *gc)
1042 camclk_div = (upll+ROUND_ADD) / camclk - 1;
1043 CLKDIVN = (CLKDIVN & 0xFF) | CLKDIVN_CAM(camclk_div);
1044 printk(KERN_INFO"CAMERA:upll %d MACRO 0x%08X CLKDIVN 0x%08X \n",
1045 - upll, CLKDIVN_CAM(camclk_div),CLKDIVN);
1046 - CIIMGCPT = 0; /* Dummy ? */
1047 + upll, CLKDIVN_CAM(camclk_div), CLKDIVN);
1048 + writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT); /* Dummy ? */
1049 +
1050 return 0;
1051 }
1052 #else
1053 int camif_clock_init(camif_gc_t *gc)
1054 {
1055 - unsigned int upll, camclk_div, camclk;
1056 - if (!gc) camclk = 24000000;
1057 - else {
1058 + unsigned int camclk;
1059 + struct clk *clk_camif = clk_get(NULL, "camif");
1060 + struct clk *clk_camif_upll = clk_get(NULL, "camif-upll");
1061 +
1062 + if (!gc)
1063 + camclk = 24000000;
1064 + else {
1065 camclk = gc->camclk;
1066 if (camclk > 48000000)
1067 printk(KERN_ERR "Wrong Camera Clock\n");
1068 }
1069
1070 + clk_set_rate(clk_camif, camclk);
1071 +
1072 + clk_enable(clk_camif);
1073 + clk_enable(clk_camif_upll);
1074 +
1075 +
1076 +#if 0
1077 CLKCON |= CLKCON_CAMIF;
1078 upll = elfin_get_bus_clk(GET_UPLL);
1079 printk(KERN_INFO "CAMERA:Default UPLL %08d and Assing 96Mhz to UPLL\n",upll);
1080 @@ -854,7 +898,9 @@ int camif_clock_init(camif_gc_t *gc)
1081 camclk_div = (upll+ROUND_ADD) /(camclk * 2) -1;
1082 CAMDIVN = CAMCLK_SET_DIV|(camclk_div&0xf);
1083 printk(KERN_INFO "CAMERA:upll %08d cam_clk %08d CAMDIVN 0x%08x \n",upll,camclk, CAMDIVN);
1084 - CIIMGCPT = 0; /* Dummy ? */
1085 +#endif
1086 + writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT); /* Dummy ? */
1087 +
1088 return 0;
1089 }
1090 #endif
1091 @@ -867,23 +913,39 @@ void camif_reset(int is, int delay)
1092 {
1093 switch (is) {
1094 case CAMIF_RESET:
1095 - CIGCTRL |= GC_SWRST;
1096 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
1097 + GC_SWRST,
1098 + camregs + S3C2440_CAM_REG_CIGCTRL);
1099 mdelay(1);
1100 - CIGCTRL &= ~GC_SWRST;
1101 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
1102 + ~GC_SWRST,
1103 + camregs + S3C2440_CAM_REG_CIGCTRL);
1104 break;
1105 case CAMIF_EX_RESET_AH: /*Active High */
1106 - CIGCTRL &= ~GC_CAMRST;
1107 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
1108 + ~GC_CAMRST,
1109 + camregs + S3C2440_CAM_REG_CIGCTRL);
1110 udelay(200);
1111 - CIGCTRL |= GC_CAMRST;
1112 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
1113 + GC_CAMRST,
1114 + camregs + S3C2440_CAM_REG_CIGCTRL);
1115 udelay(delay);
1116 - CIGCTRL &= ~GC_CAMRST;
1117 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
1118 + ~GC_CAMRST,
1119 + camregs + S3C2440_CAM_REG_CIGCTRL);
1120 break;
1121 case CAMIF_EX_RESET_AL: /*Active Low */
1122 - CIGCTRL |= GC_CAMRST;
1123 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
1124 + GC_CAMRST,
1125 + camregs + S3C2440_CAM_REG_CIGCTRL);
1126 udelay(200);
1127 - CIGCTRL &= ~GC_CAMRST;
1128 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
1129 + ~GC_CAMRST,
1130 + camregs + S3C2440_CAM_REG_CIGCTRL);
1131 udelay(delay);
1132 - CIGCTRL |= GC_CAMRST;
1133 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
1134 + GC_CAMRST,
1135 + camregs + S3C2440_CAM_REG_CIGCTRL);
1136 break;
1137 default:
1138 break;
1139 @@ -908,10 +970,10 @@ static void camif_bus_priority(int flag)
1140 PRIORITY1 = PRIORITY_I_FIX;
1141
1142 #else
1143 - old_priority = PRIORITY;
1144 - PRIORITY &= ~(3<<7);
1145 - PRIORITY |= (1<<7); /* Arbiter 1, REQ2 first */
1146 - PRIORITY &= ~(1<<1); /* Disable Priority Rotate */
1147 + old_priority = readl(S3C2410_PRIORITY);
1148 + writel(readl(S3C2410_PRIORITY) & ~(3<<7), S3C2410_PRIORITY);
1149 + writel(readl(S3C2410_PRIORITY) | (1<<7), S3C2410_PRIORITY); /* Arbiter 1, REQ2 first */
1150 + writel(readl(S3C2410_PRIORITY) & ~(1<<1), S3C2410_PRIORITY); /* Disable Priority Rotate */
1151 #endif
1152 }
1153 else {
1154 @@ -919,19 +981,26 @@ static void camif_bus_priority(int flag)
1155 PRIORITY0 = old_priority;
1156 PRIORITY1 = old_priority;
1157 #else
1158 - PRIORITY = old_priority;
1159 + writel(old_priority, S3C2410_PRIORITY);
1160 #endif
1161 }
1162 }
1163
1164 static void inline camif_clock_off(void)
1165 {
1166 - CIIMGCPT = 0;
1167 #if defined (CONFIG_ARCH_S3C24A0A)
1168 + writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT);
1169 +
1170 CLKCON &= ~CLKCON_CAM_UPLL;
1171 CLKCON &= ~CLKCON_CAM_HCLK;
1172 #else
1173 - CLKCON &= ~CLKCON_CAMIF;
1174 + struct clk *clk_camif = clk_get(NULL, "camif");
1175 + struct clk *clk_camif_upll = clk_get(NULL, "camif-upll");
1176 +
1177 + writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT);
1178 +
1179 + clk_disable(clk_camif);
1180 + clk_disable(clk_camif_upll);
1181 #endif
1182 }
1183
1184 diff --git a/arch/arm/mach-s3c2440/camera/camif_fsm.c b/arch/arm/mach-s3c2440/camera/camif_fsm.c
1185 index 3e2b71a..b534aca 100644
1186 --- a/arch/arm/mach-s3c2440/camera/camif_fsm.c
1187 +++ b/arch/arm/mach-s3c2440/camera/camif_fsm.c
1188 @@ -31,7 +31,12 @@
1189 #include <asm/semaphore.h>
1190 #include <linux/miscdevice.h>
1191
1192 +#define CONFIG_VIDEO_V4L1_COMPAT
1193 +#include <linux/videodev.h>
1194 +#include "camif.h"
1195 +
1196 //#define SW_DEBUG
1197 +static void camif_start_p_with_c(camif_cfg_t *cfg);
1198
1199 #include "camif.h"
1200 const char *fsm_version =
1201 diff --git a/arch/arm/mach-s3c2440/camera/imgsensor.c b/arch/arm/mach-s3c2440/camera/imgsensor.c
1202 index 44b7bee..2099b69 100644
1203 --- a/arch/arm/mach-s3c2440/camera/imgsensor.c
1204 +++ b/arch/arm/mach-s3c2440/camera/imgsensor.c
1205 @@ -11,7 +11,7 @@
1206 * Driver for FIMC20 Camera Decoder
1207 */
1208
1209 -#include <linux/config.h>
1210 +
1211 #include <linux/module.h>
1212 #include <linux/kernel.h>
1213 #include <linux/init.h>
1214 @@ -24,10 +24,12 @@
1215
1216 #ifdef CONFIG_ARCH_S3C24A0A
1217 #else
1218 -#include <asm/arch/S3C2440.h>
1219 +//#include <asm/arch/S3C2440.h>
1220 #endif
1221
1222 #define SW_DEBUG
1223 +#define CONFIG_VIDEO_V4L1_COMPAT
1224 +#include <linux/videodev.h>
1225 #include "camif.h"
1226 #include "sensor.h"
1227
1228 @@ -37,10 +39,6 @@
1229 #include "sxga.h"
1230 #endif
1231
1232 -static const char *sensor_version =
1233 - "$Id: imgsensor.c,v 1.11 2004/06/10 12:45:40 swlee Exp $";
1234 -
1235 -
1236 static struct i2c_driver s5x532_driver;
1237 static camif_gc_t data = {
1238 itu_fmt: CAMIF_ITU601,
1239 @@ -69,22 +67,18 @@ static camif_gc_t data = {
1240
1241 #define CAM_ID 0x5a
1242
1243 -static unsigned short ignore[] = { I2C_CLIENT_END };
1244 +static unsigned short ignore = I2C_CLIENT_END;
1245 static unsigned short normal_addr[] = { (CAM_ID>>1), I2C_CLIENT_END };
1246 static struct i2c_client_address_data addr_data = {
1247 normal_i2c: normal_addr,
1248 - normal_i2c_range: ignore,
1249 - probe: ignore,
1250 - probe_range: ignore,
1251 - ignore: ignore,
1252 - ignore_range: ignore,
1253 - force: ignore,
1254 + probe: &ignore,
1255 + ignore: &ignore,
1256 };
1257
1258 s5x532_t s5x532_regs_mirror[S5X532_REGS];
1259
1260 unsigned char
1261 -s5x532_read(struct i2c_client *client,unsigned char subaddr)
1262 +s5x532_read(struct i2c_client *client, unsigned char subaddr)
1263 {
1264 int ret;
1265 unsigned char buf[1];
1266 @@ -151,7 +145,7 @@ void inline s5x532_init(struct i2c_client *sam_client)
1267 }
1268
1269 static int
1270 -s5x532_attach(struct i2c_adapter *adap, int addr, unsigned short flags,int kind)
1271 +s5x532_attach(struct i2c_adapter *adap, int addr, int kind)
1272 {
1273 struct i2c_client *c;
1274
1275 @@ -159,13 +153,13 @@ s5x532_attach(struct i2c_adapter *adap, int addr, unsigned short flags,int kind)
1276 if (!c) return -ENOMEM;
1277
1278 strcpy(c->name, "S5X532");
1279 - c->id = s5x532_driver.id;
1280 - c->flags = I2C_CLIENT_ALLOW_USE;
1281 +// c->id = s5x532_driver.id;
1282 + c->flags = 0 /* I2C_CLIENT_ALLOW_USE */;
1283 c->addr = addr;
1284 c->adapter = adap;
1285 c->driver = &s5x532_driver;
1286 - c->data = &data;
1287 - data.sensor = c;
1288 + data.sensor = c;
1289 + i2c_set_clientdata(c, &data);
1290
1291 camif_register_decoder(c);
1292 return i2c_attach_client(c);
1293 @@ -192,10 +186,10 @@ s5x532_command(struct i2c_client *client, unsigned int cmd, void *arg)
1294 printk(KERN_INFO "CAMERA: S5X532 Sensor initialized\n");
1295 break;
1296 case USER_ADD:
1297 - MOD_INC_USE_COUNT;
1298 + /* MOD_INC_USE_COUNT; uh.. 2.6 deals with this, old-timer */
1299 break;
1300 case USER_EXIT:
1301 - MOD_DEC_USE_COUNT;
1302 + /* MOD_DEC_USE_COUNT; */
1303 break;
1304 /* Todo
1305 case SENSOR_BRIGHTNESS:
1306 @@ -210,9 +204,8 @@ s5x532_command(struct i2c_client *client, unsigned int cmd, void *arg)
1307 }
1308
1309 static struct i2c_driver s5x532_driver = {
1310 - name: "S5X532",
1311 - id: I2C_ALGO_S3C,
1312 - flags: I2C_DF_NOTIFY,
1313 + driver: { name: "S5X532" },
1314 + id: 0, /* optional in i2c-id.h I2C_ALGO_S3C, */
1315 attach_adapter: s5x532_probe,
1316 detach_client: s5x532_detach,
1317 command: s5x532_command
1318 @@ -220,11 +213,13 @@ static struct i2c_driver s5x532_driver = {
1319
1320 static void iic_gpio_port(void)
1321 {
1322 +/* FIXME: no gpio config for i2c !!!
1323 #ifdef CONFIG_ARCH_S3C24A0A
1324 #else
1325 GPECON &= ~(0xf <<28);
1326 GPECON |= 0xa <<28;
1327 #endif
1328 +*/
1329 }
1330
1331 static __init int camif_sensor_init(void)
1332 diff --git a/arch/arm/mach-s3c2440/camera/qt-driver.c b/arch/arm/mach-s3c2440/camera/qt-driver.c
1333 index 0c5dd40..cbf8565 100644
1334 --- a/arch/arm/mach-s3c2440/camera/qt-driver.c
1335 +++ b/arch/arm/mach-s3c2440/camera/qt-driver.c
1336 @@ -31,12 +31,15 @@
1337
1338 //#define SW_DEBUG
1339
1340 +#define CONFIG_VIDEO_V4L1_COMPAT
1341 +#include <linux/videodev.h>
1342 #include "camif.h"
1343 -#include "videodev.h"
1344 #include "miscdevice.h"
1345 #include "cam_reg.h"
1346 #include "sensor.h"
1347 #include "userapp.h"
1348 +
1349 +extern camif_cfg_t * get_camif(int nr);
1350
1351
1352 /************************* Sharp Zarus API **************************
1353 diff --git a/arch/arm/mach-s3c2440/camera/video-driver.c b/arch/arm/mach-s3c2440/camera/video-driver.c
1354 index fe9130c..9c77475 100644
1355 --- a/arch/arm/mach-s3c2440/camera/video-driver.c
1356 +++ b/arch/arm/mach-s3c2440/camera/video-driver.c
1357 @@ -29,11 +29,12 @@
1358 #include <asm/irq.h>
1359 #include <asm/semaphore.h>
1360 #include <linux/miscdevice.h>
1361 +#include <asm/arch/irqs.h>
1362
1363 //#define SW_DEBUG
1364 -
1365 +#define CONFIG_VIDEO_V4L1_COMPAT
1366 +#include <linux/videodev.h>
1367 #include "camif.h"
1368 -#include "videodev.h"
1369 #include "miscdevice.h"
1370 #include "cam_reg.h"
1371 #include "sensor.h"
1372 @@ -46,12 +47,14 @@
1373 /* Codec and Preview */
1374 #define CAMIF_NUM 2
1375 static camif_cfg_t fimc[CAMIF_NUM];
1376 +u32 *camregs;
1377
1378 static const char *driver_version =
1379 "$Id: video-driver.c,v 1.9 2004/06/02 03:10:36 swlee Exp $";
1380 extern const char *fimc_version;
1381 extern const char *fsm_version;
1382
1383 +extern void camif_start_c_with_p (camif_cfg_t *cfg, camif_cfg_t *other);
1384
1385 camif_cfg_t * get_camif(int nr)
1386 {
1387 @@ -177,28 +180,34 @@ camif_c_read(struct file *file, char *buf, size_t count, loff_t *pos)
1388 }
1389
1390
1391 -static void camif_c_irq(int irq, void *dev_id, struct pt_regs *regs)
1392 +static irqreturn_t camif_c_irq(int irq, void *dev_id)
1393 {
1394 camif_cfg_t *cfg = (camif_cfg_t *)dev_id;
1395 +
1396 DPRINTK("\n");
1397 camif_g_fifo_status(cfg);
1398 camif_g_frame_num(cfg);
1399 - if(camif_enter_c_4fsm(cfg) == INSTANT_SKIP) return;
1400 - wake_up_interruptible(&cfg->waitq);
1401 + if(camif_enter_c_4fsm(cfg) != INSTANT_SKIP)
1402 + wake_up_interruptible(&cfg->waitq);
1403 +
1404 + return IRQ_HANDLED;
1405 }
1406
1407 -static void camif_p_irq(int irq, void *dev_id, struct pt_regs * regs)
1408 +static irqreturn_t camif_p_irq(int irq, void *dev_id)
1409 {
1410 camif_cfg_t *cfg = (camif_cfg_t *)dev_id;
1411 +
1412 DPRINTK("\n");
1413 camif_g_fifo_status(cfg);
1414 camif_g_frame_num(cfg);
1415 - if(camif_enter_p_4fsm(cfg) == INSTANT_SKIP) return;
1416 - wake_up_interruptible(&cfg->waitq);
1417 + if(camif_enter_p_4fsm(cfg) != INSTANT_SKIP)
1418 + wake_up_interruptible(&cfg->waitq);
1419 #if 0
1420 if( (cfg->perf.frames % 5) == 0)
1421 DPRINTK("5\n");
1422 #endif
1423 +
1424 + return IRQ_HANDLED;
1425 }
1426
1427 static void camif_release_irq(camif_cfg_t *cfg)
1428 @@ -213,13 +222,13 @@ static int camif_irq_request(camif_cfg_t *cfg)
1429
1430 if (cfg->dma_type & CAMIF_CODEC) {
1431 if ((ret = request_irq(cfg->irq, camif_c_irq,
1432 - SA_INTERRUPT,cfg->shortname, cfg))) {
1433 + 0, cfg->shortname, cfg))) {
1434 printk("request_irq(CAM_C) failed.\n");
1435 }
1436 }
1437 if (cfg->dma_type & CAMIF_PREVIEW) {
1438 if ((ret = request_irq(cfg->irq, camif_p_irq,
1439 - SA_INTERRUPT,cfg->shortname, cfg))) {
1440 + 0, cfg->shortname, cfg))) {
1441 printk("request_irq(CAM_P) failed.\n");
1442 }
1443 }
1444 @@ -438,7 +447,7 @@ static struct video_device codec_template =
1445 {
1446 .name = "CODEC_IF",
1447 .type = VID_TYPE_CAPTURE|VID_TYPE_CLIPPING|VID_TYPE_SCALES,
1448 - .hardware = VID_HARDWARE_SAMSUNG_FIMC20,
1449 +/* .hardware = VID_HARDWARE_SAMSUNG_FIMC20, */
1450 .fops = &camif_c_fops,
1451 // .release = camif_release
1452 .minor = -1,
1453 @@ -448,7 +457,7 @@ static struct video_device preview_template =
1454 {
1455 .name = "PREVIEW_IF",
1456 .type = VID_TYPE_CAPTURE|VID_TYPE_CLIPPING|VID_TYPE_SCALES,
1457 - .hardware = VID_HARDWARE_SAMSUNG_FIMC20,
1458 +/* .hardware = VID_HARDWARE_SAMSUNG_FIMC20, */
1459 .fops = &camif_p_fops,
1460 .minor = -1,
1461 };
1462 @@ -465,8 +474,8 @@ static int preview_init(camif_cfg_t *cfg)
1463 cfg->fmt = CAMIF_RGB16;
1464 cfg->flip = CAMIF_FLIP_Y;
1465 cfg->v = &preview_template;
1466 - init_MUTEX(&cfg->v->lock);
1467 - cfg->irq = IRQ_CAM_P;
1468 + mutex_init(&cfg->v->lock);
1469 + cfg->irq = IRQ_S3C2440_CAM_P;
1470
1471 strcpy(cfg->shortname,name);
1472 init_waitqueue_head(&cfg->waitq);
1473 @@ -486,8 +495,8 @@ static int codec_init(camif_cfg_t *cfg)
1474 cfg->fmt = CAMIF_IN_YCBCR422|CAMIF_OUT_YCBCR420;
1475 cfg->flip = CAMIF_FLIP_X;
1476 cfg->v = &codec_template;
1477 - init_MUTEX(&cfg->v->lock);
1478 - cfg->irq = IRQ_CAM_C;
1479 + mutex_init(&cfg->v->lock);
1480 + cfg->irq = IRQ_S3C2440_CAM_C;
1481 strcpy(cfg->shortname,name);
1482 init_waitqueue_head(&cfg->waitq);
1483 cfg->status = CAMIF_STOPPED;
1484 @@ -510,25 +519,44 @@ static void print_version(void)
1485
1486 static int camif_m_in(void)
1487 {
1488 - int ret = 0;
1489 + int ret = -EINVAL;
1490 camif_cfg_t * cfg;
1491
1492 + printk(KERN_INFO"Starting S3C2440 Camera Driver\n");
1493 +
1494 + camregs = ioremap(CAM_BASE_ADD, 0x100);
1495 + if (!camregs) {
1496 + printk(KERN_ERR"Unable to map camera regs\n");
1497 + ret = -ENOMEM;
1498 + goto bail1;
1499 + }
1500 +
1501 camif_init();
1502 cfg = get_camif(CODEC_MINOR);
1503 codec_init(cfg);
1504
1505 - if (video_register_device(cfg->v,0,CODEC_MINOR)!=0) {
1506 - DPRINTK("Couldn't register codec driver.\n");
1507 - return 0;
1508 + ret = video_register_device(cfg->v,0,CODEC_MINOR);
1509 + if (ret) {
1510 + printk(KERN_ERR"Couldn't register codec driver.\n");
1511 + goto bail2;
1512 }
1513 cfg = get_camif(PREVIEW_MINOR);
1514 preview_init(cfg);
1515 - if (video_register_device(cfg->v,0,PREVIEW_MINOR)!=0) {
1516 - DPRINTK("Couldn't register preview driver.\n");
1517 - return 0;
1518 + ret = video_register_device(cfg->v,0,PREVIEW_MINOR);
1519 + if (ret) {
1520 + printk(KERN_ERR"Couldn't register preview driver.\n");
1521 + goto bail3; /* hm seems it us unregistered the once */
1522 }
1523
1524 print_version();
1525 + return 0;
1526 +
1527 +bail3:
1528 + video_unregister_device(cfg->v);
1529 +bail2:
1530 + iounmap(camregs);
1531 + camregs = NULL;
1532 +bail1:
1533 return ret;
1534 }
1535
1536 @@ -536,7 +564,9 @@ static void unconfig_device(camif_cfg_t *cfg)
1537 {
1538 video_unregister_device(cfg->v);
1539 camif_hw_close(cfg);
1540 + iounmap(camregs);
1541 //memset(cfg, 0, sizeof(camif_cfg_t));
1542 + camregs = NULL;
1543 }
1544
1545 static void camif_m_out(void) /* module out */
1546 @@ -547,20 +577,22 @@ static void camif_m_out(void) /* module out */
1547 unconfig_device(cfg);
1548 cfg = get_camif(PREVIEW_MINOR);
1549 unconfig_device(cfg);
1550 +
1551 return;
1552 }
1553
1554 void camif_register_decoder(struct i2c_client *ptr)
1555 {
1556 camif_cfg_t *cfg;
1557 + void * data = i2c_get_clientdata(ptr);
1558
1559 cfg =get_camif(CODEC_MINOR);
1560 - cfg->gc = (camif_gc_t *)(ptr->data);
1561 + cfg->gc = (camif_gc_t *)(data);
1562
1563 cfg =get_camif(PREVIEW_MINOR);
1564 - cfg->gc = (camif_gc_t *)(ptr->data);
1565 + cfg->gc = (camif_gc_t *)(data);
1566
1567 - sema_init(&cfg->gc->lock,1); /* global lock for both Codec and Preview */
1568 + sema_init(&cfg->gc->lock, 1); /* global lock for both Codec and Preview */
1569 cfg->gc->status |= PNOTWORKING; /* Default Value */
1570 camif_hw_open(cfg->gc);
1571 }
1572 @@ -568,8 +600,9 @@ void camif_register_decoder(struct i2c_client *ptr)
1573 void camif_unregister_decoder(struct i2c_client *ptr)
1574 {
1575 camif_gc_t *gc;
1576 + void * data = i2c_get_clientdata(ptr);
1577
1578 - gc = (camif_gc_t *)(ptr->data);
1579 + gc = (camif_gc_t *)(data);
1580 gc->init_sensor = 0; /* need to modify */
1581 }
1582
1583 diff --git a/arch/arm/mach-s3c2440/camera/videodev.c b/arch/arm/mach-s3c2440/camera/videodev.c
1584 index 0b3498f..6f862e4 100644
1585 --- a/arch/arm/mach-s3c2440/camera/videodev.c
1586 +++ b/arch/arm/mach-s3c2440/camera/videodev.c
1587 @@ -22,7 +22,7 @@
1588 #include <linux/init.h>
1589 #include <linux/kmod.h>
1590 #include <linux/slab.h>
1591 -#include <linux/devfs_fs_kernel.h>
1592 +/* #include <linux/devfs_fs_kernel.h> */
1593 #include <linux/miscdevice.h>
1594 #include <asm/uaccess.h>
1595 #include <asm/system.h>
1596 @@ -30,8 +30,9 @@
1597
1598
1599
1600 +#define CONFIG_VIDEO_V4L1_COMPAT
1601 +#include <linux/videodev.h>
1602 #include "camif.h"
1603 -#include "videodev.h"
1604 #include "miscdevice.h"
1605
1606
1607 @@ -42,18 +43,7 @@ const char *fimc_version = "$Id: videodev.c,v 1.1.1.1 2004/04/27 03:52:50 swlee
1608 #define VIDEO_NAME "video4linux"
1609
1610
1611 -static inline unsigned iminor(struct inode *inode)
1612 -{
1613 - return MINOR(inode->i_rdev);
1614 -}
1615 -
1616 -static inline unsigned imajor(struct inode *inode)
1617 -{
1618 - return MAJOR(inode->i_rdev);
1619 -}
1620 -
1621 -
1622 -#define VIDEO_NUM_DEVICES 2
1623 +#define VIDEO_NUM_DEVICES 2
1624 static struct video_device *video_device[VIDEO_NUM_DEVICES];
1625
1626 static inline struct video_device * get_vd(int nr)
1627 @@ -104,7 +94,7 @@ static int video_open(struct inode *inode, struct file *file)
1628 int minor = MINOR(inode->i_rdev);
1629 int err = 0;
1630 struct video_device *vfl;
1631 - struct file_operations *old_fops;
1632 + struct file_operations const *old_fops;
1633
1634 down(&videodev_lock);
1635
1636 @@ -131,13 +121,13 @@ extern int video_exclusive_open(struct inode *inode, struct file *file)
1637 struct video_device *vfl = get_vd(MINOR(inode->i_rdev));
1638 int retval = 0;
1639
1640 - down(&vfl->lock);
1641 + mutex_lock(&vfl->lock);
1642 if (vfl->users) {
1643 retval = -EBUSY;
1644 } else {
1645 vfl->users++;
1646 }
1647 - up(&vfl->lock);
1648 + mutex_unlock(&vfl->lock);
1649 return retval;
1650 }
1651
1652 diff --git a/arch/arm/mach-s3c2440/camera/videodev.h b/arch/arm/mach-s3c2440/camera/videodev.h
1653 index f12db43..1c2e35a 100644
1654 --- a/arch/arm/mach-s3c2440/camera/videodev.h
1655 +++ b/arch/arm/mach-s3c2440/camera/videodev.h
1656 @@ -1,11 +1,11 @@
1657 -#ifndef __LINUX_S3C_VIDEODEV_H
1658 -#define __LINUX_S3C_VIDEODEV_H
1659 +//#ifndef __LINUX_S3C_VIDEODEV_H
1660 +//#define __LINUX_S3C_VIDEODEV_H
1661
1662 #include <linux/types.h>
1663 #include <linux/version.h>
1664 -#include "videodev2.h"
1665 -
1666 +#include <media/v4l2-dev.h>
1667
1668 +#if 0
1669 struct video_device
1670 {
1671 /* device info */
1672 @@ -96,12 +96,10 @@ extern int video_usercopy(struct inode *inode, struct file *file,
1673
1674
1675
1676 -#define VID_HARDWARE_SAMSUNG_FIMC 255
1677 -
1678 -
1679 -
1680 -#endif
1681 +#endif
1682 +//#endif
1683
1684 +#define VID_HARDWARE_SAMSUNG_FIMC 255
1685
1686 /*
1687 * Local variables:
1688 --
1689 1.5.6.3
1690
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