[target] ixp4xx: add missing config symbol for 2.6.30
[openwrt.git] / target / linux / coldfire / patches / 027-m5445x_usb_sdram_priority.patch
1 From b6b6d18a54e22784cb48e1953201484830d030e4 Mon Sep 17 00:00:00 2001
2 From: Kurt Mahan <kmahan@freescale.com>
3 Date: Thu, 6 Dec 2007 14:17:46 -0700
4 Subject: [PATCH] Change USB to SDRAM priority.
5
6 Increase the USB priority to the maximum, above ColdfireCore,
7 in the SDRAM crossbar switch. This fixes the issues with the
8 USB core not being able to transfer to memory fast enough to
9 keep up with HS.
10
11 LTIBName: m5445x-usb-sdram-priority
12 Signed-off-by: Kurt Mahan <kmahan@freescale.com>
13 ---
14 arch/m68k/coldfire/config.c | 12 ++++++
15 include/asm-m68k/mcf5445x_xbs.h | 81 +++++++++++++++++++++++++++++++++++++++
16 2 files changed, 93 insertions(+), 0 deletions(-)
17 create mode 100644 include/asm-m68k/mcf5445x_xbs.h
18
19 --- a/arch/m68k/coldfire/config.c
20 +++ b/arch/m68k/coldfire/config.c
21 @@ -36,6 +36,7 @@
22 #include <asm/mcf5445x_sdramc.h>
23 #include <asm/mcf5445x_fbcs.h>
24 #include <asm/mcf5445x_dtim.h>
25 +#include <asm/mcf5445x_xbs.h>
26
27 /* JKM -- testing */
28 #include <linux/pfn.h>
29 @@ -131,6 +132,17 @@ asmlinkage void __init cf_early_init(voi
30 MCF_SDRAMC_SDCS(1) = (256*1024*1024) | 0x1B;
31 #endif
32
33 + /* Setup SDRAM crossbar(XBS) priorities */
34 +printk(KERN_INFO "Bumping USB Priority\n");
35 + MCF_XBS_PRS2 = (MCF_XBS_PRS_M0(MCF_XBS_PRI_2) |
36 + MCF_XBS_PRS_M1(MCF_XBS_PRI_3) |
37 + MCF_XBS_PRS_M2(MCF_XBS_PRI_4) |
38 + MCF_XBS_PRS_M3(MCF_XBS_PRI_5) |
39 + MCF_XBS_PRS_M5(MCF_XBS_PRI_6) |
40 + MCF_XBS_PRS_M6(MCF_XBS_PRI_1) |
41 + MCF_XBS_PRS_M7(MCF_XBS_PRI_7));
42 +
43 +
44 m68k_machtype = MACH_CFMMU;
45 m68k_fputype = FPU_CFV4E;
46 m68k_mmutype = MMU_CFV4E;
47 --- /dev/null
48 +++ b/include/asm-m68k/mcf5445x_xbs.h
49 @@ -0,0 +1,81 @@
50 +/*
51 + * Kurt Mahan kmahan@freescale.com
52 + *
53 + * Copyright Freescale Semiconductor, Inc. 2007
54 + *
55 + * This program is free software; you can redistribute it and/or modify it
56 + * under the terms of the GNU General Public License as published by the
57 + * Free Software Foundation; either version 2 of the License, or (at your
58 + * option) any later version.
59 + */
60 +
61 +#ifndef __MCF5445X_XBS_H__
62 +#define __MCF5445X_XBS_H__
63 +
64 +/*
65 + * Crossbar Switch (XBS)
66 + */
67 +
68 +/* Register read/write macros */
69 +#define MCF_XBS_PRS1 MCF_REG32(0xFC004100) /* Flexbus Priority */
70 +#define MCF_XBS_CRS1 MCF_REG32(0xFC004110) /* Flexbus Control */
71 +#define MCF_XBS_PRS2 MCF_REG32(0xFC004200) /* SDRam Priority */
72 +#define MCF_XBS_CRS2 MCF_REG32(0xFC004210) /* SDRam Control */
73 +#define MCF_XBS_PRS3 MCF_REG32(0xFC004300) /* ATA Priority */
74 +#define MCF_XBS_CRS3 MCF_REG32(0xFC004310) /* ATA Control */
75 +#define MCF_XBS_PRS4 MCF_REG32(0xFC004400) /* SRAM Priority */
76 +#define MCF_XBS_CRS4 MCF_REG32(0xFC004410) /* SRAM Control */
77 +#define MCF_XBS_PRS5 MCF_REG32(0xFC004500) /* PCI Priority */
78 +#define MCF_XBS_CRS5 MCF_REG32(0xFC004510) /* PCI Control */
79 +#define MCF_XBS_PRS6 MCF_REG32(0xFC004600) /* Slave6 Priority */
80 +#define MCF_XBS_CRS6 MCF_REG32(0xFC004610) /* Slave6 Control */
81 +#define MCF_XBS_PRS7 MCF_REG32(0xFC004700) /* Other Priority */
82 +#define MCF_XBS_CRS7 MCF_REG32(0xFC004710) /* Other Control */
83 +
84 +/* Priorities */
85 +#define MCF_XBS_PRI_1 0 /* Level 1 (highest) */
86 +#define MCF_XBS_PRI_2 1 /* Level 2 */
87 +#define MCF_XBS_PRI_3 2 /* Level 3 */
88 +#define MCF_XBS_PRI_4 3 /* Level 4 */
89 +#define MCF_XBS_PRI_5 4 /* Level 5 */
90 +#define MCF_XBS_PRI_6 5 /* Level 6 */
91 +#define MCF_XBS_PRI_7 6 /* Level 7 (lowest) */
92 +#define MCF_XBS_PRI_MASK 7 /* Mask (Not a valid level) */
93 +
94 +/* Priority Register (PRSn) Defs */
95 +#define MCF_XBS_PRS_MACRO(m,p) ((p)<<((m)<<2))
96 +#define MCF_XBS_PRS_M0(p) MCF_XBS_PRS_MACRO(0, p) /* Coldfire Core */
97 +#define MCF_XBS_PRS_M1(p) MCF_XBS_PRS_MACRO(1, p) /* eDMA */
98 +#define MCF_XBS_PRS_M2(p) MCF_XBS_PRS_MACRO(2, p) /* FEC0 */
99 +#define MCF_XBS_PRS_M3(p) MCF_XBS_PRS_MACRO(3, p) /* FEC1 */
100 +#define MCF_XBS_PRS_M4(p) MCF_XBS_PRS_MACRO(4, p) /* Master 4 */
101 +#define MCF_XBS_PRS_M5(p) MCF_XBS_PRS_MACRO(5, p) /* PCI */
102 +#define MCF_XBS_PRS_M6(p) MCF_XBS_PRS_MACRO(6, p) /* USB OTG */
103 +#define MCF_XBS_PRS_M7(p) MCF_XBS_PRS_MACRO(7, p) /* Serial Boot */
104 +
105 +/* Control Register (CRSn) Defs */
106 +#define MCF_XBS_CRS_RO 0x80000000 /* Read Only */
107 +#define MCF_XBS_CRS_ARB 0x00000100 /* Arbitration Mode */
108 +#define MCF_XBS_CRS_PCTL 0x00000030 /* Parking Control */
109 +#define MCF_XBS_CRS_PARK 0x00000007 /* Park Location */
110 +
111 +/* MCF_XBS_CRS_ARB Defs */
112 +#define MCF_ABS_CRS_ARB_FIXED 0x00000000 /* Fixed priority */
113 +#define MCF_ABS_CRS_ARB_ROUND 0x00000100 /* Round Robin priority */
114 +
115 +/* MCF_XBS_CRS_PCTL Defs */
116 +#define MCF_ABS_CRS_PCTL_PARK 0x00000000 /* Park on the defined PARK */
117 +#define MCF_ABS_CRS_PCTL_LAST 0x00000010 /* Park on the last master */
118 +#define MCF_ABS_CRS_PCTL_NONE 0x00000020 /* Don't park */
119 +
120 +/* MCF_XBS_CRS_PARK Defs */
121 +#define MCF_ABS_CRS_PARK_M0 0x00000000 /* Park on Coldfire Core */
122 +#define MCF_ABS_CRS_PARK_M1 0x00000001 /* Park on eDMA */
123 +#define MCF_ABS_CRS_PARK_M2 0x00000002 /* Park on FEC0 */
124 +#define MCF_ABS_CRS_PARK_M3 0x00000003 /* Park on FEC1 */
125 +#define MCF_ABS_CRS_PARK_M4 0x00000004 /* Park on Reserved */
126 +#define MCF_ABS_CRS_PARK_M5 0x00000005 /* Park on PCI */
127 +#define MCF_ABS_CRS_PARK_M6 0x00000006 /* Park on USB OTG */
128 +#define MCF_ABS_CRS_PARK_M7 0x00000007 /* Park on Serial Boot */
129 +
130 +#endif /* __MCF5445X_XBS_H__ */
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