target/linux/coldfire/patches/044-m547x_8x_initial.patch

   1 From 5b8edb0ea5cafb522e21b2973eaff6298062dd81 Mon Sep 17 00:00:00 2001
   2 From: Kurt Mahan <kmahan@freescale.com>
   3 Date: Thu, 28 Feb 2008 10:56:17 -0700
   4 Subject: [PATCH] Initial M547x/M548x port.
   5
   6 LTIBName: m547x-8x-initial
   7 Signed-off-by: Kurt Mahan <kmahan@freescale.com>
   8 ---
   9  arch/m68k/Kconfig                    |   84 ++++-
  10  arch/m68k/Makefile                   |    4 +
  11  arch/m68k/coldfire/config.c          |  112 +++++-
  12  arch/m68k/coldfire/head.S            |  153 ++++++-
  13  arch/m68k/coldfire/ints.c            |   78 ++++-
  14  arch/m68k/configs/m5485evb_defconfig |  777 ++++++++++++++++++++++++++++++++++
  15  drivers/serial/mcfserial.c           |   45 ++-
  16  include/asm-m68k/cf_pgalloc.h        |    5 +
  17  include/asm-m68k/cfcache.h           |   28 ++-
  18  include/asm-m68k/coldfire.h          |    7 +
  19  include/asm-m68k/m5485gpio.h         |  694 ++++++++++++++++++++++++++++++
  20  include/asm-m68k/m5485gpt.h          |   88 ++++
  21  include/asm-m68k/m5485psc.h          |  474 +++++++++++++++++++++
  22  include/asm-m68k/m5485sim.h          |  219 ++++++++++
  23  include/asm-m68k/mcfsim.h            |    5 +
  24  include/asm-m68k/mcfuart.h           |   14 +
  25  include/asm-m68k/mmu_context.h       |   72 ++++
  26  include/asm-m68k/page_offset.h       |    5 +
  27  18 files changed, 2824 insertions(+), 40 deletions(-)
  28  create mode 100644 arch/m68k/configs/m5485evb_defconfig
  29  create mode 100644 include/asm-m68k/m5485gpio.h
  30  create mode 100644 include/asm-m68k/m5485gpt.h
  31  create mode 100644 include/asm-m68k/m5485psc.h
  32  create mode 100644 include/asm-m68k/m5485sim.h
  33
  34 --- a/arch/m68k/Kconfig
  35 +++ b/arch/m68k/Kconfig
  36 @@ -56,7 +56,7 @@ config ARCH_MAY_HAVE_PC_FDC
  37         default y
  38
  39  config NO_IOPORT
  40 -       def_bool !M54455
  41 +       def_bool !(M54455 || M547X_8X)
  42
  43  config NO_DMA
  44         def_bool SUN3
  45 @@ -319,20 +319,80 @@ config M68060
  46  config M54455
  47         bool "MCF54455 support"
  48         depends on COLDFIRE
  49 -       default y
  50         help
  51            This option will add support for the MCF54455 processor with mmu.
  52
  53 +config M547X_8X
  54 +       bool "MCF547x/MCF548x support"
  55 +       depends on COLDFIRE
  56 +       help
  57 +          This option will add support for the MCF547x/MCF548x processor with mmu.
  58 +
  59 +config M547X
  60 +       bool
  61 +       depends on M547X_8X
  62 +       default n
  63 +
  64 +config M548X
  65 +       bool
  66 +       depends on M547X_8X
  67 +       default n
  68 +
  69 +choice
  70 +       prompt "Model"
  71 +       depends on M547X_8X
  72 +       default M5485CFE
  73 +       config M5475AFE
  74 +               bool "MCF5475AFE"
  75 +               select M547X
  76 +       config M5475BFE
  77 +               bool "MCF5475BFE"
  78 +               select M547X
  79 +       config M5475CFE
  80 +               bool "MCF5475CFE"
  81 +               select M547X
  82 +       config M5475DFE
  83 +               bool "MCF5475DFE"
  84 +               select M547X
  85 +       config M5475EFE
  86 +               bool "MCF5475EFE"
  87 +               select M547X
  88 +       config M5475FFE
  89 +               bool "MCF5475FFE"
  90 +               select M547X
  91 +
  92 +       config M5485AFE
  93 +               bool "MCF5485AFE"
  94 +               select M548X
  95 +       config M5485BFE
  96 +               bool "MCF5485BFE"
  97 +               select M548X
  98 +       config M5485CFE
  99 +               bool "MCF5485CFE"
 100 +               select M548X
 101 +       config M5485DFE
 102 +               bool "MCF5485DFE"
 103 +               select M548X
 104 +       config M5485EFE
 105 +               bool "MCF5485EFE"
 106 +               select M548X
 107 +       config M5485FFE
 108 +               bool "MCF5485FFE"
 109 +               select M548X
 110 +
 111 +endchoice
 112 +
 113  config MCFCLK
 114 -       int "M54455EVB System Clock"
 115 -       depends on M54455
 116 -       default 266666666
 117 +       int
 118 +       default 266666666 if M54455
 119 +       default 266000000 if M547X
 120 +       default 200000000 if M548X
 121         help
 122 -         System clock for EVB.  Usually 266MHz for u-boot and 200MHz for dBUG.
 123 +         Coldfire System clock.
 124
 125  config MCF_USER_HALT
 126         bool "Coldfire User Halt Enable"
 127 -       depends on M54455
 128 +       depends on M54455 || M547X_8X
 129         default n
 130         help
 131           Enables the HALT instruction in User Mode.
 132 @@ -350,13 +410,15 @@ config MMU_CFV4E
 133
 134  config SDRAM_BASE
 135         hex
 136 -       depends on M54455
 137 -       default 0x40000000
 138 +       depends on COLDFIRE
 139 +       default 0x40000000 if M54455
 140 +       default 0x00000000 if M547X_8X
 141
 142  config SDRAM_SIZE
 143         hex
 144 -       depends on M54455
 145 -       default 0x0FFFFFFF
 146 +       depends on COLDFIRE
 147 +       default 0x0FFFFFFF if M54455
 148 +       default 0x04000000 if M547X_8X
 149
 150  config NOR_FLASH_BASE
 151         hex "NOR Flash Base Address"
 152 --- a/arch/m68k/Makefile
 153 +++ b/arch/m68k/Makefile
 154 @@ -63,6 +63,10 @@ ifdef CONFIG_M54455
 155  KBUILD_CFLAGS += -march=isac -mcpu=54455 -msoft-float -g
 156  KBUILD_AFLAGS += -march=isac -mcpu=54455 -msoft-float
 157  endif
 158 +ifdef CONFIG_M547X_8X
 159 +KBUILD_CFLAGS += -mcfv4e -g
 160 +KBUILD_AFLAGS += -mcfv4e
 161 +endif
 162
 163  ifdef CONFIG_KGDB
 164  # If configured for kgdb support, include debugging infos and keep the
 165 --- a/arch/m68k/coldfire/config.c
 166 +++ b/arch/m68k/coldfire/config.c
 167 @@ -1,8 +1,9 @@
 168  /*
 169 - *  linux/arch/m68k/coldifre/config.c
 170 + *  linux/arch/m68k/coldfire/config.c
 171   *
 172 + *  Kurt Mahan kmahan@freescale.com
 173   *  Matt Waddel Matt.Waddel@freescale.com
 174 - *  Copyright Freescale Semiconductor, Inc. 2007
 175 + *  Copyright Freescale Semiconductor, Inc. 2007, 2008
 176   *
 177   *  This program is free software; you can redistribute it and/or modify
 178   *  it under the terms of the GNU General Public License as published by
 179 @@ -32,11 +33,16 @@
 180  #include <asm/movs.h>
 181  #include <asm/page.h>
 182  #include <asm/pgalloc.h>
 183 +
 184 +#include <asm/mcfsim.h>
 185 +
 186 +#if 0
 187  #include <asm/mcf5445x_intc.h>
 188  #include <asm/mcf5445x_sdramc.h>
 189  #include <asm/mcf5445x_fbcs.h>
 190  #include <asm/mcf5445x_dtim.h>
 191  #include <asm/mcf5445x_xbs.h>
 192 +#endif
 193
 194  /* JKM -- testing */
 195  #include <linux/pfn.h>
 196 @@ -85,15 +91,21 @@ int __init uboot_commandline(char *boota
 197  {
 198         int len = 0, cmd_line_len;
 199         static struct uboot_record uboot_info;
 200 +       u32 offset = PAGE_OFFSET_RAW - PHYS_OFFSET;
 201
 202         extern unsigned long uboot_info_stk;
 203
 204 -       /* Add 0x80000000 to get post-remapped kernel memory location */
 205 -       uboot_info.bd_info = (*(u32 *)(uboot_info_stk)) + 0x80000000;
 206 -       uboot_info.initrd_start = (*(u32 *)(uboot_info_stk+4)) + 0x80000000;
 207 -       uboot_info.initrd_end = (*(u32 *)(uboot_info_stk+8)) + 0x80000000;
 208 -       uboot_info.cmd_line_start = (*(u32 *)(uboot_info_stk+12)) + 0x80000000;
 209 -       uboot_info.cmd_line_stop = (*(u32 *)(uboot_info_stk+16)) + 0x80000000;
 210 +       /* validate address */
 211 +       if ((uboot_info_stk < PAGE_OFFSET_RAW) ||
 212 +           (uboot_info_stk >= (PAGE_OFFSET_RAW + CONFIG_SDRAM_SIZE)))
 213 +               return 0;
 214 +
 215 +       /* Add offset to get post-remapped kernel memory location */
 216 +       uboot_info.bd_info = (*(u32 *)(uboot_info_stk)) + offset;
 217 +       uboot_info.initrd_start = (*(u32 *)(uboot_info_stk+4)) + offset;
 218 +       uboot_info.initrd_end = (*(u32 *)(uboot_info_stk+8)) + offset;
 219 +       uboot_info.cmd_line_start = (*(u32 *)(uboot_info_stk+12)) + offset;
 220 +       uboot_info.cmd_line_stop = (*(u32 *)(uboot_info_stk+16)) + offset;
 221
 222         cmd_line_len = uboot_info.cmd_line_stop - uboot_info.cmd_line_start;
 223         if ((cmd_line_len > 0) && (cmd_line_len < CL_SIZE-1))
 224 @@ -106,21 +118,36 @@ int __init uboot_commandline(char *boota
 225  /*
 226   * This routine does things not done in the bootloader.
 227   */
 228 +#if defined(CONFIG_M54455)
 229  #define DEFAULT_COMMAND_LINE "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
 230 +#elif defined(CONFIG_M547X_8X)
 231 +#define DEFAULT_COMMAND_LINE "debug root=/dev/nfs nfsroot=172.27.155.1:/tftpboot/rigo/rootfs/ ip=172.27.155.85:172.27.155.1"
 232 +#endif
 233  asmlinkage void __init cf_early_init(void)
 234  {
 235         struct bi_record *record = (struct bi_record *) &_end;
 236
 237         extern char _end;
 238
 239 +#if defined(CONFIG_M54455)
 240         SET_VBR((void *)MCF_RAMBAR1);
 241 +#elif defined(CONFIG_M547X_8X)
 242 +       SET_VBR((void *)MCF_RAMBAR0);
 243 +#endif
 244
 245         /* Mask all interrupts */
 246 +#if defined(CONFIG_M54455)
 247         MCF_INTC0_IMRL = 0xFFFFFFFF;
 248         MCF_INTC0_IMRH = 0xFFFFFFFF;
 249         MCF_INTC1_IMRL = 0xFFFFFFFF;
 250         MCF_INTC1_IMRH = 0xFFFFFFFF;
 251 +#elif defined(CONFIG_M547X_8X)
 252 +/* JKM -- ?? */
 253 +       MCF_IMRL = 0xFFFFFFFF;
 254 +       MCF_IMRH = 0xFFFFFFFF;
 255 +#endif
 256
 257 +#if defined(CONFIG_M54455)
 258  #if defined(CONFIG_NOR_FLASH_BASE)
 259         MCF_FBCS_CSAR(1) = CONFIG_NOR_FLASH_BASE;
 260  #else
 261 @@ -131,9 +158,10 @@ asmlinkage void __init cf_early_init(voi
 262         /* Init optional SDRAM chip select */
 263         MCF_SDRAMC_SDCS(1) = (256*1024*1024) | 0x1B;
 264  #endif
 265 +#endif /* CONFIG_M54455 */
 266
 267 +#if defined(CONFIG_M54455)
 268         /* Setup SDRAM crossbar(XBS) priorities */
 269 -printk(KERN_INFO "Bumping USB Priority\n");
 270         MCF_XBS_PRS2 = (MCF_XBS_PRS_M0(MCF_XBS_PRI_2) |
 271                         MCF_XBS_PRS_M1(MCF_XBS_PRI_3) |
 272                         MCF_XBS_PRS_M2(MCF_XBS_PRI_4) |
 273 @@ -141,6 +169,7 @@ printk(KERN_INFO "Bumping USB Priority\n
 274                         MCF_XBS_PRS_M5(MCF_XBS_PRI_6) |
 275                         MCF_XBS_PRS_M6(MCF_XBS_PRI_1) |
 276                         MCF_XBS_PRS_M7(MCF_XBS_PRI_7));
 277 +#endif
 278
 279
 280         m68k_machtype = MACH_CFMMU;
 281 @@ -152,6 +181,7 @@ printk(KERN_INFO "Bumping USB Priority\n
 282         m68k_memory[m68k_num_memory].addr = CONFIG_SDRAM_BASE;
 283         m68k_memory[m68k_num_memory++].size = CONFIG_SDRAM_SIZE;
 284
 285 +#if defined(CONFIG_M54455)
 286         if (!uboot_commandline(m68k_command_line)) {
 287  #if defined(CONFIG_BOOTPARAM)
 288                 strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE-1);
 289 @@ -159,6 +189,10 @@ printk(KERN_INFO "Bumping USB Priority\n
 290                 strcpy(m68k_command_line, DEFAULT_COMMAND_LINE);
 291  #endif
 292         }
 293 +#else
 294 +/* JKM -- hack until mappings get resolved */
 295 +       strcpy(m68k_command_line, DEFAULT_COMMAND_LINE);
 296 +#endif
 297
 298
 299  #if defined(CONFIG_BLK_DEV_INITRD)
 300 @@ -185,6 +219,7 @@ printk(KERN_INFO "Bumping USB Priority\n
 301         cacr_set(CACHE_INITIAL_MODE);
 302  }
 303
 304 +#if defined(CONFIG_M54455)
 305  void settimericr(unsigned int timer, unsigned int level)
 306  {
 307         volatile unsigned char *icrp;
 308 @@ -202,6 +237,7 @@ void settimericr(unsigned int timer, uns
 309                 coldfire_enable_irq0(irq);
 310         }
 311  }
 312 +#endif
 313
 314  /* Assembler routines */
 315  asmlinkage void buserr(void);
 316 @@ -214,7 +250,11 @@ void __init coldfire_trap_init(void)
 317         int i = 0;
 318         e_vector *vectors;
 319
 320 +#if defined(CONFIG_M54455)
 321         vectors = (e_vector *)MCF_RAMBAR1;
 322 +#elif defined(CONFIG_M547X_8X)
 323 +       vectors = (e_vector *)MCF_RAMBAR0;
 324 +#endif
 325         /*
 326          * There is a common trap handler and common interrupt
 327          * handler that handle almost every vector. We treat
 328 @@ -235,6 +275,8 @@ void __init coldfire_trap_init(void)
 329         vectors[32] = system_call;
 330  }
 331
 332 +#if defined(CONFIG_M54455)
 333 +
 334  void coldfire_tick(void)
 335  {
 336         /* Reset the ColdFire timer */
 337 @@ -285,13 +327,49 @@ unsigned long coldfire_gettimeoffset(voi
 338         return offset;
 339  }
 340
 341 +#elif defined(CONFIG_M547X_8X)
 342 +
 343 +void coldfire_tick(void)
 344 +{
 345 +       /* Reset the ColdFire timer */
 346 +       MCF_SSR(0) = MCF_SSR_ST;
 347 +}
 348 +
 349 +void __init coldfire_sched_init(irq_handler_t handler)
 350 +{
 351 +       int irq = ISC_SLTn(0);
 352 +
 353 +       MCF_SCR(0) = 0;
 354 +       MCF_ICR(irq) = ILP_SLT0;
 355 +       request_irq(64 + irq, handler, IRQF_DISABLED, "ColdFire Timer 0", NULL);
 356 +       MCF_SLTCNT(0) = MCF_BUSCLK / HZ;
 357 +       MCF_SCR(0) |=  MCF_SCR_TEN | MCF_SCR_IEN | MCF_SCR_RUN;
 358 +}
 359 +
 360 +unsigned long coldfire_gettimeoffset(void)
 361 +{
 362 +       volatile unsigned long trr, tcn, offset;
 363 +       trr = MCF_SLTCNT(0);
 364 +       tcn = MCF_SCNT(0);
 365 +
 366 +       offset = (trr - tcn) * ((1000000 >> 3) / HZ) / (trr >> 3);
 367 +       if (MCF_SSR(0) & MCF_SSR_ST)
 368 +               offset += 1000000 / HZ;
 369 +
 370 +       return offset;
 371 +}
 372 +
 373 +#endif
 374 +
 375  void coldfire_reboot(void)
 376  {
 377 +#if defined(CONFIG_M54455)
 378         /* disable interrupts and do a software reset */
 379         asm("movew #0x2700, %%sr\n\t"
 380             "moveb #0x80, %%d0\n\t"
 381             "moveb %%d0, 0xfc0a0000\n\t"
 382             : : : "%d0");
 383 +#endif
 384  }
 385
 386  /* int coldfire_hwclk(int i, struct rtc_time *t)
 387 @@ -305,6 +383,7 @@ static void coldfire_get_model(char *mod
 388         sprintf(model, "Version 4 ColdFire");
 389  }
 390
 391 +/* JKM -- Why do we need these? */
 392  void coldfire_enable_irq(unsigned int vec)
 393  {
 394         unsigned long flags;
 395 @@ -318,13 +397,21 @@ void coldfire_enable_irq(unsigned int ve
 396
 397         local_irq_save(flags);
 398         irq_enable[vec]++;
 399 +#if defined(CONFIG_M54455)
 400         if (vec < 32)
 401                 MCF_INTC0_IMRL &= ~(1 << vec);
 402         else
 403                 MCF_INTC0_IMRH &= ~(1 << (vec - 32));
 404 +#elif defined(CONFIG_M547X_8X)
 405 +       if (vec < 32)
 406 +               MCF_IMRL &= ~(1 << vec);
 407 +       else
 408 +               MCF_IMRH &= ~(1 << (vec - 32));
 409 +#endif
 410         local_irq_restore(flags);
 411  }
 412
 413 +/* JKM -- Why do we need these? */
 414  void coldfire_disable_irq(unsigned int vec)
 415  {
 416         unsigned long flags;
 417 @@ -338,10 +425,17 @@ void coldfire_disable_irq(unsigned int v
 418
 419         local_irq_save(flags);
 420         if (--irq_enable[vec] == 0) {
 421 +#if defined(CONFIG_M54455)
 422                 if (vec < 32)
 423                         MCF_INTC0_IMRL |= (1 << vec);
 424                 else
 425                         MCF_INTC0_IMRH |= (1 << (vec - 32));
 426 +#elif defined(CONFIG_M547X_8X)
 427 +               if (vec < 32)
 428 +                       MCF_IMRL |= (1 << vec);
 429 +               else
 430 +                       MCF_IMRH |= (1 << (vec - 32));
 431 +#endif
 432
 433         }
 434         local_irq_restore(flags);
 435 --- a/arch/m68k/coldfire/head.S
 436 +++ b/arch/m68k/coldfire/head.S
 437 @@ -2,9 +2,9 @@
 438   *  head.S is the MMU enabled ColdFire specific initial boot code
 439   *
 440   *  Ported to ColdFire by
 441 - *  Matt Waddel Matt.Waddel@freescale.com
 442 - *  Kurt Mahan kmahan@freescale.com
 443 - *  Copyright Freescale Semiconductor, Inc. 2007
 444 + *    Matt Waddel Matt.Waddel@freescale.com
 445 + *    Kurt Mahan kmahan@freescale.com
 446 + *  Copyright Freescale Semiconductor, Inc. 2007, 2008
 447   *
 448   *  This program is free software; you can redistribute it and/or modify
 449   *  it under the terms of the GNU General Public License as published by
 450 @@ -52,6 +52,7 @@
 451  #define __FINIT                .previous
 452  #endif
 453
 454 +/* JKM -- REVISE DOCS FOR RIGO */
 455  /*
 456   * Setup ACR mappings to provide the following memory map:
 457   *   Data
 458 @@ -61,13 +62,20 @@
 459   *     None currently (mapped via TLBs)
 460   */
 461
 462 +#if defined(CONFIG_M54455)
 463  #define ACR0_DEFAULT   #0xA00FA048   /* ACR0 default value */
 464  #define ACR1_DEFAULT   #0xF00FA040   /* ACR1 default value */
 465  #define ACR2_DEFAULT   #0x00000000   /* ACR2 default value */
 466  #define ACR3_DEFAULT   #0x00000000   /* ACR3 default value */
 467 -
 468  /* ACR mapping for FPGA (maps 0) */
 469  #define ACR0_FPGA      #0x000FA048   /* ACR0 enable FPGA */
 470 +#elif defined(CONFIG_M547X_8X)
 471 +#define ACR0_DEFAULT   #0xE000C040   /* ACR0 default value */
 472 +#define ACR1_DEFAULT   #0x00000000   /* ACR1 default value */
 473 +#define ACR2_DEFAULT   #0x00000000   /* ACR2 default value */
 474 +#define ACR3_DEFAULT   #0x00000000   /* ACR3 default value */
 475 +#endif
 476 +
 477
 478  /* Several macros to make the writing of subroutines easier:
 479   * - func_start marks the beginning of the routine which setups the frame
 480 @@ -227,7 +235,7 @@ ENTRY(_stext)
 481
 482         .long   BOOTINFOV_MAGIC
 483         .long   0
 484 -1:     jmp     __start-0x80000000
 485 +1:     jmp     __start-(0xc0000000-CONFIG_SDRAM_BASE)
 486
 487  .equ   kernel_pg_dir,_stext
 488  .equ   .,_stext+0x1000
 489 @@ -237,19 +245,40 @@ ENTRY(_start)
 490  __INIT
 491  ENTRY(__start)
 492
 493 +/* JKM -- make sure Rigo handles UBOOT */
 494  /* Save the location of u-boot info - cmd line, bd_info, etc. */
 495         movel   %a7,%a4         /* Don't use %a4 before cf_early_init */
 496 +/* JKM -- fix to use CONFIG_SDRAM_BASE) */
 497 +#if defined(CONFIG_M54455)
 498         addl    #0x80000004,%a4 /* 0x80000004= 1 stack push + high mem offset */
 499 +#elif defined(CONFIG_M547X_8X)
 500 +       addl    #0xc0000004,%a4 /* 0x80000004= 1 stack push + high mem offset */
 501 +#endif
 502
 503 +/* JKM -- fix this to work off of CONFIG_SDRAM_BASE */
 504  /* Setup initial stack pointer */
 505 +#if defined(CONFIG_M54455)
 506         movel   #0x40001000,%sp
 507 +#elif defined(CONFIG_M547X_8X)
 508 +       movel   #0x00001000,%sp
 509 +#endif
 510
 511  /* Setup usp */
 512         subl    %a0,%a0
 513         movel   %a0,%usp
 514
 515 +#if defined(CONFIG_M54455)
 516         movel  #(MCF_RAMBAR1 + 0x221), %d0
 517         movec   %d0, %rambar1
 518 +#elif defined(CONFIG_M547X_8X)
 519 +       movel   #MCF_MBAR, %d0
 520 +       movec   %d0, %mbar
 521 +       move.l  #(MCF_RAMBAR0 + 0x21), %d0
 522 +       movec   %d0, %rambar0
 523 +       move.l  #(MCF_RAMBAR1 + 0x21), %d0
 524 +       movec   %d0, %rambar1
 525 +#endif
 526 +
 527         movew   #0x2700,%sr
 528
 529  /* reset cache */
 530 @@ -278,6 +307,7 @@ ENTRY(__start)
 531         /* If you change the memory size to another value make a matching
 532            change in paging_init(cf-mmu.c) to zones_size[]. */
 533
 534 +#if defined(CONFIG_M54455)
 535         /* Map 256MB as code */
 536         mmu_map (PAGE_OFFSET+0*0x1000000),  (PHYS_OFFSET+0*0x1000000), \
 537                 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_IC,  MMUDR_SP, \
 538 @@ -383,16 +413,104 @@ ENTRY(__start)
 539                 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
 540                 0, MMUDR_LK, %d0
 541
 542 -       /* Do unity mapping to enable the MMU.  Map first 16 MB in place as
 543 -          code (delete TLBs after MMU is enabled and we are executing in high
 544 -          memory). */
 545 +#elif defined(CONFIG_M547X_8X)
 546 +
 547 +       /* Map first 8 MB as code */
 548 +       mmu_map (PAGE_OFFSET+0*1024*1024),  (0*1024*1024), MMUOR_ITLB, 0, \
 549 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_IC,  MMUDR_SP, 0, 0, MMUDR_X, \
 550 +               MMUDR_LK, %d0
 551 +       mmu_map (PAGE_OFFSET+1*1024*1024),  (1*1024*1024), MMUOR_ITLB, 0, \
 552 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_IC,  MMUDR_SP, 0, 0, MMUDR_X, \
 553 +               MMUDR_LK, %d0
 554 +       mmu_map (PAGE_OFFSET+2*1024*1024),  (2*1024*1024), MMUOR_ITLB, 0, \
 555 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_IC,  MMUDR_SP, 0, 0, MMUDR_X, \
 556 +               MMUDR_LK, %d0
 557 +       mmu_map (PAGE_OFFSET+3*1024*1024),  (3*1024*1024), MMUOR_ITLB, 0, \
 558 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_IC,  MMUDR_SP, 0, 0, MMUDR_X, \
 559 +               MMUDR_LK, %d0
 560 +       mmu_map (PAGE_OFFSET+4*1024*1024),  (4*1024*1024), MMUOR_ITLB, 0, \
 561 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_IC,  MMUDR_SP, 0, 0, MMUDR_X, \
 562 +               MMUDR_LK, %d0
 563 +       mmu_map (PAGE_OFFSET+5*1024*1024),  (5*1024*1024), MMUOR_ITLB, 0, \
 564 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_IC,  MMUDR_SP, 0, 0, MMUDR_X, \
 565 +               MMUDR_LK, %d0
 566 +       mmu_map (PAGE_OFFSET+6*1024*1024),  (6*1024*1024), MMUOR_ITLB, 0, \
 567 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_IC,  MMUDR_SP, 0, 0, MMUDR_X, \
 568 +               MMUDR_LK, %d0
 569 +       mmu_map (PAGE_OFFSET+7*1024*1024),  (7*1024*1024), MMUOR_ITLB, 0, \
 570 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_IC,  MMUDR_SP, 0, 0, MMUDR_X, \
 571 +               MMUDR_LK, %d0
 572 +
 573 +       /* Map first 8 MB as data */
 574 +       mmu_map (PAGE_OFFSET+0*1024*1024),  (0*1024*1024), 0, 0, \
 575 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
 576 +               MMUDR_W, 0, MMUDR_LK, %d0
 577 +       mmu_map (PAGE_OFFSET+1*1024*1024),  (1*1024*1024), 0, 0, \
 578 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
 579 +               MMUDR_W, 0, MMUDR_LK, %d0
 580 +       mmu_map (PAGE_OFFSET+2*1024*1024),  (2*1024*1024), 0, 0, \
 581 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
 582 +               MMUDR_W, 0, MMUDR_LK, %d0
 583 +       mmu_map (PAGE_OFFSET+3*1024*1024),  (3*1024*1024), 0, 0, \
 584 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
 585 +               MMUDR_W, 0, MMUDR_LK, %d0
 586 +       mmu_map (PAGE_OFFSET+4*1024*1024),  (4*1024*1024), 0, 0, \
 587 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
 588 +               MMUDR_W, 0, MMUDR_LK, %d0
 589 +       mmu_map (PAGE_OFFSET+5*1024*1024),  (5*1024*1024), 0, 0, \
 590 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
 591 +               MMUDR_W, 0, MMUDR_LK, %d0
 592 +       mmu_map (PAGE_OFFSET+6*1024*1024),  (6*1024*1024), 0, 0, \
 593 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
 594 +               MMUDR_W, 0, MMUDR_LK, %d0
 595 +       mmu_map (PAGE_OFFSET+7*1024*1024),  (7*1024*1024), 0, 0, \
 596 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, \
 597 +               MMUDR_W, 0, MMUDR_LK, %d0
 598 +#endif
 599 +       /*
 600 +        * Do unity mapping to enable the MMU.  Map first chunk of memory
 601 +        * in place as code/data.  The TLBs will be deleted after the MMU is
 602 +        * enabled and we are executing in high memory.
 603 +        */
 604 +
 605 +#if defined(CONFIG_M54455)
 606 +       /* Map first 16 MB as code */
 607         mmu_map (PHYS_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), \
 608                 MMUOR_ITLB, 0, MMUTR_SG, MMUDR_SZ16M, MMUDR_INC,  MMUDR_SP, 0, \
 609                 0, MMUDR_X, 0, %d0
 610 -       /* Map first 16 MB as data too.  */
 611 +       /* Map first 16 MB as data too  */
 612         mmu_map (PHYS_OFFSET+0*0x1000000), (PHYS_OFFSET+0*0x1000000), 0, 0, \
 613                 MMUTR_SG, MMUDR_SZ16M, MMUDR_DNCP, MMUDR_SP, MMUDR_R, MMUDR_W, \
 614                 0, 0, %d0
 615 +#elif defined(CONFIG_M547X_8X)
 616 +       /* Map first 4 MB as code */
 617 +       mmu_map (0*1024*1024), (0*1024*1024), MMUOR_ITLB, 0, \
 618 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_IC,  MMUDR_SP, 0, 0, \
 619 +               MMUDR_X, 0, %d0
 620 +       mmu_map (1*1024*1024), (1*1024*1024), MMUOR_ITLB, 0, \
 621 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_IC,  MMUDR_SP, 0, 0, \
 622 +               MMUDR_X, 0, %d0
 623 +       mmu_map (2*1024*1024), (2*1024*1024), MMUOR_ITLB, 0, \
 624 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_IC,  MMUDR_SP, 0, 0, \
 625 +               MMUDR_X, 0, %d0
 626 +       mmu_map (3*1024*1024), (3*1024*1024), MMUOR_ITLB, 0, \
 627 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_IC,  MMUDR_SP, 0, 0, \
 628 +               MMUDR_X, 0, %d0
 629 +
 630 +       /* Map first 4 MB as data too */
 631 +       mmu_map (0*1024*1024), (0*1024*1024), 0, 0, \
 632 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
 633 +               MMUDR_W, 0, 0, %d0
 634 +       mmu_map (1*1024*1024), (1*1024*1024), 0, 0, \
 635 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
 636 +               MMUDR_W, 0, 0, %d0
 637 +       mmu_map (2*1024*1024), (2*1024*1024), 0, 0, \
 638 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
 639 +               MMUDR_W, 0, 0, %d0
 640 +       mmu_map (3*1024*1024), (3*1024*1024), 0, 0, \
 641 +               MMUTR_SG, MMUDR_SZ1M, MMUDR_DCB, MMUDR_SP, MMUDR_R, \
 642 +               MMUDR_W, 0, 0, %d0
 643 +#endif
 644
 645         /* Turn on MMU */
 646         movel   #(MMUCR_EN),%a0
 647 @@ -412,9 +530,20 @@ ENTRY(__running_high)
 648         addl    #PAGE_OFFSET,%a1
 649         movel   %a1,%a0@
 650
 651 -       /* Unmap first 16 MB, code and data.  */
 652 +       /* Unmap unity mappings */
 653 +#if defined(CONFIG_M54455)
 654         mmu_unmap (PHYS_OFFSET+0*0x1000000), MMUOR_ITLB, %d0
 655         mmu_unmap (PHYS_OFFSET+0*0x1000000), 0, %d0
 656 +#elif defined(CONFIG_M547X_8X)
 657 +       mmu_unmap (PHYS_OFFSET+0*0x1000000), MMUOR_ITLB, %d0
 658 +       mmu_unmap (PHYS_OFFSET+1*0x1000000), MMUOR_ITLB, %d0
 659 +       mmu_unmap (PHYS_OFFSET+2*0x1000000), MMUOR_ITLB, %d0
 660 +       mmu_unmap (PHYS_OFFSET+3*0x1000000), MMUOR_ITLB, %d0
 661 +       mmu_unmap (PHYS_OFFSET+0*0x1000000), 0, %d0
 662 +       mmu_unmap (PHYS_OFFSET+1*0x1000000), 0, %d0
 663 +       mmu_unmap (PHYS_OFFSET+2*0x1000000), 0, %d0
 664 +       mmu_unmap (PHYS_OFFSET+3*0x1000000), 0, %d0
 665 +#endif
 666
 667  /* Setup initial stack pointer */
 668         lea     init_task,%a2
 669 @@ -438,8 +567,9 @@ func_start  set_context,%d0,(1*4)
 670         movec   %d0,%asid
 671  func_return    set_context
 672
 673 +#ifdef CONFIG_M54455
 674  /*
 675 - * set_fpga(addr,val)
 676 + * set_fpga(addr,val) on the M54455EVB
 677   *
 678   * Map in 0x00000000 -> 0x0fffffff and then do the write.
 679   */
 680 @@ -456,6 +586,7 @@ set_fpga:
 681         nop
 682         movew   %d1,%sr
 683         rts
 684 +#endif
 685
 686         .data
 687         .align  4
 688 --- a/arch/m68k/coldfire/ints.c
 689 +++ b/arch/m68k/coldfire/ints.c
 690 @@ -5,9 +5,10 @@
 691   * Copyright (C) 1998  D. Jeff Dionne <jeff@lineo.ca>,
 692   *                     Kenneth Albanowski <kjahds@kjahds.com>,
 693   * Copyright (C) 2000  Lineo Inc. (www.lineo.com)
 694 - * Matt Waddel Matt.Waddel@freescale.com
 695 - * Copyright Freescale Semiconductor, Inc. 2007
 696 - * Kurt Mahan kmahan@freescale.com
 697 + *
 698 + * Copyright Freescale Semiconductor, Inc. 2007, 2008
 699 + *     Kurt Mahan kmahan@freescale.com
 700 + *     Matt Waddel Matt.Waddel@freescale.com
 701   *
 702   * Based on:
 703   * linux/arch/m68k/kernel/ints.c &
 704 @@ -46,7 +47,7 @@ static int irq_depth[SYS_IRQS];
 705  /*
 706   * IRQ Controller
 707   */
 708 -#ifdef CONFIG_M54455
 709 +#if defined(CONFIG_M54455)
 710  void m5445x_irq_enable(unsigned int irq);
 711  void m5445x_irq_disable(unsigned int irq);
 712  static struct irq_controller m5445x_irq_controller = {
 713 @@ -55,6 +56,17 @@ static struct irq_controller m5445x_irq_
 714         .enable         = m5445x_irq_enable,
 715         .disable        = m5445x_irq_disable,
 716  };
 717 +#elif defined(CONFIG_M547X_8X)
 718 +void m547x_8x_irq_enable(unsigned int irq);
 719 +void m547x_8x_irq_disable(unsigned int irq);
 720 +static struct irq_controller m547x_8x_irq_controller = {
 721 +       .name           = "M547X_8X",
 722 +       .lock           = SPIN_LOCK_UNLOCKED,
 723 +       .enable         = m547x_8x_irq_enable,
 724 +       .disable        = m547x_8x_irq_disable,
 725 +};
 726 +#else
 727 +# error No IRQ controller defined
 728  #endif
 729
 730  #define        POOL_SIZE       SYS_IRQS
 731 @@ -75,9 +87,12 @@ void __init init_IRQ(void)
 732  {
 733         int i;
 734
 735 -#ifdef CONFIG_M54455
 736 +#if defined(CONFIG_M54455)
 737         for (i = 0; i < SYS_IRQS; i++)
 738                 irq_controller[i] = &m5445x_irq_controller;
 739 +#elif defined(CONFIG_M547X_8X)
 740 +       for (i = 0; i < SYS_IRQS; i++)
 741 +               irq_controller[i] = &m547x_8x_irq_controller;
 742  #endif
 743  }
 744
 745 @@ -381,4 +396,57 @@ void m5445x_irq_disable(unsigned int irq
 746                 MCF_INTC1_SIMR = irq;
 747         }
 748  }
 749 +#elif defined(CONFIG_M547X_8X)
 750 +/*
 751 + * M547X_8X Implementation
 752 + */
 753 +void m547x_8x_irq_enable(unsigned int irq)
 754 +{
 755 +       /* enable the interrupt hardware */
 756 +       if (irq < 64)
 757 +               return;
 758 +
 759 +       /* adjust past non-hardware ints */
 760 +       irq -= 64;
 761 +
 762 +/* JKM -- re-add EPORT later */
 763 +#if 0
 764 +       /* check for eport */
 765 +       if ((irq > 0) && (irq < 8)) {
 766 +               /* enable eport */
 767 +               MCF_EPORT_EPPAR &= ~(3 << (irq*2));     /* level */
 768 +               MCF_EPORT_EPDDR &= ~(1 << irq);         /* input */
 769 +               MCF_EPORT_EPIER |= 1 << irq;            /* irq enabled */
 770 +       }
 771 +#endif
 772 +
 773 +       if (irq < 32)
 774 +               MCF_IMRL &= ~(1 << irq);
 775 +       else
 776 +               MCF_IMRH &= ~(1 << (irq - 32));
 777 +}
 778 +
 779 +void m547x_8x_irq_disable(unsigned int irq)
 780 +{
 781 +       /* disable the interrupt hardware */
 782 +       if (irq < 64)
 783 +               return;
 784 +
 785 +       /* adjust past non-hardware ints */
 786 +       irq -= 64;
 787 +
 788 +/* JKM -- re-add EPORT later */
 789 +#if 0
 790 +       /* check for eport */
 791 +       if ((irq > 0) && (irq < 8)) {
 792 +               /* disable eport */
 793 +               MCF_EPORT_EPIER &= ~(1 << irq);
 794 +       }
 795 +#endif
 796 +
 797 +       if (irq < 32)
 798 +               MCF_IMRL |= (1 << irq);
 799 +       else
 800 +               MCF_IMRH |= (1 << (irq - 32));
 801 +}
 802  #endif
 803 --- /dev/null
 804 +++ b/arch/m68k/configs/m5485evb_defconfig
 805 @@ -0,0 +1,777 @@
 806 +#
 807 +# Automatically generated make config: don't edit
 808 +# Linux kernel version: 2.6.24
 809 +# Thu Feb 21 00:19:01 2008
 810 +#
 811 +CONFIG_M68K=y
 812 +CONFIG_MMU=y
 813 +# CONFIG_GENERIC_TIME is not set
 814 +# CONFIG_GENERIC_CLOCKEVENTS is not set
 815 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
 816 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
 817 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
 818 +CONFIG_GENERIC_HWEIGHT=y
 819 +CONFIG_GENERIC_CALIBRATE_DELAY=y
 820 +CONFIG_TIME_LOW_RES=y
 821 +CONFIG_GENERIC_IOMAP=y
 822 +# CONFIG_NO_IOPORT is not set
 823 +# CONFIG_NO_DMA is not set
 824 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 825 +
 826 +#
 827 +# General setup
 828 +#
 829 +CONFIG_EXPERIMENTAL=y
 830 +CONFIG_BROKEN_ON_SMP=y
 831 +CONFIG_INIT_ENV_ARG_LIMIT=32
 832 +CONFIG_LOCALVERSION=""
 833 +CONFIG_LOCALVERSION_AUTO=y
 834 +CONFIG_SWAP=y
 835 +CONFIG_SYSVIPC=y
 836 +CONFIG_SYSVIPC_SYSCTL=y
 837 +# CONFIG_POSIX_MQUEUE is not set
 838 +# CONFIG_BSD_PROCESS_ACCT is not set
 839 +# CONFIG_TASKSTATS is not set
 840 +# CONFIG_USER_NS is not set
 841 +# CONFIG_PID_NS is not set
 842 +# CONFIG_AUDIT is not set
 843 +CONFIG_IKCONFIG=y
 844 +CONFIG_IKCONFIG_PROC=y
 845 +CONFIG_LOG_BUF_SHIFT=17
 846 +# CONFIG_CGROUPS is not set
 847 +CONFIG_FAIR_GROUP_SCHED=y
 848 +CONFIG_FAIR_USER_SCHED=y
 849 +# CONFIG_FAIR_CGROUP_SCHED is not set
 850 +CONFIG_SYSFS_DEPRECATED=y
 851 +# CONFIG_RELAY is not set
 852 +# CONFIG_BLK_DEV_INITRD is not set
 853 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 854 +CONFIG_SYSCTL=y
 855 +# CONFIG_EMBEDDED is not set
 856 +CONFIG_UID16=y
 857 +CONFIG_SYSCTL_SYSCALL=y
 858 +CONFIG_KALLSYMS=y
 859 +# CONFIG_KALLSYMS_ALL is not set
 860 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
 861 +CONFIG_HOTPLUG=y
 862 +CONFIG_PRINTK=y
 863 +CONFIG_BUG=y
 864 +CONFIG_ELF_CORE=y
 865 +CONFIG_BASE_FULL=y
 866 +CONFIG_FUTEX=y
 867 +CONFIG_ANON_INODES=y
 868 +CONFIG_EPOLL=y
 869 +CONFIG_SIGNALFD=y
 870 +CONFIG_EVENTFD=y
 871 +CONFIG_SHMEM=y
 872 +CONFIG_VM_EVENT_COUNTERS=y
 873 +CONFIG_SLAB=y
 874 +# CONFIG_SLUB is not set
 875 +# CONFIG_SLOB is not set
 876 +CONFIG_SLABINFO=y
 877 +CONFIG_RT_MUTEXES=y
 878 +# CONFIG_TINY_SHMEM is not set
 879 +CONFIG_BASE_SMALL=0
 880 +CONFIG_MODULES=y
 881 +CONFIG_MODULE_UNLOAD=y
 882 +CONFIG_MODULE_FORCE_UNLOAD=y
 883 +# CONFIG_MODVERSIONS is not set
 884 +# CONFIG_MODULE_SRCVERSION_ALL is not set
 885 +# CONFIG_KMOD is not set
 886 +CONFIG_BLOCK=y
 887 +CONFIG_LBD=y
 888 +# CONFIG_BLK_DEV_IO_TRACE is not set
 889 +# CONFIG_LSF is not set
 890 +# CONFIG_BLK_DEV_BSG is not set
 891 +
 892 +#
 893 +# IO Schedulers
 894 +#
 895 +CONFIG_IOSCHED_NOOP=y
 896 +CONFIG_IOSCHED_AS=y
 897 +CONFIG_IOSCHED_DEADLINE=y
 898 +CONFIG_IOSCHED_CFQ=y
 899 +# CONFIG_DEFAULT_AS is not set
 900 +# CONFIG_DEFAULT_DEADLINE is not set
 901 +CONFIG_DEFAULT_CFQ=y
 902 +# CONFIG_DEFAULT_NOOP is not set
 903 +CONFIG_DEFAULT_IOSCHED="cfq"
 904 +
 905 +#
 906 +# Platform dependent setup
 907 +#
 908 +# CONFIG_SUN3 is not set
 909 +CONFIG_COLDFIRE=y
 910 +CONFIG_CFV4E=y
 911 +# CONFIG_AMIGA is not set
 912 +# CONFIG_ATARI is not set
 913 +# CONFIG_MAC is not set
 914 +# CONFIG_APOLLO is not set
 915 +# CONFIG_VME is not set
 916 +# CONFIG_HP300 is not set
 917 +# CONFIG_SUN3X is not set
 918 +# CONFIG_Q40 is not set
 919 +
 920 +#
 921 +# Processor type
 922 +#
 923 +# CONFIG_M68020 is not set
 924 +# CONFIG_M68030 is not set
 925 +# CONFIG_M68040 is not set
 926 +# CONFIG_M68060 is not set
 927 +# CONFIG_M54455 is not set
 928 +CONFIG_M547X_8X=y
 929 +# CONFIG_M547X is not set
 930 +CONFIG_M548X=y
 931 +# CONFIG_M5475AFE is not set
 932 +# CONFIG_M5475BFE is not set
 933 +# CONFIG_M5475CFE is not set
 934 +# CONFIG_M5475DFE is not set
 935 +# CONFIG_M5475EFE is not set
 936 +# CONFIG_M5475FFE is not set
 937 +# CONFIG_M5485AFE is not set
 938 +# CONFIG_M5485BFE is not set
 939 +CONFIG_M5485CFE=y
 940 +# CONFIG_M5485DFE is not set
 941 +# CONFIG_M5485EFE is not set
 942 +# CONFIG_M5485FFE is not set
 943 +CONFIG_MCFCLK=50000000
 944 +# CONFIG_MCF_USER_HALT is not set
 945 +CONFIG_MMU_CFV4E=y
 946 +CONFIG_SDRAM_BASE=0x00000000
 947 +CONFIG_SDRAM_SIZE=0x04000000
 948 +# CONFIG_M68KFPU_EMU is not set
 949 +CONFIG_ADVANCED=y
 950 +# CONFIG_RMW_INSNS is not set
 951 +CONFIG_SINGLE_MEMORY_CHUNK=y
 952 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 953 +CONFIG_SELECT_MEMORY_MODEL=y
 954 +CONFIG_FLATMEM_MANUAL=y
 955 +# CONFIG_DISCONTIGMEM_MANUAL is not set
 956 +# CONFIG_SPARSEMEM_MANUAL is not set
 957 +CONFIG_FLATMEM=y
 958 +CONFIG_FLAT_NODE_MEM_MAP=y
 959 +CONFIG_NEED_MULTIPLE_NODES=y
 960 +# CONFIG_SPARSEMEM_STATIC is not set
 961 +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 962 +CONFIG_SPLIT_PTLOCK_CPUS=4
 963 +# CONFIG_RESOURCES_64BIT is not set
 964 +CONFIG_ZONE_DMA_FLAG=1
 965 +CONFIG_BOUNCE=y
 966 +CONFIG_VIRT_TO_BUS=y
 967 +
 968 +#
 969 +# General setup
 970 +#
 971 +CONFIG_BINFMT_ELF=y
 972 +# CONFIG_BINFMT_AOUT is not set
 973 +# CONFIG_BINFMT_MISC is not set
 974 +CONFIG_PROC_HARDWARE=y
 975 +CONFIG_ZONE_DMA=y
 976 +# CONFIG_ARCH_SUPPORTS_MSI is not set
 977 +
 978 +#
 979 +# Power management options
 980 +#
 981 +# CONFIG_PM is not set
 982 +
 983 +#
 984 +# Networking
 985 +#
 986 +CONFIG_NET=y
 987 +
 988 +#
 989 +# Networking options
 990 +#
 991 +CONFIG_PACKET=y
 992 +# CONFIG_PACKET_MMAP is not set
 993 +CONFIG_UNIX=y
 994 +CONFIG_XFRM=y
 995 +# CONFIG_XFRM_USER is not set
 996 +# CONFIG_XFRM_SUB_POLICY is not set
 997 +# CONFIG_XFRM_MIGRATE is not set
 998 +CONFIG_NET_KEY=y
 999 +# CONFIG_NET_KEY_MIGRATE is not set
1000 +CONFIG_INET=y
1001 +# CONFIG_IP_MULTICAST is not set
1002 +CONFIG_IP_ADVANCED_ROUTER=y
1003 +CONFIG_ASK_IP_FIB_HASH=y
1004 +# CONFIG_IP_FIB_TRIE is not set
1005 +CONFIG_IP_FIB_HASH=y
1006 +# CONFIG_IP_MULTIPLE_TABLES is not set
1007 +# CONFIG_IP_ROUTE_MULTIPATH is not set
1008 +# CONFIG_IP_ROUTE_VERBOSE is not set
1009 +CONFIG_IP_PNP=y
1010 +# CONFIG_IP_PNP_DHCP is not set
1011 +# CONFIG_IP_PNP_BOOTP is not set
1012 +# CONFIG_IP_PNP_RARP is not set
1013 +# CONFIG_NET_IPIP is not set
1014 +# CONFIG_NET_IPGRE is not set
1015 +# CONFIG_ARPD is not set
1016 +# CONFIG_SYN_COOKIES is not set
1017 +CONFIG_INET_AH=y
1018 +CONFIG_INET_ESP=y
1019 +# CONFIG_INET_IPCOMP is not set
1020 +# CONFIG_INET_XFRM_TUNNEL is not set
1021 +# CONFIG_INET_TUNNEL is not set
1022 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
1023 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
1024 +# CONFIG_INET_XFRM_MODE_BEET is not set
1025 +# CONFIG_INET_LRO is not set
1026 +CONFIG_INET_DIAG=y
1027 +CONFIG_INET_TCP_DIAG=y
1028 +# CONFIG_TCP_CONG_ADVANCED is not set
1029 +CONFIG_TCP_CONG_CUBIC=y
1030 +CONFIG_DEFAULT_TCP_CONG="cubic"
1031 +# CONFIG_TCP_MD5SIG is not set
1032 +# CONFIG_IPV6 is not set
1033 +# CONFIG_INET6_XFRM_TUNNEL is not set
1034 +# CONFIG_INET6_TUNNEL is not set
1035 +# CONFIG_NETWORK_SECMARK is not set
1036 +# CONFIG_NETFILTER is not set
1037 +# CONFIG_IP_DCCP is not set
1038 +# CONFIG_IP_SCTP is not set
1039 +# CONFIG_TIPC is not set
1040 +# CONFIG_ATM is not set
1041 +# CONFIG_BRIDGE is not set
1042 +# CONFIG_VLAN_8021Q is not set
1043 +# CONFIG_DECNET is not set
1044 +# CONFIG_LLC2 is not set
1045 +# CONFIG_IPX is not set
1046 +# CONFIG_ATALK is not set
1047 +# CONFIG_X25 is not set
1048 +# CONFIG_LAPB is not set
1049 +# CONFIG_ECONET is not set
1050 +# CONFIG_WAN_ROUTER is not set
1051 +# CONFIG_NET_SCHED is not set
1052 +
1053 +#
1054 +# Network testing
1055 +#
1056 +# CONFIG_NET_PKTGEN is not set
1057 +# CONFIG_HAMRADIO is not set
1058 +# CONFIG_IRDA is not set
1059 +# CONFIG_BT is not set
1060 +# CONFIG_AF_RXRPC is not set
1061 +
1062 +#
1063 +# Wireless
1064 +#
1065 +# CONFIG_CFG80211 is not set
1066 +# CONFIG_WIRELESS_EXT is not set
1067 +# CONFIG_MAC80211 is not set
1068 +# CONFIG_IEEE80211 is not set
1069 +# CONFIG_RFKILL is not set
1070 +# CONFIG_NET_9P is not set
1071 +
1072 +#
1073 +# Device Drivers
1074 +#
1075 +
1076 +#
1077 +# Generic Driver Options
1078 +#
1079 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
1080 +# CONFIG_STANDALONE is not set
1081 +CONFIG_PREVENT_FIRMWARE_BUILD=y
1082 +CONFIG_FW_LOADER=y
1083 +# CONFIG_DEBUG_DRIVER is not set
1084 +# CONFIG_DEBUG_DEVRES is not set
1085 +# CONFIG_SYS_HYPERVISOR is not set
1086 +# CONFIG_CONNECTOR is not set
1087 +# CONFIG_MTD is not set
1088 +# CONFIG_PARPORT is not set
1089 +CONFIG_BLK_DEV=y
1090 +# CONFIG_BLK_DEV_COW_COMMON is not set
1091 +CONFIG_BLK_DEV_LOOP=y
1092 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
1093 +# CONFIG_BLK_DEV_NBD is not set
1094 +CONFIG_BLK_DEV_RAM=y
1095 +CONFIG_BLK_DEV_RAM_COUNT=16
1096 +CONFIG_BLK_DEV_RAM_SIZE=64000
1097 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
1098 +# CONFIG_CDROM_PKTCDVD is not set
1099 +# CONFIG_ATA_OVER_ETH is not set
1100 +CONFIG_MISC_DEVICES=y
1101 +# CONFIG_EEPROM_93CX6 is not set
1102 +# CONFIG_IDE is not set
1103 +
1104 +#
1105 +# SCSI device support
1106 +#
1107 +# CONFIG_RAID_ATTRS is not set
1108 +CONFIG_SCSI=y
1109 +CONFIG_SCSI_DMA=y
1110 +# CONFIG_SCSI_TGT is not set
1111 +# CONFIG_SCSI_NETLINK is not set
1112 +CONFIG_SCSI_PROC_FS=y
1113 +
1114 +#
1115 +# SCSI support type (disk, tape, CD-ROM)
1116 +#
1117 +CONFIG_BLK_DEV_SD=y
1118 +# CONFIG_CHR_DEV_ST is not set
1119 +# CONFIG_CHR_DEV_OSST is not set
1120 +# CONFIG_BLK_DEV_SR is not set
1121 +# CONFIG_CHR_DEV_SG is not set
1122 +# CONFIG_CHR_DEV_SCH is not set
1123 +
1124 +#
1125 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
1126 +#
1127 +CONFIG_SCSI_MULTI_LUN=y
1128 +# CONFIG_SCSI_CONSTANTS is not set
1129 +# CONFIG_SCSI_LOGGING is not set
1130 +# CONFIG_SCSI_SCAN_ASYNC is not set
1131 +CONFIG_SCSI_WAIT_SCAN=m
1132 +
1133 +#
1134 +# SCSI Transports
1135 +#
1136 +# CONFIG_SCSI_SPI_ATTRS is not set
1137 +# CONFIG_SCSI_FC_ATTRS is not set
1138 +# CONFIG_SCSI_ISCSI_ATTRS is not set
1139 +# CONFIG_SCSI_SAS_LIBSAS is not set
1140 +# CONFIG_SCSI_SRP_ATTRS is not set
1141 +# CONFIG_SCSI_LOWLEVEL is not set
1142 +# CONFIG_ATA is not set
1143 +# CONFIG_MD is not set
1144 +CONFIG_NETDEVICES=y
1145 +# CONFIG_NETDEVICES_MULTIQUEUE is not set
1146 +# CONFIG_DUMMY is not set
1147 +# CONFIG_BONDING is not set
1148 +# CONFIG_MACVLAN is not set
1149 +# CONFIG_EQUALIZER is not set
1150 +# CONFIG_TUN is not set
1151 +# CONFIG_VETH is not set
1152 +# CONFIG_PHYLIB is not set
1153 +CONFIG_NET_ETHERNET=y
1154 +CONFIG_MII=y
1155 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
1156 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
1157 +# CONFIG_IBM_NEW_EMAC_TAH is not set
1158 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
1159 +# CONFIG_B44 is not set
1160 +# CONFIG_NETDEV_1000 is not set
1161 +# CONFIG_NETDEV_10000 is not set
1162 +
1163 +#
1164 +# Wireless LAN
1165 +#
1166 +# CONFIG_WLAN_PRE80211 is not set
1167 +# CONFIG_WLAN_80211 is not set
1168 +# CONFIG_WAN is not set
1169 +# CONFIG_PPP is not set
1170 +# CONFIG_SLIP is not set
1171 +# CONFIG_SHAPER is not set
1172 +# CONFIG_NETCONSOLE is not set
1173 +# CONFIG_NETPOLL is not set
1174 +# CONFIG_NET_POLL_CONTROLLER is not set
1175 +# CONFIG_ISDN is not set
1176 +# CONFIG_PHONE is not set
1177 +
1178 +#
1179 +# Input device support
1180 +#
1181 +CONFIG_INPUT=y
1182 +# CONFIG_INPUT_FF_MEMLESS is not set
1183 +# CONFIG_INPUT_POLLDEV is not set
1184 +
1185 +#
1186 +# Userland interfaces
1187 +#
1188 +CONFIG_INPUT_MOUSEDEV=y
1189 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1190 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
1191 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
1192 +# CONFIG_INPUT_JOYDEV is not set
1193 +CONFIG_INPUT_EVDEV=y
1194 +# CONFIG_INPUT_EVBUG is not set
1195 +
1196 +#
1197 +# Input Device Drivers
1198 +#
1199 +CONFIG_INPUT_KEYBOARD=y
1200 +# CONFIG_KEYBOARD_ATKBD is not set
1201 +# CONFIG_KEYBOARD_SUNKBD is not set
1202 +# CONFIG_KEYBOARD_LKKBD is not set
1203 +# CONFIG_KEYBOARD_XTKBD is not set
1204 +# CONFIG_KEYBOARD_NEWTON is not set
1205 +# CONFIG_KEYBOARD_STOWAWAY is not set
1206 +# CONFIG_INPUT_MOUSE is not set
1207 +# CONFIG_INPUT_JOYSTICK is not set
1208 +# CONFIG_INPUT_TABLET is not set
1209 +# CONFIG_INPUT_TOUCHSCREEN is not set
1210 +# CONFIG_INPUT_MISC is not set
1211 +
1212 +#
1213 +# Hardware I/O ports
1214 +#
1215 +CONFIG_SERIO=y
1216 +CONFIG_SERIO_SERPORT=y
1217 +# CONFIG_SERIO_RAW is not set
1218 +# CONFIG_GAMEPORT is not set
1219 +
1220 +#
1221 +# Character devices
1222 +#
1223 +CONFIG_VT=y
1224 +CONFIG_VT_CONSOLE=y
1225 +CONFIG_HW_CONSOLE=y
1226 +# CONFIG_VT_HW_CONSOLE_BINDING is not set
1227 +# CONFIG_SERIAL_NONSTANDARD is not set
1228 +
1229 +#
1230 +# Serial drivers
1231 +#
1232 +# CONFIG_SERIAL_8250 is not set
1233 +
1234 +#
1235 +# Non-8250 serial port support
1236 +#
1237 +CONFIG_SERIAL_COLDFIRE=y
1238 +CONFIG_UNIX98_PTYS=y
1239 +# CONFIG_LEGACY_PTYS is not set
1240 +# CONFIG_IPMI_HANDLER is not set
1241 +# CONFIG_HW_RANDOM is not set
1242 +# CONFIG_GEN_RTC is not set
1243 +# CONFIG_R3964 is not set
1244 +# CONFIG_RAW_DRIVER is not set
1245 +# CONFIG_TCG_TPM is not set
1246 +# CONFIG_I2C is not set
1247 +
1248 +#
1249 +# SPI support
1250 +#
1251 +# CONFIG_SPI is not set
1252 +# CONFIG_COLDFIRE_EDMA is not set
1253 +# CONFIG_SPI_MASTER is not set
1254 +# CONFIG_W1 is not set
1255 +# CONFIG_POWER_SUPPLY is not set
1256 +# CONFIG_HWMON is not set
1257 +# CONFIG_WATCHDOG is not set
1258 +
1259 +#
1260 +# Sonics Silicon Backplane
1261 +#
1262 +CONFIG_SSB_POSSIBLE=y
1263 +# CONFIG_SSB is not set
1264 +
1265 +#
1266 +# Multifunction device drivers
1267 +#
1268 +# CONFIG_MFD_SM501 is not set
1269 +
1270 +#
1271 +# Multimedia devices
1272 +#
1273 +# CONFIG_VIDEO_DEV is not set
1274 +# CONFIG_DVB_CORE is not set
1275 +CONFIG_DAB=y
1276 +
1277 +#
1278 +# Graphics support
1279 +#
1280 +# CONFIG_VGASTATE is not set
1281 +CONFIG_VIDEO_OUTPUT_CONTROL=m
1282 +# CONFIG_FB is not set
1283 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1284 +
1285 +#
1286 +# Display device support
1287 +#
1288 +# CONFIG_DISPLAY_SUPPORT is not set
1289 +
1290 +#
1291 +# Console display driver support
1292 +#
1293 +CONFIG_DUMMY_CONSOLE=y
1294 +
1295 +#
1296 +# Sound
1297 +#
1298 +# CONFIG_SOUND is not set
1299 +CONFIG_HID_SUPPORT=y
1300 +CONFIG_HID=y
1301 +CONFIG_HID_DEBUG=y
1302 +# CONFIG_HIDRAW is not set
1303 +# CONFIG_USB_SUPPORT is not set
1304 +# CONFIG_MMC is not set
1305 +# CONFIG_NEW_LEDS is not set
1306 +# CONFIG_RTC_CLASS is not set
1307 +
1308 +#
1309 +# Userspace I/O
1310 +#
1311 +# CONFIG_UIO is not set
1312 +
1313 +#
1314 +# Character devices
1315 +#
1316 +# CONFIG_SERIAL_CONSOLE is not set
1317 +
1318 +#
1319 +# File systems
1320 +#
1321 +CONFIG_EXT2_FS=y
1322 +# CONFIG_EXT2_FS_XATTR is not set
1323 +# CONFIG_EXT2_FS_XIP is not set
1324 +CONFIG_EXT3_FS=y
1325 +CONFIG_EXT3_FS_XATTR=y
1326 +# CONFIG_EXT3_FS_POSIX_ACL is not set
1327 +# CONFIG_EXT3_FS_SECURITY is not set
1328 +# CONFIG_EXT4DEV_FS is not set
1329 +CONFIG_JBD=y
1330 +CONFIG_FS_MBCACHE=y
1331 +# CONFIG_REISERFS_FS is not set
1332 +# CONFIG_JFS_FS is not set
1333 +# CONFIG_FS_POSIX_ACL is not set
1334 +# CONFIG_XFS_FS is not set
1335 +# CONFIG_GFS2_FS is not set
1336 +# CONFIG_OCFS2_FS is not set
1337 +CONFIG_MINIX_FS=y
1338 +# CONFIG_ROMFS_FS is not set
1339 +# CONFIG_INOTIFY is not set
1340 +# CONFIG_QUOTA is not set
1341 +CONFIG_DNOTIFY=y
1342 +# CONFIG_AUTOFS_FS is not set
1343 +# CONFIG_AUTOFS4_FS is not set
1344 +# CONFIG_FUSE_FS is not set
1345 +
1346 +#
1347 +# CD-ROM/DVD Filesystems
1348 +#
1349 +# CONFIG_ISO9660_FS is not set
1350 +# CONFIG_UDF_FS is not set
1351 +
1352 +#
1353 +# DOS/FAT/NT Filesystems
1354 +#
1355 +CONFIG_FAT_FS=y
1356 +CONFIG_MSDOS_FS=y
1357 +CONFIG_VFAT_FS=y
1358 +CONFIG_FAT_DEFAULT_CODEPAGE=437
1359 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1360 +CONFIG_NTFS_FS=y
1361 +# CONFIG_NTFS_DEBUG is not set
1362 +CONFIG_NTFS_RW=y
1363 +
1364 +#
1365 +# Pseudo filesystems
1366 +#
1367 +CONFIG_PROC_FS=y
1368 +# CONFIG_PROC_KCORE is not set
1369 +CONFIG_PROC_SYSCTL=y
1370 +CONFIG_SYSFS=y
1371 +CONFIG_TMPFS=y
1372 +# CONFIG_TMPFS_POSIX_ACL is not set
1373 +# CONFIG_HUGETLB_PAGE is not set
1374 +# CONFIG_CONFIGFS_FS is not set
1375 +
1376 +#
1377 +# Miscellaneous filesystems
1378 +#
1379 +# CONFIG_ADFS_FS is not set
1380 +# CONFIG_AFFS_FS is not set
1381 +# CONFIG_HFS_FS is not set
1382 +# CONFIG_HFSPLUS_FS is not set
1383 +# CONFIG_BEFS_FS is not set
1384 +# CONFIG_BFS_FS is not set
1385 +# CONFIG_EFS_FS is not set
1386 +# CONFIG_CRAMFS is not set
1387 +# CONFIG_VXFS_FS is not set
1388 +# CONFIG_HPFS_FS is not set
1389 +# CONFIG_QNX4FS_FS is not set
1390 +# CONFIG_SYSV_FS is not set
1391 +# CONFIG_UFS_FS is not set
1392 +CONFIG_NETWORK_FILESYSTEMS=y
1393 +CONFIG_NFS_FS=y
1394 +# CONFIG_NFS_V3 is not set
1395 +# CONFIG_NFS_V4 is not set
1396 +# CONFIG_NFS_DIRECTIO is not set
1397 +# CONFIG_NFSD is not set
1398 +CONFIG_ROOT_NFS=y
1399 +CONFIG_LOCKD=y
1400 +CONFIG_NFS_COMMON=y
1401 +CONFIG_SUNRPC=y
1402 +# CONFIG_SUNRPC_BIND34 is not set
1403 +# CONFIG_RPCSEC_GSS_KRB5 is not set
1404 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
1405 +# CONFIG_SMB_FS is not set
1406 +# CONFIG_CIFS is not set
1407 +# CONFIG_NCP_FS is not set
1408 +# CONFIG_CODA_FS is not set
1409 +# CONFIG_AFS_FS is not set
1410 +
1411 +#
1412 +# Partition Types
1413 +#
1414 +CONFIG_PARTITION_ADVANCED=y
1415 +# CONFIG_ACORN_PARTITION is not set
1416 +# CONFIG_OSF_PARTITION is not set
1417 +# CONFIG_AMIGA_PARTITION is not set
1418 +# CONFIG_ATARI_PARTITION is not set
1419 +# CONFIG_MAC_PARTITION is not set
1420 +CONFIG_MSDOS_PARTITION=y
1421 +# CONFIG_BSD_DISKLABEL is not set
1422 +# CONFIG_MINIX_SUBPARTITION is not set
1423 +# CONFIG_SOLARIS_X86_PARTITION is not set
1424 +# CONFIG_UNIXWARE_DISKLABEL is not set
1425 +# CONFIG_LDM_PARTITION is not set
1426 +# CONFIG_SGI_PARTITION is not set
1427 +# CONFIG_ULTRIX_PARTITION is not set
1428 +# CONFIG_SUN_PARTITION is not set
1429 +# CONFIG_KARMA_PARTITION is not set
1430 +# CONFIG_EFI_PARTITION is not set
1431 +# CONFIG_SYSV68_PARTITION is not set
1432 +CONFIG_NLS=y
1433 +CONFIG_NLS_DEFAULT="iso8859-1"
1434 +CONFIG_NLS_CODEPAGE_437=y
1435 +# CONFIG_NLS_CODEPAGE_737 is not set
1436 +# CONFIG_NLS_CODEPAGE_775 is not set
1437 +# CONFIG_NLS_CODEPAGE_850 is not set
1438 +# CONFIG_NLS_CODEPAGE_852 is not set
1439 +# CONFIG_NLS_CODEPAGE_855 is not set
1440 +# CONFIG_NLS_CODEPAGE_857 is not set
1441 +# CONFIG_NLS_CODEPAGE_860 is not set
1442 +# CONFIG_NLS_CODEPAGE_861 is not set
1443 +# CONFIG_NLS_CODEPAGE_862 is not set
1444 +# CONFIG_NLS_CODEPAGE_863 is not set
1445 +# CONFIG_NLS_CODEPAGE_864 is not set
1446 +# CONFIG_NLS_CODEPAGE_865 is not set
1447 +# CONFIG_NLS_CODEPAGE_866 is not set
1448 +# CONFIG_NLS_CODEPAGE_869 is not set
1449 +# CONFIG_NLS_CODEPAGE_936 is not set
1450 +# CONFIG_NLS_CODEPAGE_950 is not set
1451 +# CONFIG_NLS_CODEPAGE_932 is not set
1452 +# CONFIG_NLS_CODEPAGE_949 is not set
1453 +# CONFIG_NLS_CODEPAGE_874 is not set
1454 +# CONFIG_NLS_ISO8859_8 is not set
1455 +# CONFIG_NLS_CODEPAGE_1250 is not set
1456 +# CONFIG_NLS_CODEPAGE_1251 is not set
1457 +# CONFIG_NLS_ASCII is not set
1458 +CONFIG_NLS_ISO8859_1=y
1459 +# CONFIG_NLS_ISO8859_2 is not set
1460 +# CONFIG_NLS_ISO8859_3 is not set
1461 +# CONFIG_NLS_ISO8859_4 is not set
1462 +# CONFIG_NLS_ISO8859_5 is not set
1463 +# CONFIG_NLS_ISO8859_6 is not set
1464 +# CONFIG_NLS_ISO8859_7 is not set
1465 +# CONFIG_NLS_ISO8859_9 is not set
1466 +# CONFIG_NLS_ISO8859_13 is not set
1467 +# CONFIG_NLS_ISO8859_14 is not set
1468 +# CONFIG_NLS_ISO8859_15 is not set
1469 +# CONFIG_NLS_KOI8_R is not set
1470 +# CONFIG_NLS_KOI8_U is not set
1471 +CONFIG_NLS_UTF8=y
1472 +# CONFIG_DLM is not set
1473 +CONFIG_INSTRUMENTATION=y
1474 +# CONFIG_PROFILING is not set
1475 +# CONFIG_MARKERS is not set
1476 +
1477 +#
1478 +# Kernel hacking
1479 +#
1480 +# CONFIG_PRINTK_TIME is not set
1481 +CONFIG_ENABLE_WARN_DEPRECATED=y
1482 +# CONFIG_ENABLE_MUST_CHECK is not set
1483 +# CONFIG_MAGIC_SYSRQ is not set
1484 +# CONFIG_UNUSED_SYMBOLS is not set
1485 +# CONFIG_DEBUG_FS is not set
1486 +# CONFIG_HEADERS_CHECK is not set
1487 +CONFIG_DEBUG_KERNEL=y
1488 +CONFIG_DETECT_SOFTLOCKUP=y
1489 +CONFIG_SCHED_DEBUG=y
1490 +# CONFIG_SCHEDSTATS is not set
1491 +# CONFIG_TIMER_STATS is not set
1492 +CONFIG_DEBUG_SLAB=y
1493 +# CONFIG_DEBUG_SLAB_LEAK is not set
1494 +# CONFIG_DEBUG_RT_MUTEXES is not set
1495 +# CONFIG_RT_MUTEX_TESTER is not set
1496 +# CONFIG_DEBUG_SPINLOCK is not set
1497 +# CONFIG_DEBUG_MUTEXES is not set
1498 +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1499 +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1500 +# CONFIG_DEBUG_KOBJECT is not set
1501 +CONFIG_DEBUG_BUGVERBOSE=y
1502 +CONFIG_DEBUG_INFO=y
1503 +# CONFIG_DEBUG_VM is not set
1504 +# CONFIG_DEBUG_LIST is not set
1505 +# CONFIG_DEBUG_SG is not set
1506 +# CONFIG_FRAME_POINTER is not set
1507 +CONFIG_FORCED_INLINING=y
1508 +# CONFIG_BOOT_PRINTK_DELAY is not set
1509 +# CONFIG_RCU_TORTURE_TEST is not set
1510 +# CONFIG_FAULT_INJECTION is not set
1511 +# CONFIG_SAMPLES is not set
1512 +CONFIG_BOOTPARAM=y
1513 +CONFIG_BOOTPARAM_STRING="root=/dev/nfs rw nfsroot=172.27.163.2:/tftpboot/ltib ip=172.27.163.3:172.27.163.2:172.27.255.254:255.255.0.0::eth0:off mtdparts=phys_mapped_flash:16m(User)"
1514 +
1515 +#
1516 +# CodeTEST Setup
1517 +#
1518 +# CONFIG_CODETEST is not set
1519 +
1520 +#
1521 +# Security options
1522 +#
1523 +# CONFIG_KEYS is not set
1524 +# CONFIG_SECURITY is not set
1525 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1526 +CONFIG_CRYPTO=y
1527 +CONFIG_CRYPTO_ALGAPI=y
1528 +CONFIG_CRYPTO_BLKCIPHER=y
1529 +CONFIG_CRYPTO_HASH=y
1530 +CONFIG_CRYPTO_MANAGER=y
1531 +CONFIG_CRYPTO_HMAC=y
1532 +# CONFIG_CRYPTO_XCBC is not set
1533 +# CONFIG_CRYPTO_NULL is not set
1534 +# CONFIG_CRYPTO_MD4 is not set
1535 +CONFIG_CRYPTO_MD5=y
1536 +CONFIG_CRYPTO_SHA1=y
1537 +# CONFIG_CRYPTO_SHA256 is not set
1538 +# CONFIG_CRYPTO_SHA512 is not set
1539 +# CONFIG_CRYPTO_WP512 is not set
1540 +# CONFIG_CRYPTO_TGR192 is not set
1541 +# CONFIG_CRYPTO_GF128MUL is not set
1542 +# CONFIG_CRYPTO_ECB is not set
1543 +CONFIG_CRYPTO_CBC=y
1544 +# CONFIG_CRYPTO_PCBC is not set
1545 +# CONFIG_CRYPTO_LRW is not set
1546 +# CONFIG_CRYPTO_XTS is not set
1547 +# CONFIG_CRYPTO_CRYPTD is not set
1548 +CONFIG_CRYPTO_DES=y
1549 +# CONFIG_CRYPTO_FCRYPT is not set
1550 +# CONFIG_CRYPTO_BLOWFISH is not set
1551 +# CONFIG_CRYPTO_TWOFISH is not set
1552 +# CONFIG_CRYPTO_SERPENT is not set
1553 +# CONFIG_CRYPTO_AES is not set
1554 +# CONFIG_CRYPTO_CAST5 is not set
1555 +# CONFIG_CRYPTO_CAST6 is not set
1556 +# CONFIG_CRYPTO_TEA is not set
1557 +# CONFIG_CRYPTO_ARC4 is not set
1558 +# CONFIG_CRYPTO_KHAZAD is not set
1559 +# CONFIG_CRYPTO_ANUBIS is not set
1560 +# CONFIG_CRYPTO_SEED is not set
1561 +# CONFIG_CRYPTO_DEFLATE is not set
1562 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
1563 +# CONFIG_CRYPTO_CRC32C is not set
1564 +# CONFIG_CRYPTO_CAMELLIA is not set
1565 +CONFIG_CRYPTO_TEST=m
1566 +# CONFIG_CRYPTO_AUTHENC is not set
1567 +# CONFIG_CRYPTO_HW is not set
1568 +
1569 +#
1570 +# Library routines
1571 +#
1572 +CONFIG_BITREVERSE=y
1573 +CONFIG_CRC_CCITT=y
1574 +CONFIG_CRC16=y
1575 +# CONFIG_CRC_ITU_T is not set
1576 +CONFIG_CRC32=y
1577 +# CONFIG_CRC7 is not set
1578 +CONFIG_LIBCRC32C=y
1579 +CONFIG_PLIST=y
1580 +CONFIG_HAS_IOMEM=y
1581 +CONFIG_HAS_IOPORT=y
1582 +CONFIG_HAS_DMA=y
1583 --- a/drivers/serial/mcfserial.c
1584 +++ b/drivers/serial/mcfserial.c
1585 @@ -45,6 +45,11 @@
1586  #include <asm/coldfire.h>
1587  #include <asm/mcfsim.h>
1588  #include <asm/mcfuart.h>
1589 +#if defined(CONFIG_M547X_8X)
1590 +#include <asm/m5485sim.h>
1591 +#include <asm/m5485psc.h>
1592 +#include <asm/m5485gpio.h>
1593 +#endif
1594  #ifdef CONFIG_NETtel
1595  #include <asm/nettel.h>
1596  #endif
1597 @@ -64,7 +69,7 @@ struct timer_list mcfrs_timer_struct;
1598  #define        DEFAULT_CBAUD           B38400
1599  #elif defined(CONFIG_MOD5272) || defined(CONFIG_M5208EVB) || \
1600        defined(CONFIG_M5329EVB) || defined(CONFIG_GILBARCO) || \
1601 -      defined(CONFIG_M54455)
1602 +      defined(CONFIG_M54455) || defined(CONFIG_M547X_8X)
1603  #define CONSOLE_BAUD_RATE      115200
1604  #define DEFAULT_CBAUD          B115200
1605  #elif defined(CONFIG_ARNEWSH) || defined(CONFIG_FREESCALE) || \
1606 @@ -97,7 +102,8 @@ static struct tty_driver *mcfrs_serial_d
1607  #undef SERIAL_DEBUG_FLOW
1608
1609  #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
1610 -    defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_M54455)
1611 +    defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_M54455) || \
1612 +    defined(CONFIG_M547X_8X)
1613  #define        IRQBASE (MCFINT_VECBASE+MCFINT_UART0)
1614  #else
1615  #define        IRQBASE 73
1616 @@ -117,7 +123,11 @@ static struct mcf_serial mcfrs_table[] =
1617         {  /* ttyS1 */
1618                 .magic = 0,
1619                 .addr = (volatile unsigned char *) (MCF_MBAR+MCFUART_BASE2),
1620 +#if defined(CONFIG_M547X_8X)
1621 +               .irq = IRQBASE-1,
1622 +#else
1623                 .irq = IRQBASE+1,
1624 +#endif
1625                 .flags = ASYNC_BOOT_AUTOCONF,
1626         },
1627  #endif
1628 @@ -125,7 +135,11 @@ static struct mcf_serial mcfrs_table[] =
1629         {  /* ttyS2 */
1630                 .magic = 0,
1631                 .addr = (volatile unsigned char *) (MCF_MBAR+MCFUART_BASE3),
1632 +#if defined(CONFIG_M547X_8X)
1633 +               .irq = IRQBASE-2,
1634 +#else
1635                 .irq = IRQBASE+2,
1636 +#endif
1637                 .flags = ASYNC_BOOT_AUTOCONF,
1638         },
1639  #endif
1640 @@ -133,7 +147,11 @@ static struct mcf_serial mcfrs_table[] =
1641         {  /* ttyS3 */
1642                 .magic = 0,
1643                 .addr = (volatile unsigned char *) (MCF_MBAR+MCFUART_BASE4),
1644 +#if defined(CONFIG_M547X_8X)
1645 +               .irq = IRQBASE-3,
1646 +#else
1647                 .irq = IRQBASE+3,
1648 +#endif
1649                 .flags = ASYNC_BOOT_AUTOCONF,
1650         },
1651  #endif
1652 @@ -412,7 +430,12 @@ irqreturn_t mcfrs_interrupt(int irq, voi
1653         struct mcf_serial       *info;
1654         unsigned char           isr;
1655
1656 +/* JKM -- revisit! IRQ compute */
1657 +#if defined(CONFIG_M547X_8X)
1658 +       info = &mcfrs_table[(IRQBASE - irq)];
1659 +#else
1660         info = &mcfrs_table[(irq - IRQBASE)];
1661 +#endif
1662         isr = info->addr[MCFUART_UISR] & info->imr;
1663
1664         if (isr & MCFUART_UIR_RXREADY)
1665 @@ -1621,6 +1644,22 @@ static void mcfrs_irqinit(struct mcf_ser
1666                 /* GPIOs also must be initalized, depends on board */
1667                 break;
1668         }
1669 +#elif defined(CONFIG_M547X_8X)
1670 +       volatile unsigned char  *uartp;
1671 +       uartp = (volatile unsigned char *)info->addr;
1672 +
1673 +       if (info->line > 3) {
1674 +               printk("SERIAL: don't know how to handle UART %d interrupt?\n",
1675 +                       info->line);
1676 +               return;
1677 +       }
1678 +
1679 +       /* Set GPIO port register to enable PSC(port) signals */
1680 +       MCF_PAR_PSCn(info->line) = (0
1681 +               | MCF_PAR_PSC_TXD
1682 +               | MCF_PAR_PSC_RXD);
1683 +
1684 +       MCF_ICR(info->irq - 64) = ILP_PSCn(info->line);
1685  #else
1686         volatile unsigned char  *icrp, *uartp;
1687
1688 @@ -1983,7 +2022,7 @@ struct console mcfrs_console = {
1689
1690  static int __init mcfrs_console_init(void)
1691  {
1692 -#ifndef CONFIG_M54455
1693 +#if !(defined(CONFIG_M54455) || defined(CONFIG_M547X_8X))
1694         register_console(&mcfrs_console);
1695  #endif
1696         return 0;
1697 --- a/include/asm-m68k/cf_pgalloc.h
1698 +++ b/include/asm-m68k/cf_pgalloc.h
1699 @@ -1,9 +1,14 @@
1700  #ifndef M68K_CF_PGALLOC_H
1701  #define M68K_CF_PGALLOC_H
1702
1703 +/* JKM -- added -- needed? */
1704 +#include <linux/highmem.h>
1705 +
1706  #include <asm/coldfire.h>
1707  #include <asm/page.h>
1708  #include <asm/cf_tlbflush.h>
1709 +/* JKM -- added -- needed? */
1710 +#include <asm/cf_cacheflush.h>
1711
1712  extern inline void pte_free_kernel(pte_t *pte)
1713  {
1714 --- a/include/asm-m68k/cfcache.h
1715 +++ b/include/asm-m68k/cfcache.h
1716 @@ -70,7 +70,33 @@
1717  /* cache disabled for testing */
1718  #define CACHE_INITIAL_MODE     (CF_CACR_EUSP)
1719  #endif /* CONFIG_M5445X_DISABLE_CACHE */
1720 -#endif /* CONFIG_M54455 */
1721 +
1722 +#elif defined(CONFIG_M547X_8X)
1723 +/*
1724 + * M547x/M548x Cache Configuration
1725 + *     - cache line size is 16 bytes
1726 + *     - cache is 4-way set associative
1727 + *     - each cache has 512 sets (128k / 16bytes / 4way)
1728 + *     - I-Cache size is 32KB
1729 + *     - D-Cache size is 32KB
1730 + */
1731 +#define ICACHE_SIZE 0x8000             /* instruction - 32k */
1732 +#define DCACHE_SIZE 0x8000             /* data - 32k */
1733 +
1734 +#define CACHE_LINE_SIZE 0x0010         /* 16 bytes */
1735 +#define CACHE_SETS 0x0200              /* 512 sets */
1736 +#define CACHE_WAYS 0x0004              /* 4 way */
1737 +
1738 +#define CACHE_DISABLE_MODE     (CF_CACR_DCINVA+        \
1739 +                                CF_CACR_BCINVA+        \
1740 +                                CF_CACR_ICINVA)
1741 +
1742 +#define CACHE_INITIAL_MODE     (CF_CACR_DEC+           \
1743 +                                CF_CACR_BEC+           \
1744 +                                CF_CACR_IEC+           \
1745 +                                CF_CACR_DESB+          \
1746 +                                CF_CACR_EUSP)
1747 +#endif /* CONFIG_M547X_8X */
1748
1749  #ifndef __ASSEMBLY__
1750
1751 --- a/include/asm-m68k/coldfire.h
1752 +++ b/include/asm-m68k/coldfire.h
1753 @@ -1,9 +1,16 @@
1754  #ifndef _COLDFIRE_H_
1755  #define _COLDFIRE_H_
1756
1757 +#if defined(CONFIG_M54455)
1758  #define MCF_MBAR       0x0
1759  #define MCF_RAMBAR1    0x40000000
1760  #define MCF_SRAM       0x80000000
1761 +#elif defined(CONFIG_M547X_8X)
1762 +#define MCF_MBAR       0xE0000000
1763 +#define MCF_RAMBAR0    0xE3000000
1764 +#define MCF_RAMBAR1    0xE3001000
1765 +#endif
1766 +
1767  #define MCF_CLK        CONFIG_MCFCLK
1768  #define MCF_BUSCLK     (CONFIG_MCFCLK/2)
1769
1770 --- /dev/null
1771 +++ b/include/asm-m68k/m5485gpio.h
1772 @@ -0,0 +1,694 @@
1773 +/*
1774 + * File:       mcf548x_gpio.h
1775 + * Purpose:    Register and bit definitions for the MCF548X
1776 + *
1777 + * Notes:
1778 + *
1779 + */
1780 +
1781 +#ifndef _M5485GPIO_H_
1782 +#define _M5485GPIO_H_
1783 +
1784 +/*********************************************************************
1785 +*
1786 +* General Purpose I/O (GPIO)
1787 +*
1788 +*********************************************************************/
1789 +
1790 +/* Register read/write macros */
1791 +#define MCF_GPIO_PODR_FBCTL         MCF_REG08(0x000A00)
1792 +#define MCF_GPIO_PODR_FBCS          MCF_REG08(0x000A01)
1793 +#define MCF_GPIO_PODR_DMA           MCF_REG08(0x000A02)
1794 +#define MCF_GPIO_PODR_FEC0H         MCF_REG08(0x000A04)
1795 +#define MCF_GPIO_PODR_FEC0L         MCF_REG08(0x000A05)
1796 +#define MCF_GPIO_PODR_FEC1H         MCF_REG08(0x000A06)
1797 +#define MCF_GPIO_PODR_FEC1L         MCF_REG08(0x000A07)
1798 +#define MCF_GPIO_PODR_FECI2C        MCF_REG08(0x000A08)
1799 +#define MCF_GPIO_PODR_PCIBG         MCF_REG08(0x000A09)
1800 +#define MCF_GPIO_PODR_PCIBR         MCF_REG08(0x000A0A)
1801 +#define MCF_GPIO_PODR_PSC3PSC2      MCF_REG08(0x000A0C)
1802 +#define MCF_GPIO_PODR_PSC1PSC0      MCF_REG08(0x000A0D)
1803 +#define MCF_GPIO_PODR_DSPI          MCF_REG08(0x000A0E)
1804 +#define MCF_GPIO_PDDR_FBCTL         MCF_REG08(0x000A10)
1805 +#define MCF_GPIO_PDDR_FBCS          MCF_REG08(0x000A11)
1806 +#define MCF_GPIO_PDDR_DMA           MCF_REG08(0x000A12)
1807 +#define MCF_GPIO_PDDR_FEC0H         MCF_REG08(0x000A14)
1808 +#define MCF_GPIO_PDDR_FEC0L         MCF_REG08(0x000A15)
1809 +#define MCF_GPIO_PDDR_FEC1H         MCF_REG08(0x000A16)
1810 +#define MCF_GPIO_PDDR_FEC1L         MCF_REG08(0x000A17)
1811 +#define MCF_GPIO_PDDR_FECI2C        MCF_REG08(0x000A18)
1812 +#define MCF_GPIO_PDDR_PCIBG         MCF_REG08(0x000A19)
1813 +#define MCF_GPIO_PDDR_PCIBR         MCF_REG08(0x000A1A)
1814 +#define MCF_GPIO_PDDR_PSC3PSC2      MCF_REG08(0x000A1C)
1815 +#define MCF_GPIO_PDDR_PSC1PSC0      MCF_REG08(0x000A1D)
1816 +#define MCF_GPIO_PDDR_DSPI          MCF_REG08(0x000A1E)
1817 +#define MCF_GPIO_PPDSDR_FBCTL       MCF_REG08(0x000A20)
1818 +#define MCF_GPIO_PPDSDR_FBCS        MCF_REG08(0x000A21)
1819 +#define MCF_GPIO_PPDSDR_DMA         MCF_REG08(0x000A22)
1820 +#define MCF_GPIO_PPDSDR_FEC0H       MCF_REG08(0x000A24)
1821 +#define MCF_GPIO_PPDSDR_FEC0L       MCF_REG08(0x000A25)
1822 +#define MCF_GPIO_PPDSDR_FEC1H       MCF_REG08(0x000A26)
1823 +#define MCF_GPIO_PPDSDR_FEC1L       MCF_REG08(0x000A27)
1824 +#define MCF_GPIO_PPDSDR_FECI2C      MCF_REG08(0x000A28)
1825 +#define MCF_GPIO_PPDSDR_PCIBG       MCF_REG08(0x000A29)
1826 +#define MCF_GPIO_PPDSDR_PCIBR       MCF_REG08(0x000A2A)
1827 +#define MCF_GPIO_PPDSDR_PSC3PSC2    MCF_REG08(0x000A2C)
1828 +#define MCF_GPIO_PPDSDR_PSC1PSC0    MCF_REG08(0x000A2D)
1829 +#define MCF_GPIO_PPDSDR_DSPI        MCF_REG08(0x000A2E)
1830 +#define MCF_GPIO_PCLRR_FBCTL        MCF_REG08(0x000A30)
1831 +#define MCF_GPIO_PCLRR_FBCS         MCF_REG08(0x000A31)
1832 +#define MCF_GPIO_PCLRR_DMA          MCF_REG08(0x000A32)
1833 +#define MCF_GPIO_PCLRR_FEC0H        MCF_REG08(0x000A34)
1834 +#define MCF_GPIO_PCLRR_FEC0L        MCF_REG08(0x000A35)
1835 +#define MCF_GPIO_PCLRR_FEC1H        MCF_REG08(0x000A36)
1836 +#define MCF_GPIO_PCLRR_FEC1L        MCF_REG08(0x000A37)
1837 +#define MCF_GPIO_PCLRR_FECI2C       MCF_REG08(0x000A38)
1838 +#define MCF_GPIO_PCLRR_PCIBG        MCF_REG08(0x000A39)
1839 +#define MCF_GPIO_PCLRR_PCIBR        MCF_REG08(0x000A3A)
1840 +#define MCF_GPIO_PCLRR_PSC3PSC2     MCF_REG08(0x000A3C)
1841 +#define MCF_GPIO_PCLRR_PSC1PSC0     MCF_REG08(0x000A3D)
1842 +#define MCF_GPIO_PCLRR_DSPI         MCF_REG08(0x000A3E)
1843 +#define MCF_GPIO_PAR_FBCTL          MCF_REG16(0x000A40)
1844 +#define MCF_GPIO_PAR_FBCS           MCF_REG08(0x000A42)
1845 +#define MCF_GPIO_PAR_DMA            MCF_REG08(0x000A43)
1846 +#define MCF_GPIO_PAR_FECI2CIRQ      MCF_REG16(0x000A44)
1847 +#define MCF_GPIO_PAR_PCIBG          MCF_REG16(0x000A48)
1848 +#define MCF_GPIO_PAR_PCIBR          MCF_REG16(0x000A4A)
1849 +#define MCF_GPIO_PAR_PSC3           MCF_REG08(0x000A4C)
1850 +#define MCF_GPIO_PAR_PSC2           MCF_REG08(0x000A4D)
1851 +#define MCF_GPIO_PAR_PSC1           MCF_REG08(0x000A4E)
1852 +#define MCF_GPIO_PAR_PSC0           MCF_REG08(0x000A4F)
1853 +#define MCF_GPIO_PAR_DSPI           MCF_REG16(0x000A50)
1854 +#define MCF_GPIO_PAR_TIMER          MCF_REG08(0x000A52)
1855 +
1856 +/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
1857 +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL0              (0x01)
1858 +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL1              (0x02)
1859 +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL2              (0x04)
1860 +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL3              (0x08)
1861 +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL4              (0x10)
1862 +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL5              (0x20)
1863 +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL6              (0x40)
1864 +#define MCF_GPIO_PODR_FBCTL_PODRFBCTL7              (0x80)
1865 +
1866 +/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
1867 +#define MCF_GPIO_PODR_FBCS_PODRFBCS1                (0x02)
1868 +#define MCF_GPIO_PODR_FBCS_PODRFBCS2                (0x04)
1869 +#define MCF_GPIO_PODR_FBCS_PODRFBCS3                (0x08)
1870 +#define MCF_GPIO_PODR_FBCS_PODRFBCS4                (0x10)
1871 +#define MCF_GPIO_PODR_FBCS_PODRFBCS5                (0x20)
1872 +
1873 +/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
1874 +#define MCF_GPIO_PODR_DMA_PODRDMA0                  (0x01)
1875 +#define MCF_GPIO_PODR_DMA_PODRDMA1                  (0x02)
1876 +#define MCF_GPIO_PODR_DMA_PODRDMA2                  (0x04)
1877 +#define MCF_GPIO_PODR_DMA_PODRDMA3                  (0x08)
1878 +
1879 +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
1880 +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H0              (0x01)
1881 +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H1              (0x02)
1882 +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H2              (0x04)
1883 +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H3              (0x08)
1884 +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H4              (0x10)
1885 +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H5              (0x20)
1886 +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H6              (0x40)
1887 +#define MCF_GPIO_PODR_FEC0H_PODRFEC0H7              (0x80)
1888 +
1889 +/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
1890 +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L0              (0x01)
1891 +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L1              (0x02)
1892 +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L2              (0x04)
1893 +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L3              (0x08)
1894 +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L4              (0x10)
1895 +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L5              (0x20)
1896 +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L6              (0x40)
1897 +#define MCF_GPIO_PODR_FEC0L_PODRFEC0L7              (0x80)
1898 +
1899 +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
1900 +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H0              (0x01)
1901 +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H1              (0x02)
1902 +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H2              (0x04)
1903 +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H3              (0x08)
1904 +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H4              (0x10)
1905 +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H5              (0x20)
1906 +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H6              (0x40)
1907 +#define MCF_GPIO_PODR_FEC1H_PODRFEC1H7              (0x80)
1908 +
1909 +/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
1910 +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L0              (0x01)
1911 +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L1              (0x02)
1912 +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L2              (0x04)
1913 +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L3              (0x08)
1914 +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L4              (0x10)
1915 +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L5              (0x20)
1916 +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L6              (0x40)
1917 +#define MCF_GPIO_PODR_FEC1L_PODRFEC1L7              (0x80)
1918 +
1919 +/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
1920 +#define MCF_GPIO_PODR_FECI2C_PODRFECI2C0            (0x01)
1921 +#define MCF_GPIO_PODR_FECI2C_PODRFECI2C1            (0x02)
1922 +#define MCF_GPIO_PODR_FECI2C_PODRFECI2C2            (0x04)
1923 +#define MCF_GPIO_PODR_FECI2C_PODRFECI2C3            (0x08)
1924 +
1925 +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
1926 +#define MCF_GPIO_PODR_PCIBG_PODRPCIBG0              (0x01)
1927 +#define MCF_GPIO_PODR_PCIBG_PODRPCIBG1              (0x02)
1928 +#define MCF_GPIO_PODR_PCIBG_PODRPCIBG2              (0x04)
1929 +#define MCF_GPIO_PODR_PCIBG_PODRPCIBG3              (0x08)
1930 +#define MCF_GPIO_PODR_PCIBG_PODRPCIBG4              (0x10)
1931 +
1932 +/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
1933 +#define MCF_GPIO_PODR_PCIBR_PODRPCIBR0              (0x01)
1934 +#define MCF_GPIO_PODR_PCIBR_PODRPCIBR1              (0x02)
1935 +#define MCF_GPIO_PODR_PCIBR_PODRPCIBR2              (0x04)
1936 +#define MCF_GPIO_PODR_PCIBR_PODRPCIBR3              (0x08)
1937 +#define MCF_GPIO_PODR_PCIBR_PODRPCIBR4              (0x10)
1938 +
1939 +/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC2 */
1940 +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC20        (0x01)
1941 +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC21        (0x02)
1942 +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC22        (0x04)
1943 +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC23        (0x08)
1944 +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC24        (0x10)
1945 +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC25        (0x20)
1946 +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC26        (0x40)
1947 +#define MCF_GPIO_PODR_PSC3PSC2_PODRPSC3PSC27        (0x80)
1948 +
1949 +/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC0 */
1950 +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC00        (0x01)
1951 +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC01        (0x02)
1952 +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC02        (0x04)
1953 +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC03        (0x08)
1954 +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC04        (0x10)
1955 +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC05        (0x20)
1956 +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC06        (0x40)
1957 +#define MCF_GPIO_PODR_PSC1PSC0_PODRPSC1PSC07        (0x80)
1958 +
1959 +/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
1960 +#define MCF_GPIO_PODR_DSPI_PODRDSPI0                (0x01)
1961 +#define MCF_GPIO_PODR_DSPI_PODRDSPI1                (0x02)
1962 +#define MCF_GPIO_PODR_DSPI_PODRDSPI2                (0x04)
1963 +#define MCF_GPIO_PODR_DSPI_PODRDSPI3                (0x08)
1964 +#define MCF_GPIO_PODR_DSPI_PODRDSPI4                (0x10)
1965 +#define MCF_GPIO_PODR_DSPI_PODRDSPI5                (0x20)
1966 +#define MCF_GPIO_PODR_DSPI_PODRDSPI6                (0x40)
1967 +
1968 +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
1969 +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL0              (0x01)
1970 +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL1              (0x02)
1971 +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL2              (0x04)
1972 +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL3              (0x08)
1973 +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL4              (0x10)
1974 +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL5              (0x20)
1975 +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL6              (0x40)
1976 +#define MCF_GPIO_PDDR_FBCTL_PDDRFBCTL7              (0x80)
1977 +
1978 +/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
1979 +#define MCF_GPIO_PDDR_FBCS_PDDRFBCS1                (0x02)
1980 +#define MCF_GPIO_PDDR_FBCS_PDDRFBCS2                (0x04)
1981 +#define MCF_GPIO_PDDR_FBCS_PDDRFBCS3                (0x08)
1982 +#define MCF_GPIO_PDDR_FBCS_PDDRFBCS4                (0x10)
1983 +#define MCF_GPIO_PDDR_FBCS_PDDRFBCS5                (0x20)
1984 +
1985 +/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
1986 +#define MCF_GPIO_PDDR_DMA_PDDRDMA0                  (0x01)
1987 +#define MCF_GPIO_PDDR_DMA_PDDRDMA1                  (0x02)
1988 +#define MCF_GPIO_PDDR_DMA_PDDRDMA2                  (0x04)
1989 +#define MCF_GPIO_PDDR_DMA_PDDRDMA3                  (0x08)
1990 +
1991 +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
1992 +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H0              (0x01)
1993 +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H1              (0x02)
1994 +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H2              (0x04)
1995 +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H3              (0x08)
1996 +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H4              (0x10)
1997 +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H5              (0x20)
1998 +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H6              (0x40)
1999 +#define MCF_GPIO_PDDR_FEC0H_PDDRFEC0H7              (0x80)
2000 +
2001 +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
2002 +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L0              (0x01)
2003 +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L1              (0x02)
2004 +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L2              (0x04)
2005 +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L3              (0x08)
2006 +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L4              (0x10)
2007 +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L5              (0x20)
2008 +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L6              (0x40)
2009 +#define MCF_GPIO_PDDR_FEC0L_PDDRFEC0L7              (0x80)
2010 +
2011 +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
2012 +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H0              (0x01)
2013 +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H1              (0x02)
2014 +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H2              (0x04)
2015 +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H3              (0x08)
2016 +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H4              (0x10)
2017 +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H5              (0x20)
2018 +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H6              (0x40)
2019 +#define MCF_GPIO_PDDR_FEC1H_PDDRFEC1H7              (0x80)
2020 +
2021 +/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
2022 +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L0              (0x01)
2023 +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L1              (0x02)
2024 +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L2              (0x04)
2025 +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L3              (0x08)
2026 +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L4              (0x10)
2027 +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L5              (0x20)
2028 +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L6              (0x40)
2029 +#define MCF_GPIO_PDDR_FEC1L_PDDRFEC1L7              (0x80)
2030 +
2031 +/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
2032 +#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C0            (0x01)
2033 +#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C1            (0x02)
2034 +#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C2            (0x04)
2035 +#define MCF_GPIO_PDDR_FECI2C_PDDRFECI2C3            (0x08)
2036 +
2037 +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
2038 +#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG0              (0x01)
2039 +#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG1              (0x02)
2040 +#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG2              (0x04)
2041 +#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG3              (0x08)
2042 +#define MCF_GPIO_PDDR_PCIBG_PDDRPCIBG4              (0x10)
2043 +
2044 +/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
2045 +#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR0              (0x01)
2046 +#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR1              (0x02)
2047 +#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR2              (0x04)
2048 +#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR3              (0x08)
2049 +#define MCF_GPIO_PDDR_PCIBR_PDDRPCIBR4              (0x10)
2050 +
2051 +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC2 */
2052 +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC20        (0x01)
2053 +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC21        (0x02)
2054 +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC22        (0x04)
2055 +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC23        (0x08)
2056 +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC24        (0x10)
2057 +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC25        (0x20)
2058 +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC26        (0x40)
2059 +#define MCF_GPIO_PDDR_PSC3PSC2_PDDRPSC3PSC27        (0x80)
2060 +
2061 +/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC0 */
2062 +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC00        (0x01)
2063 +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC01        (0x02)
2064 +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC02        (0x04)
2065 +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC03        (0x08)
2066 +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC04        (0x10)
2067 +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC05        (0x20)
2068 +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC06        (0x40)
2069 +#define MCF_GPIO_PDDR_PSC1PSC0_PDDRPSC1PSC07        (0x80)
2070 +
2071 +/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
2072 +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI0                (0x01)
2073 +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI1                (0x02)
2074 +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI2                (0x04)
2075 +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI3                (0x08)
2076 +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI4                (0x10)
2077 +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI5                (0x20)
2078 +#define MCF_GPIO_PDDR_DSPI_PDDRDSPI6                (0x40)
2079 +
2080 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
2081 +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL0          (0x01)
2082 +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL1          (0x02)
2083 +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL2          (0x04)
2084 +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL3          (0x08)
2085 +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL4          (0x10)
2086 +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL5          (0x20)
2087 +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL6          (0x40)
2088 +#define MCF_GPIO_PPDSDR_FBCTL_PPDSDRFBCTL7          (0x80)
2089 +
2090 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
2091 +#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS1            (0x02)
2092 +#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS2            (0x04)
2093 +#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS3            (0x08)
2094 +#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS4            (0x10)
2095 +#define MCF_GPIO_PPDSDR_FBCS_PPDSDRFBCS5            (0x20)
2096 +
2097 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
2098 +#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA0              (0x01)
2099 +#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA1              (0x02)
2100 +#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA2              (0x04)
2101 +#define MCF_GPIO_PPDSDR_DMA_PPDSDRDMA3              (0x08)
2102 +
2103 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
2104 +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H0          (0x01)
2105 +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H1          (0x02)
2106 +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H2          (0x04)
2107 +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H3          (0x08)
2108 +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H4          (0x10)
2109 +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H5          (0x20)
2110 +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H6          (0x40)
2111 +#define MCF_GPIO_PPDSDR_FEC0H_PPDSDRFEC0H7          (0x80)
2112 +
2113 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
2114 +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L0          (0x01)
2115 +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L1          (0x02)
2116 +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L2          (0x04)
2117 +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L3          (0x08)
2118 +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L4          (0x10)
2119 +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L5          (0x20)
2120 +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L6          (0x40)
2121 +#define MCF_GPIO_PPDSDR_FEC0L_PPDSDRFEC0L7          (0x80)
2122 +
2123 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
2124 +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H0          (0x01)
2125 +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H1          (0x02)
2126 +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H2          (0x04)
2127 +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H3          (0x08)
2128 +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H4          (0x10)
2129 +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H5          (0x20)
2130 +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H6          (0x40)
2131 +#define MCF_GPIO_PPDSDR_FEC1H_PPDSDRFEC1H7          (0x80)
2132 +
2133 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
2134 +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L0          (0x01)
2135 +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L1          (0x02)
2136 +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L2          (0x04)
2137 +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L3          (0x08)
2138 +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L4          (0x10)
2139 +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L5          (0x20)
2140 +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L6          (0x40)
2141 +#define MCF_GPIO_PPDSDR_FEC1L_PPDSDRFEC1L7          (0x80)
2142 +
2143 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
2144 +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C0        (0x01)
2145 +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C1        (0x02)
2146 +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C2        (0x04)
2147 +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDRFECI2C3        (0x08)
2148 +
2149 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
2150 +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG0          (0x01)
2151 +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG1          (0x02)
2152 +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG2          (0x04)
2153 +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG3          (0x08)
2154 +#define MCF_GPIO_PPDSDR_PCIBG_PPDSDRPCIBG4          (0x10)
2155 +
2156 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
2157 +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR0          (0x01)
2158 +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR1          (0x02)
2159 +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR2          (0x04)
2160 +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR3          (0x08)
2161 +#define MCF_GPIO_PPDSDR_PCIBR_PPDSDRPCIBR4          (0x10)
2162 +
2163 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC2 */
2164 +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC20    (0x01)
2165 +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC21    (0x02)
2166 +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC22    (0x04)
2167 +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC23    (0x08)
2168 +#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC24      (0x10)
2169 +#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDRPSC3PSC25      (0x20)
2170 +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC26    (0x40)
2171 +#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDRPSC3PSC27    (0x80)
2172 +
2173 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC0 */
2174 +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC00    (0x01)
2175 +#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC01      (0x02)
2176 +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC02    (0x04)
2177 +#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDRPSC1PSC03      (0x08)
2178 +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC04    (0x10)
2179 +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC05    (0x20)
2180 +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC06    (0x40)
2181 +#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDRPSC1PSC07    (0x80)
2182 +
2183 +/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
2184 +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI0            (0x01)
2185 +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI1            (0x02)
2186 +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI2            (0x04)
2187 +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI3            (0x08)
2188 +#define MCF_GPIO_PPDSDR_DSPI_PDDRDSPI4              (0x10)
2189 +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI5            (0x20)
2190 +#define MCF_GPIO_PPDSDR_DSPI_PPDSDRDSPI6            (0x40)
2191 +
2192 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
2193 +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL0            (0x01)
2194 +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL1            (0x02)
2195 +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL2            (0x04)
2196 +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL3            (0x08)
2197 +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL4            (0x10)
2198 +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL5            (0x20)
2199 +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL6            (0x40)
2200 +#define MCF_GPIO_PCLRR_FBCTL_PCLRRFBCTL7            (0x80)
2201 +
2202 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
2203 +#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS1              (0x02)
2204 +#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS2              (0x04)
2205 +#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS3              (0x08)
2206 +#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS4              (0x10)
2207 +#define MCF_GPIO_PCLRR_FBCS_PCLRRFBCS5              (0x20)
2208 +
2209 +/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
2210 +#define MCF_GPIO_PCLRR_DMA_PCLRRDMA0                (0x01)
2211 +#define MCF_GPIO_PCLRR_DMA_PCLRRDMA1                (0x02)
2212 +#define MCF_GPIO_PCLRR_DMA_PCLRRDMA2                (0x04)
2213 +#define MCF_GPIO_PCLRR_DMA_PCLRRDMA3                (0x08)
2214 +
2215 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
2216 +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H0            (0x01)
2217 +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H1            (0x02)
2218 +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H2            (0x04)
2219 +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H3            (0x08)
2220 +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H4            (0x10)
2221 +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H5            (0x20)
2222 +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H6            (0x40)
2223 +#define MCF_GPIO_PCLRR_FEC0H_PCLRRFEC0H7            (0x80)
2224 +
2225 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
2226 +#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L0            (0x01)
2227 +#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L1             (0x02)
2228 +#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L2            (0x04)
2229 +#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L3            (0x08)
2230 +#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L4             (0x10)
2231 +#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L5             (0x20)
2232 +#define MCF_GPIO_PCLRR_FEC0L_PODRFEC0L6             (0x40)
2233 +#define MCF_GPIO_PCLRR_FEC0L_PCLRRFEC0L7            (0x80)
2234 +
2235 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
2236 +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H0            (0x01)
2237 +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H1            (0x02)
2238 +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H2            (0x04)
2239 +#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H3             (0x08)
2240 +#define MCF_GPIO_PCLRR_FEC1H_PODRFEC1H4             (0x10)
2241 +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H5            (0x20)
2242 +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H6            (0x40)
2243 +#define MCF_GPIO_PCLRR_FEC1H_PCLRRFEC1H7            (0x80)
2244 +
2245 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
2246 +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L0            (0x01)
2247 +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L1            (0x02)
2248 +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L2            (0x04)
2249 +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L3            (0x08)
2250 +#define MCF_GPIO_PCLRR_FEC1L_PODRFEC1L4             (0x10)
2251 +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L5            (0x20)
2252 +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L6            (0x40)
2253 +#define MCF_GPIO_PCLRR_FEC1L_PCLRRFEC1L7            (0x80)
2254 +
2255 +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
2256 +#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C0          (0x01)
2257 +#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C1          (0x02)
2258 +#define MCF_GPIO_PCLRR_FECI2C_PODRFECI2C2           (0x04)
2259 +#define MCF_GPIO_PCLRR_FECI2C_PCLRRFECI2C3          (0x08)
2260 +
2261 +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
2262 +#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG0             (0x01)
2263 +#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG1             (0x02)
2264 +#define MCF_GPIO_PCLRR_PCIBG_PODRPCIBG2             (0x04)
2265 +#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG3            (0x08)
2266 +#define MCF_GPIO_PCLRR_PCIBG_PCLRRPCIBG4            (0x10)
2267 +
2268 +/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
2269 +#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR0            (0x01)
2270 +#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR1            (0x02)
2271 +#define MCF_GPIO_PCLRR_PCIBR_PCLRRPCIBR2            (0x04)
2272 +#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR3             (0x08)
2273 +#define MCF_GPIO_PCLRR_PCIBR_PODRPCIBR4             (0x10)
2274 +
2275 +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC2 */
2276 +#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC20       (0x01)
2277 +#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC21       (0x02)
2278 +#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC22      (0x04)
2279 +#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC23      (0x08)
2280 +#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC24      (0x10)
2281 +#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC25       (0x20)
2282 +#define MCF_GPIO_PCLRR_PSC3PSC2_PODRPSC3PSC26       (0x40)
2283 +#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRRPSC3PSC27      (0x80)
2284 +
2285 +/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC0 */
2286 +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC00      (0x01)
2287 +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC01      (0x02)
2288 +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC02      (0x04)
2289 +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC03      (0x08)
2290 +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC04      (0x10)
2291 +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC05      (0x20)
2292 +#define MCF_GPIO_PCLRR_PSC1PSC0_PODRPSC1PSC06       (0x40)
2293 +#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRRPSC1PSC07      (0x80)
2294 +
2295 +/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
2296 +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI0              (0x01)
2297 +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI1              (0x02)
2298 +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI2              (0x04)
2299 +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI3              (0x08)
2300 +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI4              (0x10)
2301 +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI5              (0x20)
2302 +#define MCF_GPIO_PCLRR_DSPI_PCLRRDSPI6              (0x40)
2303 +
2304 +/* Bit definitions and macros for MCF_GPIO_PAR_FBCTL */
2305 +#define MCF_GPIO_PAR_FBCTL_PAR_TS(x)                (((x)&0x0003)<<0)
2306 +#define MCF_GPIO_PAR_FBCTL_PAR_TA                   (0x0004)
2307 +#define MCF_GPIO_PAR_FBCTL_PAR_RWB                  (0x0010)
2308 +#define MCF_GPIO_PAR_FBCTL_PAR_OE                   (0x0040)
2309 +#define MCF_GPIO_PAR_FBCTL_PAR_BWE0                 (0x0100)
2310 +#define MCF_GPIO_PAR_FBCTL_PAR_BWE1                 (0x0400)
2311 +#define MCF_GPIO_PAR_FBCTL_PAR_BWE2                 (0x1000)
2312 +#define MCF_GPIO_PAR_FBCTL_PAR_BWE3                 (0x4000)
2313 +#define MCF_GPIO_PAR_FBCTL_PAR_TS_GPIO              (0)
2314 +#define MCF_GPIO_PAR_FBCTL_PAR_TS_TBST              (2)
2315 +#define MCF_GPIO_PAR_FBCTL_PAR_TS_TS                (3)
2316 +
2317 +/* Bit definitions and macros for MCF_GPIO_PAR_FBCS */
2318 +#define MCF_GPIO_PAR_FBCS_PAR_CS1                   (0x02)
2319 +#define MCF_GPIO_PAR_FBCS_PAR_CS2                   (0x04)
2320 +#define MCF_GPIO_PAR_FBCS_PAR_CS3                   (0x08)
2321 +#define MCF_GPIO_PAR_FBCS_PAR_CS4                   (0x10)
2322 +#define MCF_GPIO_PAR_FBCS_PAR_CS5                   (0x20)
2323 +
2324 +/* Bit definitions and macros for MCF_GPIO_PAR_DMA */
2325 +#define MCF_GPIO_PAR_DMA_PAR_DREQ0(x)               (((x)&0x03)<<0)
2326 +#define MCF_GPIO_PAR_DMA_PAR_DREQ1(x)               (((x)&0x03)<<2)
2327 +#define MCF_GPIO_PAR_DMA_PAR_DACK0(x)               (((x)&0x03)<<4)
2328 +#define MCF_GPIO_PAR_DMA_PAR_DACK1(x)               (((x)&0x03)<<6)
2329 +#define MCF_GPIO_PAR_DMA_PAR_DACKx_GPIO             (0)
2330 +#define MCF_GPIO_PAR_DMA_PAR_DACKx_TOUT             (2)
2331 +#define MCF_GPIO_PAR_DMA_PAR_DACKx_DACK             (3)
2332 +#define MCF_GPIO_PAR_DMA_PAR_DREQx_GPIO             (0)
2333 +#define MCF_GPIO_PAR_DMA_PAR_DREQx_TIN              (2)
2334 +#define MCF_GPIO_PAR_DMA_PAR_DREQx_DREQ             (3)
2335 +
2336 +/* Bit definitions and macros for MCF_GPIO_PAR_FECI2CIRQ */
2337 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ5             (0x0001)
2338 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ6             (0x0002)
2339 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SCL              (0x0004)
2340 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SDA              (0x0008)
2341 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x)         (((x)&0x0003)<<6)
2342 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x)        (((x)&0x0003)<<8)
2343 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII            (0x0400)
2344 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E17              (0x0800)
2345 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC            (0x1000)
2346 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO           (0x2000)
2347 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII            (0x4000)
2348 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E07              (0x8000)
2349 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX     (0x0000)
2350 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA       (0x0200)
2351 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO     (0x0300)
2352 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX      (0x0000)
2353 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL        (0x0080)
2354 +#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC       (0x00C0)
2355 +
2356 +/* Bit definitions and macros for MCF_GPIO_PAR_PCIBG */
2357 +#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG0(x)            (((x)&0x0003)<<0)
2358 +#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG1(x)            (((x)&0x0003)<<2)
2359 +#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG2(x)            (((x)&0x0003)<<4)
2360 +#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG3(x)            (((x)&0x0003)<<6)
2361 +#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG4(x)            (((x)&0x0003)<<8)
2362 +
2363 +/* Bit definitions and macros for MCF_GPIO_PAR_PCIBR */
2364 +#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG0(x)            (((x)&0x0003)<<0)
2365 +#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG1(x)            (((x)&0x0003)<<2)
2366 +#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG2(x)            (((x)&0x0003)<<4)
2367 +#define MCF_GPIO_PAR_PCIBR_PAR_PCIBG3(x)            (((x)&0x0003)<<6)
2368 +#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR4(x)            (((x)&0x0003)<<8)
2369 +
2370 +/* Bit definitions and macros for MCF_GPIO_PAR_PSC3 */
2371 +#define MCF_GPIO_PAR_PSC3_PAR_TXD3                  (0x04)
2372 +#define MCF_GPIO_PAR_PSC3_PAR_RXD3                  (0x08)
2373 +#define MCF_GPIO_PAR_PSC3_PAR_RTS3(x)               (((x)&0x03)<<4)
2374 +#define MCF_GPIO_PAR_PSC3_PAR_CTS3(x)               (((x)&0x03)<<6)
2375 +#define MCF_GPIO_PAR_PSC3_PAR_CTS3_GPIO             (0x00)
2376 +#define MCF_GPIO_PAR_PSC3_PAR_CTS3_BCLK             (0x80)
2377 +#define MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS              (0xC0)
2378 +#define MCF_GPIO_PAR_PSC3_PAR_RTS3_GPIO             (0x00)
2379 +#define MCF_GPIO_PAR_PSC3_PAR_RTS3_FSYNC            (0x20)
2380 +#define MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS              (0x30)
2381 +#define MCF_GPIO_PAR_PSC3_PAR_CTS2_CANRX            (0x40)
2382 +
2383 +/* Bit definitions and macros for MCF_GPIO_PAR_PSC2 */
2384 +#define MCF_GPIO_PAR_PSC2_PAR_TXD2                  (0x04)
2385 +#define MCF_GPIO_PAR_PSC2_PAR_RXD2                  (0x08)
2386 +#define MCF_GPIO_PAR_PSC2_PAR_RTS2(x)               (((x)&0x03)<<4)
2387 +#define MCF_GPIO_PAR_PSC2_PAR_CTS2(x)               (((x)&0x03)<<6)
2388 +#define MCF_GPIO_PAR_PSC2_PAR_CTS2_GPIO             (0x00)
2389 +#define MCF_GPIO_PAR_PSC2_PAR_CTS2_BCLK             (0x80)
2390 +#define MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS              (0xC0)
2391 +#define MCF_GPIO_PAR_PSC2_PAR_RTS2_GPIO             (0x00)
2392 +#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANTX            (0x10)
2393 +#define MCF_GPIO_PAR_PSC2_PAR_RTS2_FSYNC            (0x20)
2394 +#define MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS              (0x30)
2395 +#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANRX            (0x40)
2396 +
2397 +/* Bit definitions and macros for MCF_GPIO_PAR_PSC1 */
2398 +#define MCF_GPIO_PAR_PSC1_PAR_TXD1                  (0x04)
2399 +#define MCF_GPIO_PAR_PSC1_PAR_RXD1                  (0x08)
2400 +#define MCF_GPIO_PAR_PSC1_PAR_RTS1(x)               (((x)&0x03)<<4)
2401 +#define MCF_GPIO_PAR_PSC1_PAR_CTS1(x)               (((x)&0x03)<<6)
2402 +#define MCF_GPIO_PAR_PSC1_PAR_CTS1_GPIO             (0x00)
2403 +#define MCF_GPIO_PAR_PSC1_PAR_CTS1_BCLK             (0x80)
2404 +#define MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS              (0xC0)
2405 +#define MCF_GPIO_PAR_PSC1_PAR_RTS1_GPIO             (0x00)
2406 +#define MCF_GPIO_PAR_PSC1_PAR_RTS1_FSYNC            (0x20)
2407 +#define MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS              (0x30)
2408 +
2409 +/* Bit definitions and macros for MCF_GPIO_PAR_PSC0 */
2410 +#define MCF_GPIO_PAR_PSC0_PAR_TXD0                  (0x04)
2411 +#define MCF_GPIO_PAR_PSC0_PAR_RXD0                  (0x08)
2412 +#define MCF_GPIO_PAR_PSC0_PAR_RTS0(x)               (((x)&0x03)<<4)
2413 +#define MCF_GPIO_PAR_PSC0_PAR_CTS0(x)               (((x)&0x03)<<6)
2414 +#define MCF_GPIO_PAR_PSC0_PAR_CTS0_GPIO             (0x00)
2415 +#define MCF_GPIO_PAR_PSC0_PAR_CTS0_BCLK             (0x80)
2416 +#define MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS              (0xC0)
2417 +#define MCF_GPIO_PAR_PSC0_PAR_RTS0_GPIO             (0x00)
2418 +#define MCF_GPIO_PAR_PSC0_PAR_RTS0_FSYNC            (0x20)
2419 +#define MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS              (0x30)
2420 +
2421 +/* Bit definitions and macros for MCF_GPIO_PAR_DSPI */
2422 +#define MCF_GPIO_PAR_DSPI_PAR_SOUT(x)               (((x)&0x0003)<<0)
2423 +#define MCF_GPIO_PAR_DSPI_PAR_SIN(x)                (((x)&0x0003)<<2)
2424 +#define MCF_GPIO_PAR_DSPI_PAR_SCK(x)                (((x)&0x0003)<<4)
2425 +#define MCF_GPIO_PAR_DSPI_PAR_CS0(x)                (((x)&0x0003)<<6)
2426 +#define MCF_GPIO_PAR_DSPI_PAR_CS2(x)                (((x)&0x0003)<<8)
2427 +#define MCF_GPIO_PAR_DSPI_PAR_CS3(x)                (((x)&0x0003)<<10)
2428 +#define MCF_GPIO_PAR_DSPI_PAR_CS5                   (0x1000)
2429 +#define MCF_GPIO_PAR_DSPI_PAR_CS3_GPIO              (0x0000)
2430 +#define MCF_GPIO_PAR_DSPI_PAR_CS3_CANTX             (0x0400)
2431 +#define MCF_GPIO_PAR_DSPI_PAR_CS3_TOUT              (0x0800)
2432 +#define MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS            (0x0C00)
2433 +#define MCF_GPIO_PAR_DSPI_PAR_CS2_GPIO              (0x0000)
2434 +#define MCF_GPIO_PAR_DSPI_PAR_CS2_CANTX             (0x0100)
2435 +#define MCF_GPIO_PAR_DSPI_PAR_CS2_TOUT              (0x0200)
2436 +#define MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS            (0x0300)
2437 +#define MCF_GPIO_PAR_DSPI_PAR_CS0_GPIO              (0x0000)
2438 +#define MCF_GPIO_PAR_DSPI_PAR_CS0_FSYNC             (0x0040)
2439 +#define MCF_GPIO_PAR_DSPI_PAR_CS0_RTS               (0x0080)
2440 +#define MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS            (0x00C0)
2441 +#define MCF_GPIO_PAR_DSPI_PAR_SCK_GPIO              (0x0000)
2442 +#define MCF_GPIO_PAR_DSPI_PAR_SCK_BCLK              (0x0010)
2443 +#define MCF_GPIO_PAR_DSPI_PAR_SCK_CTS               (0x0020)
2444 +#define MCF_GPIO_PAR_DSPI_PAR_SCK_SCK               (0x0030)
2445 +#define MCF_GPIO_PAR_DSPI_PAR_SIN_GPIO              (0x0000)
2446 +#define MCF_GPIO_PAR_DSPI_PAR_SIN_RXD               (0x0008)
2447 +#define MCF_GPIO_PAR_DSPI_PAR_SIN_SIN               (0x000C)
2448 +#define MCF_GPIO_PAR_DSPI_PAR_SOUT_GPIO             (0x0000)
2449 +#define MCF_GPIO_PAR_DSPI_PAR_SOUT_TXD              (0x0002)
2450 +#define MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT             (0x0003)
2451 +
2452 +/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
2453 +#define MCF_GPIO_PAR_TIMER_PAR_TOUT2                (0x01)
2454 +#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x)              (((x)&0x03)<<1)
2455 +#define MCF_GPIO_PAR_TIMER_PAR_TOUT3                (0x08)
2456 +#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x)              (((x)&0x03)<<4)
2457 +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_CANRX           (0x00)
2458 +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_IRQ             (0x20)
2459 +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN             (0x30)
2460 +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_CANRX           (0x00)
2461 +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_IRQ             (0x04)
2462 +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN             (0x06)
2463 +
2464 +/********************************************************************/
2465 +
2466 +#endif /* _M5485GPIO_H_ */
2467 --- /dev/null
2468 +++ b/include/asm-m68k/m5485gpt.h
2469 @@ -0,0 +1,88 @@
2470 +/*
2471 + * File:       mcf548x_gpt.h
2472 + * Purpose:    Register and bit definitions for the MCF548X
2473 + *
2474 + * Notes:
2475 + *
2476 + */
2477 +
2478 +#ifndef __MCF548X_GPT_H__
2479 +#define __MCF548X_GPT_H__
2480 +
2481 +/*********************************************************************
2482 +*
2483 +* General Purpose Timers (GPT)
2484 +*
2485 +*********************************************************************/
2486 +
2487 +/* Register read/write macros */
2488 +#define MCF_GPT_GMS0       MCF_REG32(0x000800)
2489 +#define MCF_GPT_GCIR0      MCF_REG32(0x000804)
2490 +#define MCF_GPT_GPWM0      MCF_REG32(0x000808)
2491 +#define MCF_GPT_GSR0       MCF_REG32(0x00080C)
2492 +#define MCF_GPT_GMS1       MCF_REG32(0x000810)
2493 +#define MCF_GPT_GCIR1      MCF_REG32(0x000814)
2494 +#define MCF_GPT_GPWM1      MCF_REG32(0x000818)
2495 +#define MCF_GPT_GSR1       MCF_REG32(0x00081C)
2496 +#define MCF_GPT_GMS2       MCF_REG32(0x000820)
2497 +#define MCF_GPT_GCIR2      MCF_REG32(0x000824)
2498 +#define MCF_GPT_GPWM2      MCF_REG32(0x000828)
2499 +#define MCF_GPT_GSR2       MCF_REG32(0x00082C)
2500 +#define MCF_GPT_GMS3       MCF_REG32(0x000830)
2501 +#define MCF_GPT_GCIR3      MCF_REG32(0x000834)
2502 +#define MCF_GPT_GPWM3      MCF_REG32(0x000838)
2503 +#define MCF_GPT_GSR3       MCF_REG32(0x00083C)
2504 +#define MCF_GPT_GMS(x)     MCF_REG32(0x000800+((x)*0x010))
2505 +#define MCF_GPT_GCIR(x)    MCF_REG32(0x000804+((x)*0x010))
2506 +#define MCF_GPT_GPWM(x)    MCF_REG32(0x000808+((x)*0x010))
2507 +#define MCF_GPT_GSR(x)     MCF_REG32(0x00080C+((x)*0x010))
2508 +
2509 +/* Bit definitions and macros for MCF_GPT_GMS */
2510 +#define MCF_GPT_GMS_TMS(x)         (((x)&0x00000007)<<0)
2511 +#define MCF_GPT_GMS_GPIO(x)        (((x)&0x00000003)<<4)
2512 +#define MCF_GPT_GMS_IEN            (0x00000100)
2513 +#define MCF_GPT_GMS_OD             (0x00000200)
2514 +#define MCF_GPT_GMS_SC             (0x00000400)
2515 +#define MCF_GPT_GMS_CE             (0x00001000)
2516 +#define MCF_GPT_GMS_WDEN           (0x00008000)
2517 +#define MCF_GPT_GMS_ICT(x)         (((x)&0x00000003)<<16)
2518 +#define MCF_GPT_GMS_OCT(x)         (((x)&0x00000003)<<20)
2519 +#define MCF_GPT_GMS_OCPW(x)        (((x)&0x000000FF)<<24)
2520 +#define MCF_GPT_GMS_OCT_FRCLOW     (0x00000000)
2521 +#define MCF_GPT_GMS_OCT_PULSEHI    (0x00100000)
2522 +#define MCF_GPT_GMS_OCT_PULSELO    (0x00200000)
2523 +#define MCF_GPT_GMS_OCT_TOGGLE     (0x00300000)
2524 +#define MCF_GPT_GMS_ICT_ANY        (0x00000000)
2525 +#define MCF_GPT_GMS_ICT_RISE       (0x00010000)
2526 +#define MCF_GPT_GMS_ICT_FALL       (0x00020000)
2527 +#define MCF_GPT_GMS_ICT_PULSE      (0x00030000)
2528 +#define MCF_GPT_GMS_GPIO_INPUT     (0x00000000)
2529 +#define MCF_GPT_GMS_GPIO_OUTLO     (0x00000020)
2530 +#define MCF_GPT_GMS_GPIO_OUTHI     (0x00000030)
2531 +#define MCF_GPT_GMS_TMS_DISABLE    (0x00000000)
2532 +#define MCF_GPT_GMS_TMS_INCAPT     (0x00000001)
2533 +#define MCF_GPT_GMS_TMS_OUTCAPT    (0x00000002)
2534 +#define MCF_GPT_GMS_TMS_PWM        (0x00000003)
2535 +#define MCF_GPT_GMS_TMS_GPIO       (0x00000004)
2536 +
2537 +/* Bit definitions and macros for MCF_GPT_GCIR */
2538 +#define MCF_GPT_GCIR_CNT(x)        (((x)&0x0000FFFF)<<0)
2539 +#define MCF_GPT_GCIR_PRE(x)        (((x)&0x0000FFFF)<<16)
2540 +
2541 +/* Bit definitions and macros for MCF_GPT_GPWM */
2542 +#define MCF_GPT_GPWM_LOAD          (0x00000001)
2543 +#define MCF_GPT_GPWM_PWMOP         (0x00000100)
2544 +#define MCF_GPT_GPWM_WIDTH(x)      (((x)&0x0000FFFF)<<16)
2545 +
2546 +/* Bit definitions and macros for MCF_GPT_GSR */
2547 +#define MCF_GPT_GSR_CAPT           (0x00000001)
2548 +#define MCF_GPT_GSR_COMP           (0x00000002)
2549 +#define MCF_GPT_GSR_PWMP           (0x00000004)
2550 +#define MCF_GPT_GSR_TEXP           (0x00000008)
2551 +#define MCF_GPT_GSR_PIN            (0x00000100)
2552 +#define MCF_GPT_GSR_OVF(x)         (((x)&0x00000007)<<12)
2553 +#define MCF_GPT_GSR_CAPTURE(x)     (((x)&0x0000FFFF)<<16)
2554 +
2555 +/********************************************************************/
2556 +
2557 +#endif /* __MCF548X_GPT_H__ */
2558 --- /dev/null
2559 +++ b/include/asm-m68k/m5485psc.h
2560 @@ -0,0 +1,474 @@
2561 +/*
2562 + * File:       mcf548x_psc.h
2563 + * Purpose:    Register and bit definitions for the MCF548X
2564 + *
2565 + * Notes:
2566 + *
2567 + */
2568 +
2569 +#ifndef __MCF548X_PSC_H__
2570 +#define __MCF548X_PSC_H__
2571 +
2572 +/*********************************************************************
2573 +*
2574 +* Programmable Serial Controller (PSC)
2575 +*
2576 +*********************************************************************/
2577 +
2578 +/* Register read/write macros */
2579 +#define MCF_PSC_MR0            (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008600))
2580 +#define MCF_PSC_SR0            (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008604))
2581 +#define MCF_PSC_CSR0           (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008604))
2582 +#define MCF_PSC_CR0            (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008608))
2583 +#define MCF_PSC_RB0            (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C))
2584 +#define MCF_PSC_TB0            (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C))
2585 +#define MCF_PSC_TB_8BIT0       (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C))
2586 +#define MCF_PSC_TB_16BIT0      (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C))
2587 +#define MCF_PSC_TB_AC970       (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C))
2588 +#define MCF_PSC_IPCR0          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008610))
2589 +#define MCF_PSC_ACR0           (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008610))
2590 +#define MCF_PSC_ISR0           (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008614))
2591 +#define MCF_PSC_IMR0           (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008614))
2592 +#define MCF_PSC_CTUR0          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008618))
2593 +#define MCF_PSC_CTLR0          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00861C))
2594 +#define MCF_PSC_IP0            (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008634))
2595 +#define MCF_PSC_OPSET0         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008638))
2596 +#define MCF_PSC_OPRESET0       (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00863C))
2597 +#define MCF_PSC_SICR0          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008640))
2598 +#define MCF_PSC_IRCR10         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008644))
2599 +#define MCF_PSC_IRCR20         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008648))
2600 +#define MCF_PSC_IRSDR0         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00864C))
2601 +#define MCF_PSC_IRMDR0         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008650))
2602 +#define MCF_PSC_IRFDR0         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008654))
2603 +#define MCF_PSC_RFCNT0         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008658))
2604 +#define MCF_PSC_TFCNT0         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00865C))
2605 +#define MCF_PSC_RFSR0          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008664))
2606 +#define MCF_PSC_TFSR0          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008684))
2607 +#define MCF_PSC_RFCR0          (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008668))
2608 +#define MCF_PSC_TFCR0          (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008688))
2609 +#define MCF_PSC_RFAR0          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00866E))
2610 +#define MCF_PSC_TFAR0          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00868E))
2611 +#define MCF_PSC_RFRP0          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008672))
2612 +#define MCF_PSC_TFRP0          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008692))
2613 +#define MCF_PSC_RFWP0          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008676))
2614 +#define MCF_PSC_TFWP0          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008696))
2615 +#define MCF_PSC_RLRFP0         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00867A))
2616 +#define MCF_PSC_TLRFP0         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00869A))
2617 +#define MCF_PSC_RLWFP0         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00867E))
2618 +#define MCF_PSC_TLWFP0         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00869E))
2619 +#define MCF_PSC_MR1            (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008700))
2620 +#define MCF_PSC_SR1            (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008704))
2621 +#define MCF_PSC_CSR1           (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008704))
2622 +#define MCF_PSC_CR1            (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008708))
2623 +#define MCF_PSC_RB1            (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C))
2624 +#define MCF_PSC_TB1            (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C))
2625 +#define MCF_PSC_TB_8BIT1       (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C))
2626 +#define MCF_PSC_TB_16BIT1      (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C))
2627 +#define MCF_PSC_TB_AC971       (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00870C))
2628 +#define MCF_PSC_IPCR1          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008710))
2629 +#define MCF_PSC_ACR1           (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008710))
2630 +#define MCF_PSC_ISR1           (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008714))
2631 +#define MCF_PSC_IMR1           (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008714))
2632 +#define MCF_PSC_CTUR1          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008718))
2633 +#define MCF_PSC_CTLR1          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00871C))
2634 +#define MCF_PSC_IP1            (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008734))
2635 +#define MCF_PSC_OPSET1         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008738))
2636 +#define MCF_PSC_OPRESET1       (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00873C))
2637 +#define MCF_PSC_SICR1          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008740))
2638 +#define MCF_PSC_IRCR11         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008744))
2639 +#define MCF_PSC_IRCR21         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008748))
2640 +#define MCF_PSC_IRSDR1         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00874C))
2641 +#define MCF_PSC_IRMDR1         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008750))
2642 +#define MCF_PSC_IRFDR1         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008754))
2643 +#define MCF_PSC_RFCNT1         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008758))
2644 +#define MCF_PSC_TFCNT1         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00875C))
2645 +#define MCF_PSC_RFSR1          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008764))
2646 +#define MCF_PSC_TFSR1          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008784))
2647 +#define MCF_PSC_RFCR1          (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008768))
2648 +#define MCF_PSC_TFCR1          (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008788))
2649 +#define MCF_PSC_RFAR1          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00876E))
2650 +#define MCF_PSC_TFAR1          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00878E))
2651 +#define MCF_PSC_RFRP1          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008772))
2652 +#define MCF_PSC_TFRP1          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008792))
2653 +#define MCF_PSC_RFWP1          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008776))
2654 +#define MCF_PSC_TFWP1          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008796))
2655 +#define MCF_PSC_RLRFP1         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00877A))
2656 +#define MCF_PSC_TLRFP1         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00879A))
2657 +#define MCF_PSC_RLWFP1         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00877E))
2658 +#define MCF_PSC_TLWFP1         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00879E))
2659 +#define MCF_PSC_MR2            (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008800))
2660 +#define MCF_PSC_SR2            (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008804))
2661 +#define MCF_PSC_CSR2           (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008804))
2662 +#define MCF_PSC_CR2            (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008808))
2663 +#define MCF_PSC_RB2            (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C))
2664 +#define MCF_PSC_TB2            (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C))
2665 +#define MCF_PSC_TB_8BIT2       (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C))
2666 +#define MCF_PSC_TB_16BIT2      (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C))
2667 +#define MCF_PSC_TB_AC972       (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00880C))
2668 +#define MCF_PSC_IPCR2          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008810))
2669 +#define MCF_PSC_ACR2           (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008810))
2670 +#define MCF_PSC_ISR2           (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008814))
2671 +#define MCF_PSC_IMR2           (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008814))
2672 +#define MCF_PSC_CTUR2          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008818))
2673 +#define MCF_PSC_CTLR2          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00881C))
2674 +#define MCF_PSC_IP2            (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008834))
2675 +#define MCF_PSC_OPSET2         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008838))
2676 +#define MCF_PSC_OPRESET2       (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00883C))
2677 +#define MCF_PSC_SICR2          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008840))
2678 +#define MCF_PSC_IRCR12         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008844))
2679 +#define MCF_PSC_IRCR22         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008848))
2680 +#define MCF_PSC_IRSDR2         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00884C))
2681 +#define MCF_PSC_IRMDR2         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008850))
2682 +#define MCF_PSC_IRFDR2         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008854))
2683 +#define MCF_PSC_RFCNT2         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008858))
2684 +#define MCF_PSC_TFCNT2         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00885C))
2685 +#define MCF_PSC_RFSR2          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008864))
2686 +#define MCF_PSC_TFSR2          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008884))
2687 +#define MCF_PSC_RFCR2          (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008868))
2688 +#define MCF_PSC_TFCR2          (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008888))
2689 +#define MCF_PSC_RFAR2          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00886E))
2690 +#define MCF_PSC_TFAR2          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00888E))
2691 +#define MCF_PSC_RFRP2          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008872))
2692 +#define MCF_PSC_TFRP2          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008892))
2693 +#define MCF_PSC_RFWP2          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008876))
2694 +#define MCF_PSC_TFWP2          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008896))
2695 +#define MCF_PSC_RLRFP2         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00887A))
2696 +#define MCF_PSC_TLRFP2         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00889A))
2697 +#define MCF_PSC_RLWFP2         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00887E))
2698 +#define MCF_PSC_TLWFP2         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00889E))
2699 +#define MCF_PSC_MR3            (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008900))
2700 +#define MCF_PSC_SR3            (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008904))
2701 +#define MCF_PSC_CSR3           (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008904))
2702 +#define MCF_PSC_CR3            (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008908))
2703 +#define MCF_PSC_RB3            (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C))
2704 +#define MCF_PSC_TB3            (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C))
2705 +#define MCF_PSC_TB_8BIT3       (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C))
2706 +#define MCF_PSC_TB_16BIT3      (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C))
2707 +#define MCF_PSC_TB_AC973       (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00890C))
2708 +#define MCF_PSC_IPCR3          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008910))
2709 +#define MCF_PSC_ACR3           (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008910))
2710 +#define MCF_PSC_ISR3           (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008914))
2711 +#define MCF_PSC_IMR3           (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008914))
2712 +#define MCF_PSC_CTUR3          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008918))
2713 +#define MCF_PSC_CTLR3          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00891C))
2714 +#define MCF_PSC_IP3            (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008934))
2715 +#define MCF_PSC_OPSET3         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008938))
2716 +#define MCF_PSC_OPRESET3       (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00893C))
2717 +#define MCF_PSC_SICR3          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008940))
2718 +#define MCF_PSC_IRCR13         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008944))
2719 +#define MCF_PSC_IRCR23         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008948))
2720 +#define MCF_PSC_IRSDR3         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00894C))
2721 +#define MCF_PSC_IRMDR3         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008950))
2722 +#define MCF_PSC_IRFDR3         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008954))
2723 +#define MCF_PSC_RFCNT3         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008958))
2724 +#define MCF_PSC_TFCNT3         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00895C))
2725 +#define MCF_PSC_RFSR3          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008964))
2726 +#define MCF_PSC_TFSR3          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008984))
2727 +#define MCF_PSC_RFCR3          (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008968))
2728 +#define MCF_PSC_TFCR3          (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008988))
2729 +#define MCF_PSC_RFAR3          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00896E))
2730 +#define MCF_PSC_TFAR3          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00898E))
2731 +#define MCF_PSC_RFRP3          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008972))
2732 +#define MCF_PSC_TFRP3          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008992))
2733 +#define MCF_PSC_RFWP3          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008976))
2734 +#define MCF_PSC_TFWP3          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008996))
2735 +#define MCF_PSC_RLRFP3         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00897A))
2736 +#define MCF_PSC_TLRFP3         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00899A))
2737 +#define MCF_PSC_RLWFP3         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00897E))
2738 +#define MCF_PSC_TLWFP3         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00899E))
2739 +#define MCF_PSC_MR(x)          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008600+((x)*0x100)))
2740 +#define MCF_PSC_SR(x)          (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008604+((x)*0x100)))
2741 +#define MCF_PSC_CSR(x)         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008604+((x)*0x100)))
2742 +#define MCF_PSC_CR(x)          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008608+((x)*0x100)))
2743 +#define MCF_PSC_RB(x)          (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100)))
2744 +#define MCF_PSC_TB(x)          (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100)))
2745 +#define MCF_PSC_TB_8BIT(x)     (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100)))
2746 +#define MCF_PSC_TB_16BIT(x)    (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100)))
2747 +#define MCF_PSC_TB_AC97(x)     (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x00860C+((x)*0x100)))
2748 +#define MCF_PSC_IPCR(x)        (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008610+((x)*0x100)))
2749 +#define MCF_PSC_ACR(x)         (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008610+((x)*0x100)))
2750 +#define MCF_PSC_ISR(x)         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008614+((x)*0x100)))
2751 +#define MCF_PSC_IMR(x)         (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008614+((x)*0x100)))
2752 +#define MCF_PSC_CTUR(x)        (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008618+((x)*0x100)))
2753 +#define MCF_PSC_CTLR(x)        (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00861C+((x)*0x100)))
2754 +#define MCF_PSC_IP(x)          (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008634+((x)*0x100)))
2755 +#define MCF_PSC_OPSET(x)       (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008638+((x)*0x100)))
2756 +#define MCF_PSC_OPRESET(x)     (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00863C+((x)*0x100)))
2757 +#define MCF_PSC_SICR(x)        (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008640+((x)*0x100)))
2758 +#define MCF_PSC_IRCR1(x)       (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008644+((x)*0x100)))
2759 +#define MCF_PSC_IRCR2(x)       (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008648+((x)*0x100)))
2760 +#define MCF_PSC_IRSDR(x)       (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x00864C+((x)*0x100)))
2761 +#define MCF_PSC_IRMDR(x)       (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008650+((x)*0x100)))
2762 +#define MCF_PSC_IRFDR(x)       (*(volatile uint8_t *)(void*)(MCF_MBAR + 0x008654+((x)*0x100)))
2763 +#define MCF_PSC_RFCNT(x)       (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008658+((x)*0x100)))
2764 +#define MCF_PSC_TFCNT(x)       (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00865C+((x)*0x100)))
2765 +#define MCF_PSC_RFSR(x)        (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008664+((x)*0x100)))
2766 +#define MCF_PSC_TFSR(x)        (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008684+((x)*0x100)))
2767 +#define MCF_PSC_RFCR(x)        (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008668+((x)*0x100)))
2768 +#define MCF_PSC_TFCR(x)        (*(volatile uint32_t*)(void*)(MCF_MBAR + 0x008688+((x)*0x100)))
2769 +#define MCF_PSC_RFAR(x)        (*(volatile uint16_t*)(void*)(MCF_MBAR + (0x00866E)+((x)*0x100)))
2770 +#define MCF_PSC_TFAR(x)        (*(volatile uint16_t*)(void*)(MCF_MBAR + (0x00868E)+((x)*0x100)))
2771 +#define MCF_PSC_RFRP(x)        (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008672+((x)*0x100)))
2772 +#define MCF_PSC_TFRP(x)        (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008692+((x)*0x100)))
2773 +#define MCF_PSC_RFWP(x)        (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008676+((x)*0x100)))
2774 +#define MCF_PSC_TFWP(x)        (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x008696+((x)*0x100)))
2775 +#define MCF_PSC_RLRFP(x)       (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00867A+((x)*0x100)))
2776 +#define MCF_PSC_TLRFP(x)       (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00869A+((x)*0x100)))
2777 +#define MCF_PSC_RLWFP(x)       (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00867E+((x)*0x100)))
2778 +#define MCF_PSC_TLWFP(x)       (*(volatile uint16_t*)(void*)(MCF_MBAR + 0x00869E+((x)*0x100)))
2779 +
2780 +/* Bit definitions and macros for MCF_PSC_MR */
2781 +#define MCF_PSC_MR_BC(x)              (((x)&0x03)<<0)
2782 +#define MCF_PSC_MR_PT                 (0x04)
2783 +#define MCF_PSC_MR_PM(x)              (((x)&0x03)<<3)
2784 +#define MCF_PSC_MR_ERR                (0x20)
2785 +#define MCF_PSC_MR_RXIRQ              (0x40)
2786 +#define MCF_PSC_MR_RXRTS              (0x80)
2787 +#define MCF_PSC_MR_SB(x)              (((x)&0x0F)<<0)
2788 +#define MCF_PSC_MR_TXCTS              (0x10)
2789 +#define MCF_PSC_MR_TXRTS              (0x20)
2790 +#define MCF_PSC_MR_CM(x)              (((x)&0x03)<<6)
2791 +#define MCF_PSC_MR_PM_MULTI_ADDR      (0x1C)
2792 +#define MCF_PSC_MR_PM_MULTI_DATA      (0x18)
2793 +#define MCF_PSC_MR_PM_NONE            (0x10)
2794 +#define MCF_PSC_MR_PM_FORCE_HI        (0x0C)
2795 +#define MCF_PSC_MR_PM_FORCE_LO        (0x08)
2796 +#define MCF_PSC_MR_PM_ODD             (0x04)
2797 +#define MCF_PSC_MR_PM_EVEN            (0x00)
2798 +#define MCF_PSC_MR_BC_5               (0x00)
2799 +#define MCF_PSC_MR_BC_6               (0x01)
2800 +#define MCF_PSC_MR_BC_7               (0x02)
2801 +#define MCF_PSC_MR_BC_8               (0x03)
2802 +#define MCF_PSC_MR_CM_NORMAL          (0x00)
2803 +#define MCF_PSC_MR_CM_ECHO            (0x40)
2804 +#define MCF_PSC_MR_CM_LOCAL_LOOP      (0x80)
2805 +#define MCF_PSC_MR_CM_REMOTE_LOOP     (0xC0)
2806 +#define MCF_PSC_MR_SB_STOP_BITS_1     (0x07)
2807 +#define MCF_PSC_MR_SB_STOP_BITS_15    (0x08)
2808 +#define MCF_PSC_MR_SB_STOP_BITS_2     (0x0F)
2809 +
2810 +/* Bit definitions and macros for MCF_PSC_SR */
2811 +#define MCF_PSC_SR_ERR                (0x0040)
2812 +#define MCF_PSC_SR_CDE_DEOF           (0x0080)
2813 +#define MCF_PSC_SR_RXRDY              (0x0100)
2814 +#define MCF_PSC_SR_FU                 (0x0200)
2815 +#define MCF_PSC_SR_TXRDY              (0x0400)
2816 +#define MCF_PSC_SR_TXEMP_URERR        (0x0800)
2817 +#define MCF_PSC_SR_OE                 (0x1000)
2818 +#define MCF_PSC_SR_PE_CRCERR          (0x2000)
2819 +#define MCF_PSC_SR_FE_PHYERR          (0x4000)
2820 +#define MCF_PSC_SR_RB_NEOF            (0x8000)
2821 +
2822 +/* Bit definitions and macros for MCF_PSC_CSR */
2823 +#define MCF_PSC_CSR_TCSEL(x)          (((x)&0x0F)<<0)
2824 +#define MCF_PSC_CSR_RCSEL(x)          (((x)&0x0F)<<4)
2825 +#define MCF_PSC_CSR_RCSEL_SYS_CLK     (0xD0)
2826 +#define MCF_PSC_CSR_RCSEL_CTM16       (0xE0)
2827 +#define MCF_PSC_CSR_RCSEL_CTM         (0xF0)
2828 +#define MCF_PSC_CSR_TCSEL_SYS_CLK     (0x0D)
2829 +#define MCF_PSC_CSR_TCSEL_CTM16       (0x0E)
2830 +#define MCF_PSC_CSR_TCSEL_CTM         (0x0F)
2831 +
2832 +/* Bit definitions and macros for MCF_PSC_CR */
2833 +#define MCF_PSC_CR_RXC(x)             (((x)&0x03)<<0)
2834 +#define MCF_PSC_CR_TXC(x)             (((x)&0x03)<<2)
2835 +#define MCF_PSC_CR_MISC(x)            (((x)&0x07)<<4)
2836 +#define MCF_PSC_CR_NONE               (0x00)
2837 +#define MCF_PSC_CR_STOP_BREAK         (0x70)
2838 +#define MCF_PSC_CR_START_BREAK        (0x60)
2839 +#define MCF_PSC_CR_BKCHGINT           (0x50)
2840 +#define MCF_PSC_CR_RESET_ERROR        (0x40)
2841 +#define MCF_PSC_CR_RESET_TX           (0x30)
2842 +#define MCF_PSC_CR_RESET_RX           (0x20)
2843 +#define MCF_PSC_CR_RESET_MR           (0x10)
2844 +#define MCF_PSC_CR_TX_DISABLED        (0x08)
2845 +#define MCF_PSC_CR_TX_ENABLED         (0x04)
2846 +#define MCF_PSC_CR_RX_DISABLED        (0x02)
2847 +#define MCF_PSC_CR_RX_ENABLED         (0x01)
2848 +
2849 +/* Bit definitions and macros for MCF_PSC_TB_8BIT */
2850 +#define MCF_PSC_TB_8BIT_TB3(x)        (((x)&0x000000FF)<<0)
2851 +#define MCF_PSC_TB_8BIT_TB2(x)        (((x)&0x000000FF)<<8)
2852 +#define MCF_PSC_TB_8BIT_TB1(x)        (((x)&0x000000FF)<<16)
2853 +#define MCF_PSC_TB_8BIT_TB0(x)        (((x)&0x000000FF)<<24)
2854 +
2855 +/* Bit definitions and macros for MCF_PSC_TB_16BIT */
2856 +#define MCF_PSC_TB_16BIT_TB1(x)       (((x)&0x0000FFFF)<<0)
2857 +#define MCF_PSC_TB_16BIT_TB0(x)       (((x)&0x0000FFFF)<<16)
2858 +
2859 +/* Bit definitions and macros for MCF_PSC_TB_AC97 */
2860 +#define MCF_PSC_TB_AC97_SOF           (0x00000800)
2861 +#define MCF_PSC_TB_AC97_TB(x)         (((x)&0x000FFFFF)<<12)
2862 +
2863 +/* Bit definitions and macros for MCF_PSC_IPCR */
2864 +#define MCF_PSC_IPCR_RESERVED         (0x0C)
2865 +#define MCF_PSC_IPCR_CTS              (0x0D)
2866 +#define MCF_PSC_IPCR_D_CTS            (0x1C)
2867 +#define MCF_PSC_IPCR_SYNC             (0x8C)
2868 +
2869 +/* Bit definitions and macros for MCF_PSC_ACR */
2870 +#define MCF_PSC_ACR_IEC0              (0x01)
2871 +#define MCF_PSC_ACR_CTMS(x)           (((x)&0x07)<<4)
2872 +#define MCF_PSC_ACR_BRG               (0x80)
2873 +
2874 +/* Bit definitions and macros for MCF_PSC_ISR */
2875 +#define MCF_PSC_ISR_ERR               (0x0040)
2876 +#define MCF_PSC_ISR_DEOF              (0x0080)
2877 +#define MCF_PSC_ISR_TXRDY             (0x0100)
2878 +#define MCF_PSC_ISR_RXRDY_FU          (0x0200)
2879 +#define MCF_PSC_ISR_DB                (0x0400)
2880 +#define MCF_PSC_ISR_IPC               (0x8000)
2881 +
2882 +/* Bit definitions and macros for MCF_PSC_IMR */
2883 +#define MCF_PSC_IMR_ERR               (0x0040)
2884 +#define MCF_PSC_IMR_DEOF              (0x0080)
2885 +#define MCF_PSC_IMR_TXRDY             (0x0100)
2886 +#define MCF_PSC_IMR_RXRDY_FU          (0x0200)
2887 +#define MCF_PSC_IMR_DB                (0x0400)
2888 +#define MCF_PSC_IMR_IPC               (0x8000)
2889 +
2890 +/* Bit definitions and macros for MCF_PSC_IP */
2891 +#define MCF_PSC_IP_CTS                (0x01)
2892 +#define MCF_PSC_IP_TGL                (0x40)
2893 +#define MCF_PSC_IP_LWPR_B             (0x80)
2894 +
2895 +/* Bit definitions and macros for MCF_PSC_OPSET */
2896 +#define MCF_PSC_OPSET_RTS             (0x01)
2897 +
2898 +/* Bit definitions and macros for MCF_PSC_OPRESET */
2899 +#define MCF_PSC_OPRESET_RTS           (0x01)
2900 +
2901 +/* Bit definitions and macros for MCF_PSC_SICR */
2902 +#define MCF_PSC_SICR_SIM(x)           (((x)&0x07)<<0)
2903 +#define MCF_PSC_SICR_SHDIR            (0x10)
2904 +#define MCF_PSC_SICR_DTS              (0x20)
2905 +#define MCF_PSC_SICR_AWR              (0x40)
2906 +#define MCF_PSC_SICR_ACRB             (0x80)
2907 +#define MCF_PSC_SICR_SIM_UART         (0x00)
2908 +#define MCF_PSC_SICR_SIM_MODEM8       (0x01)
2909 +#define MCF_PSC_SICR_SIM_MODEM16      (0x02)
2910 +#define MCF_PSC_SICR_SIM_AC97         (0x03)
2911 +#define MCF_PSC_SICR_SIM_SIR          (0x04)
2912 +#define MCF_PSC_SICR_SIM_MIR          (0x05)
2913 +#define MCF_PSC_SICR_SIM_FIR          (0x06)
2914 +
2915 +/* Bit definitions and macros for MCF_PSC_IRCR1 */
2916 +#define MCF_PSC_IRCR1_SPUL            (0x01)
2917 +#define MCF_PSC_IRCR1_SIPEN           (0x02)
2918 +#define MCF_PSC_IRCR1_FD              (0x04)
2919 +
2920 +/* Bit definitions and macros for MCF_PSC_IRCR2 */
2921 +#define MCF_PSC_IRCR2_NXTEOF          (0x01)
2922 +#define MCF_PSC_IRCR2_ABORT           (0x02)
2923 +#define MCF_PSC_IRCR2_SIPREQ          (0x04)
2924 +
2925 +/* Bit definitions and macros for MCF_PSC_IRMDR */
2926 +#define MCF_PSC_IRMDR_M_FDIV(x)       (((x)&0x7F)<<0)
2927 +#define MCF_PSC_IRMDR_FREQ            (0x80)
2928 +
2929 +/* Bit definitions and macros for MCF_PSC_IRFDR */
2930 +#define MCF_PSC_IRFDR_F_FDIV(x)       (((x)&0x0F)<<0)
2931 +
2932 +/* Bit definitions and macros for MCF_PSC_RFCNT */
2933 +#define MCF_PSC_RFCNT_CNT(x)          (((x)&0x01FF)<<0)
2934 +
2935 +/* Bit definitions and macros for MCF_PSC_TFCNT */
2936 +#define MCF_PSC_TFCNT_CNT(x)          (((x)&0x01FF)<<0)
2937 +
2938 +/* Bit definitions and macros for MCF_PSC_RFSR */
2939 +#define MCF_PSC_RFSR_EMT              (0x0001)
2940 +#define MCF_PSC_RFSR_ALARM            (0x0002)
2941 +#define MCF_PSC_RFSR_FU               (0x0004)
2942 +#define MCF_PSC_RFSR_FRMRY            (0x0008)
2943 +#define MCF_PSC_RFSR_OF               (0x0010)
2944 +#define MCF_PSC_RFSR_UF               (0x0020)
2945 +#define MCF_PSC_RFSR_RXW              (0x0040)
2946 +#define MCF_PSC_RFSR_FAE              (0x0080)
2947 +#define MCF_PSC_RFSR_FRM(x)           (((x)&0x000F)<<8)
2948 +#define MCF_PSC_RFSR_TAG              (0x1000)
2949 +#define MCF_PSC_RFSR_TXW              (0x4000)
2950 +#define MCF_PSC_RFSR_IP               (0x8000)
2951 +#define MCF_PSC_RFSR_FRM_BYTE0        (0x0800)
2952 +#define MCF_PSC_RFSR_FRM_BYTE1        (0x0400)
2953 +#define MCF_PSC_RFSR_FRM_BYTE2        (0x0200)
2954 +#define MCF_PSC_RFSR_FRM_BYTE3        (0x0100)
2955 +
2956 +/* Bit definitions and macros for MCF_PSC_TFSR */
2957 +#define MCF_PSC_TFSR_EMT              (0x0001)
2958 +#define MCF_PSC_TFSR_ALARM            (0x0002)
2959 +#define MCF_PSC_TFSR_FU               (0x0004)
2960 +#define MCF_PSC_TFSR_FRMRY            (0x0008)
2961 +#define MCF_PSC_TFSR_OF               (0x0010)
2962 +#define MCF_PSC_TFSR_UF               (0x0020)
2963 +#define MCF_PSC_TFSR_RXW              (0x0040)
2964 +#define MCF_PSC_TFSR_FAE              (0x0080)
2965 +#define MCF_PSC_TFSR_FRM(x)           (((x)&0x000F)<<8)
2966 +#define MCF_PSC_TFSR_TAG              (0x1000)
2967 +#define MCF_PSC_TFSR_TXW              (0x4000)
2968 +#define MCF_PSC_TFSR_IP               (0x8000)
2969 +#define MCF_PSC_TFSR_FRM_BYTE0        (0x0800)
2970 +#define MCF_PSC_TFSR_FRM_BYTE1        (0x0400)
2971 +#define MCF_PSC_TFSR_FRM_BYTE2        (0x0200)
2972 +#define MCF_PSC_TFSR_FRM_BYTE3        (0x0100)
2973 +
2974 +/* Bit definitions and macros for MCF_PSC_RFCR */
2975 +#define MCF_PSC_RFCR_CNTR(x)          (((x)&0x0000FFFF)<<0)
2976 +#define MCF_PSC_RFCR_TXW_MSK          (0x00040000)
2977 +#define MCF_PSC_RFCR_OF_MSK           (0x00080000)
2978 +#define MCF_PSC_RFCR_UF_MSK           (0x00100000)
2979 +#define MCF_PSC_RFCR_RXW_MSK          (0x00200000)
2980 +#define MCF_PSC_RFCR_FAE_MSK          (0x00400000)
2981 +#define MCF_PSC_RFCR_IP_MSK           (0x00800000)
2982 +#define MCF_PSC_RFCR_GR(x)            (((x)&0x00000007)<<24)
2983 +#define MCF_PSC_RFCR_FRMEN            (0x08000000)
2984 +#define MCF_PSC_RFCR_TIMER            (0x10000000)
2985 +#define MCF_PSC_RFCR_WRITETAG         (0x20000000)
2986 +#define MCF_PSC_RFCR_SHADOW           (0x80000000)
2987 +
2988 +/* Bit definitions and macros for MCF_PSC_TFCR */
2989 +#define MCF_PSC_TFCR_CNTR(x)          (((x)&0x0000FFFF)<<0)
2990 +#define MCF_PSC_TFCR_TXW_MSK          (0x00040000)
2991 +#define MCF_PSC_TFCR_OF_MSK           (0x00080000)
2992 +#define MCF_PSC_TFCR_UF_MSK           (0x00100000)
2993 +#define MCF_PSC_TFCR_RXW_MSK          (0x00200000)
2994 +#define MCF_PSC_TFCR_FAE_MSK          (0x00400000)
2995 +#define MCF_PSC_TFCR_IP_MSK           (0x00800000)
2996 +#define MCF_PSC_TFCR_GR(x)            (((x)&0x00000007)<<24)
2997 +#define MCF_PSC_TFCR_FRMEN            (0x08000000)
2998 +#define MCF_PSC_TFCR_TIMER            (0x10000000)
2999 +#define MCF_PSC_TFCR_WRITETAG         (0x20000000)
3000 +#define MCF_PSC_TFCR_SHADOW           (0x80000000)
3001 +
3002 +/* Bit definitions and macros for MCF_PSC_RFAR */
3003 +#define MCF_PSC_RFAR_ALARM(x)         (((x)&0x01FF)<<0)
3004 +
3005 +/* Bit definitions and macros for MCF_PSC_TFAR */
3006 +#define MCF_PSC_TFAR_ALARM(x)         (((x)&0x01FF)<<0)
3007 +
3008 +/* Bit definitions and macros for MCF_PSC_RFRP */
3009 +#define MCF_PSC_RFRP_READ(x)          (((x)&0x01FF)<<0)
3010 +
3011 +/* Bit definitions and macros for MCF_PSC_TFRP */
3012 +#define MCF_PSC_TFRP_READ(x)          (((x)&0x01FF)<<0)
3013 +
3014 +/* Bit definitions and macros for MCF_PSC_RFWP */
3015 +#define MCF_PSC_RFWP_WRITE(x)         (((x)&0x01FF)<<0)
3016 +
3017 +/* Bit definitions and macros for MCF_PSC_TFWP */
3018 +#define MCF_PSC_TFWP_WRITE(x)         (((x)&0x01FF)<<0)
3019 +
3020 +/* Bit definitions and macros for MCF_PSC_RLRFP */
3021 +#define MCF_PSC_RLRFP_LFP(x)          (((x)&0x01FF)<<0)
3022 +
3023 +/* Bit definitions and macros for MCF_PSC_TLRFP */
3024 +#define MCF_PSC_TLRFP_LFP(x)          (((x)&0x01FF)<<0)
3025 +
3026 +/* Bit definitions and macros for MCF_PSC_RLWFP */
3027 +#define MCF_PSC_RLWFP_LFP(x)          (((x)&0x01FF)<<0)
3028 +
3029 +/* Bit definitions and macros for MCF_PSC_TLWFP */
3030 +#define MCF_PSC_TLWFP_LFP(x)          (((x)&0x01FF)<<0)
3031 +
3032 +/********************************************************************/
3033 +
3034 +#endif /* __MCF548X_PSC_H__ */
3035 --- /dev/null
3036 +++ b/include/asm-m68k/m5485sim.h
3037 @@ -0,0 +1,219 @@
3038 +/*
3039 + *     m5485sim.h -- ColdFire 547x/548x System Integration Unit support.
3040 + */
3041 +
3042 +#ifndef        m5485sim_h
3043 +#define        m5485sim_h
3044 +
3045 +
3046 +/*
3047 + *      System Integration Unit Registers
3048 + */
3049 +#define MCF_SDRAMDS    MCF_REG32(0x000004)     /* SDRAM Drive Strength         */
3050 +#define MCF_SBCR               MCF_REG32(0x000010)     /* System Breakpoint Control    */
3051 +#define MCF_CSnCFG(x)  MCF_REG32(0x000020+(x*4))/* SDRAM Chip Select X         */
3052 +#define MCF_SECSACR     MCF_REG32(0x000038)    /* Sequential Access Control    */
3053 +#define MCF_RSR         MCF_REG32(0x000044)    /* Reset Status                 */
3054 +#define MCF_JTAGID      MCF_REG32(0x000050)    /* JTAG Device Identification   */
3055 +
3056 +/*
3057 + *      FlexBus Chip Selects Registers
3058 + */
3059 +#define MCF_CSARn(x)    MCF_REG32(0x000500+(x*0xC))
3060 +#define MCF_CSMRn(x)    MCF_REG32(0x000504+(x*0xC))
3061 +#define MCF_CSCRn(x)    MCF_REG32(0x000508+(x*0xC))
3062 +
3063 +/*
3064 + *      Interrupt Controller Registers
3065 + */
3066 +#define MCF_IPRH       MCF_REG32(0x000700)
3067 +#define MCF_IPRL       MCF_REG32(0x000704)
3068 +#define MCF_IMRH       MCF_REG32(0x000708)
3069 +#define MCF_IMRL       MCF_REG32(0x00070C)
3070 +#define MCF_INTFRCH    MCF_REG32(0x000710)
3071 +#define MCF_INTFRCL    MCF_REG32(0x000714)
3072 +#define MCF_IRLR       MCF_REG08(0x000718)
3073 +#define MCF_IACKLPR    MCF_REG08(0x000719)
3074 +#define MCF_SWIACK     MCF_REG08(0x0007E0)
3075 +#define MCF_LnIACK(x)  MCF_REG08(0x0007E4+((x)*0x004))
3076 +#define MCF_ICR(x)     MCF_REG08(0x000740+((x)*0x001))
3077 +
3078 +/*
3079 + *     Slice Timers Registers
3080 + */
3081 +#define MCF_SLTCNT(x)   MCF_REG32(0x000900+((x)*0x010))
3082 +#define MCF_SCR(x)      MCF_REG32(0x000904+((x)*0x010))
3083 +#define MCF_SCNT(x)     MCF_REG32(0x000908+((x)*0x010))
3084 +#define MCF_SSR(x)      MCF_REG32(0x00090C+((x)*0x010))
3085 +
3086 +/*
3087 + *     Interrupt sources
3088 + */
3089 +#define ISC_EPORT_Fn(x)                (x)             /* EPORT Interrupts     */
3090 +#define ISC_USB_EPn(x)         (15+(x))        /* USB Endopint         */
3091 +#define ISC_USB_ISR            (22)            /* USB General source   */
3092 +#define ISC_USB_AISR           (22)            /* USB core source      */
3093 +#define ISC_DSPI_OVRFW         (25)            /* DSPI overflow        */
3094 +#define ISC_DSPI_RFOF          (26)
3095 +#define ISC_DSPI_RFDF          (27)
3096 +#define ISC_DSPI_TFUF          (28)
3097 +#define ISC_DSPI_TCF           (29)
3098 +#define ISC_DSPI_TFFF          (30)
3099 +#define ISC_DSPI_EOQF          (31)
3100 +#define ISC_PSCn(x)            (35-(x))
3101 +#define ISC_COMM_TIM           (36)
3102 +#define ISC_SEC                        (37)
3103 +#define ISC_FEC1               (38)
3104 +#define ISC_FEC0               (39)
3105 +#define ISC_I2C                        (40)
3106 +#define ISC_PCI_ARB            (41)
3107 +#define ISC_PCI_CB             (42)
3108 +#define ISC_PCI_XLB            (43)
3109 +#define ISC_DMA                        (48)
3110 +#define ISC_CANn_ERR(x)                (49+(6*(x)))
3111 +#define ISC_CANn_BUSOFF(x)     (50+(6*(x)))
3112 +#define ISC_CANn_MBOR(x)       (51+(6*(x)))
3113 +#define ISC_CAN0_WAKEIN                (52)
3114 +#define ISC_SLTn(x)            (54-(x))
3115 +#define ISC_GPTn(x)            (62-(x))
3116 +
3117 +/*
3118 + *     Interrupt level and priorities
3119 + */
3120 +#define ILP_TOP                        (MCF_ICR_IL(5) | MCF_ICR_IP(3))
3121 +#define ILP_SLT0               (MCF_ICR_IL(5) | MCF_ICR_IP(2))
3122 +#define ILP_SLT1               (MCF_ICR_IL(5) | MCF_ICR_IP(1))
3123 +#define ILP_DMA                        (MCF_ICR_IL(5) | MCF_ICR_IP(0))
3124 +#define ILP_SEC                        (MCF_ICR_IL(4) | MCF_ICR_IP(7))
3125 +#define ILP_FEC0               (MCF_ICR_IL(4) | MCF_ICR_IP(6))
3126 +#define ILP_FEC1               (MCF_ICR_IL(4) | MCF_ICR_IP(5))
3127 +#define ILP_PCI_XLB            (MCF_ICR_IL(4) | MCF_ICR_IP(4))
3128 +#define ILP_PCI_ARB            (MCF_ICR_IL(4) | MCF_ICR_IP(3))
3129 +#define ILP_PCI_CB             (MCF_ICR_IL(4) | MCF_ICR_IP(2))
3130 +#define ILP_I2C                        (MCF_ICR_IL(4) | MCF_ICR_IP(1))
3131 +
3132 +#define ILP_USB_EPn(x)         (MCF_ICR_IL(3) | MCF_ICR_IP(7-(x)))
3133 +#define ILP_USB_EP0            (MCF_ICR_IL(3) | MCF_ICR_IP(7))
3134 +#define ILP_USB_EP1            (MCF_ICR_IL(3) | MCF_ICR_IP(6))
3135 +#define ILP_USB_EP2            (MCF_ICR_IL(3) | MCF_ICR_IP(5))
3136 +#define ILP_USB_EP3            (MCF_ICR_IL(3) | MCF_ICR_IP(4))
3137 +#define ILP_USB_EP4            (MCF_ICR_IL(3) | MCF_ICR_IP(3))
3138 +#define ILP_USB_EP5            (MCF_ICR_IL(3) | MCF_ICR_IP(2))
3139 +#define ILP_USB_EP6            (MCF_ICR_IL(3) | MCF_ICR_IP(1))
3140 +#define ILP_USB_ISR            (MCF_ICR_IL(3) | MCF_ICR_IP(0))
3141 +
3142 +#define ILP_USB_AISR           (MCF_ICR_IL(2) | MCF_ICR_IP(7))
3143 +#define ILP_DSPI_OVRFW         (MCF_ICR_IL(2) | MCF_ICR_IP(6))
3144 +#define ILP_DSPI_RFOF          (MCF_ICR_IL(2) | MCF_ICR_IP(5))
3145 +#define ILP_DSPI_RFDF          (MCF_ICR_IL(2) | MCF_ICR_IP(4))
3146 +#define ILP_DSPI_TFUF          (MCF_ICR_IL(2) | MCF_ICR_IP(3))
3147 +#define ILP_DSPI_TCF           (MCF_ICR_IL(2) | MCF_ICR_IP(2))
3148 +#define ILP_DSPI_TFFF          (MCF_ICR_IL(2) | MCF_ICR_IP(1))
3149 +#define ILP_DSPI_EOQF          (MCF_ICR_IL(2) | MCF_ICR_IP(0))
3150 +
3151 +#define ILP_COMM_TIM           (MCF_ICR_IL(1) | MCF_ICR_IP(7))
3152 +#define ILP_PSCn(x)            (MCF_ICR_IL(1) | MCF_ICR_IP(3-((x)&3)))
3153 +#define ILP_PSC0               (MCF_ICR_IL(1) | MCF_ICR_IP(3))
3154 +#define ILP_PSC1               (MCF_ICR_IL(1) | MCF_ICR_IP(2))
3155 +#define ILP_PSC2               (MCF_ICR_IL(1) | MCF_ICR_IP(1))
3156 +#define ILP_PSC3               (MCF_ICR_IL(1) | MCF_ICR_IP(0))
3157 +
3158 +
3159 +
3160 +
3161 +
3162 +/********************************************************************/
3163 +
3164 +/*
3165 + *      System Integration Unit Bitfields
3166 + */
3167 +
3168 +/* SBCR */
3169 +#define MCF_SBCR_PIN2DSPI       (0x08000000)
3170 +#define MCF_SBCR_DMA2CPU        (0x10000000)
3171 +#define MCF_SBCR_CPU2DMA        (0x20000000)
3172 +#define MCF_SBCR_PIN2DMA        (0x40000000)
3173 +#define MCF_SBCR_PIN2CPU        (0x80000000)
3174 +
3175 +/* SECSACR */
3176 +#define MCF_SECSACR_SEQEN       (0x00000001)
3177 +
3178 +/* RSR */
3179 +#define MCF_RSR_RST             (0x00000001)
3180 +#define MCF_RSR_RSTWD           (0x00000002)
3181 +#define MCF_RSR_RSTJTG          (0x00000008)
3182 +
3183 +/* JTAGID */
3184 +#define MCF_JTAGID_REV          (0xF0000000)
3185 +#define MCF_JTAGID_PROCESSOR    (0x0FFFFFFF)
3186 +#define MCF_JTAGID_MCF5485      (0x0800C01D)
3187 +#define MCF_JTAGID_MCF5484      (0x0800D01D)
3188 +#define MCF_JTAGID_MCF5483      (0x0800E01D)
3189 +#define MCF_JTAGID_MCF5482      (0x0800F01D)
3190 +#define MCF_JTAGID_MCF5481      (0x0801001D)
3191 +#define MCF_JTAGID_MCF5480      (0x0801101D)
3192 +#define MCF_JTAGID_MCF5475      (0x0801201D)
3193 +#define MCF_JTAGID_MCF5474      (0x0801301D)
3194 +#define MCF_JTAGID_MCF5473      (0x0801401D)
3195 +#define MCF_JTAGID_MCF5472      (0x0801501D)
3196 +#define MCF_JTAGID_MCF5471      (0x0801601D)
3197 +#define MCF_JTAGID_MCF5470      (0x0801701D)
3198 +
3199 +
3200 +/*
3201 + *      Interrupt Controller Bitfields
3202 + */
3203 +#define MCF_IRLR_IRQ(x)         (((x)&0x7F)<<1)
3204 +#define MCF_IACKLPR_PRI(x)      (((x)&0x0F)<<0)
3205 +#define MCF_IACKLPR_LEVEL(x)    (((x)&0x07)<<4)
3206 +#define MCF_ICR_IP(x)           (((x)&0x07)<<0)
3207 +#define MCF_ICR_IL(x)           (((x)&0x07)<<3)
3208 +
3209 +/*
3210 + *      Slice Timers Bitfields
3211 + */
3212 +#define MCF_SCR_TEN                    (0x01000000)
3213 +#define MCF_SCR_IEN                    (0x02000000)
3214 +#define MCF_SCR_RUN                    (0x04000000)
3215 +#define MCF_SSR_ST                     (0x01000000)
3216 +#define MCF_SSR_BE                     (0x02000000)
3217 +
3218 +
3219 +/*
3220 + * Some needed coldfire registers
3221 + */
3222 +#define MCF_PAR_PCIBG             MCF_REG16(0x000A48)
3223 +#define MCF_PAR_PCIBR             MCF_REG16(0x000A4A)
3224 +#define MCF_PAR_PSCn(x)            MCF_REG08(0x000A4F-((x)&0x3))
3225 +#define MCF_PAR_FECI2CIRQ         MCF_REG16(0x000A44)
3226 +#define MCF_EPPAR                 MCF_REG16(0x000F00)
3227 +#define MCF_EPIER                 MCF_REG08(0x000F05)
3228 +#define MCF_EPFR                          MCF_REG08(0x000F0C)
3229 +
3230 +/*
3231 + * Some GPIO bitfields
3232 + */
3233 +#define MCF_PAR_SDA                    (0x0008)
3234 +#define MCF_PAR_SCL                    (0x0004)
3235 +#define MCF_PAR_PSC_TXD                (0x04)
3236 +#define MCF_PAR_PSC_RXD                (0x08)
3237 +#define MCF_PAR_PSC_RTS(x)             (((x)&0x03)<<4)
3238 +#define MCF_PAR_PSC_CTS(x)             (((x)&0x03)<<6)
3239 +#define MCF_PAR_PSC_CTS_GPIO           (0x00)
3240 +#define MCF_PAR_PSC_CTS_BCLK           (0x80)
3241 +#define MCF_PAR_PSC_CTS_CTS            (0xC0)
3242 +#define MCF_PAR_PSC_RTS_GPIO           (0x00)
3243 +#define MCF_PAR_PSC_RTS_FSYNC          (0x20)
3244 +#define MCF_PAR_PSC_RTS_RTS            (0x30)
3245 +#define MCF_PAR_PSC_CANRX              (0x40)
3246 +
3247 +
3248 +/*
3249 + * Some used coldfire values
3250 + */
3251 +#define MCF_EPIER_EPIE(x)          (0x01 << (x))
3252 +#define MCF_EPPAR_EPPAx_FALLING    (2)
3253 +#define MCF_EPPAR_EPPA(n,x)        (((x)&0x0003) << (2*n))
3254 +
3255 +
3256 +#endif /* m5485sim_h */
3257 --- a/include/asm-m68k/mcfsim.h
3258 +++ b/include/asm-m68k/mcfsim.h
3259 @@ -20,6 +20,11 @@
3260  #include <asm/mcf5445x_pci.h>
3261  #include <asm/mcf5445x_pciarb.h>
3262  #include <asm/mcf5445x_eport.h>
3263 +#include <asm/mcf5445x_fbcs.h>
3264 +#include <asm/mcf5445x_xbs.h>
3265 +#include <asm/mcf5445x_dtim.h>
3266 +#elif defined(CONFIG_M547X_8X)
3267 +#include <asm/m5485sim.h>
3268  #endif
3269
3270  /*
3271 --- a/include/asm-m68k/mcfuart.h
3272 +++ b/include/asm-m68k/mcfuart.h
3273 @@ -22,6 +22,15 @@
3274  #define MCFUART_BASE3          0xfc068000      /* Base address of UART3 */
3275  #define MCFINT_VECBASE         64
3276  #define MCFINT_UART0           26
3277 +
3278 +#elif defined(CONFIG_M547X_8X)
3279 +
3280 +#define MCFUART_BASE1          0x8600          /* Base address of UART1 */
3281 +#define MCFUART_BASE2          0x8700          /* Base address of UART2 */
3282 +#define MCFUART_BASE3          0x8800          /* Base address of UART3 */
3283 +#define MCFUART_BASE4          0x8900          /* Base address of UART4 */
3284 +#define MCFINT_VECBASE         64
3285 +#define MCFINT_UART0           35
3286  #endif
3287
3288
3289 @@ -97,6 +106,11 @@
3290  #define        MCFUART_USR_RXFULL      0x02            /* Receiver full */
3291  #define        MCFUART_USR_RXREADY     0x01            /* Receiver ready */
3292
3293 +#if defined(CONFIG_M547X_8X)
3294 +#define        MCFUART_USR_TXREADY_BN  0x0a
3295 +#define        MCFUART_USR_TXEMPTY_BN  0x0b
3296 +#endif
3297 +
3298  #define        MCFUART_USR_RXERR       (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
3299                                 MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
3300
3301 --- a/include/asm-m68k/mmu_context.h
3302 +++ b/include/asm-m68k/mmu_context.h
3303 @@ -152,6 +152,7 @@ static inline void activate_mm(struct mm
3304
3305  #else /* CONFIG_COLDFIRE */
3306
3307 +#include <asm/coldfire.h>
3308  #include <asm/atomic.h>
3309  #include <asm/bitops.h>
3310  #include <asm/mmu.h>
3311 @@ -227,6 +228,77 @@ static inline void activate_mm(struct mm
3312  #define deactivate_mm(tsk, mm) do { } while (0)
3313
3314  extern void mmu_context_init(void);
3315 +#if defined(CONFIG_M547X_8X)
3316 +#define prepare_arch_switch(next) load_ksp_mmu(next)
3317 +
3318 +static inline void load_ksp_mmu(struct task_struct *task)
3319 +{
3320 +       int flags;
3321 +       struct mm_struct *mm;
3322 +       int asid;
3323 +       pgd_t *pgd;
3324 +       pmd_t *pmd;
3325 +       pte_t *pte;
3326 +       unsigned long mmuar;
3327 +
3328 +       local_irq_save(flags);
3329 +       mmuar = task->thread.ksp;
3330 +
3331 +       /* Search for a valid TLB entry, if one is found, don't remap */
3332 +       *MMUAR = mmuar;
3333 +       *MMUOR = MMUOR_STLB | MMUOR_ADR;
3334 +       if ((*MMUSR) & MMUSR_HIT)
3335 +               goto end;
3336 +
3337 +       if (mmuar >= PAGE_OFFSET) {
3338 +               mm = &init_mm;
3339 +       } else {
3340 +               printk ("load_ksp_mmu: non-kernel mm found: 0x%08x\n", (unsigned int) task->mm);
3341 +               mm = task->mm;
3342 +       }
3343 +
3344 +        if (!mm)
3345 +           goto bug;
3346 +
3347 +        pgd = pgd_offset(mm, mmuar);
3348 +        if (pgd_none(*pgd))
3349 +           goto bug;
3350 +
3351 +       pmd = pmd_offset(pgd, mmuar);
3352 +       if (pmd_none(*pmd))
3353 +           goto bug;
3354 +
3355 +       pte = (mmuar >= PAGE_OFFSET) ? pte_offset_kernel(pmd, mmuar)
3356 +                                    : pte_offset_map(pmd, mmuar);
3357 +       if (pte_none(*pte) || !pte_present(*pte))
3358 +           goto bug;
3359 +
3360 +        set_pte(pte, pte_mkyoung(*pte));
3361 +        asid = mm->context & 0xff;
3362 +        if (!pte_dirty(*pte) && mmuar<=PAGE_OFFSET)
3363 +           set_pte(pte, pte_wrprotect(*pte));
3364 +
3365 +        *MMUTR = (mmuar & PAGE_MASK) | (asid << CF_ASID_MMU_SHIFT)
3366 +               | (((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK ) >> CF_PAGE_MMUTR_SHIFT)
3367 +               | MMUTR_V;
3368 +
3369 +        *MMUDR = (pte_val(*pte) & PAGE_MASK)
3370 +              | ((pte->pte) & CF_PAGE_MMUDR_MASK)
3371 +               | MMUDR_SZ8K | MMUDR_X;
3372 +
3373 +       *MMUOR = MMUOR_ACC | MMUOR_UAA;
3374 +       asm ("nop");
3375 +
3376 +       goto end;
3377 +
3378 +bug:
3379 +       printk ("ksp load failed: mm=0x%08x ksp=0x%08x\n", (unsigned int) mm, (unsigned int) mmuar);
3380 +
3381 +end:
3382 +       local_irq_restore(flags);
3383 +}
3384 +
3385 +#endif /* CONFIG_M547X_8X */
3386
3387  #endif /* CONFIG_COLDFIRE */
3388  #endif
3389 --- a/include/asm-m68k/page_offset.h
3390 +++ b/include/asm-m68k/page_offset.h
3391 @@ -5,7 +5,12 @@
3392  #elif defined(CONFIG_SUN3)
3393  #define PAGE_OFFSET_RAW                0x0E000000
3394  #else /* CONFIG_COLDFIRE */
3395 +#if defined(CONFIG_M54455)
3396  #define PAGE_OFFSET_RAW                0xC0000000
3397  #define        PHYS_OFFSET             0x40000000
3398 +#elif defined(CONFIG_M547X_8X)
3399 +#define PAGE_OFFSET_RAW                0xC0000000
3400 +#define        PHYS_OFFSET             0x00000000
3401 +#endif
3402  #endif
3403