target/linux/coldfire/patches/067-mcfv4e_acr_cleanup.patch

   1 From ddc092180bd24b34afdd6fd7cd48b77b55a5bd5e Mon Sep 17 00:00:00 2001
   2 From: Kurt Mahan <kmahan@freescale.com>
   3 Date: Tue, 24 Jun 2008 23:21:07 -0600
   4 Subject: [PATCH] Cleanup ACR mappings and document.
   5
   6 LTIBName: mcfv4e-acr-cleanup
   7 Signed-off-by: Kurt Mahan <kmahan@freescale.com>
   8 ---
   9  arch/m68k/coldfire/head.S |   81 +++++++++++++++++++++++++-------------------
  10  1 files changed, 46 insertions(+), 35 deletions(-)
  11
  12 --- a/arch/m68k/coldfire/head.S
  13 +++ b/arch/m68k/coldfire/head.S
  14 @@ -53,52 +53,63 @@
  15  #define __FINIT                .previous
  16  #endif
  17
  18 -/* JKM -- REVISE DOCS FOR M547x_8x and PHYS MAPPING */
  19 +#if CONFIG_SDRAM_BASE != PAGE_OFFSET
  20  /*
  21 - * Setup ACR mappings to provide the following memory map:
  22 - *   Data
  23 - *     0xA0000000 -> 0xAFFFFFFF [0] NO CACHE / PRECISE / SUPER ONLY
  24 - *     0xF0000000 -> 0xFFFFFFFF [1] NO CACHE / PRECISE / SUPER ONLY
  25 - *   Code
  26 - *     None currently (mapped via TLBs)
  27 + * Kernel mapped to virtual ram address.
  28 + *
  29 + * M5445x:
  30 + *    Data[0]: 0xF0000000 -> 0xFFFFFFFF        System regs
  31 + *    Data[1]: 0xA0000000 -> 0xAFFFFFFF        PCI
  32 + *    Code[0]: Not Mapped
  33 + *    Code[1]: Not Mapped
  34 + *
  35 + * M547x/M548x
  36 + *    Data[0]: 0xF0000000 -> 0xFFFFFFFF        System regs
  37 + *    Data[1]: Not Mapped
  38 + *    Code[0]: Not Mapped
  39 + *    Code[1]: Not Mapped
  40   */
  41 -
  42 -#if CONFIG_SDRAM_BASE != PAGE_OFFSET
  43  #if defined(CONFIG_M5445X)
  44 -#if 0
  45 -#define ACR0_DEFAULT   #0xA00FA048   /* ACR0 default value */
  46 -#endif
  47 -#define ACR0_DEFAULT   #0x400FA028   /* ACR0 default value */
  48 -#define ACR1_DEFAULT   #0xF00FA040   /* ACR1 default value */
  49 -#if 0
  50 -#define ACR2_DEFAULT   #0x00000000   /* ACR2 default value */
  51 -#endif
  52 -#define ACR2_DEFAULT   #0x400FA028   /* ACR2 default value */
  53 -#define ACR3_DEFAULT   #0x00000000   /* ACR3 default value */
  54 -/* ACR mapping for FPGA (maps 0) */
  55 -#define ACR0_FPGA      #0x000FA048   /* ACR0 enable FPGA */
  56 +#define ACR0_DEFAULT   #0xF00FA048   /* System regs */
  57 +#define ACR1_DEFAULT   #0xA00FA048   /* PCI */
  58 +#define ACR2_DEFAULT   #0x00000000   /* Not Mapped */
  59 +#define ACR3_DEFAULT   #0x00000000   /* Not Mapped */
  60  #elif defined(CONFIG_M547X_8X)
  61 -#define ACR0_DEFAULT   #0xE000C040   /* ACR0 default value */
  62 -#define ACR1_DEFAULT   #0x00000000   /* ACR1 default value */
  63 -#define ACR2_DEFAULT   #0x00000000   /* ACR2 default value */
  64 -#define ACR3_DEFAULT   #0x00000000   /* ACR3 default value */
  65 +#define ACR0_DEFAULT   #0xF00FA048   /* System Regs */
  66 +#define ACR1_DEFAULT   #0x00000000   /* Not Mapped */
  67 +#define ACR2_DEFAULT   #0x00000000   /* Not Mapped */
  68 +#define ACR3_DEFAULT   #0x00000000   /* Not Mapped */
  69  #endif
  70
  71 -#else
  72 +#else /* CONFIG_SDRAM_BASE = PAGE_OFFSET */
  73 +/*
  74 + * Kernel mapped to physical ram address.
  75 + *
  76 + * M5445x:
  77 + *    Data[0]: 0xF0000000 -> 0xFFFFFFFF        System regs
  78 + *    Data[1]: 0x40000000 -> 0x4FFFFFFF        SDRAM - uncached
  79 + *    Code[0]: Not Mapped
  80 + *    Code[1]: 0x40000000 -> 0x4FFFFFFF        SDRAM - cached
  81 + *
  82 + * M547x/M548x
  83 + *    Data[0]: 0xF0000000 -> 0xFFFFFFFF        System regs
  84 + *    Data[1]: 0x00000000 -> 0x0FFFFFFF        SDRAM - uncached
  85 + *    Code[0]: Not Mapped
  86 + *    Code[1]: 0x00000000 -> 0x0FFFFFFF        SDRAM - cached
  87 + */
  88  #if defined(CONFIG_M5445X)
  89 -#define ACR0_DEFAULT   #0xF00FC040   /* ACR0 default value */
  90 -#define ACR1_DEFAULT   #0x400FA008   /* ACR1 default value */
  91 -#define ACR2_DEFAULT   #0x00000000   /* ACR2 default value */
  92 -#define ACR3_DEFAULT   #0x400FA008   /* ACR3 default value */
  93 +#define ACR0_DEFAULT   #0xF00FA048   /* System Regs */
  94 +#define ACR1_DEFAULT   #0x400FA048   /* SDRAM uncached */
  95 +#define ACR2_DEFAULT   #0x00000000   /* Not mapped */
  96 +#define ACR3_DEFAULT   #0x400FA008   /* SDRAM cached */
  97  #elif defined(CONFIG_M547X_8X)
  98 -#define ACR0_DEFAULT   #0xF00FC040   /* ACR0 default value */
  99 -#define ACR1_DEFAULT   #0x000FA008   /* ACR1 default value */
 100 -#define ACR2_DEFAULT   #0x00000000   /* ACR2 default value */
 101 -#define ACR3_DEFAULT   #0x000FA008   /* ACR3 default value */
 102 +#define ACR0_DEFAULT   #0xF00FA048   /* System Regs */
 103 +#define ACR1_DEFAULT   #0x000FA048   /* SDRAM uncached */
 104 +#define ACR2_DEFAULT   #0x00000000   /* Not mapped */
 105 +#define ACR3_DEFAULT   #0x000FA008   /* SDRAM cached */
 106  #endif
 107  #endif
 108
 109 -
 110  /* Several macros to make the writing of subroutines easier:
 111   * - func_start marks the beginning of the routine which setups the frame
 112   *   register and saves the registers, it also defines another macro