target/linux/atheros/patches-2.6.32/105-ar2315_pci.patch

   1 Index: linux-2.6.32.7/arch/mips/ar231x/Makefile
   2 ===================================================================
   3 --- linux-2.6.32.7.orig/arch/mips/ar231x/Makefile       2010-02-03 17:00:08.814429898 +0100
   4 +++ linux-2.6.32.7/arch/mips/ar231x/Makefile    2010-02-03 17:00:21.031428952 +0100
   5 @@ -11,3 +11,4 @@
   6  obj-y += board.o prom.o devices.o
   7  obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
   8  obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
   9 +obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
  10 Index: linux-2.6.32.7/arch/mips/ar231x/pci.c
  11 ===================================================================
  12 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  13 +++ linux-2.6.32.7/arch/mips/ar231x/pci.c       2010-02-03 17:00:21.031428952 +0100
  14 @@ -0,0 +1,230 @@
  15 +/*
  16 + * This program is free software; you can redistribute it and/or
  17 + * modify it under the terms of the GNU General Public License
  18 + * as published by the Free Software Foundation; either version 2
  19 + * of the License, or (at your option) any later version.
  20 + *
  21 + * This program is distributed in the hope that it will be useful,
  22 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24 + * GNU General Public License for more details.
  25 + *
  26 + * You should have received a copy of the GNU General Public License
  27 + * along with this program; if not, write to the Free Software
  28 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  29 + */
  30 +
  31 +#include <linux/types.h>
  32 +#include <linux/pci.h>
  33 +#include <linux/kernel.h>
  34 +#include <linux/init.h>
  35 +#include <linux/mm.h>
  36 +#include <linux/spinlock.h>
  37 +#include <linux/delay.h>
  38 +#include <linux/irq.h>
  39 +#include <asm/bootinfo.h>
  40 +#include <asm/paccess.h>
  41 +#include <asm/irq_cpu.h>
  42 +#include <asm/io.h>
  43 +#include <ar231x_platform.h>
  44 +#include <ar231x.h>
  45 +#include <ar2315_regs.h>
  46 +#include "devices.h"
  47 +
  48 +#define AR531X_MEM_BASE    0x80800000UL
  49 +#define AR531X_MEM_SIZE    0x00ffffffUL
  50 +#define AR531X_IO_SIZE     0x00007fffUL
  51 +
  52 +static unsigned long configspace;
  53 +
  54 +static int config_access(int devfn, int where, int size, u32 *ptr, bool write)
  55 +{
  56 +       unsigned long flags;
  57 +       int func = PCI_FUNC(devfn);
  58 +       int dev = PCI_SLOT(devfn);
  59 +       u32 value = 0;
  60 +       int err = 0;
  61 +       u32 addr;
  62 +
  63 +       if (((dev != 0) && (dev != 3)) || (func > 2))
  64 +               return PCIBIOS_DEVICE_NOT_FOUND;
  65 +
  66 +       /* Select Configuration access */
  67 +       local_irq_save(flags);
  68 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
  69 +       mb();
  70 +
  71 +       addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where;
  72 +       if (size == 1)
  73 +               addr ^= 0x3;
  74 +       else if (size == 2)
  75 +               addr ^= 0x2;
  76 +
  77 +       if (write) {
  78 +               value = *ptr;
  79 +               if (size == 1)
  80 +                       err = put_dbe(value, (u8 *) addr);
  81 +               else if (size == 2)
  82 +                       err = put_dbe(value, (u16 *) addr);
  83 +               else if (size == 4)
  84 +                       err = put_dbe(value, (u32 *) addr);
  85 +       } else {
  86 +               if (size == 1)
  87 +                       err = get_dbe(value, (u8 *) addr);
  88 +               else if (size == 2)
  89 +                       err = get_dbe(value, (u16 *) addr);
  90 +               else if (size == 4)
  91 +                       err = get_dbe(value, (u32 *) addr);
  92 +               if (err)
  93 +                       *ptr = 0xffffffff;
  94 +               else
  95 +                       *ptr = value;
  96 +       }
  97 +
  98 +       /* Select Memory access */
  99 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
 100 +       local_irq_restore(flags);
 101 +
 102 +       return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL);
 103 +}
 104 +
 105 +static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value)
 106 +{
 107 +       return config_access(devfn, where, size, value, 0);
 108 +}
 109 +
 110 +static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
 111 +{
 112 +       return config_access(devfn, where, size, &value, 1);
 113 +}
 114 +
 115 +struct pci_ops ar231x_pci_ops = {
 116 +       .read   = ar231x_pci_read,
 117 +       .write  = ar231x_pci_write,
 118 +};
 119 +
 120 +static struct resource ar231x_mem_resource = {
 121 +       .name   = "AR531x PCI MEM",
 122 +       .start  = AR531X_MEM_BASE,
 123 +       .end    = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000,
 124 +       .flags  = IORESOURCE_MEM,
 125 +};
 126 +
 127 +static struct resource ar231x_io_resource = {
 128 +       .name   = "AR531x PCI I/O",
 129 +       .start  = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE,
 130 +       .end    = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1,
 131 +       .flags  = IORESOURCE_IO,
 132 +};
 133 +
 134 +struct pci_controller ar231x_pci_controller = {
 135 +       .pci_ops                = &ar231x_pci_ops,
 136 +       .mem_resource   = &ar231x_mem_resource,
 137 +       .io_resource    = &ar231x_io_resource,
 138 +       .mem_offset     = 0x00000000UL,
 139 +       .io_offset      = 0x00000000UL,
 140 +};
 141 +
 142 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 143 +{
 144 +       return AR2315_IRQ_LCBUS_PCI;
 145 +}
 146 +
 147 +int pcibios_plat_dev_init(struct pci_dev *dev)
 148 +{
 149 +       pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5);
 150 +       pci_write_config_word(dev, 0x40, 0);
 151 +
 152 +       /* Clear any pending Abort or external Interrupts
 153 +        * and enable interrupt processing */
 154 +       ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0);
 155 +       ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
 156 +       ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
 157 +       ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE);
 158 +
 159 +       return 0;
 160 +}
 161 +
 162 +static void
 163 +ar2315_pci_fixup(struct pci_dev *dev)
 164 +{
 165 +       unsigned int devfn = dev->devfn;
 166 +
 167 +       if (dev->bus->number != 0)
 168 +               return;
 169 +
 170 +       /* Only fix up the PCI host settings */
 171 +       if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0))
 172 +               return;
 173 +
 174 +       /* Fix up MBARs */
 175 +       pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0);
 176 +       pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1);
 177 +       pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2);
 178 +       pci_write_config_dword(dev, PCI_COMMAND,
 179 +               PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
 180 +               PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
 181 +               PCI_COMMAND_FAST_BACK);
 182 +}
 183 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup);
 184 +
 185 +static int __init
 186 +ar2315_pci_init(void)
 187 +{
 188 +       u32 reg;
 189 +
 190 +       if (ar231x_devtype != DEV_TYPE_AR2315)
 191 +               return -ENODEV;
 192 +
 193 +       configspace = (unsigned long) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */
 194 +       ar231x_pci_controller.io_map_base =
 195 +               (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE);
 196 +       set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */
 197 +
 198 +       reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
 199 +       msleep(10);
 200 +
 201 +       reg &= ~AR2315_RESET_PCIDMA;
 202 +       ar231x_write_reg(AR2315_RESET, reg);
 203 +       msleep(10);
 204 +
 205 +       ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
 206 +               AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
 207 +
 208 +       ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
 209 +               (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
 210 +       ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
 211 +       ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
 212 +               AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
 213 +                (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT));
 214 +
 215 +       /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
 216 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
 217 +               AR2315_PCIRST_LOW);
 218 +       msleep(100);
 219 +
 220 +       /* Bring the PCI out of reset */
 221 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
 222 +               AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
 223 +
 224 +       ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
 225 +                       0x1E | /* 1GB uncached */
 226 +                       (1 << 5) | /* Enable uncached */
 227 +                       (0x2 << 30) /* Base: 0x80000000 */
 228 +       );
 229 +       ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
 230 +
 231 +       msleep(500);
 232 +
 233 +       /* dirty hack - anyone with a datasheet that knows the memory map ? */
 234 +       ioport_resource.start = 0x10000000;
 235 +       ioport_resource.end = 0xffffffff;
 236 +       iomem_resource.start = 0x10000000;
 237 +       iomem_resource.end = 0xffffffff;
 238 +
 239 +       register_pci_controller(&ar231x_pci_controller);
 240 +
 241 +       return 0;
 242 +}
 243 +
 244 +arch_initcall(ar2315_pci_init);
 245 Index: linux-2.6.32.7/arch/mips/ar231x/Kconfig
 246 ===================================================================
 247 --- linux-2.6.32.7.orig/arch/mips/ar231x/Kconfig        2010-02-03 17:00:08.814429898 +0100
 248 +++ linux-2.6.32.7/arch/mips/ar231x/Kconfig     2010-02-03 17:00:21.031428952 +0100
 249 @@ -15,3 +15,13 @@
 250         select SYS_SUPPORTS_BIG_ENDIAN
 251         select GENERIC_GPIO
 252         default y
 253 +
 254 +config ATHEROS_AR2315_PCI
 255 +       bool "PCI support"
 256 +       depends on ATHEROS_AR2315
 257 +       select HW_HAS_PCI
 258 +       select PCI
 259 +       select USB_ARCH_HAS_HCD
 260 +       select USB_ARCH_HAS_OHCI
 261 +       select USB_ARCH_HAS_EHCI
 262 +       default y
 263 Index: linux-2.6.32.7/arch/mips/ar231x/ar2315.c
 264 ===================================================================
 265 --- linux-2.6.32.7.orig/arch/mips/ar231x/ar2315.c       2010-02-03 17:00:08.818431986 +0100
 266 +++ linux-2.6.32.7/arch/mips/ar231x/ar2315.c    2010-02-03 17:00:21.031428952 +0100
 267 @@ -63,6 +63,27 @@
 268                 do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
 269  }
 270
 271 +#ifdef CONFIG_ATHEROS_AR2315_PCI
 272 +static inline void pci_abort_irq(void)
 273 +{
 274 +       ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT);
 275 +}
 276 +
 277 +static inline void pci_ack_irq(void)
 278 +{
 279 +       ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT);
 280 +}
 281 +
 282 +void ar2315_pci_irq(int irq)
 283 +{
 284 +       if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT)
 285 +               pci_abort_irq();
 286 +       else {
 287 +               do_IRQ(irq);
 288 +               pci_ack_irq();
 289 +       }
 290 +}
 291 +#endif /* CONFIG_ATHEROS_AR2315_PCI */
 292
 293  /*
 294   * Called when an interrupt is received, this function
 295 @@ -81,6 +102,10 @@
 296                 do_IRQ(AR2315_IRQ_WLAN0_INTRS);
 297         else if (pending & CAUSEF_IP4)
 298                 do_IRQ(AR2315_IRQ_ENET0_INTRS);
 299 +#ifdef CONFIG_ATHEROS_AR2315_PCI
 300 +       else if (pending & CAUSEF_IP5)
 301 +               ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI);
 302 +#endif
 303         else if (pending & CAUSEF_IP2) {
 304                 unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
 305