5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /***********************************************************************/
25 /* Module : PMU register address and bits */
26 /***********************************************************************/
27 #define AR9_PMU (0xBF102000)
28 /* PMU Power down Control Register */
29 #define AR9_PMU_PWDCR ((volatile u32*)(AR9_PMU + 0x001C))
30 /* PMU Status Register */
31 #define AR9_PMU_SR ((volatile u32*)(AR9_PMU + 0x0020))
33 #define AR9_PMU_DMA (1<<5)
34 #define AR9_PMU_SDIO (1<<16)
35 #define AR9_PMU_USB0 (1<<6)
36 #define AR9_PMU_USB0_P (1<<0)
37 #define AR9_PMU_SWITCH (1<<28)
40 /***********************************************************************/
41 /* Module : RCU register address and bits */
42 /***********************************************************************/
43 #define AR9_RCU_BASE_ADDR (0xBF203000)
44 #define AR9_RCU_RST_REQ ((volatile u32*)(AR9_RCU_BASE_ADDR + 0x0010))
45 #define AR9_RCU_RST_STAT ((volatile u32*)(AR9_RCU_BASE_ADDR + 0x0014))
46 #define AR9_RST_ALL (1 << 30)
48 /*** Reset Request Register Bits ***/
49 #define AR9_RCU_RST_REQ_SRST (1 << 30)
50 #define AR9_RCU_RST_REQ_ARC_JTAG (1 << 20)
51 #define AR9_RCU_RST_REQ_PCI (1 << 13)
52 #define AR9_RCU_RST_REQ_AFE (1 << 11)
53 #define AR9_RCU_RST_REQ_SDIO (1 << 19)
54 #define AR9_RCU_RST_REQ_DMA (1 << 9)
55 #define AR9_RCU_RST_REQ_PPE (1 << 8)
56 #define AR9_RCU_RST_REQ_DFE (1 << 7)
58 /***********************************************************************/
59 /* Module : GPIO register address and bits */
60 /***********************************************************************/
61 #define AR9_GPIO (0xBE100B00)
62 /***Port 0 Data Output Register (0010H)***/
63 #define AR9_GPIO_P0_OUT ((volatile u32 *)(AR9_GPIO+ 0x0010))
64 /***Port 1 Data Output Register (0040H)***/
65 #define AR9_GPIO_P1_OUT ((volatile u32 *)(AR9_GPIO+ 0x0040))
66 /***Port 2 Data Output Register (0070H)***/
67 #define AR9_GPIO_P2_OUT ((volatile u32 *)(AR9_GPIO+ 0x0070))
68 /***Port 3 Data Output Register (00A0H)***/
69 #define AR9_GPIO_P3_OUT ((volatile u32 *)(AR9_GPIO+ 0x00A0))
70 /***Port 0 Data Input Register (0014H)***/
71 #define AR9_GPIO_P0_IN ((volatile u32 *)(AR9_GPIO+ 0x0014))
72 /***Port 1 Data Input Register (0044H)***/
73 #define AR9_GPIO_P1_IN ((volatile u32 *)(AR9_GPIO+ 0x0044))
74 /***Port 2 Data Input Register (0074H)***/
75 #define AR9_GPIO_P2_IN ((volatile u32 *)(AR9_GPIO+ 0x0074))
76 /***Port 3 Data Input Register (00A4H)***/
77 #define AR9_GPIO_P3_IN ((volatile u32 *)(AR9_GPIO+ 0x00A4))
78 /***Port 0 Direction Register (0018H)***/
79 #define AR9_GPIO_P0_DIR ((volatile u32 *)(AR9_GPIO+ 0x0018))
80 /***Port 1 Direction Register (0048H)***/
81 #define AR9_GPIO_P1_DIR ((volatile u32 *)(AR9_GPIO+ 0x0048))
82 /***Port 2 Direction Register (0078H)***/
83 #define AR9_GPIO_P2_DIR ((volatile u32 *)(AR9_GPIO+ 0x0078))
84 /***Port 3 Direction Register (0048H)***/
85 #define AR9_GPIO_P3_DIR ((volatile u32 *)(AR9_GPIO+ 0x00A8))
86 /***Port 0 Alternate Function Select Register 0 (001C H) ***/
87 #define AR9_GPIO_P0_ALTSEL0 ((volatile u32 *)(AR9_GPIO+ 0x001C))
88 /***Port 1 Alternate Function Select Register 0 (004C H) ***/
89 #define AR9_GPIO_P1_ALTSEL0 ((volatile u32 *)(AR9_GPIO+ 0x004C))
90 /***Port 2 Alternate Function Select Register 0 (007C H) ***/
91 #define AR9_GPIO_P2_ALTSEL0 ((volatile u32 *)(AR9_GPIO+ 0x007C))
92 /***Port 3 Alternate Function Select Register 0 (00AC H) ***/
93 #define AR9_GPIO_P3_ALTSEL0 ((volatile u32 *)(AR9_GPIO+ 0x00AC))
94 /***Port 0 Alternate Function Select Register 1 (0020 H) ***/
95 #define AR9_GPIO_P0_ALTSEL1 ((volatile u32 *)(AR9_GPIO+ 0x0020))
96 /***Port 1 Alternate Function Select Register 0 (0050 H) ***/
97 #define AR9_GPIO_P1_ALTSEL1 ((volatile u32 *)(AR9_GPIO+ 0x0050))
98 /***Port 2 Alternate Function Select Register 0 (0080 H) ***/
99 #define AR9_GPIO_P2_ALTSEL1 ((volatile u32 *)(AR9_GPIO+ 0x0080))
100 /***Port 3 Alternate Function Select Register 0 (0064 H) ***/
101 #define AR9_GPIO_P3_ALTSEL1 ((volatile u32 *)(AR9_GPIO+ 0x0064))
102 /***Port 0 Open Drain Control Register (0024H)***/
103 #define AR9_GPIO_P0_OD ((volatile u32 *)(AR9_GPIO+ 0x0024))
104 /***Port 1 Open Drain Control Register (0054H)***/
105 #define AR9_GPIO_P1_OD ((volatile u32 *)(AR9_GPIO+ 0x0054))
106 /***Port 2 Open Drain Control Register (0084H)***/
107 #define AR9_GPIO_P2_OD ((volatile u32 *)(AR9_GPIO+ 0x0084))
108 /***Port 3 Open Drain Control Register (0034H)***/
109 #define AR9_GPIO_P3_OD ((volatile u32 *)(AR9_GPIO+ 0x0034))
110 /***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/
111 #define AR9_GPIO_P0_STOFF ((volatile u32 *)(AR9_GPIO+ 0x0028))
112 /***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/
113 #define AR9_GPIO_P1_STOFF ((volatile u32 *)(AR9_GPIO+ 0x0058))
114 /***Port 2 Input Schmitt-Trigger Off Register (0088 H) ***/
115 #define AR9_GPIO_P2_STOFF ((volatile u32 *)(AR9_GPIO+ 0x0088))
116 /***Port 3 Input Schmitt-Trigger Off Register (0094 H) ***/
117 //#define AR9_GPIO_P3_STOFF ((volatile u32 *)(AR9_GPIO+ 0x0094))
118 /***Port 0 Pull Up/Pull Down Select Register (002C H)***/
119 #define AR9_GPIO_P0_PUDSEL ((volatile u32 *)(AR9_GPIO+ 0x002C))
120 /***Port 1 Pull Up/Pull Down Select Register (005C H)***/
121 #define AR9_GPIO_P1_PUDSEL ((volatile u32 *)(AR9_GPIO+ 0x005C))
122 /***Port 2 Pull Up/Pull Down Select Register (008C H)***/
123 #define AR9_GPIO_P2_PUDSEL ((volatile u32 *)(AR9_GPIO+ 0x008C))
124 /***Port 3 Pull Up/Pull Down Select Register (0038 H)***/
125 #define AR9_GPIO_P3_PUDSEL ((volatile u32 *)(AR9_GPIO+ 0x0038))
126 /***Port 0 Pull Up Device Enable Register (0030 H)***/
127 #define AR9_GPIO_P0_PUDEN ((volatile u32 *)(AR9_GPIO+ 0x0030))
128 /***Port 1 Pull Up Device Enable Register (0060 H)***/
129 #define AR9_GPIO_P1_PUDEN ((volatile u32 *)(AR9_GPIO+ 0x0060))
130 /***Port 2 Pull Up Device Enable Register (0090 H)***/
131 #define AR9_GPIO_P2_PUDEN ((volatile u32 *)(AR9_GPIO+ 0x0090))
132 /***Port 3 Pull Up Device Enable Register (003c H)***/
133 #define AR9_GPIO_P3_PUDEN ((volatile u32 *)(AR9_GPIO+ 0x003C))
135 /***********************************************************************/
136 /* Module : CGU register address and bits */
137 /***********************************************************************/
138 #define AR9_CGU (0xBF103000)
139 /***CGU Clock PLL0 ***/
140 #define AR9_CGU_PLL0_CFG ((volatile u32*)(AR9_CGU+ 0x0004))
141 /***CGU Clock PLL1 ***/
142 #define AR9_CGU_PLL1_CFG ((volatile u32*)(AR9_CGU+ 0x0008))
143 /***CGU Clock SYS Mux Register***/
144 #define AR9_CGU_SYS ((volatile u32*)(AR9_CGU+ 0x0010))
145 /***CGU Interface Clock Control Register***/
146 #define AR9_CGU_IFCCR ((volatile u32*)(AR9_CGU+ 0x0018))
147 /***CGU PCI Clock Control Register**/
148 #define AR9_CGU_PCICR ((volatile u32*)(AR9_CGU+ 0x0034))
149 #define CLOCK_60M 60000000
150 #define CLOCK_83M 83333333
151 #define CLOCK_111M 111111111
152 #define CLOCK_133M 133333333
153 #define CLOCK_166M 166666667
154 #define CLOCK_196M 196666667
155 #define CLOCK_333M 333333333
156 #define CLOCK_366M 366666667
157 #define CLOCK_500M 500000000
159 /***********************************************************************/
160 /* Module : MPS register address and bits */
161 /***********************************************************************/
162 #define AR9_MPS (KSEG1+0x1F107000)
163 #define AR9_MPS_CHIPID ((volatile u32*)(AR9_MPS + 0x0344))
164 #define AR9_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
165 #define AR9_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
166 #define AR9_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
168 /***********************************************************************/
169 /* Module : EBU register address and bits */
170 /***********************************************************************/
171 #define AR9_EBU (0xBE105300)
173 #define AR9_EBU_CLC ((volatile u32*)(AR9_EBU+ 0x0000))
174 #define AR9_EBU_CLC_DISS (1 << 1)
175 #define AR9_EBU_CLC_DISR (1 << 0)
177 #define AR9_EBU_ID ((volatile u32*)(AR9_EBU+ 0x0008))
179 /***EBU Global Control Register***/
180 #define AR9_EBU_CON ((volatile u32*)(AR9_EBU+ 0x0010))
181 #define AR9_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20)
182 #define AR9_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16)
183 #define AR9_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8)
184 #define AR9_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6)
185 #define AR9_EBU_CON_ARBSYNC (1 << 5)
186 //#define AR9_EBU_CON_1 (1 << 3)
188 /***EBU Address Select Register 0***/
189 #define AR9_EBU_ADDSEL0 ((volatile u32*)(AR9_EBU + 0x0020))
190 /***EBU Address Select Register 1***/
191 #define AR9_EBU_ADDSEL1 ((volatile u32*)(AR9_EBU + 0x0024))
192 /***EBU Address Select Register 2***/
193 #define AR9_EBU_ADDSEL2 ((volatile u32*)(AR9_EBU + 0x0028))
194 /***EBU Address Select Register 3***/
195 #define AR9_EBU_ADDSEL3 ((volatile u32*)(AR9_EBU + 0x002C))
196 #define AR9_EBU_ADDSEL_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
197 #define AR9_EBU_ADDSEL_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
198 #define AR9_EBU_ADDSEL_MIRRORE (1 << 1)
199 #define AR9_EBU_ADDSEL_REGEN (1 << 0)
201 /***EBU Bus Configuration Register 0***/
202 #define AR9_EBU_BUSCON0 ((volatile u32*)(AR9_EBU+ 0x0060))
203 #define AR9_EBU_BUSCON0_WRDIS (1 << 31)
204 #define AR9_EBU_BUSCON0_ADSWP (value) (1 << 30)
205 #define AR9_EBU_BUSCON0_PG_EN (value) (1 << 29)
206 #define AR9_EBU_BUSCON0_AGEN (value) (((( 1 << 3) - 1) & (value)) << 24)
207 #define AR9_EBU_BUSCON0_SETUP (1 << 22)
208 #define AR9_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
209 #define AR9_EBU_BUSCON0_WAITINV (1 << 19)
210 #define AR9_EBU_BUSCON0_VN_EN (1 << 18)
211 #define AR9_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
212 #define AR9_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 14)
213 #define AR9_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 12)
214 #define AR9_EBU_BUSCON0_WAITWDC (value) (((( 1 << 4) - 1) & (value)) << 8)
215 #define AR9_EBU_BUSCON0_WAITRRC (value) (((( 1 << 2) - 1) & (value)) << 6)
216 #define AR9_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
217 #define AR9_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
218 #define AR9_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
220 /***EBU Bus Configuration Register 1***/
221 #define AR9_EBU_BUSCON1 ((volatile u32*)(AR9_EBU+ 0x0064))
222 #define AR9_EBU_BUSCON1_WRDIS (1 << 31)
223 #define AR9_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
224 #define AR9_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
225 #define AR9_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
226 #define AR9_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
227 #define AR9_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
228 #define AR9_EBU_BUSCON1_WAITINV (1 << 19)
229 #define AR9_EBU_BUSCON1_SETUP (1 << 18)
230 #define AR9_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
231 #define AR9_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
232 #define AR9_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
233 #define AR9_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
234 #define AR9_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
235 #define AR9_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
237 /***EBU Bus Configuration Register 2***/
238 #define AR9_EBU_BUSCON2 ((volatile u32*)(AR9_EBU+ 0x0068))
239 #define AR9_EBU_BUSCON2_WRDIS (1 << 31)
240 #define AR9_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
241 #define AR9_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
242 #define AR9_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
243 #define AR9_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
244 #define AR9_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
245 #define AR9_EBU_BUSCON2_WAITINV (1 << 19)
246 #define AR9_EBU_BUSCON2_SETUP (1 << 18)
247 #define AR9_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
248 #define AR9_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
249 #define AR9_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
250 #define AR9_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
251 #define AR9_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
252 #define AR9_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
254 /***EBU Bus Configuration Register 2***/
255 #define AR9_EBU_BUSCON3 ((volatile u32*)(AR9_EBU+ 0x006C))
256 #define AR9_EBU_BUSCON3_WRDIS (1 << 31)
257 #define AR9_EBU_BUSCON3_ADSWP (value) (1 << 30)
258 #define AR9_EBU_BUSCON3_PG_EN (value) (1 << 29)
259 #define AR9_EBU_BUSCON3_AGEN (value) (((( 1 << 3) - 1) & (value)) << 24)
260 #define AR9_EBU_BUSCON3_SETUP (1 << 22)
261 #define AR9_EBU_BUSCON3_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
262 #define AR9_EBU_BUSCON3_WAITINV (1 << 19)
263 #define AR9_EBU_BUSCON3_VN_EN (1 << 18)
264 #define AR9_EBU_BUSCON3_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
265 #define AR9_EBU_BUSCON3_ALEC (value) (((( 1 << 2) - 1) & (value)) << 14)
266 #define AR9_EBU_BUSCON3_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 12)
267 #define AR9_EBU_BUSCON3_WAITWDC (value) (((( 1 << 4) - 1) & (value)) << 8)
268 #define AR9_EBU_BUSCON3_WAITRRC (value) (((( 1 << 2) - 1) & (value)) << 6)
269 #define AR9_EBU_BUSCON3_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
270 #define AR9_EBU_BUSCON3_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
271 #define AR9_EBU_BUSCON3_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
273 /***********************************************************************/
274 /* Module : SDRAM register address and bits */
275 /***********************************************************************/
276 #define AR9_SDRAM (0xBF800000)
278 /***********************************************************************/
279 /* Module : ASC0 register address and bits */
280 /***********************************************************************/
281 #define AR9_ASC0 (KSEG1 | 0x1E100400)
282 #define AR9_ASC0_TBUF ((volatile u32*)(AR9_ASC0 + 0x0020))
283 #define AR9_ASC0_RBUF ((volatile u32*)(AR9_ASC0 + 0x0024))
284 #define AR9_ASC0_FSTAT ((volatile u32*)(AR9_ASC0 + 0x0048))
286 /***********************************************************************/
287 /* Module : ASC1 register address and bits */
288 /***********************************************************************/
289 #define AR9_ASC1 (KSEG1 | 0x1E100C00)
290 #define AR9_ASC1_TBUF ((volatile u32*)(AR9_ASC1 + 0x0020))
291 #define AR9_ASC1_RBUF ((volatile u32*)(AR9_ASC1 + 0x0024))
292 #define AR9_ASC1_FSTAT ((volatile u32*)(AR9_ASC1 + 0x0048))
294 /***********************************************************************/
295 /* Module : DMA register address and bits */
296 /***********************************************************************/
297 #define AR9_DMA_OFFSET (0xBE104100)
298 /***********************************************************************/
299 #define AR9_DMA_CLC ((volatile u32*)(AR9_DMA_OFFSET + 0x0000))
300 #define AR9_DMA_ID ((volatile u32*)(AR9_DMA_OFFSET + 0x0008))
301 #define AR9_DMA_CTRL (volatile u32*)(AR9_DMA_BASE + 0x10)
303 /** DMA Port Select Register */
304 #define AR9_DMA_PS ((volatile u32*)(AR9_DMA_OFFSET + 0x0040))
305 /** DMA Port Control Register */
306 #define AR9_DMA_PCTRL ((volatile u32*)(AR9_DMA_OFFSET + 0x0044))
307 #define AR9_DMA_IRNEN ((volatile u32*)(AR9_DMA_OFFSET + 0x00F4))
308 #define AR9_DMA_IRNCR ((volatile u32*)(AR9_DMA_OFFSET + 0x00F8))
309 #define AR9_DMA_IRNICR ((volatile u32*)(AR9_DMA_OFFSET + 0x00FC))
311 #define AR9_DMA_CS ((volatile u32*)(AR9_DMA_OFFSET + 0x0018))
312 #define AR9_DMA_CCTRL ((volatile u32*)(AR9_DMA_OFFSET + 0x001C))
313 #define AR9_DMA_CDBA ((volatile u32*)(AR9_DMA_OFFSET + 0x0020))
314 #define AR9_DMA_CIE ((volatile u32*)(AR9_DMA_OFFSET + 0x002C))
315 #define AR9_DMA_CIS ((volatile u32*)(AR9_DMA_OFFSET + 0x0028))
316 #define AR9_DMA_CDLEN ((volatile u32*)(AR9_DMA_OFFSET + 0x0024))
317 #define AR9_DMA_CPOLL ((volatile u32*)(AR9_DMA_OFFSET + 0x0014))
319 /***********************************************************************/
320 /* Module : GPORT switch register */
321 /***********************************************************************/
322 #define AR9_SW (0xBE108000)
323 #define AR9_SW_PS (AR9_SW + 0x000)
324 #define AR9_SW_P0_CTL (AR9_SW + 0x004)
325 #define AR9_SW_P1_CTL (AR9_SW + 0x008)
326 #define AR9_SW_P2_CTL (AR9_SW + 0x00C)
327 #define AR9_SW_P0_VLAN (AR9_SW + 0x010)
328 #define AR9_SW_P1_VLAN (AR9_SW + 0x014)
329 #define AR9_SW_P2_VLAN (AR9_SW + 0x018)
330 #define AR9_SW_P0_INCTL (AR9_SW + 0x020)
331 #define AR9_SW_P1_INCTL (AR9_SW + 0x024)
332 #define AR9_SW_P2_INCTL (AR9_SW + 0x028)
333 #define AR9_SW_DF_PORTMAP (AR9_SW + 0x02C)
334 #define AR9_SW_P0_ECS_Q32 (AR9_SW + 0x030)
335 #define AR9_SW_P0_ECS_Q10 (AR9_SW + 0x034)
336 #define AR9_SW_P0_ECW_Q32 (AR9_SW + 0x038)
337 #define AR9_SW_P0_ECW_Q10 (AR9_SW + 0x03C)
338 #define AR9_SW_P1_ECS_Q32 (AR9_SW + 0x040)
339 #define AR9_SW_P1_ECS_Q10 (AR9_SW + 0x044)
340 #define AR9_SW_P1_ECW_Q32 (AR9_SW + 0x048)
341 #define AR9_SW_P1_ECW_Q10 (AR9_SW + 0x04C)
342 #define AR9_SW_P2_ECS_Q32 (AR9_SW + 0x050)
343 #define AR9_SW_P2_ECS_Q10 (AR9_SW + 0x054)
344 #define AR9_SW_P2_ECW_Q32 (AR9_SW + 0x058)
345 #define AR9_SW_P2_ECW_Q10 (AR9_SW + 0x05C)
346 #define AR9_SW_INT_ENA (AR9_SW + 0x060)
347 #define AR9_SW_INT_ST (AR9_SW + 0x064)
348 #define AR9_SW_GCTL0 (AR9_SW + 0x068)
349 #define AR9_SW_GCTL1 (AR9_SW + 0x06C)
350 #define AR9_SW_ARP (AR9_SW + 0x070)
351 #define AR9_SW_STRM_CTL (AR9_SW + 0x074)
352 #define AR9_SW_RGMII_CTL (AR9_SW + 0x078)
353 #define AR9_SW_1P_PRT (AR9_SW + 0x07C)
354 #define AR9_SW_GBKT_SZBS (AR9_SW + 0x080)
355 #define AR9_SW_GBKT_SZEBS (AR9_SW + 0x084)
356 #define AR9_SW_BF_TH (AR9_SW + 0x088)
357 #define AR9_SW_PMAC_HD_CTL (AR9_SW + 0x08C)
358 #define AR9_SW_PMAC_SA1 (AR9_SW + 0x090)
359 #define AR9_SW_PMAC_SA2 (AR9_SW + 0x094)
360 #define AR9_SW_PMAC_DA1 (AR9_SW + 0x098)
361 #define AR9_SW_PMAC_DA2 (AR9_SW + 0x09C)
362 #define AR9_SW_PMAC_VLAN (AR9_SW + 0x0A0)
363 #define AR9_SW_PMAC_TX_IPG (AR9_SW + 0x0A4)
364 #define AR9_SW_PMAC_RX_IPG (AR9_SW + 0x0A8)
365 #define AR9_SW_ADR_TB_CTL0 (AR9_SW + 0x0AC)
366 #define AR9_SW_ADR_TB_CTL1 (AR9_SW + 0x0B0)
367 #define AR9_SW_ADR_TB_CTL2 (AR9_SW + 0x0B4)
368 #define AR9_SW_ADR_TB_ST0 (AR9_SW + 0x0B8)
369 #define AR9_SW_ADR_TB_ST1 (AR9_SW + 0x0BC)
370 #define AR9_SW_ADR_TB_ST2 (AR9_SW + 0x0C0)
371 #define AR9_SW_RMON_CTL (AR9_SW + 0x0C4)
372 #define AR9_SW_RMON_ST (AR9_SW + 0x0C8)
373 #define AR9_SW_MDIO_CTL (AR9_SW + 0x0CC)
374 #define AR9_SW_MDIO_DATA (AR9_SW + 0x0D0)
375 #define AR9_SW_TP_FLT_ACT (AR9_SW + 0x0D4)
376 #define AR9_SW_PRTCL_FLT_ACT (AR9_SW + 0x0D8)
377 #define AR9_SW_VLAN_FLT0 (AR9_SW + 0x100)
378 #define AR9_SW_VLAN_FLT1 (AR9_SW + 0x104)
379 #define AR9_SW_VLAN_FLT2 (AR9_SW + 0x108)
380 #define AR9_SW_VLAN_FLT3 (AR9_SW + 0x10C)
381 #define AR9_SW_VLAN_FLT4 (AR9_SW + 0x110)
382 #define AR9_SW_VLAN_FLT5 (AR9_SW + 0x114)
383 #define AR9_SW_VLAN_FLT6 (AR9_SW + 0x118)
384 #define AR9_SW_VLAN_FLT7 (AR9_SW + 0x11C)
385 #define AR9_SW_VLAN_FLT8 (AR9_SW + 0x120)
386 #define AR9_SW_VLAN_FLT9 (AR9_SW + 0x124)
387 #define AR9_SW_VLAN_FLT10 (AR9_SW + 0x128)
388 #define AR9_SW_VLAN_FLT11 (AR9_SW + 0x12C)
389 #define AR9_SW_VLAN_FLT12 (AR9_SW + 0x130)
390 #define AR9_SW_VLAN_FLT13 (AR9_SW + 0x134)
391 #define AR9_SW_VLAN_FLT14 (AR9_SW + 0x138)
392 #define AR9_SW_VLAN_FLT15 (AR9_SW + 0x13C)
393 #define AR9_SW_TP_FLT10 (AR9_SW + 0x140)
394 #define AR9_SW_TP_FLT32 (AR9_SW + 0x144)
395 #define AR9_SW_TP_FLT54 (AR9_SW + 0x148)
396 #define AR9_SW_TP_FLT76 (AR9_SW + 0x14C)
397 #define AR9_SW_DFSRV_MAP0 (AR9_SW + 0x150)
398 #define AR9_SW_DFSRV_MAP1 (AR9_SW + 0x154)
399 #define AR9_SW_DFSRV_MAP2 (AR9_SW + 0x158)
400 #define AR9_SW_DFSRV_MAP3 (AR9_SW + 0x15C)
401 #define AR9_SW_TCP_PF0 (AR9_SW + 0x160)
402 #define AR9_SW_TCP_PF1 (AR9_SW + 0x164)
403 #define AR9_SW_TCP_PF2 (AR9_SW + 0x168)
404 #define AR9_SW_TCP_PF3 (AR9_SW + 0x16C)
405 #define AR9_SW_TCP_PF4 (AR9_SW + 0x170)
406 #define AR9_SW_TCP_PF5 (AR9_SW + 0x174)
407 #define AR9_SW_TCP_PF6 (AR9_SW + 0x178)
408 #define AR9_SW_TCP_PF7 (AR9_SW + 0x17C)
409 #define AR9_SW_RA_03_00 (AR9_SW + 0x180)
410 #define AR9_SW_RA_07_04 (AR9_SW + 0x184)
411 #define AR9_SW_RA_0B_08 (AR9_SW + 0x188)
412 #define AR9_SW_RA_0F_0C (AR9_SW + 0x18C)
413 #define AR9_SW_RA_13_10 (AR9_SW + 0x190)
414 #define AR9_SW_RA_17_14 (AR9_SW + 0x194)
415 #define AR9_SW_RA_1B_18 (AR9_SW + 0x198)
416 #define AR9_SW_RA_1F_1C (AR9_SW + 0x19C)
417 #define AR9_SW_RA_23_20 (AR9_SW + 0x1A0)
418 #define AR9_SW_RA_27_24 (AR9_SW + 0x1A4)
419 #define AR9_SW_RA_2B_28 (AR9_SW + 0x1A8)
420 #define AR9_SW_RA_2F_2C (AR9_SW + 0x1AC)
421 #define AR9_SW_F0 (AR9_SW + 0x1B0)
422 #define AR9_SW_F1 (AR9_SW + 0x1B4)
424 #define REG32(addr) *((volatile u32 *)(addr))
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