target/linux/s3c24xx/patches-2.6.30/010-s3c-dma.patch

   1 Index: linux-2.6.30-rc6/arch/arm/mach-s3c2410/include/mach/dma.h
   2 ===================================================================
   3 --- linux-2.6.30-rc6.orig/arch/arm/mach-s3c2410/include/mach/dma.h      2009-05-16 06:12:57.000000000 +0200
   4 +++ linux-2.6.30-rc6/arch/arm/mach-s3c2410/include/mach/dma.h   2009-05-18 19:08:29.000000000 +0200
   5 @@ -3,7 +3,7 @@
   6   * Copyright (C) 2003,2004,2006 Simtec Electronics
   7   *     Ben Dooks <ben@simtec.co.uk>
   8   *
   9 - * Samsung S3C241XX DMA support
  10 + * Samsung S3C24XX DMA support
  11   *
  12   * This program is free software; you can redistribute it and/or modify
  13   * it under the terms of the GNU General Public License version 2 as
  14 @@ -13,8 +13,8 @@
  15  #ifndef __ASM_ARCH_DMA_H
  16  #define __ASM_ARCH_DMA_H __FILE__
  17
  18 +#include <plat/dma.h>
  19  #include <linux/sysdev.h>
  20 -#include <mach/hardware.h>
  21
  22  #define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
  23
  24 @@ -55,9 +55,9 @@
  25
  26  /* we have 4 dma channels */
  27  #ifndef CONFIG_CPU_S3C2443
  28 -#define S3C2410_DMA_CHANNELS           (4)
  29 +#define S3C_DMA_CHANNELS               (4)
  30  #else
  31 -#define S3C2410_DMA_CHANNELS           (6)
  32 +#define S3C_DMA_CHANNELS               (6)
  33  #endif
  34
  35  /* types */
  36 @@ -68,7 +68,6 @@
  37         S3C2410_DMA_PAUSED
  38  };
  39
  40 -
  41  /* enum s3c2410_dma_loadst
  42   *
  43   * This represents the state of the DMA engine, wrt to the loaded / running
  44 @@ -104,32 +103,6 @@
  45         S3C2410_DMALOAD_1LOADED_1RUNNING,
  46  };
  47
  48 -enum s3c2410_dma_buffresult {
  49 -       S3C2410_RES_OK,
  50 -       S3C2410_RES_ERR,
  51 -       S3C2410_RES_ABORT
  52 -};
  53 -
  54 -enum s3c2410_dmasrc {
  55 -       S3C2410_DMASRC_HW,              /* source is memory */
  56 -       S3C2410_DMASRC_MEM              /* source is hardware */
  57 -};
  58 -
  59 -/* enum s3c2410_chan_op
  60 - *
  61 - * operation codes passed to the DMA code by the user, and also used
  62 - * to inform the current channel owner of any changes to the system state
  63 -*/
  64 -
  65 -enum s3c2410_chan_op {
  66 -       S3C2410_DMAOP_START,
  67 -       S3C2410_DMAOP_STOP,
  68 -       S3C2410_DMAOP_PAUSE,
  69 -       S3C2410_DMAOP_RESUME,
  70 -       S3C2410_DMAOP_FLUSH,
  71 -       S3C2410_DMAOP_TIMEOUT,          /* internal signal to handler */
  72 -       S3C2410_DMAOP_STARTED,          /* indicate channel started */
  73 -};
  74
  75  /* flags */
  76
  77 @@ -137,19 +110,18 @@
  78                                             * waiting for reloads */
  79  #define S3C2410_DMAF_AUTOSTART    (1<<1)   /* auto-start if buffer queued */
  80
  81 +#define S3C2410_DMAF_CIRCULAR    (0x00)   /* circular enqueue not supp. */
  82 +
  83  /* dma buffer */
  84
  85 -struct s3c2410_dma_client {
  86 -       char                *name;
  87 -};
  88 +struct s3c2410_dma_buf;
  89
  90 -/* s3c2410_dma_buf_s
  91 +/* s3c2410_dma_buf
  92   *
  93   * internally used buffer structure to describe a queued or running
  94   * buffer.
  95  */
  96
  97 -struct s3c2410_dma_buf;
  98  struct s3c2410_dma_buf {
  99         struct s3c2410_dma_buf  *next;
 100         int                      magic;         /* magic */
 101 @@ -161,20 +133,6 @@
 102
 103  /* [1] is this updated for both recv/send modes? */
 104
 105 -struct s3c2410_dma_chan;
 106 -
 107 -/* s3c2410_dma_cbfn_t
 108 - *
 109 - * buffer callback routine type
 110 -*/
 111 -
 112 -typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
 113 -                                  void *buf, int size,
 114 -                                  enum s3c2410_dma_buffresult result);
 115 -
 116 -typedef int  (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
 117 -                                  enum s3c2410_chan_op );
 118 -
 119  struct s3c2410_dma_stats {
 120         unsigned long           loads;
 121         unsigned long           timeout_longest;
 122 @@ -206,10 +164,10 @@
 123
 124         /* channel configuration */
 125         enum s3c2410_dmasrc      source;
 126 +       enum dma_ch              req_ch;
 127         unsigned long            dev_addr;
 128         unsigned long            load_timeout;
 129         unsigned int             flags;         /* channel flags */
 130 -       unsigned int             hw_cfg;        /* last hw config */
 131
 132         struct s3c24xx_dma_map  *map;           /* channel hw maps */
 133
 134 @@ -236,213 +194,12 @@
 135         struct sys_device       dev;
 136  };
 137
 138 -/* the currently allocated channel information */
 139 -extern struct s3c2410_dma_chan s3c2410_chans[];
 140 -
 141 -/* note, we don't really use dma_device_t at the moment */
 142  typedef unsigned long dma_device_t;
 143
 144 -/* functions --------------------------------------------------------------- */
 145 -
 146 -/* s3c2410_dma_request
 147 - *
 148 - * request a dma channel exclusivley
 149 -*/
 150 -
 151 -extern int s3c2410_dma_request(unsigned int channel,
 152 -                              struct s3c2410_dma_client *, void *dev);
 153 -
 154 -
 155 -/* s3c2410_dma_ctrl
 156 - *
 157 - * change the state of the dma channel
 158 -*/
 159 -
 160 -extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
 161 -
 162 -/* s3c2410_dma_setflags
 163 - *
 164 - * set the channel's flags to a given state
 165 -*/
 166 -
 167 -extern int s3c2410_dma_setflags(unsigned int channel,
 168 -                               unsigned int flags);
 169 -
 170 -/* s3c2410_dma_free
 171 - *
 172 - * free the dma channel (will also abort any outstanding operations)
 173 -*/
 174 -
 175 -extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
 176 -
 177 -/* s3c2410_dma_enqueue
 178 - *
 179 - * place the given buffer onto the queue of operations for the channel.
 180 - * The buffer must be allocated from dma coherent memory, or the Dcache/WB
 181 - * drained before the buffer is given to the DMA system.
 182 -*/
 183 -
 184 -extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
 185 -                              dma_addr_t data, int size);
 186 -
 187 -/* s3c2410_dma_config
 188 - *
 189 - * configure the dma channel
 190 -*/
 191 -
 192 -extern int s3c2410_dma_config(unsigned int channel, int xferunit, int dcon);
 193 -
 194 -/* s3c2410_dma_devconfig
 195 - *
 196 - * configure the device we're talking to
 197 -*/
 198 -
 199 -extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
 200 -                                int hwcfg, unsigned long devaddr);
 201 -
 202 -/* s3c2410_dma_getposition
 203 - *
 204 - * get the position that the dma transfer is currently at
 205 -*/
 206 -
 207 -extern int s3c2410_dma_getposition(unsigned int channel,
 208 -                                  dma_addr_t *src, dma_addr_t *dest);
 209 -
 210 -extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
 211 -extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
 212 -
 213 -/* DMA Register definitions */
 214 -
 215 -#define S3C2410_DMA_DISRC       (0x00)
 216 -#define S3C2410_DMA_DISRCC      (0x04)
 217 -#define S3C2410_DMA_DIDST       (0x08)
 218 -#define S3C2410_DMA_DIDSTC      (0x0C)
 219 -#define S3C2410_DMA_DCON        (0x10)
 220 -#define S3C2410_DMA_DSTAT       (0x14)
 221 -#define S3C2410_DMA_DCSRC       (0x18)
 222 -#define S3C2410_DMA_DCDST       (0x1C)
 223 -#define S3C2410_DMA_DMASKTRIG   (0x20)
 224 -#define S3C2412_DMA_DMAREQSEL  (0x24)
 225 -#define S3C2443_DMA_DMAREQSEL  (0x24)
 226 -
 227 -#define S3C2410_DISRCC_INC     (1<<0)
 228 -#define S3C2410_DISRCC_APB     (1<<1)
 229 -
 230 -#define S3C2410_DMASKTRIG_STOP   (1<<2)
 231 -#define S3C2410_DMASKTRIG_ON     (1<<1)
 232 -#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
 233 -
 234 -#define S3C2410_DCON_DEMAND     (0<<31)
 235 -#define S3C2410_DCON_HANDSHAKE  (1<<31)
 236 -#define S3C2410_DCON_SYNC_PCLK  (0<<30)
 237 -#define S3C2410_DCON_SYNC_HCLK  (1<<30)
 238 -
 239 -#define S3C2410_DCON_INTREQ     (1<<29)
 240 -
 241 -#define S3C2410_DCON_CH0_XDREQ0        (0<<24)
 242 -#define S3C2410_DCON_CH0_UART0 (1<<24)
 243 -#define S3C2410_DCON_CH0_SDI   (2<<24)
 244 -#define S3C2410_DCON_CH0_TIMER (3<<24)
 245 -#define S3C2410_DCON_CH0_USBEP1        (4<<24)
 246 -
 247 -#define S3C2410_DCON_CH1_XDREQ1        (0<<24)
 248 -#define S3C2410_DCON_CH1_UART1 (1<<24)
 249 -#define S3C2410_DCON_CH1_I2SSDI        (2<<24)
 250 -#define S3C2410_DCON_CH1_SPI   (3<<24)
 251 -#define S3C2410_DCON_CH1_USBEP2        (4<<24)
 252 -
 253 -#define S3C2410_DCON_CH2_I2SSDO        (0<<24)
 254 -#define S3C2410_DCON_CH2_I2SSDI        (1<<24)
 255 -#define S3C2410_DCON_CH2_SDI   (2<<24)
 256 -#define S3C2410_DCON_CH2_TIMER (3<<24)
 257 -#define S3C2410_DCON_CH2_USBEP3        (4<<24)
 258 -
 259 -#define S3C2410_DCON_CH3_UART2 (0<<24)
 260 -#define S3C2410_DCON_CH3_SDI   (1<<24)
 261 -#define S3C2410_DCON_CH3_SPI   (2<<24)
 262 -#define S3C2410_DCON_CH3_TIMER (3<<24)
 263 -#define S3C2410_DCON_CH3_USBEP4        (4<<24)
 264 -
 265 -#define S3C2410_DCON_SRCSHIFT   (24)
 266 -#define S3C2410_DCON_SRCMASK   (7<<24)
 267 -
 268 -#define S3C2410_DCON_BYTE       (0<<20)
 269 -#define S3C2410_DCON_HALFWORD   (1<<20)
 270 -#define S3C2410_DCON_WORD       (2<<20)
 271 -
 272 -#define S3C2410_DCON_AUTORELOAD (0<<22)
 273 -#define S3C2410_DCON_NORELOAD   (1<<22)
 274 -#define S3C2410_DCON_HWTRIG     (1<<23)
 275 -
 276 -#ifdef CONFIG_CPU_S3C2440
 277 -#define S3C2440_DIDSTC_CHKINT  (1<<2)
 278 -
 279 -#define S3C2440_DCON_CH0_I2SSDO        (5<<24)
 280 -#define S3C2440_DCON_CH0_PCMIN (6<<24)
 281 -
 282 -#define S3C2440_DCON_CH1_PCMOUT        (5<<24)
 283 -#define S3C2440_DCON_CH1_SDI   (6<<24)
 284 -
 285 -#define S3C2440_DCON_CH2_PCMIN (5<<24)
 286 -#define S3C2440_DCON_CH2_MICIN (6<<24)
 287 -
 288 -#define S3C2440_DCON_CH3_MICIN (5<<24)
 289 -#define S3C2440_DCON_CH3_PCMOUT        (6<<24)
 290 -#endif
 291 -
 292 -#ifdef CONFIG_CPU_S3C2412
 293 -
 294 -#define S3C2412_DMAREQSEL_SRC(x)       ((x)<<1)
 295 -
 296 -#define S3C2412_DMAREQSEL_HW           (1)
 297 -
 298 -#define S3C2412_DMAREQSEL_SPI0TX       S3C2412_DMAREQSEL_SRC(0)
 299 -#define S3C2412_DMAREQSEL_SPI0RX       S3C2412_DMAREQSEL_SRC(1)
 300 -#define S3C2412_DMAREQSEL_SPI1TX       S3C2412_DMAREQSEL_SRC(2)
 301 -#define S3C2412_DMAREQSEL_SPI1RX       S3C2412_DMAREQSEL_SRC(3)
 302 -#define S3C2412_DMAREQSEL_I2STX                S3C2412_DMAREQSEL_SRC(4)
 303 -#define S3C2412_DMAREQSEL_I2SRX                S3C2412_DMAREQSEL_SRC(5)
 304 -#define S3C2412_DMAREQSEL_TIMER                S3C2412_DMAREQSEL_SRC(9)
 305 -#define S3C2412_DMAREQSEL_SDI          S3C2412_DMAREQSEL_SRC(10)
 306 -#define S3C2412_DMAREQSEL_USBEP1       S3C2412_DMAREQSEL_SRC(13)
 307 -#define S3C2412_DMAREQSEL_USBEP2       S3C2412_DMAREQSEL_SRC(14)
 308 -#define S3C2412_DMAREQSEL_USBEP3       S3C2412_DMAREQSEL_SRC(15)
 309 -#define S3C2412_DMAREQSEL_USBEP4       S3C2412_DMAREQSEL_SRC(16)
 310 -#define S3C2412_DMAREQSEL_XDREQ0       S3C2412_DMAREQSEL_SRC(17)
 311 -#define S3C2412_DMAREQSEL_XDREQ1       S3C2412_DMAREQSEL_SRC(18)
 312 -#define S3C2412_DMAREQSEL_UART0_0      S3C2412_DMAREQSEL_SRC(19)
 313 -#define S3C2412_DMAREQSEL_UART0_1      S3C2412_DMAREQSEL_SRC(20)
 314 -#define S3C2412_DMAREQSEL_UART1_0      S3C2412_DMAREQSEL_SRC(21)
 315 -#define S3C2412_DMAREQSEL_UART1_1      S3C2412_DMAREQSEL_SRC(22)
 316 -#define S3C2412_DMAREQSEL_UART2_0      S3C2412_DMAREQSEL_SRC(23)
 317 -#define S3C2412_DMAREQSEL_UART2_1      S3C2412_DMAREQSEL_SRC(24)
 318 -
 319 -#endif
 320 -
 321 -#define S3C2443_DMAREQSEL_SRC(x)       ((x)<<1)
 322 -
 323 -#define S3C2443_DMAREQSEL_HW           (1)
 324
 325 -#define S3C2443_DMAREQSEL_SPI0TX       S3C2443_DMAREQSEL_SRC(0)
 326 -#define S3C2443_DMAREQSEL_SPI0RX       S3C2443_DMAREQSEL_SRC(1)
 327 -#define S3C2443_DMAREQSEL_SPI1TX       S3C2443_DMAREQSEL_SRC(2)
 328 -#define S3C2443_DMAREQSEL_SPI1RX       S3C2443_DMAREQSEL_SRC(3)
 329 -#define S3C2443_DMAREQSEL_I2STX                S3C2443_DMAREQSEL_SRC(4)
 330 -#define S3C2443_DMAREQSEL_I2SRX                S3C2443_DMAREQSEL_SRC(5)
 331 -#define S3C2443_DMAREQSEL_TIMER                S3C2443_DMAREQSEL_SRC(9)
 332 -#define S3C2443_DMAREQSEL_SDI          S3C2443_DMAREQSEL_SRC(10)
 333 -#define S3C2443_DMAREQSEL_XDREQ0       S3C2443_DMAREQSEL_SRC(17)
 334 -#define S3C2443_DMAREQSEL_XDREQ1       S3C2443_DMAREQSEL_SRC(18)
 335 -#define S3C2443_DMAREQSEL_UART0_0      S3C2443_DMAREQSEL_SRC(19)
 336 -#define S3C2443_DMAREQSEL_UART0_1      S3C2443_DMAREQSEL_SRC(20)
 337 -#define S3C2443_DMAREQSEL_UART1_0      S3C2443_DMAREQSEL_SRC(21)
 338 -#define S3C2443_DMAREQSEL_UART1_1      S3C2443_DMAREQSEL_SRC(22)
 339 -#define S3C2443_DMAREQSEL_UART2_0      S3C2443_DMAREQSEL_SRC(23)
 340 -#define S3C2443_DMAREQSEL_UART2_1      S3C2443_DMAREQSEL_SRC(24)
 341 -#define S3C2443_DMAREQSEL_UART3_0      S3C2443_DMAREQSEL_SRC(25)
 342 -#define S3C2443_DMAREQSEL_UART3_1      S3C2443_DMAREQSEL_SRC(26)
 343 -#define S3C2443_DMAREQSEL_PCMOUT       S3C2443_DMAREQSEL_SRC(27)
 344 -#define S3C2443_DMAREQSEL_PCMIN        S3C2443_DMAREQSEL_SRC(28)
 345 -#define S3C2443_DMAREQSEL_MICIN                S3C2443_DMAREQSEL_SRC(29)
 346 +static int s3c_dma_has_circular(void)
 347 +{
 348 +       return 0;
 349 +}
 350
 351  #endif /* __ASM_ARCH_DMA_H */
 352 Index: linux-2.6.30-rc6/arch/arm/mach-s3c2442/Kconfig
 353 ===================================================================
 354 --- linux-2.6.30-rc6.orig/arch/arm/mach-s3c2442/Kconfig 2009-05-16 06:12:57.000000000 +0200
 355 +++ linux-2.6.30-rc6/arch/arm/mach-s3c2442/Kconfig      2009-05-18 19:08:29.000000000 +0200
 356 @@ -11,6 +11,7 @@
 357         select S3C2410_CLOCK
 358         select S3C2410_GPIO
 359         select S3C2410_PM if PM
 360 +       select S3C2440_DMA if S3C2410_DMA
 361         select CPU_S3C244X
 362         select CPU_LLSERIAL_S3C2440
 363         help
 364 Index: linux-2.6.30-rc6/arch/arm/plat-s3c/dma.c
 365 ===================================================================
 366 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 367 +++ linux-2.6.30-rc6/arch/arm/plat-s3c/dma.c    2009-05-18 19:08:29.000000000 +0200
 368 @@ -0,0 +1,86 @@
 369 +/* linux/arch/arm/plat-s3c/dma.c
 370 + *
 371 + * Copyright (c) 2003-2005,2006,2009 Simtec Electronics
 372 + *     Ben Dooks <ben@simtec.co.uk>
 373 + *     http://armlinux.simtec.co.uk/
 374 + *
 375 + * S3C DMA core
 376 + *
 377 + * This program is free software; you can redistribute it and/or modify
 378 + * it under the terms of the GNU General Public License version 2 as
 379 + * published by the Free Software Foundation.
 380 +*/
 381 +
 382 +struct s3c2410_dma_buf;
 383 +
 384 +#include <linux/kernel.h>
 385 +#include <linux/module.h>
 386 +#include <linux/errno.h>
 387 +
 388 +#include <mach/dma.h>
 389 +#include <mach/irqs.h>
 390 +
 391 +#include <plat/dma-plat.h>
 392 +
 393 +/* dma channel state information */
 394 +struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
 395 +struct s3c2410_dma_chan *s3c_dma_chan_map[DMACH_MAX];
 396 +
 397 +/* s3c_dma_lookup_channel
 398 + *
 399 + * change the dma channel number given into a real dma channel id
 400 +*/
 401 +
 402 +struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel)
 403 +{
 404 +       if (channel & DMACH_LOW_LEVEL)
 405 +               return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
 406 +       else
 407 +               return s3c_dma_chan_map[channel];
 408 +}
 409 +
 410 +/* do we need to protect the settings of the fields from
 411 + * irq?
 412 +*/
 413 +
 414 +int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
 415 +{
 416 +       struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 417 +
 418 +       if (chan == NULL)
 419 +               return -EINVAL;
 420 +
 421 +       pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
 422 +
 423 +       chan->op_fn = rtn;
 424 +
 425 +       return 0;
 426 +}
 427 +EXPORT_SYMBOL(s3c2410_dma_set_opfn);
 428 +
 429 +int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
 430 +{
 431 +       struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 432 +
 433 +       if (chan == NULL)
 434 +               return -EINVAL;
 435 +
 436 +       pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
 437 +
 438 +       chan->callback_fn = rtn;
 439 +
 440 +       return 0;
 441 +}
 442 +EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
 443 +
 444 +int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
 445 +{
 446 +       struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 447 +
 448 +       if (chan == NULL)
 449 +               return -EINVAL;
 450 +
 451 +       chan->flags = flags;
 452 +       return 0;
 453 +}
 454 +EXPORT_SYMBOL(s3c2410_dma_setflags);
 455 Index: linux-2.6.30-rc6/arch/arm/plat-s3c/include/plat/dma-core.h
 456 ===================================================================
 457 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 458 +++ linux-2.6.30-rc6/arch/arm/plat-s3c/include/plat/dma-core.h  2009-05-18 19:08:29.000000000 +0200
 459 @@ -0,0 +1,22 @@
 460 +/* arch/arm/plat-s3c/include/plat/dma.h
 461 + *
 462 + * Copyright 2008 Openmoko, Inc.
 463 + * Copyright 2008 Simtec Electronics
 464 + *     Ben Dooks <ben@simtec.co.uk>
 465 + *     http://armlinux.simtec.co.uk/
 466 + *
 467 + * Samsung S3C DMA core support
 468 + *
 469 + * This program is free software; you can redistribute it and/or modify
 470 + * it under the terms of the GNU General Public License version 2 as
 471 + * published by the Free Software Foundation.
 472 +*/
 473 +
 474 +extern struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel);
 475 +
 476 +extern struct s3c2410_dma_chan *s3c_dma_chan_map[];
 477 +
 478 +/* the currently allocated channel information */
 479 +extern struct s3c2410_dma_chan s3c2410_chans[];
 480 +
 481 +
 482 Index: linux-2.6.30-rc6/arch/arm/plat-s3c/include/plat/dma.h
 483 ===================================================================
 484 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 485 +++ linux-2.6.30-rc6/arch/arm/plat-s3c/include/plat/dma.h       2009-05-18 19:08:29.000000000 +0200
 486 @@ -0,0 +1,128 @@
 487 +/* arch/arm/plat-s3c/include/plat/dma.h
 488 + *
 489 + * Copyright (C) 2003,2004,2006 Simtec Electronics
 490 + *     Ben Dooks <ben@simtec.co.uk>
 491 + *
 492 + * Samsung S3C DMA support
 493 + *
 494 + * This program is free software; you can redistribute it and/or modify
 495 + * it under the terms of the GNU General Public License version 2 as
 496 + * published by the Free Software Foundation.
 497 +*/
 498 +
 499 +enum s3c2410_dma_buffresult {
 500 +       S3C2410_RES_OK,
 501 +       S3C2410_RES_ERR,
 502 +       S3C2410_RES_ABORT
 503 +};
 504 +
 505 +enum s3c2410_dmasrc {
 506 +       S3C2410_DMASRC_HW,              /* source is memory */
 507 +       S3C2410_DMASRC_MEM              /* source is hardware */
 508 +};
 509 +
 510 +/* enum s3c2410_chan_op
 511 + *
 512 + * operation codes passed to the DMA code by the user, and also used
 513 + * to inform the current channel owner of any changes to the system state
 514 +*/
 515 +
 516 +enum s3c2410_chan_op {
 517 +       S3C2410_DMAOP_START,
 518 +       S3C2410_DMAOP_STOP,
 519 +       S3C2410_DMAOP_PAUSE,
 520 +       S3C2410_DMAOP_RESUME,
 521 +       S3C2410_DMAOP_FLUSH,
 522 +       S3C2410_DMAOP_TIMEOUT,          /* internal signal to handler */
 523 +       S3C2410_DMAOP_STARTED,          /* indicate channel started */
 524 +};
 525 +
 526 +struct s3c2410_dma_client {
 527 +       char                *name;
 528 +};
 529 +
 530 +struct s3c2410_dma_chan;
 531 +
 532 +/* s3c2410_dma_cbfn_t
 533 + *
 534 + * buffer callback routine type
 535 +*/
 536 +
 537 +typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
 538 +                                  void *buf, int size,
 539 +                                  enum s3c2410_dma_buffresult result);
 540 +
 541 +typedef int  (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
 542 +                                  enum s3c2410_chan_op );
 543 +
 544 +
 545 +
 546 +/* s3c2410_dma_request
 547 + *
 548 + * request a dma channel exclusivley
 549 +*/
 550 +
 551 +extern int s3c2410_dma_request(unsigned int channel,
 552 +                              struct s3c2410_dma_client *, void *dev);
 553 +
 554 +
 555 +/* s3c2410_dma_ctrl
 556 + *
 557 + * change the state of the dma channel
 558 +*/
 559 +
 560 +extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
 561 +
 562 +/* s3c2410_dma_setflags
 563 + *
 564 + * set the channel's flags to a given state
 565 +*/
 566 +
 567 +extern int s3c2410_dma_setflags(unsigned int channel,
 568 +                               unsigned int flags);
 569 +
 570 +/* s3c2410_dma_free
 571 + *
 572 + * free the dma channel (will also abort any outstanding operations)
 573 +*/
 574 +
 575 +extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
 576 +
 577 +/* s3c2410_dma_enqueue
 578 + *
 579 + * place the given buffer onto the queue of operations for the channel.
 580 + * The buffer must be allocated from dma coherent memory, or the Dcache/WB
 581 + * drained before the buffer is given to the DMA system.
 582 +*/
 583 +
 584 +extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
 585 +                              dma_addr_t data, int size);
 586 +
 587 +
 588 +/* s3c2410_dma_config
 589 + *
 590 + * configure the dma channel
 591 +*/
 592 +
 593 +extern int s3c2410_dma_config(unsigned int channel, int xferunit);
 594 +
 595 +/* s3c2410_dma_devconfig
 596 + *
 597 + * configure the device we're talking to
 598 +*/
 599 +
 600 +extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
 601 +                                unsigned long devaddr);
 602 +
 603 +/* s3c2410_dma_getposition
 604 + *
 605 + * get the position that the dma transfer is currently at
 606 +*/
 607 +
 608 +extern int s3c2410_dma_getposition(unsigned int channel,
 609 +                                  dma_addr_t *src, dma_addr_t *dest);
 610 +
 611 +extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
 612 +extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
 613 +
 614 +
 615 Index: linux-2.6.30-rc6/arch/arm/plat-s3c/Kconfig
 616 ===================================================================
 617 --- linux-2.6.30-rc6.orig/arch/arm/plat-s3c/Kconfig     2009-05-16 06:12:57.000000000 +0200
 618 +++ linux-2.6.30-rc6/arch/arm/plat-s3c/Kconfig  2009-05-18 19:08:29.000000000 +0200
 619 @@ -150,6 +150,13 @@
 620           Internal configuration to enable S3C64XX style GPIO configuration
 621           functions.
 622
 623 +# DMA
 624 +
 625 +config S3C_DMA
 626 +       bool
 627 +       help
 628 +         Internal configuration for S3C DMA core
 629 +
 630  # device definitions to compile in
 631
 632  config S3C_DEV_HSMMC
 633 Index: linux-2.6.30-rc6/arch/arm/plat-s3c/Makefile
 634 ===================================================================
 635 --- linux-2.6.30-rc6.orig/arch/arm/plat-s3c/Makefile    2009-05-18 19:07:48.000000000 +0200
 636 +++ linux-2.6.30-rc6/arch/arm/plat-s3c/Makefile 2009-05-18 19:08:29.000000000 +0200
 637 @@ -18,6 +18,10 @@
 638  obj-y                          += gpio.o
 639  obj-y                          += gpio-config.o
 640
 641 +# DMA support
 642 +
 643 +obj-$(CONFIG_S3C_DMA)          += dma.o
 644 +
 645  # PM support
 646
 647  obj-$(CONFIG_PM)               += pm.o
 648 @@ -31,3 +35,5 @@
 649  obj-y                          += dev-i2c0.o
 650  obj-$(CONFIG_S3C_DEV_I2C1)     += dev-i2c1.o
 651  obj-$(CONFIG_S3C_DEV_FB)       += dev-fb.o
 652 +obj-$(CONFIG_S3C_DMA)          += dma.o
 653 +
 654 Index: linux-2.6.30-rc6/arch/arm/plat-s3c24xx/dma.c
 655 ===================================================================
 656 --- linux-2.6.30-rc6.orig/arch/arm/plat-s3c24xx/dma.c   2009-05-16 06:12:57.000000000 +0200
 657 +++ linux-2.6.30-rc6/arch/arm/plat-s3c24xx/dma.c        2009-05-18 19:08:29.000000000 +0200
 658 @@ -31,10 +31,11 @@
 659  #include <asm/irq.h>
 660  #include <mach/hardware.h>
 661  #include <mach/dma.h>
 662 -
 663  #include <mach/map.h>
 664
 665 -#include <plat/dma.h>
 666 +#include <plat/dma-core.h>
 667 +#include <plat/regs-dma.h>
 668 +#include <plat/dma-plat.h>
 669
 670  /* io map for dma */
 671  static void __iomem *dma_base;
 672 @@ -44,8 +45,6 @@
 673
 674  static struct s3c24xx_dma_selection dma_sel;
 675
 676 -/* dma channel state information */
 677 -struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
 678
 679  /* debugging functions */
 680
 681 @@ -135,21 +134,6 @@
 682  #define dbg_showchan(chan) do { } while(0)
 683  #endif /* CONFIG_S3C2410_DMA_DEBUG */
 684
 685 -static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
 686 -
 687 -/* lookup_dma_channel
 688 - *
 689 - * change the dma channel number given into a real dma channel id
 690 -*/
 691 -
 692 -static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
 693 -{
 694 -       if (channel & DMACH_LOW_LEVEL)
 695 -               return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
 696 -       else
 697 -               return dma_chan_map[channel];
 698 -}
 699 -
 700  /* s3c2410_dma_stats_timeout
 701   *
 702   * Update DMA stats from timeout info
 703 @@ -214,8 +198,6 @@
 704         return 0;
 705  }
 706
 707 -
 708 -
 709  /* s3c2410_dma_loadbuffer
 710   *
 711   * load a buffer, and update the channel state
 712 @@ -453,7 +435,7 @@
 713  int s3c2410_dma_enqueue(unsigned int channel, void *id,
 714                         dma_addr_t data, int size)
 715  {
 716 -       struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
 717 +       struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 718         struct s3c2410_dma_buf *buf;
 719         unsigned long flags;
 720
 721 @@ -804,7 +786,7 @@
 722
 723  int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
 724  {
 725 -       struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
 726 +       struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 727         unsigned long flags;
 728
 729         if (chan == NULL)
 730 @@ -836,7 +818,7 @@
 731         chan->irq_claimed = 0;
 732
 733         if (!(channel & DMACH_LOW_LEVEL))
 734 -               dma_chan_map[channel] = NULL;
 735 +               s3c_dma_chan_map[channel] = NULL;
 736
 737         local_irq_restore(flags);
 738
 739 @@ -995,7 +977,7 @@
 740  int
 741  s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
 742  {
 743 -       struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
 744 +       struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 745
 746         if (chan == NULL)
 747                 return -EINVAL;
 748 @@ -1038,14 +1020,13 @@
 749  /* s3c2410_dma_config
 750   *
 751   * xfersize:     size of unit in bytes (1,2,4)
 752 - * dcon:         base value of the DCONx register
 753  */
 754
 755  int s3c2410_dma_config(unsigned int channel,
 756 -                      int xferunit,
 757 -                      int dcon)
 758 +                      int xferunit)
 759  {
 760 -       struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
 761 +       struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 762 +       unsigned int dcon;
 763
 764         pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
 765                  __func__, channel, xferunit, dcon);
 766 @@ -1055,10 +1036,33 @@
 767
 768         pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
 769
 770 -       dcon |= chan->dcon & dma_sel.dcon_mask;
 771 +       dcon = chan->dcon & dma_sel.dcon_mask;
 772
 773         pr_debug("%s: New dcon is %08x\n", __func__, dcon);
 774
 775 +       switch (chan->req_ch) {
 776 +       case DMACH_I2S_IN:
 777 +       case DMACH_I2S_OUT:
 778 +       case DMACH_PCM_IN:
 779 +       case DMACH_PCM_OUT:
 780 +       case DMACH_MIC_IN:
 781 +       default:
 782 +               dcon |= S3C2410_DCON_HANDSHAKE;
 783 +               dcon |= S3C2410_DCON_SYNC_PCLK;
 784 +               break;
 785 +
 786 +       case DMACH_SDI:
 787 +               /* note, ensure if need HANDSHAKE or not */
 788 +               dcon |= S3C2410_DCON_SYNC_PCLK;
 789 +               break;
 790 +
 791 +       case DMACH_XD0:
 792 +       case DMACH_XD1:
 793 +               dcon |= S3C2410_DCON_HANDSHAKE;
 794 +               dcon |= S3C2410_DCON_SYNC_HCLK;
 795 +               break;
 796 +       }
 797 +
 798         switch (xferunit) {
 799         case 1:
 800                 dcon |= S3C2410_DCON_BYTE;
 801 @@ -1089,10 +1093,10 @@
 802  }
 803
 804  EXPORT_SYMBOL(s3c2410_dma_config);
 805 -
 806 +#if 0 /* moved to plat-s3c? */
 807  int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
 808  {
 809 -       struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
 810 +       struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 811
 812         if (chan == NULL)
 813                 return -EINVAL;
 814 @@ -1105,43 +1109,7 @@
 815  }
 816
 817  EXPORT_SYMBOL(s3c2410_dma_setflags);
 818 -
 819 -
 820 -/* do we need to protect the settings of the fields from
 821 - * irq?
 822 -*/
 823 -
 824 -int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
 825 -{
 826 -       struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
 827 -
 828 -       if (chan == NULL)
 829 -               return -EINVAL;
 830 -
 831 -       pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
 832 -
 833 -       chan->op_fn = rtn;
 834 -
 835 -       return 0;
 836 -}
 837 -
 838 -EXPORT_SYMBOL(s3c2410_dma_set_opfn);
 839 -
 840 -int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
 841 -{
 842 -       struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
 843 -
 844 -       if (chan == NULL)
 845 -               return -EINVAL;
 846 -
 847 -       pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
 848 -
 849 -       chan->callback_fn = rtn;
 850 -
 851 -       return 0;
 852 -}
 853 -
 854 -EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
 855 +#endif
 856
 857  /* s3c2410_dma_devconfig
 858   *
 859 @@ -1150,29 +1118,38 @@
 860   * source:    S3C2410_DMASRC_HW: source is hardware
 861   *            S3C2410_DMASRC_MEM: source is memory
 862   *
 863 - * hwcfg:     the value for xxxSTCn register,
 864 - *            bit 0: 0=increment pointer, 1=leave pointer
 865 - *            bit 1: 0=source is AHB, 1=source is APB
 866 - *
 867   * devaddr:   physical address of the source
 868  */
 869
 870  int s3c2410_dma_devconfig(int channel,
 871                           enum s3c2410_dmasrc source,
 872 -                         int hwcfg,
 873                           unsigned long devaddr)
 874  {
 875 -       struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
 876 +       struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 877 +       unsigned int hwcfg;
 878
 879         if (chan == NULL)
 880                 return -EINVAL;
 881
 882 -       pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
 883 -                __func__, (int)source, hwcfg, devaddr);
 884 +       pr_debug("%s: source=%d, devaddr=%08lx\n",
 885 +                __func__, (int)source, devaddr);
 886
 887         chan->source = source;
 888         chan->dev_addr = devaddr;
 889 -       chan->hw_cfg = hwcfg;
 890 +
 891 +       switch (chan->req_ch) {
 892 +       case DMACH_XD0:
 893 +       case DMACH_XD1:
 894 +               hwcfg = 0; /* AHB */
 895 +               break;
 896 +
 897 +       default:
 898 +               hwcfg = S3C2410_DISRCC_APB;
 899 +       }
 900 +
 901 +       /* always assume our peripheral desintation is a fixed
 902 +        * address in memory. */
 903 +        hwcfg |= S3C2410_DISRCC_INC;
 904
 905         switch (source) {
 906         case S3C2410_DMASRC_HW:
 907 @@ -1219,7 +1196,7 @@
 908
 909  int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dst)
 910  {
 911 -       struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
 912 +       struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
 913
 914         if (chan == NULL)
 915                 return -EINVAL;
 916 @@ -1278,8 +1255,8 @@
 917
 918         printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
 919
 920 -       s3c2410_dma_config(no, cp->xfer_unit, cp->dcon);
 921 -       s3c2410_dma_devconfig(no, cp->source, cp->hw_cfg, cp->dev_addr);
 922 +       s3c2410_dma_config(no, cp->xfer_unit);
 923 +       s3c2410_dma_devconfig(no, cp->source, cp->dev_addr);
 924
 925         /* re-select the dma source for this channel */
 926
 927 @@ -1476,7 +1453,8 @@
 928   found:
 929         dmach = &s3c2410_chans[ch];
 930         dmach->map = ch_map;
 931 -       dma_chan_map[channel] = dmach;
 932 +       dmach->req_ch = channel;
 933 +       s3c_dma_chan_map[channel] = dmach;
 934
 935         /* select the channel */
 936
 937 Index: linux-2.6.30-rc6/arch/arm/plat-s3c24xx/include/plat/dma.h
 938 ===================================================================
 939 --- linux-2.6.30-rc6.orig/arch/arm/plat-s3c24xx/include/plat/dma.h      2009-05-16 06:12:57.000000000 +0200
 940 +++ /dev/null   1970-01-01 00:00:00.000000000 +0000
 941 @@ -1,82 +0,0 @@
 942 -/* linux/include/asm-arm/plat-s3c24xx/dma.h
 943 - *
 944 - * Copyright (C) 2006 Simtec Electronics
 945 - *     Ben Dooks <ben@simtec.co.uk>
 946 - *
 947 - * Samsung S3C24XX DMA support
 948 - *
 949 - * This program is free software; you can redistribute it and/or modify
 950 - * it under the terms of the GNU General Public License version 2 as
 951 - * published by the Free Software Foundation.
 952 -*/
 953 -
 954 -extern struct sysdev_class dma_sysclass;
 955 -extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
 956 -
 957 -#define DMA_CH_VALID           (1<<31)
 958 -#define DMA_CH_NEVER           (1<<30)
 959 -
 960 -struct s3c24xx_dma_addr {
 961 -       unsigned long           from;
 962 -       unsigned long           to;
 963 -};
 964 -
 965 -/* struct s3c24xx_dma_map
 966 - *
 967 - * this holds the mapping information for the channel selected
 968 - * to be connected to the specified device
 969 -*/
 970 -
 971 -struct s3c24xx_dma_map {
 972 -       const char              *name;
 973 -       struct s3c24xx_dma_addr  hw_addr;
 974 -
 975 -       unsigned long            channels[S3C2410_DMA_CHANNELS];
 976 -       unsigned long            channels_rx[S3C2410_DMA_CHANNELS];
 977 -};
 978 -
 979 -struct s3c24xx_dma_selection {
 980 -       struct s3c24xx_dma_map  *map;
 981 -       unsigned long            map_size;
 982 -       unsigned long            dcon_mask;
 983 -
 984 -       void    (*select)(struct s3c2410_dma_chan *chan,
 985 -                         struct s3c24xx_dma_map *map);
 986 -
 987 -       void    (*direction)(struct s3c2410_dma_chan *chan,
 988 -                            struct s3c24xx_dma_map *map,
 989 -                            enum s3c2410_dmasrc dir);
 990 -};
 991 -
 992 -extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
 993 -
 994 -/* struct s3c24xx_dma_order_ch
 995 - *
 996 - * channel map for one of the `enum dma_ch` dma channels. the list
 997 - * entry contains a set of low-level channel numbers, orred with
 998 - * DMA_CH_VALID, which are checked in the order in the array.
 999 -*/
1000 -
1001 -struct s3c24xx_dma_order_ch {
1002 -       unsigned int    list[S3C2410_DMA_CHANNELS];     /* list of channels */
1003 -       unsigned int    flags;                          /* flags */
1004 -};
1005 -
1006 -/* struct s3c24xx_dma_order
1007 - *
1008 - * information provided by either the core or the board to give the
1009 - * dma system a hint on how to allocate channels
1010 -*/
1011 -
1012 -struct s3c24xx_dma_order {
1013 -       struct s3c24xx_dma_order_ch     channels[DMACH_MAX];
1014 -};
1015 -
1016 -extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
1017 -
1018 -/* DMA init code, called from the cpu support code */
1019 -
1020 -extern int s3c2410_dma_init(void);
1021 -
1022 -extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq,
1023 -                           unsigned int stride);
1024 Index: linux-2.6.30-rc6/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
1025 ===================================================================
1026 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
1027 +++ linux-2.6.30-rc6/arch/arm/plat-s3c24xx/include/plat/dma-plat.h      2009-05-18 19:08:29.000000000 +0200
1028 @@ -0,0 +1,84 @@
1029 +/* linux/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
1030 + *
1031 + * Copyright (C) 2006 Simtec Electronics
1032 + *     Ben Dooks <ben@simtec.co.uk>
1033 + *
1034 + * Samsung S3C24XX DMA support
1035 + *
1036 + * This program is free software; you can redistribute it and/or modify
1037 + * it under the terms of the GNU General Public License version 2 as
1038 + * published by the Free Software Foundation.
1039 +*/
1040 +
1041 +#include <plat/dma-core.h>
1042 +
1043 +extern struct sysdev_class dma_sysclass;
1044 +extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
1045 +
1046 +#define DMA_CH_VALID           (1<<31)
1047 +#define DMA_CH_NEVER           (1<<30)
1048 +
1049 +struct s3c24xx_dma_addr {
1050 +       unsigned long           from;
1051 +       unsigned long           to;
1052 +};
1053 +
1054 +/* struct s3c24xx_dma_map
1055 + *
1056 + * this holds the mapping information for the channel selected
1057 + * to be connected to the specified device
1058 +*/
1059 +
1060 +struct s3c24xx_dma_map {
1061 +       const char              *name;
1062 +       struct s3c24xx_dma_addr  hw_addr;
1063 +
1064 +       unsigned long            channels[S3C_DMA_CHANNELS];
1065 +       unsigned long            channels_rx[S3C_DMA_CHANNELS];
1066 +};
1067 +
1068 +struct s3c24xx_dma_selection {
1069 +       struct s3c24xx_dma_map  *map;
1070 +       unsigned long            map_size;
1071 +       unsigned long            dcon_mask;
1072 +
1073 +       void    (*select)(struct s3c2410_dma_chan *chan,
1074 +                         struct s3c24xx_dma_map *map);
1075 +
1076 +       void    (*direction)(struct s3c2410_dma_chan *chan,
1077 +                            struct s3c24xx_dma_map *map,
1078 +                            enum s3c2410_dmasrc dir);
1079 +};
1080 +
1081 +extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
1082 +
1083 +/* struct s3c24xx_dma_order_ch
1084 + *
1085 + * channel map for one of the `enum dma_ch` dma channels. the list
1086 + * entry contains a set of low-level channel numbers, orred with
1087 + * DMA_CH_VALID, which are checked in the order in the array.
1088 +*/
1089 +
1090 +struct s3c24xx_dma_order_ch {
1091 +       unsigned int    list[S3C_DMA_CHANNELS]; /* list of channels */
1092 +       unsigned int    flags;                          /* flags */
1093 +};
1094 +
1095 +/* struct s3c24xx_dma_order
1096 + *
1097 + * information provided by either the core or the board to give the
1098 + * dma system a hint on how to allocate channels
1099 +*/
1100 +
1101 +struct s3c24xx_dma_order {
1102 +       struct s3c24xx_dma_order_ch     channels[DMACH_MAX];
1103 +};
1104 +
1105 +extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
1106 +
1107 +/* DMA init code, called from the cpu support code */
1108 +
1109 +extern int s3c2410_dma_init(void);
1110 +
1111 +extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq,
1112 +                           unsigned int stride);
1113 Index: linux-2.6.30-rc6/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
1114 ===================================================================
1115 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
1116 +++ linux-2.6.30-rc6/arch/arm/plat-s3c24xx/include/plat/regs-dma.h      2009-05-18 19:08:29.000000000 +0200
1117 @@ -0,0 +1,145 @@
1118 +/* arch/arm/mach-s3c2410/include/mach/dma.h
1119 + *
1120 + * Copyright (C) 2003,2004,2006 Simtec Electronics
1121 + *     Ben Dooks <ben@simtec.co.uk>
1122 + *
1123 + * Samsung S3C24XX DMA support
1124 + *
1125 + * This program is free software; you can redistribute it and/or modify
1126 + * it under the terms of the GNU General Public License version 2 as
1127 + * published by the Free Software Foundation.
1128 +*/
1129 +
1130 +/* DMA Register definitions */
1131 +
1132 +#define S3C2410_DMA_DISRC              (0x00)
1133 +#define S3C2410_DMA_DISRCC             (0x04)
1134 +#define S3C2410_DMA_DIDST              (0x08)
1135 +#define S3C2410_DMA_DIDSTC             (0x0C)
1136 +#define S3C2410_DMA_DCON               (0x10)
1137 +#define S3C2410_DMA_DSTAT              (0x14)
1138 +#define S3C2410_DMA_DCSRC              (0x18)
1139 +#define S3C2410_DMA_DCDST              (0x1C)
1140 +#define S3C2410_DMA_DMASKTRIG          (0x20)
1141 +#define S3C2412_DMA_DMAREQSEL          (0x24)
1142 +#define S3C2443_DMA_DMAREQSEL          (0x24)
1143 +
1144 +#define S3C2410_DISRCC_INC             (1<<0)
1145 +#define S3C2410_DISRCC_APB             (1<<1)
1146 +
1147 +#define S3C2410_DMASKTRIG_STOP         (1<<2)
1148 +#define S3C2410_DMASKTRIG_ON           (1<<1)
1149 +#define S3C2410_DMASKTRIG_SWTRIG       (1<<0)
1150 +
1151 +#define S3C2410_DCON_DEMAND            (0<<31)
1152 +#define S3C2410_DCON_HANDSHAKE         (1<<31)
1153 +#define S3C2410_DCON_SYNC_PCLK         (0<<30)
1154 +#define S3C2410_DCON_SYNC_HCLK         (1<<30)
1155 +
1156 +#define S3C2410_DCON_INTREQ            (1<<29)
1157 +
1158 +#define S3C2410_DCON_CH0_XDREQ0                (0<<24)
1159 +#define S3C2410_DCON_CH0_UART0         (1<<24)
1160 +#define S3C2410_DCON_CH0_SDI           (2<<24)
1161 +#define S3C2410_DCON_CH0_TIMER         (3<<24)
1162 +#define S3C2410_DCON_CH0_USBEP1                (4<<24)
1163 +
1164 +#define S3C2410_DCON_CH1_XDREQ1                (0<<24)
1165 +#define S3C2410_DCON_CH1_UART1         (1<<24)
1166 +#define S3C2410_DCON_CH1_I2SSDI                (2<<24)
1167 +#define S3C2410_DCON_CH1_SPI           (3<<24)
1168 +#define S3C2410_DCON_CH1_USBEP2                (4<<24)
1169 +
1170 +#define S3C2410_DCON_CH2_I2SSDO                (0<<24)
1171 +#define S3C2410_DCON_CH2_I2SSDI                (1<<24)
1172 +#define S3C2410_DCON_CH2_SDI           (2<<24)
1173 +#define S3C2410_DCON_CH2_TIMER         (3<<24)
1174 +#define S3C2410_DCON_CH2_USBEP3                (4<<24)
1175 +
1176 +#define S3C2410_DCON_CH3_UART2         (0<<24)
1177 +#define S3C2410_DCON_CH3_SDI           (1<<24)
1178 +#define S3C2410_DCON_CH3_SPI           (2<<24)
1179 +#define S3C2410_DCON_CH3_TIMER         (3<<24)
1180 +#define S3C2410_DCON_CH3_USBEP4                (4<<24)
1181 +
1182 +#define S3C2410_DCON_SRCSHIFT          (24)
1183 +#define S3C2410_DCON_SRCMASK           (7<<24)
1184 +
1185 +#define S3C2410_DCON_BYTE              (0<<20)
1186 +#define S3C2410_DCON_HALFWORD          (1<<20)
1187 +#define S3C2410_DCON_WORD              (2<<20)
1188 +
1189 +#define S3C2410_DCON_AUTORELOAD                (0<<22)
1190 +#define S3C2410_DCON_NORELOAD          (1<<22)
1191 +#define S3C2410_DCON_HWTRIG            (1<<23)
1192 +
1193 +#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
1194 +#define S3C2440_DIDSTC_CHKINT          (1<<2)
1195 +
1196 +#define S3C2440_DCON_CH0_I2SSDO                (5<<24)
1197 +#define S3C2440_DCON_CH0_PCMIN         (6<<24)
1198 +
1199 +#define S3C2440_DCON_CH1_PCMOUT                (5<<24)
1200 +#define S3C2440_DCON_CH1_SDI           (6<<24)
1201 +
1202 +#define S3C2440_DCON_CH2_PCMIN         (5<<24)
1203 +#define S3C2440_DCON_CH2_MICIN         (6<<24)
1204 +
1205 +#define S3C2440_DCON_CH3_MICIN         (5<<24)
1206 +#define S3C2440_DCON_CH3_PCMOUT                (6<<24)
1207 +#endif
1208 +
1209 +#ifdef CONFIG_CPU_S3C2412
1210 +
1211 +#define S3C2412_DMAREQSEL_SRC(x)       ((x)<<1)
1212 +
1213 +#define S3C2412_DMAREQSEL_HW           (1)
1214 +
1215 +#define S3C2412_DMAREQSEL_SPI0TX       S3C2412_DMAREQSEL_SRC(0)
1216 +#define S3C2412_DMAREQSEL_SPI0RX       S3C2412_DMAREQSEL_SRC(1)
1217 +#define S3C2412_DMAREQSEL_SPI1TX       S3C2412_DMAREQSEL_SRC(2)
1218 +#define S3C2412_DMAREQSEL_SPI1RX       S3C2412_DMAREQSEL_SRC(3)
1219 +#define S3C2412_DMAREQSEL_I2STX                S3C2412_DMAREQSEL_SRC(4)
1220 +#define S3C2412_DMAREQSEL_I2SRX                S3C2412_DMAREQSEL_SRC(5)
1221 +#define S3C2412_DMAREQSEL_TIMER                S3C2412_DMAREQSEL_SRC(9)
1222 +#define S3C2412_DMAREQSEL_SDI          S3C2412_DMAREQSEL_SRC(10)
1223 +#define S3C2412_DMAREQSEL_USBEP1       S3C2412_DMAREQSEL_SRC(13)
1224 +#define S3C2412_DMAREQSEL_USBEP2       S3C2412_DMAREQSEL_SRC(14)
1225 +#define S3C2412_DMAREQSEL_USBEP3       S3C2412_DMAREQSEL_SRC(15)
1226 +#define S3C2412_DMAREQSEL_USBEP4       S3C2412_DMAREQSEL_SRC(16)
1227 +#define S3C2412_DMAREQSEL_XDREQ0       S3C2412_DMAREQSEL_SRC(17)
1228 +#define S3C2412_DMAREQSEL_XDREQ1       S3C2412_DMAREQSEL_SRC(18)
1229 +#define S3C2412_DMAREQSEL_UART0_0      S3C2412_DMAREQSEL_SRC(19)
1230 +#define S3C2412_DMAREQSEL_UART0_1      S3C2412_DMAREQSEL_SRC(20)
1231 +#define S3C2412_DMAREQSEL_UART1_0      S3C2412_DMAREQSEL_SRC(21)
1232 +#define S3C2412_DMAREQSEL_UART1_1      S3C2412_DMAREQSEL_SRC(22)
1233 +#define S3C2412_DMAREQSEL_UART2_0      S3C2412_DMAREQSEL_SRC(23)
1234 +#define S3C2412_DMAREQSEL_UART2_1      S3C2412_DMAREQSEL_SRC(24)
1235 +
1236 +#endif
1237 +
1238 +#define S3C2443_DMAREQSEL_SRC(x)       ((x)<<1)
1239 +
1240 +#define S3C2443_DMAREQSEL_HW           (1)
1241 +
1242 +#define S3C2443_DMAREQSEL_SPI0TX       S3C2443_DMAREQSEL_SRC(0)
1243 +#define S3C2443_DMAREQSEL_SPI0RX       S3C2443_DMAREQSEL_SRC(1)
1244 +#define S3C2443_DMAREQSEL_SPI1TX       S3C2443_DMAREQSEL_SRC(2)
1245 +#define S3C2443_DMAREQSEL_SPI1RX       S3C2443_DMAREQSEL_SRC(3)
1246 +#define S3C2443_DMAREQSEL_I2STX                S3C2443_DMAREQSEL_SRC(4)
1247 +#define S3C2443_DMAREQSEL_I2SRX                S3C2443_DMAREQSEL_SRC(5)
1248 +#define S3C2443_DMAREQSEL_TIMER                S3C2443_DMAREQSEL_SRC(9)
1249 +#define S3C2443_DMAREQSEL_SDI          S3C2443_DMAREQSEL_SRC(10)
1250 +#define S3C2443_DMAREQSEL_XDREQ0       S3C2443_DMAREQSEL_SRC(17)
1251 +#define S3C2443_DMAREQSEL_XDREQ1       S3C2443_DMAREQSEL_SRC(18)
1252 +#define S3C2443_DMAREQSEL_UART0_0      S3C2443_DMAREQSEL_SRC(19)
1253 +#define S3C2443_DMAREQSEL_UART0_1      S3C2443_DMAREQSEL_SRC(20)
1254 +#define S3C2443_DMAREQSEL_UART1_0      S3C2443_DMAREQSEL_SRC(21)
1255 +#define S3C2443_DMAREQSEL_UART1_1      S3C2443_DMAREQSEL_SRC(22)
1256 +#define S3C2443_DMAREQSEL_UART2_0      S3C2443_DMAREQSEL_SRC(23)
1257 +#define S3C2443_DMAREQSEL_UART2_1      S3C2443_DMAREQSEL_SRC(24)
1258 +#define S3C2443_DMAREQSEL_UART3_0      S3C2443_DMAREQSEL_SRC(25)
1259 +#define S3C2443_DMAREQSEL_UART3_1      S3C2443_DMAREQSEL_SRC(26)
1260 +#define S3C2443_DMAREQSEL_PCMOUT       S3C2443_DMAREQSEL_SRC(27)
1261 +#define S3C2443_DMAREQSEL_PCMIN        S3C2443_DMAREQSEL_SRC(28)
1262 +#define S3C2443_DMAREQSEL_MICIN                S3C2443_DMAREQSEL_SRC(29)
1263 Index: linux-2.6.30-rc6/arch/arm/plat-s3c24xx/Kconfig
1264 ===================================================================
1265 --- linux-2.6.30-rc6.orig/arch/arm/plat-s3c24xx/Kconfig 2009-05-16 06:12:57.000000000 +0200
1266 +++ linux-2.6.30-rc6/arch/arm/plat-s3c24xx/Kconfig      2009-05-18 19:08:29.000000000 +0200
1267 @@ -71,6 +71,7 @@
1268  config S3C2410_DMA
1269         bool "S3C2410 DMA support"
1270         depends on ARCH_S3C2410
1271 +       select S3C_DMA
1272         help
1273           S3C2410 DMA support. This is needed for drivers like sound which
1274           use the S3C2410's DMA system to move data to and from the
1275 Index: linux-2.6.30-rc6/arch/arm/mach-s3c2410/dma.c
1276 ===================================================================
1277 --- linux-2.6.30-rc6.orig/arch/arm/mach-s3c2410/dma.c   2009-05-16 06:12:57.000000000 +0200
1278 +++ linux-2.6.30-rc6/arch/arm/mach-s3c2410/dma.c        2009-05-18 19:08:29.000000000 +0200
1279 @@ -17,14 +17,16 @@
1280  #include <linux/sysdev.h>
1281  #include <linux/serial_core.h>
1282
1283 +#include <mach/map.h>
1284  #include <mach/dma.h>
1285
1286  #include <plat/cpu.h>
1287 -#include <plat/dma.h>
1288 +#include <plat/dma-plat.h>
1289
1290  #include <plat/regs-serial.h>
1291  #include <mach/regs-gpio.h>
1292  #include <plat/regs-ac97.h>
1293 +#include <plat/regs-dma.h>
1294  #include <mach/regs-mem.h>
1295  #include <mach/regs-lcd.h>
1296  #include <mach/regs-sdi.h>
1297 Index: linux-2.6.30-rc6/arch/arm/mach-s3c2440/dma.c
1298 ===================================================================
1299 --- linux-2.6.30-rc6.orig/arch/arm/mach-s3c2440/dma.c   2009-05-16 06:12:57.000000000 +0200
1300 +++ linux-2.6.30-rc6/arch/arm/mach-s3c2440/dma.c        2009-05-18 19:08:29.000000000 +0200
1301 @@ -17,14 +17,16 @@
1302  #include <linux/sysdev.h>
1303  #include <linux/serial_core.h>
1304
1305 +#include <mach/map.h>
1306  #include <mach/dma.h>
1307
1308 -#include <plat/dma.h>
1309 +#include <plat/dma-plat.h>
1310  #include <plat/cpu.h>
1311
1312  #include <plat/regs-serial.h>
1313  #include <mach/regs-gpio.h>
1314  #include <plat/regs-ac97.h>
1315 +#include <plat/regs-dma.h>
1316  #include <mach/regs-mem.h>
1317  #include <mach/regs-lcd.h>
1318  #include <mach/regs-sdi.h>