target/linux/ppc40x/patches/007-openrb-light.patch

   1 --- a/arch/powerpc/boot/Makefile
   2 +++ b/arch/powerpc/boot/Makefile
   3 @@ -70,7 +70,8 @@ src-plat := of.c cuboot-52xx.c cuboot-82
   4                 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
   5                 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
   6                 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
   7 -               cuboot-acadia.c cuboot-magicboxv1.c cuboot-magicboxv2.c
   8 +               cuboot-acadia.c cuboot-magicboxv1.c cuboot-magicboxv2.c \
   9 +               cuboot-openrb-light.c
  10  src-boot := $(src-wlib) $(src-plat) empty.c
  11
  12  src-boot := $(addprefix $(obj)/, $(src-boot))
  13 @@ -216,6 +217,7 @@ image-$(CONFIG_WALNUT)                      += treeImage.wa
  14  image-$(CONFIG_ACADIA)                 += cuImage.acadia
  15  image-$(CONFIG_MAGICBOXV1)             += cuImage.magicboxv1
  16  image-$(CONFIG_MAGICBOXV2)             += cuImage.magicboxv2
  17 +image-$(CONFIG_OPENRB_LIGHT)           += cuImage.openrb-light
  18
  19  # Board ports in arch/powerpc/platform/44x/Kconfig
  20  image-$(CONFIG_EBONY)                  += treeImage.ebony cuImage.ebony
  21 --- a/arch/powerpc/platforms/40x/Kconfig
  22 +++ b/arch/powerpc/platforms/40x/Kconfig
  23 @@ -79,6 +79,16 @@ config MAKALU
  24         help
  25           This option enables support for the AMCC PPC405EX board.
  26
  27 +config OPENRB_LIGHT
  28 +       bool "OpenRB Light"
  29 +       depends on 40x
  30 +       default n
  31 +       select PPC40x_SIMPLE
  32 +       select 405EP
  33 +       select PCI
  34 +       help
  35 +         This option enables support for the OpenRB Light board.
  36 +
  37  #config REDWOOD_5
  38  #      bool "Redwood-5"
  39  #      depends on 40x
  40 --- a/arch/powerpc/platforms/40x/ppc40x_simple.c
  41 +++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
  42 @@ -54,6 +54,7 @@ static char *board[] __initdata = {
  43         "amcc,acadia",
  44         "magicboxv1",
  45         "magicboxv2",
  46 +       "openrb,light",
  47  };
  48
  49  static int __init ppc40x_probe(void)
  50 --- /dev/null
  51 +++ b/arch/powerpc/boot/cuboot-openrb-light.c
  52 @@ -0,0 +1,69 @@
  53 +/*
  54 + * Old U-boot compatibility for OpenRB Light board
  55 + *
  56 + * Author: Gabor Juhos <juhosg@openwrt.org>
  57 + *
  58 + * This program is free software; you can redistribute it and/or modify it
  59 + * under the terms of the GNU General Public License version 2 as published
  60 + * by the Free Software Foundation.
  61 + */
  62 +
  63 +#include "ops.h"
  64 +#include "io.h"
  65 +#include "dcr.h"
  66 +#include "stdio.h"
  67 +#include "4xx.h"
  68 +#include "44x.h"
  69 +#include "cuboot.h"
  70 +
  71 +#define TARGET_4xx
  72 +#define TARGET_405EP
  73 +#include "ppcboot.h"
  74 +
  75 +static bd_t bd;
  76 +
  77 +static void fixup_cf_card(void)
  78 +{
  79 +#define DCRN_CPC0_PCI_BASE     0xf9
  80 +#define CF_CS0_BASE            0xff100000
  81 +#define CF_CS1_BASE            0xff200000
  82 +
  83 +       /* Turn on PerWE instead of PCIsomething */
  84 +       mtdcr(DCRN_CPC0_PCI_BASE,
  85 +             mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
  86 +
  87 +       /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
  88 +       mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
  89 +       mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
  90 +       mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
  91 +       mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
  92 +
  93 +       /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
  94 +       mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
  95 +       mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
  96 +       mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
  97 +       mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
  98 +
  99 +#undef DCRN_CPC0_PCI_BASE
 100 +#undef CF_CS0_BASE
 101 +#undef CF_CS1_BASE
 102 +}
 103 +
 104 +static void openrb_light_fixups(void)
 105 +{
 106 +       fixup_cf_card();
 107 +       ibm405ep_fixup_clocks(33333000);
 108 +       ibm4xx_sdram_fixup_memsize();
 109 +       dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
 110 +}
 111 +
 112 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 113 +               unsigned long r6, unsigned long r7)
 114 +{
 115 +       CUBOOT_INIT();
 116 +       platform_ops.fixups = openrb_light_fixups;
 117 +       platform_ops.exit = ibm40x_dbcr_reset;
 118 +       fdt_init(_dtb_start);
 119 +       serial_console_init();
 120 +}
 121 +
 122 --- /dev/null
 123 +++ b/arch/powerpc/boot/dts/openrb-light.dts
 124 @@ -0,0 +1,252 @@
 125 +/*
 126 + * Device Tree Source for OpenRB Light board
 127 + *
 128 + * Copyright 2009 Gabor Juhos <juhosg@openwrt.org>
 129 + *
 130 + * Based on magicboxv2.dts
 131 + *
 132 + * This file is licensed under the terms of the GNU General Public
 133 + * License version 2.  This program is licensed "as is" without
 134 + * any warranty of any kind, whether express or implied.
 135 + */
 136 +
 137 +/dts-v1/;
 138 +
 139 +/ {
 140 +       #address-cells = <1>;
 141 +       #size-cells = <1>;
 142 +       model = "openrb,light";
 143 +       compatible = "openrb,light";
 144 +       dcr-parent = <&{/cpus/cpu@0}>;
 145 +
 146 +       aliases {
 147 +               ethernet0 = &EMAC0;
 148 +               serial0 = &UART0;
 149 +               serial1 = &UART1;
 150 +       };
 151 +
 152 +       cpus {
 153 +               #address-cells = <1>;
 154 +               #size-cells = <0>;
 155 +
 156 +               cpu@0 {
 157 +                       device_type = "cpu";
 158 +                       model = "PowerPC,405EP";
 159 +                       reg = <0x00000000>;
 160 +                       clock-frequency = <0xbebc200>; /* Filled in by zImage */
 161 +                       timebase-frequency = <0>; /* Filled in by zImage */
 162 +                       i-cache-line-size = <20>;
 163 +                       d-cache-line-size = <20>;
 164 +                       i-cache-size = <4000>;
 165 +                       d-cache-size = <4000>;
 166 +                       dcr-controller;
 167 +                       dcr-access-method = "native";
 168 +               };
 169 +       };
 170 +
 171 +       memory {
 172 +               device_type = "memory";
 173 +               reg = <0x00000000 0x00000000>; /* Filled in by zImage */
 174 +       };
 175 +
 176 +       UIC0: interrupt-controller {
 177 +               compatible = "ibm,uic";
 178 +               interrupt-controller;
 179 +               cell-index = <0>;
 180 +               dcr-reg = <0x0c0 0x009>;
 181 +               #address-cells = <0>;
 182 +               #size-cells = <0>;
 183 +               #interrupt-cells = <2>;
 184 +       };
 185 +
 186 +       plb {
 187 +               compatible = "ibm,plb3";
 188 +               #address-cells = <1>;
 189 +               #size-cells = <1>;
 190 +               ranges;
 191 +               clock-frequency = <0>; /* Filled in by zImage */
 192 +
 193 +               SDRAM0: memory-controller {
 194 +                       compatible = "ibm,sdram-405ep";
 195 +                       dcr-reg = <0x010 0x002>;
 196 +               };
 197 +
 198 +               MAL: mcmal {
 199 +                       compatible = "ibm,mcmal-405ep", "ibm,mcmal";
 200 +                       dcr-reg = <0x180 0x062>;
 201 +                       num-tx-chans = <4>;
 202 +                       num-rx-chans = <2>;
 203 +                       interrupt-parent = <&UIC0>;
 204 +                       interrupts = <
 205 +                               0xb 0x4 /* TXEOB */
 206 +                               0xc 0x4 /* RXEOB */
 207 +                               0xa 0x4 /* SERR */
 208 +                               0xd 0x4 /* TXDE */
 209 +                               0xe 0x4 /* RXDE */>;
 210 +               };
 211 +
 212 +               OPB0: opb {
 213 +                       compatible = "ibm,opb-405ep", "ibm,opb";
 214 +                       #address-cells = <1>;
 215 +                       #size-cells = <1>;
 216 +                       ranges = <0xef600000 0xef600000 0x00a00000>;
 217 +                       dcr-reg = <0x0a0 0x005>;
 218 +                       clock-frequency = <0>; /* Filled in by zImage */
 219 +
 220 +                       UART0: serial@ef600300 {
 221 +                               device_type = "serial";
 222 +                               compatible = "ns16550";
 223 +                               reg = <0xef600300 0x00000008>;
 224 +                               virtual-reg = <0xef600300>;
 225 +                               clock-frequency = <0>; /* Filled in by zImage */
 226 +                               current-speed = <115200>;
 227 +                               interrupt-parent = <&UIC0>;
 228 +                               interrupts = <0x0 0x4>;
 229 +                       };
 230 +
 231 +                       UART1: serial@ef600400 {
 232 +                               device_type = "serial";
 233 +                               compatible = "ns16550";
 234 +                               reg = <0xef600400 0x00000008>;
 235 +                               virtual-reg = <0xef600400>;
 236 +                               clock-frequency = <0>; /* Filled in by zImage */
 237 +                               current-speed = <115200>;
 238 +                               interrupt-parent = <&UIC0>;
 239 +                               interrupts = <0x1 0x4>;
 240 +                       };
 241 +
 242 +                       IIC: i2c@ef600500 {
 243 +                               #address-cells = <1>;
 244 +                               #size-cells = <0>;
 245 +                               compatible = "ibm,iic-405ep", "ibm,iic";
 246 +                               reg = <0xef600500 0x00000011>;
 247 +                               interrupt-parent = <&UIC0>;
 248 +                               interrupts = <0x2 0x4>;
 249 +
 250 +                               eeprom@50 {
 251 +                                       compatible = "at24,24c16";
 252 +                                       reg = <0x50>;
 253 +                               };
 254 +                       };
 255 +
 256 +                       GPIO0: gpio-controller@ef600700 {
 257 +                               compatible = "ibm,ppc4xx-gpio";
 258 +                               reg = <0xef600700 0x00000020>;
 259 +                               #gpio-cells = <2>;
 260 +                               gpio-controller;
 261 +                       };
 262 +
 263 +                       EMAC0: ethernet@ef600800 {
 264 +                               linux,network-index = <0x0>;
 265 +                               device_type = "network";
 266 +                               compatible = "ibm,emac-405ep", "ibm,emac";
 267 +                               interrupt-parent = <&UIC0>;
 268 +                               interrupts = <
 269 +                                       0xf 0x4 /* Ethernet */
 270 +                                       0x9 0x4 /* Ethernet Wake Up */>;
 271 +                               local-mac-address = [000000000000]; /* Filled in by zImage */
 272 +                               reg = <0xef600800 0x00000070>;
 273 +                               mal-device = <&MAL>;
 274 +                               mal-tx-channel = <0>;
 275 +                               mal-rx-channel = <0>;
 276 +                               cell-index = <0>;
 277 +                               max-frame-size = <0x5dc>;
 278 +                               rx-fifo-size = <0x1000>;
 279 +                               tx-fifo-size = <0x800>;
 280 +                               phy-mode = "mii";
 281 +                               phy-map = <0x00000000>;
 282 +                       };
 283 +
 284 +                       leds {
 285 +                               compatible = "gpio-leds";
 286 +                               user {
 287 +                                       label = "openrb:green:user";
 288 +                                       gpios = <&GPIO0 2 1>;
 289 +                               };
 290 +                       };
 291 +               };
 292 +
 293 +               EBC0: ebc {
 294 +                       compatible = "ibm,ebc-405ep", "ibm,ebc";
 295 +                       dcr-reg = <0x012 0x002>;
 296 +                       #address-cells = <2>;
 297 +                       #size-cells = <1>;
 298 +                       /* The ranges property is supplied by the bootwrapper
 299 +                        * and is based on the firmware's configuration of the
 300 +                        * EBC bridge
 301 +                        */
 302 +                       clock-frequency = <0>; /* Filled in by zImage */
 303 +
 304 +                       cf_card@ff100000 {
 305 +                               compatible = "magicbox-cf", "pata-magicbox-cf";
 306 +                               reg = <0x00000000 0xff100000 0x00001000
 307 +                                      0x00000000 0xff200000 0x00001000>;
 308 +                               interrupt-parent = <&UIC0>;
 309 +                               interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
 310 +                       };
 311 +
 312 +                       nor_flash@ff800000 {
 313 +                               compatible = "cfi-flash";
 314 +                               bank-width = <2>;
 315 +                               reg = <0x00000000 0xff800000 0x00800000>;
 316 +                               #address-cells = <1>;
 317 +                               #size-cells = <1>;
 318 +                               partition@0 {
 319 +                                       label = "linux";
 320 +                                       reg = <0x0 0x120000>;
 321 +                               };
 322 +                               partition@120000 {
 323 +                                       label = "rootfs";
 324 +                                       reg = <0x120000 0x6a0000>;
 325 +                               };
 326 +                               partition@7c0000 {
 327 +                                       label = "u-boot";
 328 +                                       reg = <0x7c0000 0x30000>;
 329 +                                       read-only;
 330 +                               };
 331 +                       };
 332 +               };
 333 +
 334 +               PCI0: pci@ec000000 {
 335 +                       device_type = "pci";
 336 +                       #interrupt-cells = <1>;
 337 +                       #size-cells = <2>;
 338 +                       #address-cells = <3>;
 339 +                       compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
 340 +                       primary;
 341 +                       reg = <0xeec00000 0x00000008    /* Config space access */
 342 +                              0xeed80000 0x00000004    /* IACK */
 343 +                              0xeed80000 0x00000004    /* Special cycle */
 344 +                              0xef480000 0x00000040>;  /* Internal registers */
 345 +
 346 +                       /* Outbound ranges, one memory and one IO,
 347 +                        * later cannot be changed. Chip supports a second
 348 +                        * IO range but we don't use it for now
 349 +                        */
 350 +                       ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
 351 +                                 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
 352 +
 353 +                       /* Inbound 2GB range starting at 0 */
 354 +                       dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
 355 +
 356 +                       interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
 357 +                       interrupt-map = <
 358 +                               /* IDSEL 1 */
 359 +                               0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
 360 +
 361 +                               /* IDSEL 2 */
 362 +                               0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8
 363 +
 364 +                               /* IDSEL 3 */
 365 +                               0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8
 366 +
 367 +                               /* IDSEL 4 */
 368 +                               0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8
 369 +                       >;
 370 +               };
 371 +       };
 372 +
 373 +       chosen {
 374 +               linux,stdout-path = "/plb/opb/serial@ef600300";
 375 +       };
 376 +};