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[ifxmips-dsl-api] fix firmware handling
[openwrt.git] / target / linux / brcm-2.4 / files / arch / mips / bcm947xx / include / sbchipc.h
1 /*
2 * SiliconBackplane Chipcommon core hardware definitions.
3 *
4 * The chipcommon core provides chip identification, SB control,
5 * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6 * gpio interface, extbus, and support for serial and parallel flashes.
7 *
8 * Copyright 2007, Broadcom Corporation
9 * All Rights Reserved.
10 *
11 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 *
16 */
17
18 #ifndef _SBCHIPC_H
19 #define _SBCHIPC_H
20
21 #ifndef _LANGUAGE_ASSEMBLY
22
23 /* cpp contortions to concatenate w/arg prescan */
24 #ifndef PAD
25 #define _PADLINE(line) pad ## line
26 #define _XSTR(line) _PADLINE(line)
27 #define PAD _XSTR(__LINE__)
28 #endif /* PAD */
29
30
31 typedef volatile struct {
32 uint32 chipid; /* 0x0 */
33 uint32 capabilities;
34 uint32 corecontrol; /* corerev >= 1 */
35 uint32 bist;
36
37 /* OTP */
38 uint32 otpstatus; /* 0x10, corerev >= 10 */
39 uint32 otpcontrol;
40 uint32 otpprog;
41 uint32 PAD;
42
43 /* Interrupt control */
44 uint32 intstatus; /* 0x20 */
45 uint32 intmask;
46 uint32 chipcontrol; /* 0x28, rev >= 11 */
47 uint32 chipstatus; /* 0x2c, rev >= 11 */
48
49 /* Jtag Master */
50 uint32 jtagcmd; /* 0x30, rev >= 10 */
51 uint32 jtagir;
52 uint32 jtagdr;
53 uint32 jtagctrl;
54
55 /* serial flash interface registers */
56 uint32 flashcontrol; /* 0x40 */
57 uint32 flashaddress;
58 uint32 flashdata;
59 uint32 PAD[1];
60
61 /* Silicon backplane configuration broadcast control */
62 uint32 broadcastaddress; /* 0x50 */
63 uint32 broadcastdata;
64
65 /* gpio - cleared only by power-on-reset */
66 uint32 gpiopullup; /* 0x58, corerev >= 20 */
67 uint32 gpiopulldown; /* 0x5c, corerev >= 20 */
68 uint32 gpioin; /* 0x60 */
69 uint32 gpioout;
70 uint32 gpioouten;
71 uint32 gpiocontrol;
72 uint32 gpiointpolarity;
73 uint32 gpiointmask;
74
75 /* GPIO events corerev >= 11 */
76 uint32 gpioevent;
77 uint32 gpioeventintmask;
78
79 /* Watchdog timer */
80 uint32 watchdog; /* 0x80 */
81
82 /* GPIO events corerev >= 11 */
83 uint32 gpioeventintpolarity;
84
85 /* GPIO based LED powersave registers corerev >= 16 */
86 uint32 gpiotimerval; /* 0x88 */
87 uint32 gpiotimeroutmask;
88
89 /* clock control */
90 uint32 clockcontrol_n; /* 0x90 */
91 uint32 clockcontrol_sb; /* aka m0 */
92 uint32 clockcontrol_pci; /* aka m1 */
93 uint32 clockcontrol_m2; /* mii/uart/mipsref */
94 uint32 clockcontrol_m3; /* cpu */
95 uint32 clkdiv; /* corerev >= 3 */
96 uint32 PAD[2];
97
98 /* pll delay registers (corerev >= 4) */
99 uint32 pll_on_delay; /* 0xb0 */
100 uint32 fref_sel_delay;
101 uint32 slow_clk_ctl; /* 5 < corerev < 10 */
102 uint32 PAD[1];
103
104 /* Instaclock registers (corerev >= 10) */
105 uint32 system_clk_ctl; /* 0xc0 */
106 uint32 clkstatestretch;
107 uint32 PAD[14];
108
109 /* ExtBus control registers (corerev >= 3) */
110 uint32 pcmcia_config; /* 0x100 */
111 uint32 pcmcia_memwait;
112 uint32 pcmcia_attrwait;
113 uint32 pcmcia_iowait;
114 uint32 ide_config;
115 uint32 ide_memwait;
116 uint32 ide_attrwait;
117 uint32 ide_iowait;
118 uint32 prog_config;
119 uint32 prog_waitcount;
120 uint32 flash_config;
121 uint32 flash_waitcount;
122 uint32 PAD[4];
123
124 /* Enhanced Coexistance Interface (ECI) registers (corerev >= 21) */
125 uint32 eci_output; /* 0x140 */
126 uint32 eci_control;
127 uint32 eci_inputlo;
128 uint32 eci_inputmi;
129 uint32 eci_inputhi;
130 uint32 eci_inputintpolaritylo;
131 uint32 eci_inputintpolaritymi;
132 uint32 eci_inputintpolarityhi;
133 uint32 eci_intmasklo;
134 uint32 eci_intmaskmi;
135 uint32 eci_intmaskhi;
136 uint32 eci_eventlo;
137 uint32 eci_eventmi;
138 uint32 eci_eventhi;
139 uint32 eci_eventmasklo;
140 uint32 eci_eventmaskmi;
141 uint32 eci_eventmaskhi;
142 uint32 PAD[23];
143
144
145 /* Clock control and hardware workarounds (corerev >= 20) */
146 uint32 clk_ctl_st; /* 0x1e0 */
147 uint32 hw_war;
148 uint32 PAD[70];
149
150 /* uarts */
151 uint8 uart0data; /* 0x300 */
152 uint8 uart0imr;
153 uint8 uart0fcr;
154 uint8 uart0lcr;
155 uint8 uart0mcr;
156 uint8 uart0lsr;
157 uint8 uart0msr;
158 uint8 uart0scratch;
159 uint8 PAD[248]; /* corerev >= 1 */
160
161 uint8 uart1data; /* 0x400 */
162 uint8 uart1imr;
163 uint8 uart1fcr;
164 uint8 uart1lcr;
165 uint8 uart1mcr;
166 uint8 uart1lsr;
167 uint8 uart1msr;
168 uint8 uart1scratch;
169 uint32 PAD[126];
170
171 /* PMU registers (corerev >= 20) */
172 uint32 pmucontrol; /* 0x600 */
173 uint32 pmucapabilities;
174 uint32 pmustatus;
175 uint32 res_state;
176 uint32 res_pending;
177 uint32 pmutimer;
178 uint32 min_res_mask;
179 uint32 max_res_mask;
180 uint32 res_table_sel;
181 uint32 res_dep_mask;
182 uint32 res_updn_timer;
183 uint32 res_timer;
184 uint32 clkstretch;
185 uint32 pmuwatchdog;
186 uint32 PAD[2];
187 uint32 res_req_timer_sel;
188 uint32 res_req_timer;
189 uint32 res_req_mask;
190 uint32 PAD;
191 uint32 chipcontrol_addr;
192 uint32 chipcontrol_data;
193 uint32 regcontrol_addr;
194 uint32 regcontrol_data;
195 uint32 pllcontrol_addr;
196 uint32 pllcontrol_data;
197 uint32 PAD[102];
198 uint16 otp[512];
199 } chipcregs_t;
200
201 #endif /* _LANGUAGE_ASSEMBLY */
202
203 /* corecontrol */
204 #define CC_UE (1 << 0) /* uart enable */
205
206 #define CC_CHIPID 0
207 #define CC_CAPABILITIES 4
208 #define CC_OTPST 0x10
209 #define CC_CHIPST 0x2c
210 #define CC_JTAGCMD 0x30
211 #define CC_JTAGIR 0x34
212 #define CC_JTAGDR 0x38
213 #define CC_JTAGCTRL 0x3c
214 #define CC_WATCHDOG 0x80
215 #define CC_CLKC_N 0x90
216 #define CC_CLKC_M0 0x94
217 #define CC_CLKC_M1 0x98
218 #define CC_CLKC_M2 0x9c
219 #define CC_CLKC_M3 0xa0
220 #define CC_CLKDIV 0xa4
221 #define CC_SYS_CLK_CTL 0xc0
222 #define CC_CLK_CTL_ST SB_CLK_CTL_ST
223 #define PMU_CTL 0x600
224 #define PMU_CAP 0x604
225 #define PMU_ST 0x608
226 #define PMU_TIMER 0x614
227 #define PMU_MIN_RES_MASK 0x618
228 #define PMU_MAX_RES_MASK 0x61c
229 #define PMU_REG_CONTROL_ADDR 0x658
230 #define PMU_REG_CONTROL_DATA 0x65C
231 #define PMU_PLL_CONTROL_ADDR 0x660
232 #define PMU_PLL_CONTROL_DATA 0x664
233 #define CC_OTP 0x800 /* OTP address space */
234
235 /* chipid */
236 #define CID_ID_MASK 0x0000ffff /* Chip Id mask */
237 #define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
238 #define CID_REV_SHIFT 16 /* Chip Revision shift */
239 #define CID_PKG_MASK 0x00f00000 /* Package Option mask */
240 #define CID_PKG_SHIFT 20 /* Package Option shift */
241 #define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
242 #define CID_CC_SHIFT 24
243
244 /* capabilities */
245 #define CC_CAP_UARTS_MASK 0x00000003 /* Number of uarts */
246 #define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
247 #define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
248 #define CC_CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
249 #define CC_CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
250 #define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
251 #define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
252 #define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
253 #define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
254 #define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */
255 #define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */
256 #define CC_CAP_PWR_CTL 0x00040000 /* Power control */
257 #define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
258 #define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
259 #define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */
260 #define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */
261 #define CC_CAP_ROM 0x00800000 /* Internal boot rom active */
262 #define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
263 #define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
264 #define CC_CAP_ECI 0x20000000 /* ECI Present, rev >= 21 */
265
266 /* PLL type */
267 #define PLL_NONE 0x00000000
268 #define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
269 #define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
270 #define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
271 #define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
272 #define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
273 #define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
274 #define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
275
276 /* ALP clock on pre-PMU chips */
277 #define ALP_CLOCK 20000000
278
279 /* HT clock */
280 #define HT_CLOCK 80000000
281
282 /* watchdog clock */
283 #define WATCHDOG_CLOCK_5354 32000 /* Hz */
284
285 /* corecontrol */
286 #define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
287 #define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
288 #define CC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */
289
290 /* chipcontrol */
291 #define CHIPCTRL_4321A0_DEFAULT 0x3a4
292 #define CHIPCTRL_4321A1_DEFAULT 0x0a4
293
294 /* Fields in the otpstatus register in rev >= 21 */
295 #define OTPS_OL_MASK 0x000000ff
296 #define OTPS_OL_MFG 0x00000001 /* manuf row is locked */
297 #define OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */
298 #define OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */
299 #define OTPS_OL_GU 0x00000008 /* general use region is locked */
300 #define OTPS_GUP_MASK 0x00000f00
301 #define OTPS_GUP_SHIFT 8
302 #define OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */
303 #define OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */
304 #define OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */
305 #define OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */
306 #define OTPS_READY 0x00001000
307 #define OTPS_RV(x) (1 << (16 + (x)))
308
309 /* Fields in the otpcontrol register in rev >= 21 */
310 #define OTPC_PROGSEL 0x00000001
311 #define OTPC_PCOUNT_MASK 0x0000000e
312 #define OTPC_PCOUNT_SHIFT 1
313 #define OTPC_VSEL_MASK 0x000000f0
314 #define OTPC_VSEL_SHIFT 4
315 #define OTPC_TMM_MASK 0x00000700
316 #define OTPC_TMM_SHIFT 8
317 #define OTPC_ODM 0x00000800
318 #define OTPC_PROGEN 0x80000000
319
320 /* Fields in otpprog in rev >= 21 */
321 #define OTPP_COL_MASK 0x000000ff
322 #define OTPP_COL_SHIFT 0
323 #define OTPP_ROW_MASK 0x0000ff00
324 #define OTPP_ROW_SHIFT 8
325 #define OTPP_OC_MASK 0x0f000000
326 #define OTPP_OC_SHIFT 24
327 #define OTPP_READERR 0x10000000
328 #define OTPP_VALUE_MASK 0x20000000
329 #define OTPP_VALUE_SHIFT 29
330 #define OTPP_START_BUSY 0x80000000
331
332 /* Opcodes for OTPP_OC field */
333 #define OTPPOC_READ 0
334 #define OTPPOC_BIT_PROG 1
335 #define OTPPOC_VERIFY 3
336 #define OTPPOC_INIT 4
337 #define OTPPOC_SET 5
338 #define OTPPOC_RESET 6
339 #define OTPPOC_OCST 7
340 #define OTPPOC_ROW_LOCK 8
341 #define OTPPOC_PRESCN_TEST 9
342
343 /* jtagcmd */
344 #define JCMD_START 0x80000000
345 #define JCMD_BUSY 0x80000000
346 #define JCMD_PAUSE 0x40000000
347 #define JCMD0_ACC_MASK 0x0000f000
348 #define JCMD0_ACC_IRDR 0x00000000
349 #define JCMD0_ACC_DR 0x00001000
350 #define JCMD0_ACC_IR 0x00002000
351 #define JCMD0_ACC_RESET 0x00003000
352 #define JCMD0_ACC_IRPDR 0x00004000
353 #define JCMD0_ACC_PDR 0x00005000
354 #define JCMD0_IRW_MASK 0x00000f00
355 #define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
356 #define JCMD_ACC_IRDR 0x00000000
357 #define JCMD_ACC_DR 0x00010000
358 #define JCMD_ACC_IR 0x00020000
359 #define JCMD_ACC_RESET 0x00030000
360 #define JCMD_ACC_IRPDR 0x00040000
361 #define JCMD_ACC_PDR 0x00050000
362 #define JCMD_IRW_MASK 0x00001f00
363 #define JCMD_IRW_SHIFT 8
364 #define JCMD_DRW_MASK 0x0000003f
365
366 /* jtagctrl */
367 #define JCTRL_FORCE_CLK 4 /* Force clock */
368 #define JCTRL_EXT_EN 2 /* Enable external targets */
369 #define JCTRL_EN 1 /* Enable Jtag master */
370
371 /* Fields in clkdiv */
372 #define CLKD_SFLASH 0x0f000000
373 #define CLKD_SFLASH_SHIFT 24
374 #define CLKD_OTP 0x000f0000
375 #define CLKD_OTP_SHIFT 16
376 #define CLKD_JTAG 0x00000f00
377 #define CLKD_JTAG_SHIFT 8
378 #define CLKD_UART 0x000000ff
379
380 /* intstatus/intmask */
381 #define CI_GPIO 0x00000001 /* gpio intr */
382 #define CI_EI 0x00000002 /* extif intr (corerev >= 3) */
383 #define CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */
384 #define CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */
385 #define CI_ECI 0x00000010 /* eci intr (corerev >= 21) */
386 #define CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */
387 #define CI_UART 0x00000040 /* uart intr (corerev >= 21) */
388 #define CI_WDRESET 0x80000000 /* watchdog reset occurred */
389
390 /* slow_clk_ctl */
391 #define SCC_SS_MASK 0x00000007 /* slow clock source mask */
392 #define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
393 #define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
394 #define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
395 #define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
396 #define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
397 * 0: LPO is enabled
398 */
399 #define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
400 * 0: power logic control
401 */
402 #define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
403 * PLL clock disable requests from core
404 */
405 #define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
406 * disable crystal when appropriate
407 */
408 #define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
409 #define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
410 #define SCC_CD_SHIFT 16
411
412 /* system_clk_ctl */
413 #define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
414 #define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
415 #define SYCC_FP 0x00000004 /* ForcePLLOn */
416 #define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
417 #define SYCC_HR 0x00000010 /* Force HT */
418 #define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
419 #define SYCC_CD_SHIFT 16
420
421 /* pcmcia_iowait */
422 #define PI_W0_MASK 0x0000003f /* waitcount0 */
423 #define PI_W1_MASK 0x00001f00 /* waitcount1 */
424 #define PI_W1_SHIFT 8
425 #define PI_W2_MASK 0x001f0000 /* waitcount2 */
426 #define PI_W2_SHIFT 16
427 #define PI_W3_MASK 0x1f000000 /* waitcount3 */
428 #define PI_W3_SHIFT 24
429
430 /* prog_waitcount */
431 #define PW_W0_MASK 0x0000001f /* waitcount0 */
432 #define PW_W1_MASK 0x00001f00 /* waitcount1 */
433 #define PW_W1_SHIFT 8
434 #define PW_W2_MASK 0x001f0000 /* waitcount2 */
435 #define PW_W2_SHIFT 16
436 #define PW_W3_MASK 0x1f000000 /* waitcount3 */
437 #define PW_W3_SHIFT 24
438
439 #define PW_W0 0x0000000c
440 #define PW_W1 0x00000a00
441 #define PW_W2 0x00020000
442 #define PW_W3 0x01000000
443
444 /* watchdog */
445 #define WATCHDOG_CLOCK 48000000 /* Hz */
446
447 /* Fields in pmucontrol */
448 #define PCTL_ILP_DIV_MASK 0xffff0000
449 #define PCTL_ILP_DIV_SHIFT 16
450 #define PCTL_NOILP_ON_WAIT 0x00000200
451 #define PCTL_HT_REQ_EN 0x00000100
452 #define PCTL_ALP_REQ_EN 0x00000080
453 #define PCTL_XTALFREQ_MASK 0x0000007c
454 #define PCTL_XTALFREQ_SHIFT 2
455 #define PCTL_ILP_DIV_EN 0x00000002
456 #define PCTL_LPO_SEL 0x00000001
457
458 /* gpiotimerval */
459 #define GPIO_ONTIME_SHIFT 16
460
461 /* clockcontrol_n */
462 #define CN_N1_MASK 0x3f /* n1 control */
463 #define CN_N2_MASK 0x3f00 /* n2 control */
464 #define CN_N2_SHIFT 8
465 #define CN_PLLC_MASK 0xf0000 /* pll control */
466 #define CN_PLLC_SHIFT 16
467
468 /* clockcontrol_sb/pci/uart */
469 #define CC_M1_MASK 0x3f /* m1 control */
470 #define CC_M2_MASK 0x3f00 /* m2 control */
471 #define CC_M2_SHIFT 8
472 #define CC_M3_MASK 0x3f0000 /* m3 control */
473 #define CC_M3_SHIFT 16
474 #define CC_MC_MASK 0x1f000000 /* mux control */
475 #define CC_MC_SHIFT 24
476
477 /* N3M Clock control magic field values */
478 #define CC_F6_2 0x02 /* A factor of 2 in */
479 #define CC_F6_3 0x03 /* 6-bit fields like */
480 #define CC_F6_4 0x05 /* N1, M1 or M3 */
481 #define CC_F6_5 0x09
482 #define CC_F6_6 0x11
483 #define CC_F6_7 0x21
484
485 #define CC_F5_BIAS 5 /* 5-bit fields get this added */
486
487 #define CC_MC_BYPASS 0x08
488 #define CC_MC_M1 0x04
489 #define CC_MC_M1M2 0x02
490 #define CC_MC_M1M2M3 0x01
491 #define CC_MC_M1M3 0x11
492
493 /* Type 2 Clock control magic field values */
494 #define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
495 #define CC_T2M2_BIAS 3 /* m2 bias */
496
497 #define CC_T2MC_M1BYP 1
498 #define CC_T2MC_M2BYP 2
499 #define CC_T2MC_M3BYP 4
500
501 /* Type 6 Clock control magic field values */
502 #define CC_T6_MMASK 1 /* bits of interest in m */
503 #define CC_T6_M0 120000000 /* sb clock for m = 0 */
504 #define CC_T6_M1 100000000 /* sb clock for m = 1 */
505 #define SB2MIPS_T6(sb) (2 * (sb))
506
507 /* Common clock base */
508 #define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
509 #define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
510
511 /* Clock control values for 200Mhz in 5350 */
512 #define CLKC_5350_N 0x0311
513 #define CLKC_5350_M 0x04020009
514
515 /* Flash types in the chipcommon capabilities register */
516 #define FLASH_NONE 0x000 /* No flash */
517 #define SFLASH_ST 0x100 /* ST serial flash */
518 #define SFLASH_AT 0x200 /* Atmel serial flash */
519 #define PFLASH 0x700 /* Parallel flash */
520
521 /* Bits in the ExtBus config registers */
522 #define CC_CFG_EN 0x0001 /* Enable */
523 #define CC_CFG_EM_MASK 0x000e /* Extif Mode */
524 #define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */
525 #define CC_CFG_EM_SYNC 0x0002 /* Synchronous */
526 #define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
527 #define CC_CFG_EM_IDE 0x0006 /* IDE */
528 #define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
529 #define CC_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */
530 #define CC_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */
531 #define CC_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */
532 #define CC_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */
533
534 /* ExtBus address space */
535 #define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
536 #define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */
537 #define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */
538 #define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */
539 #define CC_EB_IDE 0x1a800000 /* IDE memory base */
540 #define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */
541 #define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */
542 #define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */
543 #define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */
544
545
546 /* Start/busy bit in flashcontrol */
547 #define SFLASH_OPCODE 0x000000ff
548 #define SFLASH_ACTION 0x00000700
549 #define SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
550 #define SFLASH_START 0x80000000
551 #define SFLASH_BUSY SFLASH_START
552
553 /* flashcontrol action codes */
554 #define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */
555 #define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */
556 #define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 address bytes */
557 #define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addres & 1 data bytes */
558 #define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addres & 4 data bytes */
559 #define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addres, 4 don't care & 4 data bytes */
560 #define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addres, 1 don't care & 4 data bytes */
561
562 /* flashcontrol action+opcodes for ST flashes */
563 #define SFLASH_ST_WREN 0x0006 /* Write Enable */
564 #define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
565 #define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
566 #define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
567 #define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
568 #define SFLASH_ST_PP 0x0302 /* Page Program */
569 #define SFLASH_ST_SE 0x02d8 /* Sector Erase */
570 #define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
571 #define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
572 #define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
573 #define SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */
574
575 /* Status register bits for ST flashes */
576 #define SFLASH_ST_WIP 0x01 /* Write In Progress */
577 #define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
578 #define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
579 #define SFLASH_ST_BP_SHIFT 2
580 #define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
581
582 /* flashcontrol action+opcodes for Atmel flashes */
583 #define SFLASH_AT_READ 0x07e8
584 #define SFLASH_AT_PAGE_READ 0x07d2
585 #define SFLASH_AT_BUF1_READ
586 #define SFLASH_AT_BUF2_READ
587 #define SFLASH_AT_STATUS 0x01d7
588 #define SFLASH_AT_BUF1_WRITE 0x0384
589 #define SFLASH_AT_BUF2_WRITE 0x0387
590 #define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
591 #define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
592 #define SFLASH_AT_BUF1_PROGRAM 0x0288
593 #define SFLASH_AT_BUF2_PROGRAM 0x0289
594 #define SFLASH_AT_PAGE_ERASE 0x0281
595 #define SFLASH_AT_BLOCK_ERASE 0x0250
596 #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
597 #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
598 #define SFLASH_AT_BUF1_LOAD 0x0253
599 #define SFLASH_AT_BUF2_LOAD 0x0255
600 #define SFLASH_AT_BUF1_COMPARE 0x0260
601 #define SFLASH_AT_BUF2_COMPARE 0x0261
602 #define SFLASH_AT_BUF1_REPROGRAM 0x0258
603 #define SFLASH_AT_BUF2_REPROGRAM 0x0259
604
605 /* Status register bits for Atmel flashes */
606 #define SFLASH_AT_READY 0x80
607 #define SFLASH_AT_MISMATCH 0x40
608 #define SFLASH_AT_ID_MASK 0x38
609 #define SFLASH_AT_ID_SHIFT 3
610
611 /*
612 * These are the UART port assignments, expressed as offsets from the base
613 * register. These assignments should hold for any serial port based on
614 * a 8250, 16450, or 16550(A).
615 */
616
617 #define UART_RX 0 /* In: Receive buffer (DLAB=0) */
618 #define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
619 #define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
620 #define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */
621 #define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
622 #define UART_IIR 2 /* In: Interrupt Identity Register */
623 #define UART_FCR 2 /* Out: FIFO Control Register */
624 #define UART_LCR 3 /* Out: Line Control Register */
625 #define UART_MCR 4 /* Out: Modem Control Register */
626 #define UART_LSR 5 /* In: Line Status Register */
627 #define UART_MSR 6 /* In: Modem Status Register */
628 #define UART_SCR 7 /* I/O: Scratch Register */
629 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
630 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
631 #define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */
632 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
633 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
634 #define UART_LSR_RXRDY 0x01 /* Receiver ready */
635 #define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
636
637 /* Interrupt Identity Register (IIR) bits */
638 #define UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */
639 #define UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */
640 #define UART_IIR_MDM_CHG 0x0 /* Modem status changed */
641 #define UART_IIR_NOINT 0x1 /* No interrupt pending */
642 #define UART_IIR_THRE 0x2 /* THR empty */
643 #define UART_IIR_RCVD_DATA 0x4 /* Received data available */
644 #define UART_IIR_RCVR_STATUS 0x6 /* Receiver status */
645 #define UART_IIR_CHAR_TIME 0xc /* Character time */
646
647 /* Interrupt Enable Register (IER) bits */
648 #define UART_IER_EDSSI 8 /* enable modem status interrupt */
649 #define UART_IER_ELSI 4 /* enable receiver line status interrupt */
650 #define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
651 #define UART_IER_ERBFI 1 /* enable data available interrupt */
652
653 /* pmustatus */
654 #define PST_INTPEND 0x0040
655 #define PST_SBCLKST 0x0030
656 #define PST_ALPAVAIL 0x0008
657 #define PST_HTAVAIL 0x0004
658 #define PST_RESINIT 0x0003
659
660 /* pmucapabilities */
661 #define PCAP_REV_MASK 0x000000ff
662
663 /* PMU Resource Request Timer registers */
664 /* This is based on PmuRev0 */
665 #define PRRT_TIME_MASK 0x03ff
666 #define PRRT_INTEN 0x0400
667 #define PRRT_REQ_ACTIVE 0x0800
668 #define PRRT_ALP_REQ 0x1000
669 #define PRRT_HT_REQ 0x2000
670
671 /* PMU resource bit position */
672 #define PMURES_BIT(bit) (1 << (bit))
673
674 /* PMU corerev and chip specific PLL controls.
675 * PMU<rev>_PLL<num>_XXXX where <rev> is PMU corerev and <num> is an arbitary number
676 * to differentiate different PLLs controlled by the same PMU rev.
677 */
678 /* pllcontrol registers */
679 /* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */
680 #define PMU0_PLL0_PLLCTL0 0
681 #define PMU0_PLL0_PC0_PDIV_MASK 1
682 #define PMU0_PLL0_PC0_PDIV_FREQ 25000
683 #define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038
684 #define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3
685 #define PMU0_PLL0_PC0_DIV_ARM_BASE 8
686
687 /* PC0_DIV_ARM for PLLOUT_ARM */
688 #define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0
689 #define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1
690 #define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2
691 #define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */
692 #define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4
693 #define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5
694 #define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6
695 #define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7
696
697 /* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */
698 #define PMU0_PLL0_PLLCTL1 1
699 #define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000
700 #define PMU0_PLL0_PC1_WILD_INT_SHIFT 28
701 #define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00
702 #define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8
703 #define PMU0_PLL0_PC1_STOP_MOD 0x00000040
704
705 /* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */
706 #define PMU0_PLL0_PLLCTL2 2
707 #define PMU0_PLL0_PC2_WILD_INT_MASK 0xf
708 #define PMU0_PLL0_PC2_WILD_INT_SHIFT 4
709
710 /* Chip specific PMU resources. */
711 #define RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */
712 #define RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */
713 #define RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */
714 #define RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
715 #define RES4328_ILP_REQUEST 4 /* 0x00010 */
716 #define RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */
717 #define RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */
718 #define RES4328_ROM_SWITCH 7 /* 0x00080 */
719 #define RES4328_PA_REF_LDO 8 /* 0x00100 */
720 #define RES4328_RADIO_LDO 9 /* 0x00200 */
721 #define RES4328_AFE_LDO 10 /* 0x00400 */
722 #define RES4328_PLL_LDO 11 /* 0x00800 */
723 #define RES4328_BG_FILTBYP 12 /* 0x01000 */
724 #define RES4328_TX_FILTBYP 13 /* 0x02000 */
725 #define RES4328_RX_FILTBYP 14 /* 0x04000 */
726 #define RES4328_XTAL_PU 15 /* 0x08000 */
727 #define RES4328_XTAL_EN 16 /* 0x10000 */
728 #define RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */
729 #define RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */
730 #define RES4328_BB_PLL_PU 19 /* 0x80000 */
731
732 #define RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */
733 #define RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */
734 #define RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */
735 #define RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
736 #define RES5354_ILP_REQUEST 4 /* 0x00010 */
737 #define RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */
738 #define RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */
739 #define RES5354_ROM_SWITCH 7 /* 0x00080 */
740 #define RES5354_PA_REF_LDO 8 /* 0x00100 */
741 #define RES5354_RADIO_LDO 9 /* 0x00200 */
742 #define RES5354_AFE_LDO 10 /* 0x00400 */
743 #define RES5354_PLL_LDO 11 /* 0x00800 */
744 #define RES5354_BG_FILTBYP 12 /* 0x01000 */
745 #define RES5354_TX_FILTBYP 13 /* 0x02000 */
746 #define RES5354_RX_FILTBYP 14 /* 0x04000 */
747 #define RES5354_XTAL_PU 15 /* 0x08000 */
748 #define RES5354_XTAL_EN 16 /* 0x10000 */
749 #define RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */
750 #define RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */
751 #define RES5354_BB_PLL_PU 19 /* 0x80000 */
752
753 /* pllcontrol registers */
754 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypsss_sdmod */
755 #define PMU1_PLL0_PLLCTL0 0
756 #define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
757 #define PMU1_PLL0_PC0_P1DIV_SHIFT 20
758 #define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000
759 #define PMU1_PLL0_PC0_P2DIV_SHIFT 24
760
761 /* m<x>div */
762 #define PMU1_PLL0_PLLCTL1 1
763 #define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff
764 #define PMU1_PLL0_PC1_M1DIV_SHIFT 0
765 #define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00
766 #define PMU1_PLL0_PC1_M2DIV_SHIFT 8
767 #define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000
768 #define PMU1_PLL0_PC1_M3DIV_SHIFT 16
769 #define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000
770 #define PMU1_PLL0_PC1_M4DIV_SHIFT 24
771
772 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
773 #define PMU1_PLL0_PLLCTL2 2
774 #define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff
775 #define PMU1_PLL0_PC2_M5DIV_SHIFT 0
776 #define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00
777 #define PMU1_PLL0_PC2_M6DIV_SHIFT 8
778 #define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000
779 #define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17
780 #define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
781 #define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
782
783 /* ndiv_frac */
784 #define PMU1_PLL0_PLLCTL3 3
785 #define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff
786 #define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0
787
788 /* pll_ctrl */
789 #define PMU1_PLL0_PLLCTL4 4
790
791 /* pll_ctrl, vco_rng, clkdrive_ch<x> */
792 #define PMU1_PLL0_PLLCTL5 5
793 #define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
794 #define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8
795
796 #define RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */
797 #define RES4325_CBUCK_BURST 1 /* 0x00000002 */
798 #define RES4325_CBUCK_PWM 2 /* 0x00000004 */
799 #define RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */
800 #define RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */
801 #define RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */
802 #define RES4325_ILP_REQUEST 6 /* 0x00000040 */
803 #define RES4325_ABUCK_BURST 7 /* 0x00000080 */
804 #define RES4325_ABUCK_PWM 8 /* 0x00000100 */
805 #define RES4325_LNLDO1_PU 9 /* 0x00000200 */
806 #define RES4325_LNLDO2_PU 10 /* 0x00000400 */
807 #define RES4325_LNLDO3_PU 11 /* 0x00000800 */
808 #define RES4325_LNLDO4_PU 12 /* 0x00001000 */
809 #define RES4325_XTAL_PU 13 /* 0x00002000 */
810 #define RES4325_ALP_AVAIL 14 /* 0x00004000 */
811 #define RES4325_RX_PWRSW_PU 15 /* 0x00008000 */
812 #define RES4325_TX_PWRSW_PU 16 /* 0x00010000 */
813 #define RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */
814 #define RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */
815 #define RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */
816 #define RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */
817 #define RES4325_HT_AVAIL 21 /* 0x00200000 */
818
819 /* Chip specific ChipStatus register bits */
820 #define CST4325_SPROM_OTP_SEL_MASK 0x00000003
821 #define CST4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
822 #define CST4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
823 #define CST4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
824 #define CST4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
825 #define CST4325_SDIO_USB_MODE_MASK 0x00000004
826 #define CST4325_SDIO_USB_MODE_SHIFT 2
827 #define CST4325_RCAL_VALID_MASK 0x00000008
828 #define CST4325_RCAL_VALID_SHIFT 3
829 #define CST4325_RCAL_VALUE_MASK 0x000001f0
830 #define CST4325_RCAL_VALUE_SHIFT 4
831 #define CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */
832 #define CST4325_PMUTOP_2B_SHIFT 9
833
834 #define RES4312_SWITCHER_BURST 0 /* 0x00000001 */
835 #define RES4312_SWITCHER_PWM 1 /* 0x00000002 */
836 #define RES4312_PA_REF_LDO 2 /* 0x00000004 */
837 #define RES4312_CORE_LDO_BURST 3 /* 0x00000008 */
838 #define RES4312_CORE_LDO_PWM 4 /* 0x00000010 */
839 #define RES4312_RADIO_LDO 5 /* 0x00000020 */
840 #define RES4312_ILP_REQUEST 6 /* 0x00000040 */
841 #define RES4312_BG_FILTBYP 7 /* 0x00000080 */
842 #define RES4312_TX_FILTBYP 8 /* 0x00000100 */
843 #define RES4312_RX_FILTBYP 9 /* 0x00000200 */
844 #define RES4312_XTAL_PU 10 /* 0x00000400 */
845 #define RES4312_ALP_AVAIL 11 /* 0x00000800 */
846 #define RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */
847 #define RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */
848 #define RES4312_HT_AVAIL 14 /* 0x00004000 */
849
850 /*
851 * Maximum delay for the PMU state transition.
852 * This is an upper bound intended for spinwaits etc.
853 */
854 #define PMU_MAX_TRANSITION_DLY 15000
855
856 #endif /* _SBCHIPC_H */
Personal OpenWRT clone
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