{
.name = "mdio_base",
.flags = IORESOURCE_MEM,
{
.name = "mdio_base",
.flags = IORESOURCE_MEM,
- .start = AR71XX_GE0_BASE + 0x20,
- .end = AR71XX_GE0_BASE + 0x38 - 1,
+ .start = AR71XX_GE0_BASE,
+ .end = AR71XX_GE0_BASE + 0x200 - 1,
.name = "mac_base",
.flags = IORESOURCE_MEM,
.start = AR71XX_GE0_BASE,
.name = "mac_base",
.flags = IORESOURCE_MEM,
.start = AR71XX_GE0_BASE,
- .end = AR71XX_GE0_BASE + 0x20 - 1,
- }, {
- .name = "mac_base2",
- .flags = IORESOURCE_MEM,
- .start = AR71XX_GE0_BASE + 0x38,
.end = AR71XX_GE0_BASE + 0x200 - 1,
}, {
.name = "mii_ctrl",
.end = AR71XX_GE0_BASE + 0x200 - 1,
}, {
.name = "mii_ctrl",
.name = "mac_base",
.flags = IORESOURCE_MEM,
.start = AR71XX_GE1_BASE,
.name = "mac_base",
.flags = IORESOURCE_MEM,
.start = AR71XX_GE1_BASE,
- .end = AR71XX_GE1_BASE + 0x20 - 1,
- }, {
- .name = "mac_base2",
- .flags = IORESOURCE_MEM,
- .start = AR71XX_GE1_BASE + 0x38,
.end = AR71XX_GE1_BASE + 0x200 - 1,
}, {
.name = "mii_ctrl",
.end = AR71XX_GE1_BASE + 0x200 - 1,
}, {
.name = "mii_ctrl",
#define ETH_FCS_LEN 4
#define AG71XX_DRV_NAME "ag71xx"
#define ETH_FCS_LEN 4
#define AG71XX_DRV_NAME "ag71xx"
-#define AG71XX_DRV_VERSION "0.5.23"
+#define AG71XX_DRV_VERSION "0.5.24"
#define AG71XX_NAPI_WEIGHT 64
#define AG71XX_OOM_REFILL (1 + HZ/10)
#define AG71XX_NAPI_WEIGHT 64
#define AG71XX_OOM_REFILL (1 + HZ/10)
struct ag71xx {
void __iomem *mac_base;
struct ag71xx {
void __iomem *mac_base;
- void __iomem *mac_base2;
void __iomem *mii_ctrl;
spinlock_t lock;
void __iomem *mii_ctrl;
spinlock_t lock;
switch (reg) {
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
switch (reg) {
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
- r = ag->mac_base + reg;
- __raw_writel(value, r);
- __raw_readl(r);
- break;
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
- r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+ r = ag->mac_base + reg;
+
+ /* flush write */
+ (void) __raw_readl(r);
switch (reg) {
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
switch (reg) {
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
- r = ag->mac_base + reg;
- ret = __raw_readl(r);
- break;
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
- r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+ r = ag->mac_base + reg;
ret = __raw_readl(r);
break;
default:
ret = __raw_readl(r);
break;
default:
switch (reg) {
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
switch (reg) {
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
- r = ag->mac_base + reg;
- __raw_writel(__raw_readl(r) | mask, r);
- __raw_readl(r);
- break;
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
- r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+ r = ag->mac_base + reg;
__raw_writel(__raw_readl(r) | mask, r);
__raw_writel(__raw_readl(r) | mask, r);
+
+ /* flush write */
+ (void)__raw_readl(r);
switch (reg) {
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
switch (reg) {
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
- r = ag->mac_base + reg;
- __raw_writel(__raw_readl(r) & ~mask, r);
- __raw_readl(r);
- break;
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
- r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+ r = ag->mac_base + reg;
__raw_writel(__raw_readl(r) & ~mask, r);
__raw_writel(__raw_readl(r) & ~mask, r);
+
+ /* flush write */
+ (void) __raw_readl(r);
return;
__raw_writel(value, ag->mii_ctrl);
return;
__raw_writel(value, ag->mii_ctrl);
__raw_readl(ag->mii_ctrl);
}
__raw_readl(ag->mii_ctrl);
}
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
- if (!res) {
- dev_err(&pdev->dev, "no mac_base2 resource found\n");
- err = -ENXIO;
- goto err_unmap_base1;
- }
-
- ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
- if (!ag->mac_base) {
- dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
- err = -ENOMEM;
- goto err_unmap_base1;
- }
-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
if (!res) {
dev_err(&pdev->dev, "no mii_ctrl resource found\n");
err = -ENXIO;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
if (!res) {
dev_err(&pdev->dev, "no mii_ctrl resource found\n");
err = -ENXIO;
}
ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
if (!ag->mii_ctrl) {
dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
err = -ENOMEM;
}
ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
if (!ag->mii_ctrl) {
dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
err = -ENOMEM;
}
dev->irq = platform_get_irq(pdev, 0);
}
dev->irq = platform_get_irq(pdev, 0);
free_irq(dev->irq, dev);
err_unmap_mii_ctrl:
iounmap(ag->mii_ctrl);
free_irq(dev->irq, dev);
err_unmap_mii_ctrl:
iounmap(ag->mii_ctrl);
- err_unmap_base2:
- iounmap(ag->mac_base2);
- err_unmap_base1:
iounmap(ag->mac_base);
err_free_dev:
kfree(dev);
iounmap(ag->mac_base);
err_free_dev:
kfree(dev);
unregister_netdev(dev);
free_irq(dev->irq, dev);
iounmap(ag->mii_ctrl);
unregister_netdev(dev);
free_irq(dev->irq, dev);
iounmap(ag->mii_ctrl);
- iounmap(ag->mac_base2);
iounmap(ag->mac_base);
kfree(dev);
platform_set_drvdata(pdev, NULL);
iounmap(ag->mac_base);
kfree(dev);
platform_set_drvdata(pdev, NULL);
static inline void ag71xx_mdio_wr(struct ag71xx_mdio *am, unsigned reg,
u32 value)
{
static inline void ag71xx_mdio_wr(struct ag71xx_mdio *am, unsigned reg,
u32 value)
{
- __raw_writel(value, am->mdio_base + reg - AG71XX_REG_MII_CFG);
+ __raw_writel(value, am->mdio_base + reg);
}
static inline u32 ag71xx_mdio_rr(struct ag71xx_mdio *am, unsigned reg)
{
}
static inline u32 ag71xx_mdio_rr(struct ag71xx_mdio *am, unsigned reg)
{
- return __raw_readl(am->mdio_base + reg - AG71XX_REG_MII_CFG);
+ return __raw_readl(am->mdio_base + reg);
}
static void ag71xx_mdio_dump_regs(struct ag71xx_mdio *am)
}
static void ag71xx_mdio_dump_regs(struct ag71xx_mdio *am)