add support for serial console with different rate (specified by the boot loader...

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@1366 3c298f89-4303-0410-b956-a3cf2f4a3e73

diff --git a/openwrt/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch b/openwrt/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch
index a6c8e05..4505296 100644 (file)
--- a/openwrt/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch
+++ b/openwrt/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch
@@ -1,71 +1,6 @@
-diff -urN linux-2.4.30/Makefile linux-2.4.30.dev/Makefile
---- linux-2.4.30/Makefile      2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/Makefile  2005-06-14 15:36:59.000000000 +0200
-@@ -91,7 +91,7 @@
- 
- CPPFLAGS := -D__KERNEL__ -I$(HPATH)
- 
--CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
-+CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
-         -fno-strict-aliasing -fno-common
- ifndef CONFIG_FRAME_POINTER
- CFLAGS += -fomit-frame-pointer
-diff -urN linux-2.4.30/arch/mips/Makefile linux-2.4.30.dev/arch/mips/Makefile
---- linux-2.4.30/arch/mips/Makefile    2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/Makefile        2005-06-14 15:36:59.000000000 +0200
-@@ -369,6 +369,16 @@
- endif
- 
- #
-+# Texas Instruments AR7
-+#
-+
-+ifdef CONFIG_AR7
-+LIBS          += arch/mips/ar7/ar7.o arch/mips/ar7/avalanche/avalanche.o
-+SUBDIRS               += arch/mips/ar7 arch/mips/ar7/avalanche
-+LOADADDR      += 0x94020000
-+endif
-+
-+#
- # DECstation family
- #
- ifdef CONFIG_DECSTATION
-diff -urN linux-2.4.30/arch/mips/ar7/Makefile linux-2.4.30.dev/arch/mips/ar7/Makefile
---- linux-2.4.30/arch/mips/ar7/Makefile        1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/Makefile    2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,12 @@
-+.S.s:
-+      $(CPP) $(AFLAGS) $< -o $*.s
-+
-+.S.o:
-+      $(CC) $(AFLAGS) -c $< -o $*.o
-+
-+O_TARGET := ar7.o
-+
-+obj-y := tnetd73xx_misc.o
-+obj-y += setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
-+
-+include $(TOPDIR)/Rules.make
-diff -urN linux-2.4.30/arch/mips/ar7/avalanche/Makefile linux-2.4.30.dev/arch/mips/ar7/avalanche/Makefile
---- linux-2.4.30/arch/mips/ar7/avalanche/Makefile      1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/avalanche/Makefile  2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,13 @@
-+.S.s:
-+      $(CPP) $(AFLAGS) $< -o $*.s
-+
-+.S.o:
-+      $(CC) $(AFLAGS) -c $< -o $*.o
-+
-+EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
-+
-+O_TARGET := avalanche.o
-+
-+obj-y += avalanche_paging.o avalanche_jump.o
-+
-+include $(TOPDIR)/Rules.make
-diff -urN linux-2.4.30/arch/mips/ar7/avalanche/avalanche_jump.S linux-2.4.30.dev/arch/mips/ar7/avalanche/avalanche_jump.S
---- linux-2.4.30/arch/mips/ar7/avalanche/avalanche_jump.S      1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/avalanche/avalanche_jump.S  2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_jump.S linux.dev/arch/mips/ar7/avalanche/avalanche_jump.S
+--- linux.old/arch/mips/ar7/avalanche/avalanche_jump.S 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/avalanche/avalanche_jump.S 2005-07-07 04:39:14.418226000 +0200

 @@ -0,0 +1,69 @@
 +#include <linux/config.h>
 +#include <linux/threads.h>
 @@ -0,0 +1,69 @@
 +#include <linux/config.h>
 +#include <linux/threads.h>


@@ -136,9 +71,9 @@ diff -urN linux-2.4.30/arch/mips/ar7/avalanche/avalanche_jump.S linux-2.4.30.dev
 +END(jump_dedicated_interrupt)
 +
 +      .set at
 +END(jump_dedicated_interrupt)
 +
 +      .set at

-diff -urN linux-2.4.30/arch/mips/ar7/avalanche/avalanche_paging.c linux-2.4.30.dev/arch/mips/ar7/avalanche/avalanche_paging.c
---- linux-2.4.30/arch/mips/ar7/avalanche/avalanche_paging.c    1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/avalanche/avalanche_paging.c        2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_paging.c linux.dev/arch/mips/ar7/avalanche/avalanche_paging.c
+--- linux.old/arch/mips/ar7/avalanche/avalanche_paging.c       1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/avalanche/avalanche_paging.c       2005-07-07 04:39:14.418226000 +0200

 @@ -0,0 +1,314 @@
 +/*
 + *  -*- linux-c -*-
 @@ -0,0 +1,314 @@
 +/*
 + *  -*- linux-c -*-


@@ -454,9 +389,26 @@ diff -urN linux-2.4.30/arch/mips/ar7/avalanche/avalanche_paging.c linux-2.4.30.d
 +
 +      return;
 +}
 +
 +      return;
 +}

-diff -urN linux-2.4.30/arch/mips/ar7/cmdline.c linux-2.4.30.dev/arch/mips/ar7/cmdline.c
---- linux-2.4.30/arch/mips/ar7/cmdline.c       1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/cmdline.c   2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/ar7/avalanche/Makefile linux.dev/arch/mips/ar7/avalanche/Makefile
+--- linux.old/arch/mips/ar7/avalanche/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/avalanche/Makefile 2005-07-07 04:39:14.417226000 +0200
+@@ -0,0 +1,13 @@
++.S.s:
++      $(CPP) $(AFLAGS) $< -o $*.s
++
++.S.o:
++      $(CC) $(AFLAGS) -c $< -o $*.o
++
++EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
++
++O_TARGET := avalanche.o
++
++obj-y += avalanche_paging.o avalanche_jump.o
++
++include $(TOPDIR)/Rules.make
+diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c
+--- linux.old/arch/mips/ar7/cmdline.c  1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/cmdline.c  2005-07-07 04:39:14.419226000 +0200

 @@ -0,0 +1,64 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com
 @@ -0,0 +1,64 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com


@@ -522,9 +474,9 @@ diff -urN linux-2.4.30/arch/mips/ar7/cmdline.c linux-2.4.30.dev/arch/mips/ar7/cm
 +              --cp;
 +      *cp = '\0';
 +}
 +              --cp;
 +      *cp = '\0';
 +}

-diff -urN linux-2.4.30/arch/mips/ar7/init.c linux-2.4.30.dev/arch/mips/ar7/init.c
---- linux-2.4.30/arch/mips/ar7/init.c  1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/init.c      2005-06-14 19:15:15.000000000 +0200
+diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c
+--- linux.old/arch/mips/ar7/init.c     1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/init.c     2005-07-07 04:39:14.419226000 +0200

 @@ -0,0 +1,144 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com
 @@ -0,0 +1,144 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com


@@ -670,9 +622,9 @@ diff -urN linux-2.4.30/arch/mips/ar7/init.c linux-2.4.30.dev/arch/mips/ar7/init.
 +
 +      return 0;
 +}
 +
 +      return 0;
 +}

-diff -urN linux-2.4.30/arch/mips/ar7/irq.c linux-2.4.30.dev/arch/mips/ar7/irq.c
---- linux-2.4.30/arch/mips/ar7/irq.c   1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/irq.c       2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c
+--- linux.old/arch/mips/ar7/irq.c      1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/irq.c      2005-07-07 04:39:14.420226000 +0200

 @@ -0,0 +1,669 @@
 +/*
 + * Nitin Dhingra, iamnd@ti.com
 @@ -0,0 +1,669 @@
 +/*
 + * Nitin Dhingra, iamnd@ti.com


@@ -1343,9 +1295,25 @@ diff -urN linux-2.4.30/arch/mips/ar7/irq.c linux-2.4.30.dev/arch/mips/ar7/irq.c
 +
 +}
 +
 +
 +}
 +

-diff -urN linux-2.4.30/arch/mips/ar7/memory.c linux-2.4.30.dev/arch/mips/ar7/memory.c
---- linux-2.4.30/arch/mips/ar7/memory.c        1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/memory.c    2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile
+--- linux.old/arch/mips/ar7/Makefile   1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/Makefile   2005-07-07 04:39:14.417226000 +0200
+@@ -0,0 +1,12 @@
++.S.s:
++      $(CPP) $(AFLAGS) $< -o $*.s
++
++.S.o:
++      $(CC) $(AFLAGS) -c $< -o $*.o
++
++O_TARGET := ar7.o
++
++obj-y := tnetd73xx_misc.o
++obj-y += setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
++
++include $(TOPDIR)/Rules.make
+diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c
+--- linux.old/arch/mips/ar7/memory.c   1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/memory.c   2005-07-07 04:39:14.420226000 +0200

 @@ -0,0 +1,130 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com
 @@ -0,0 +1,130 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com


@@ -1477,9 +1445,9 @@ diff -urN linux-2.4.30/arch/mips/ar7/memory.c linux-2.4.30.dev/arch/mips/ar7/mem
 +      }
 +      printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
 +}
 +      }
 +      printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
 +}

-diff -urN linux-2.4.30/arch/mips/ar7/mipsIRQ.S linux-2.4.30.dev/arch/mips/ar7/mipsIRQ.S
---- linux-2.4.30/arch/mips/ar7/mipsIRQ.S       1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/mipsIRQ.S   2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/ar7/mipsIRQ.S linux.dev/arch/mips/ar7/mipsIRQ.S
+--- linux.old/arch/mips/ar7/mipsIRQ.S  1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/mipsIRQ.S  2005-07-07 04:39:14.421226000 +0200

 @@ -0,0 +1,120 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com
 @@ -0,0 +1,120 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com


@@ -1601,9 +1569,9 @@ diff -urN linux-2.4.30/arch/mips/ar7/mipsIRQ.S linux-2.4.30.dev/arch/mips/ar7/mi
 +      j       ret_from_irq
 +      nop
 +END(mipsIRQ)
 +      j       ret_from_irq
 +      nop
 +END(mipsIRQ)

-diff -urN linux-2.4.30/arch/mips/ar7/printf.c linux-2.4.30.dev/arch/mips/ar7/printf.c
---- linux-2.4.30/arch/mips/ar7/printf.c        1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/printf.c    2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/ar7/printf.c linux.dev/arch/mips/ar7/printf.c
+--- linux.old/arch/mips/ar7/printf.c   1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/printf.c   2005-07-07 04:39:14.421226000 +0200

 @@ -0,0 +1,51 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com
 @@ -0,0 +1,51 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com


@@ -1656,9 +1624,9 @@ diff -urN linux-2.4.30/arch/mips/ar7/printf.c linux-2.4.30.dev/arch/mips/ar7/pri
 +      return;
 +
 +}
 +      return;
 +
 +}

-diff -urN linux-2.4.30/arch/mips/ar7/reset.c linux-2.4.30.dev/arch/mips/ar7/reset.c
---- linux-2.4.30/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/reset.c     2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c
+--- linux.old/arch/mips/ar7/reset.c    1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/reset.c    2005-07-07 04:39:14.421226000 +0200

 @@ -0,0 +1,54 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com
 @@ -0,0 +1,54 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com


@@ -1714,10 +1682,10 @@ diff -urN linux-2.4.30/arch/mips/ar7/reset.c linux-2.4.30.dev/arch/mips/ar7/rese
 +      _machine_halt = ar7_machine_halt;
 +      _machine_power_off = ar7_machine_power_off;
 +}
 +      _machine_halt = ar7_machine_halt;
 +      _machine_power_off = ar7_machine_power_off;
 +}

-diff -urN linux-2.4.30/arch/mips/ar7/setup.c linux-2.4.30.dev/arch/mips/ar7/setup.c
---- linux-2.4.30/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/setup.c     2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,150 @@
+diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c
+--- linux.old/arch/mips/ar7/setup.c    1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/setup.c    2005-07-07 06:45:41.786771352 +0200
+@@ -0,0 +1,167 @@

 +/*
 + * Carsten Langgaard, carstenl@mips.com
 + * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
 +/*
 + * Carsten Langgaard, carstenl@mips.com
 + * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.


@@ -1822,12 +1790,29 @@ diff -urN linux-2.4.30/arch/mips/ar7/setup.c linux-2.4.30.dev/arch/mips/ar7/setu
 +      extern char (*generic_getDebugChar)(void);
 +#endif
 +      char *argptr;
 +      extern char (*generic_getDebugChar)(void);
 +#endif
 +      char *argptr;

-+

 +#ifdef CONFIG_SERIAL_CONSOLE
 +      argptr = prom_getcmdline();
 +      if ((argptr = strstr(argptr, "console=")) == NULL) {
 +#ifdef CONFIG_SERIAL_CONSOLE
 +      argptr = prom_getcmdline();
 +      if ((argptr = strstr(argptr, "console=")) == NULL) {

++              char console[20];
++              char *s;
++              int i = 0;
++              
++              s = prom_getenv("modetty0");
++              strcpy(console, "38400");
++              
++              if (s != NULL) {
++                      while (s[i] >= '0' && s[i] <= '9')
++                              i++;
++              
++                      if (i > 0) {
++                              strncpy(console, s, i);
++                              console[i] = 0;
++                      }
++              }
++              

 +              argptr = prom_getcmdline();
 +              argptr = prom_getcmdline();

-+              strcat(argptr, " console=ttyS0,38400");
++              strcat(argptr, " console=ttyS0,");
++              strcat(argptr, console);

 +      }
 +#endif
 +
 +      }
 +#endif
 +


@@ -1868,9 +1853,9 @@ diff -urN linux-2.4.30/arch/mips/ar7/setup.c linux-2.4.30.dev/arch/mips/ar7/setu
 +      board_time_init = ar7_time_init;
 +      board_timer_setup = ar7_timer_setup;
 +}
 +      board_time_init = ar7_time_init;
 +      board_timer_setup = ar7_timer_setup;
 +}

-diff -urN linux-2.4.30/arch/mips/ar7/time.c linux-2.4.30.dev/arch/mips/ar7/time.c
---- linux-2.4.30/arch/mips/ar7/time.c  1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/time.c      2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/ar7/time.c linux.dev/arch/mips/ar7/time.c
+--- linux.old/arch/mips/ar7/time.c     1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/time.c     2005-07-07 04:39:14.422226000 +0200

 @@ -0,0 +1,125 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com
 @@ -0,0 +1,125 @@
 +/*
 + * Carsten Langgaard, carstenl@mips.com


@@ -1997,9 +1982,9 @@ diff -urN linux-2.4.30/arch/mips/ar7/time.c linux-2.4.30.dev/arch/mips/ar7/time.
 +      write_c0_compare(r4k_cur);
 +      set_c0_status(ALLINTS);
 +}
 +      write_c0_compare(r4k_cur);
 +      set_c0_status(ALLINTS);
 +}

-diff -urN linux-2.4.30/arch/mips/ar7/tnetd73xx_misc.c linux-2.4.30.dev/arch/mips/ar7/tnetd73xx_misc.c
---- linux-2.4.30/arch/mips/ar7/tnetd73xx_misc.c        1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/arch/mips/ar7/tnetd73xx_misc.c    2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c
+--- linux.old/arch/mips/ar7/tnetd73xx_misc.c   1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c   2005-07-07 04:39:14.423225000 +0200

 @@ -0,0 +1,924 @@
 +/******************************************************************************
 + * FILE PURPOSE:    TNETD73xx Misc modules API Source
 @@ -0,0 +1,924 @@
 +/******************************************************************************
 + * FILE PURPOSE:    TNETD73xx Misc modules API Source


@@ -2925,9 +2910,9 @@ diff -urN linux-2.4.30/arch/mips/ar7/tnetd73xx_misc.c linux-2.4.30.dev/arch/mips
 +      return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
 +}
 +
 +      return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
 +}
 +

-diff -urN linux-2.4.30/arch/mips/config-shared.in linux-2.4.30.dev/arch/mips/config-shared.in
---- linux-2.4.30/arch/mips/config-shared.in    2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/config-shared.in        2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
+--- linux.old/arch/mips/config-shared.in       2005-07-07 05:38:31.343491864 +0200
++++ linux.dev/arch/mips/config-shared.in       2005-07-07 04:39:14.424225000 +0200

 @@ -20,6 +20,15 @@
  mainmenu_option next_comment
  comment 'Machine selection'
 @@ -20,6 +20,15 @@
  mainmenu_option next_comment
  comment 'Machine selection'


@@ -2972,9 +2957,9 @@ diff -urN linux-2.4.30/arch/mips/config-shared.in linux-2.4.30.dev/arch/mips/con
       "$CONFIG_CASIO_E55" = "y" -o \
       "$CONFIG_DECSTATION" = "y" -o \
       "$CONFIG_IBM_WORKPAD" = "y" -o \
       "$CONFIG_CASIO_E55" = "y" -o \
       "$CONFIG_DECSTATION" = "y" -o \
       "$CONFIG_IBM_WORKPAD" = "y" -o \

-diff -urN linux-2.4.30/arch/mips/kernel/irq.c linux-2.4.30.dev/arch/mips/kernel/irq.c
---- linux-2.4.30/arch/mips/kernel/irq.c        2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/kernel/irq.c    2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/kernel/irq.c linux.dev/arch/mips/kernel/irq.c
+--- linux.old/arch/mips/kernel/irq.c   2005-07-07 05:38:31.343491864 +0200
++++ linux.dev/arch/mips/kernel/irq.c   2005-07-07 04:39:14.424225000 +0200

 @@ -76,6 +76,7 @@
   * Generic, controller-independent functions:
   */
 @@ -76,6 +76,7 @@
   * Generic, controller-independent functions:
   */


@@ -3023,9 +3008,9 @@ diff -urN linux-2.4.30/arch/mips/kernel/irq.c linux-2.4.30.dev/arch/mips/kernel/
  
  /*
   * IRQ autodetection code..
  
  /*
   * IRQ autodetection code..

-diff -urN linux-2.4.30/arch/mips/kernel/setup.c linux-2.4.30.dev/arch/mips/kernel/setup.c
---- linux-2.4.30/arch/mips/kernel/setup.c      2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/kernel/setup.c  2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
+--- linux.old/arch/mips/kernel/setup.c 2005-07-07 05:38:31.344491712 +0200
++++ linux.dev/arch/mips/kernel/setup.c 2005-07-07 04:39:14.425225000 +0200

 @@ -109,6 +109,7 @@
  unsigned long isa_slot_offset;
  EXPORT_SYMBOL(isa_slot_offset);
 @@ -109,6 +109,7 @@
  unsigned long isa_slot_offset;
  EXPORT_SYMBOL(isa_slot_offset);


@@ -3073,9 +3058,9 @@ diff -urN linux-2.4.30/arch/mips/kernel/setup.c linux-2.4.30.dev/arch/mips/kerne
        default:
                panic("Unsupported architecture");
        }
        default:
                panic("Unsupported architecture");
        }

-diff -urN linux-2.4.30/arch/mips/kernel/traps.c linux-2.4.30.dev/arch/mips/kernel/traps.c
---- linux-2.4.30/arch/mips/kernel/traps.c      2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/kernel/traps.c  2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
+--- linux.old/arch/mips/kernel/traps.c 2005-07-07 05:38:31.345491560 +0200
++++ linux.dev/arch/mips/kernel/traps.c 2005-07-07 04:39:14.425225000 +0200

 @@ -40,6 +40,10 @@
  #include <asm/uaccess.h>
  #include <asm/mmu_context.h>
 @@ -40,6 +40,10 @@
  #include <asm/uaccess.h>
  #include <asm/mmu_context.h>


@@ -3193,9 +3178,9 @@ diff -urN linux-2.4.30/arch/mips/kernel/traps.c linux-2.4.30.dev/arch/mips/kerne
  
        per_cpu_trap_init();
  }
  
        per_cpu_trap_init();
  }

-diff -urN linux-2.4.30/arch/mips/lib/promlib.c linux-2.4.30.dev/arch/mips/lib/promlib.c
---- linux-2.4.30/arch/mips/lib/promlib.c       2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/lib/promlib.c   2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/lib/promlib.c linux.dev/arch/mips/lib/promlib.c
+--- linux.old/arch/mips/lib/promlib.c  2005-07-07 05:38:31.345491560 +0200
++++ linux.dev/arch/mips/lib/promlib.c  2005-07-07 04:39:14.426225000 +0200

 @@ -1,3 +1,4 @@
 +#ifndef CONFIG_AR7
  #include <stdarg.h>
 @@ -1,3 +1,4 @@
 +#ifndef CONFIG_AR7
  #include <stdarg.h>


@@ -3206,9 +3191,29 @@ diff -urN linux-2.4.30/arch/mips/lib/promlib.c linux-2.4.30.dev/arch/mips/lib/pr
        va_end(args);
  }
 +#endif
        va_end(args);
  }
 +#endif

-diff -urN linux-2.4.30/arch/mips/mm/init.c linux-2.4.30.dev/arch/mips/mm/init.c
---- linux-2.4.30/arch/mips/mm/init.c   2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/mm/init.c       2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
+--- linux.old/arch/mips/Makefile       2005-07-07 05:38:31.320495360 +0200
++++ linux.dev/arch/mips/Makefile       2005-07-07 04:39:14.510212000 +0200
+@@ -369,6 +369,16 @@
+ endif
+ 
+ #
++# Texas Instruments AR7
++#
++
++ifdef CONFIG_AR7
++LIBS          += arch/mips/ar7/ar7.o arch/mips/ar7/avalanche/avalanche.o
++SUBDIRS               += arch/mips/ar7 arch/mips/ar7/avalanche
++LOADADDR      += 0x94020000
++endif
++
++#
+ # DECstation family
+ #
+ ifdef CONFIG_DECSTATION
+diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c
+--- linux.old/arch/mips/mm/init.c      2005-07-07 05:38:31.345491560 +0200
++++ linux.dev/arch/mips/mm/init.c      2005-07-07 04:39:14.426225000 +0200

 @@ -40,8 +40,10 @@
  
  mmu_gather_t mmu_gathers[NR_CPUS];
 @@ -40,8 +40,10 @@
  
  mmu_gather_t mmu_gathers[NR_CPUS];


@@ -3275,9 +3280,9 @@ diff -urN linux-2.4.30/arch/mips/mm/init.c linux-2.4.30.dev/arch/mips/mm/init.c
        return;
  }
 +#endif
        return;
  }
 +#endif

-diff -urN linux-2.4.30/arch/mips/mm/tlb-r4k.c linux-2.4.30.dev/arch/mips/mm/tlb-r4k.c
---- linux-2.4.30/arch/mips/mm/tlb-r4k.c        2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/arch/mips/mm/tlb-r4k.c    2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/arch/mips/mm/tlb-r4k.c linux.dev/arch/mips/mm/tlb-r4k.c
+--- linux.old/arch/mips/mm/tlb-r4k.c   2005-07-07 05:38:31.346491408 +0200
++++ linux.dev/arch/mips/mm/tlb-r4k.c   2005-07-07 04:39:14.427225000 +0200

 @@ -20,6 +20,10 @@
  #include <asm/pgtable.h>
  #include <asm/system.h>
 @@ -20,6 +20,10 @@
  #include <asm/pgtable.h>
  #include <asm/system.h>


@@ -3302,9 +3307,9 @@ diff -urN linux-2.4.30/arch/mips/mm/tlb-r4k.c linux-2.4.30.dev/arch/mips/mm/tlb-
 +#endif
        }
  }
 +#endif
        }
  }

-diff -urN linux-2.4.30/drivers/char/serial.c linux-2.4.30.dev/drivers/char/serial.c
---- linux-2.4.30/drivers/char/serial.c 2005-06-14 18:42:06.000000000 +0200
-+++ linux-2.4.30.dev/drivers/char/serial.c     2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
+--- linux.old/drivers/char/serial.c    2005-07-07 05:38:31.348491104 +0200
++++ linux.dev/drivers/char/serial.c    2005-07-07 04:39:14.429225000 +0200

 @@ -419,7 +419,40 @@
        return 0;
  }
 @@ -419,7 +419,40 @@
        return 0;
  }


@@ -3378,7 +3383,7 @@ diff -urN linux-2.4.30/drivers/char/serial.c linux-2.4.30.dev/drivers/char/seria
                state->irq = irq_cannonicalize(state->irq);
                if (state->hub6)
                        state->io_type = SERIAL_IO_HUB6;
                state->irq = irq_cannonicalize(state->irq);
                if (state->hub6)
                        state->io_type = SERIAL_IO_HUB6;

-+#ifdef CONFIG_AR7
++#ifndef CONFIG_AR7

                if (state->port && check_region(state->port,8))
                        continue;
 +#endif
                if (state->port && check_region(state->port,8))
                        continue;
 +#endif


@@ -3401,9 +3406,9 @@ diff -urN linux-2.4.30/drivers/char/serial.c linux-2.4.30.dev/drivers/char/seria
        cval = cflag & (CSIZE | CSTOPB);
  #if defined(__powerpc__) || defined(__alpha__)
        cval >>= 8;
        cval = cflag & (CSIZE | CSTOPB);
  #if defined(__powerpc__) || defined(__alpha__)
        cval >>= 8;

-diff -urN linux-2.4.30/include/asm-mips/ar7/ar7.h linux-2.4.30.dev/include/asm-mips/ar7/ar7.h
---- linux-2.4.30/include/asm-mips/ar7/ar7.h    1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/ar7.h        2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar7.h
+--- linux.old/include/asm-mips/ar7/ar7.h       1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/ar7.h       2005-07-07 04:39:14.430224000 +0200

 @@ -0,0 +1,137 @@
 +#ifndef _MIPS_AR7_H
 +#define _MIPS_AR7_H
 @@ -0,0 +1,137 @@
 +#ifndef _MIPS_AR7_H
 +#define _MIPS_AR7_H


@@ -3542,9 +3547,9 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/ar7.h linux-2.4.30.dev/include/asm-m
 +}
 +
 +#endif /*_MIPS_AR7_H */
 +}
 +
 +#endif /*_MIPS_AR7_H */

-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche.h      1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche.h  2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/include/asm-mips/ar7/avalanche.h linux.dev/include/asm-mips/ar7/avalanche.h
+--- linux.old/include/asm-mips/ar7/avalanche.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/avalanche.h 2005-07-07 04:39:14.430224000 +0200

 @@ -0,0 +1,183 @@
 +/* $Id$
 + *
 @@ -0,0 +1,183 @@
 +/* $Id$
 + *


@@ -3729,16 +3734,14 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche.h linux-2.4.30.dev/include
 +
 +
 +
 +
 +
 +

-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_int.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche_int.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche_int.h  1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche_int.h      2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,298 @@
-+/* $Id$
-+ *
-+ * avalancheint.h
+diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm-mips/ar7/avalanche_intc.h
+--- linux.old/include/asm-mips/ar7/avalanche_intc.h    1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/avalanche_intc.h    2005-07-07 04:39:14.431224000 +0200
+@@ -0,0 +1,273 @@
++ /*
++ * Nitin Dhingra, iamnd@ti.com
++ * Copyright (C) 2000 Texas Instruments Inc.

 + *
 + *

-+ * Jeff Harrell, jharrell@ti.com
-+ * Copyright (C) 2000,2001 Texas Instruments , Inc.

 + *
 + * ########################################################################
 + *
 + *
 + * ########################################################################
 + *


@@ -3757,25 +3760,26 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_int.h linux-2.4.30.dev/inc
 + *
 + * ########################################################################
 + *
 + *
 + * ########################################################################
 + *

-+ * Defines for the AVALANCHE interrupt controller.
++ * Defines of the Sead board specific address-MAP, registers, etc.

 + *
 + */
 + *
 + */

-+#ifndef _MIPS_AVALANCHEINT_H
-+#define _MIPS_AVALANCHEINT_H
++#ifndef _AVALANCHE_INTC_H
++#define _AVALANCHE_INTC_H

 +
 +

-+#include <linux/config.h>
++#define MIPS_EXCEPTION_OFFSET 8

 +
 +

-+/* Avalanche Interrupt number */
++/******************************************************************************
++ Avalanche Interrupt number
++******************************************************************************/

 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)

-+/* Linux Interrupt number     */ 
++
++/*******************************************************************************
++*Linux Interrupt number
++*******************************************************************************/

 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)

-+/* Number of IRQ supported on hw interrupt 0. */

 +
 +

-+//#define SEADINT_UART0      3            /* TTYS0 interrupt on SEAD */
-+//#define SEADINT_UART1      4            /* TTYS1 interrupt on SEAD */

 +
 +
 +
 +

-+#define MIPS_EXCEPTION_OFFSET 8

 +#define AVALANCHE_INT_END_PRIMARY      (40 + MIPS_EXCEPTION_OFFSET)
 +#define AVALANCHE_INT_END_SECONDARY    (32 + MIPS_EXCEPTION_OFFSET)
 +
 +#define AVALANCHE_INT_END_PRIMARY      (40 + MIPS_EXCEPTION_OFFSET)
 +#define AVALANCHE_INT_END_SECONDARY    (32 + MIPS_EXCEPTION_OFFSET)
 +


@@ -3783,91 +3787,127 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_int.h linux-2.4.30.dev/inc
 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
 +
 +
 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
 +
 +

-+#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + AVINTNUM(AVALANCHE_INT_END_SECONDARY)  \
-+                     + MIPS_EXCEPTION_OFFSET - 1)
++#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
++                          AVINTNUM(AVALANCHE_INT_END_SECONDARY)  \
++                                    + MIPS_EXCEPTION_OFFSET - 1) /* Suraj, check */
++
++
++/*
++ * Avalanche interrupt controller register base (primary)
++ */
++#define AVALANCHE_ICTRL_REGS_BASE  AVALANCHE_INTC_BASE
++
++/******************************************************************************
++ * Avalanche exception controller register base (secondary)
++ ******************************************************************************/
++#define AVALANCHE_ECTRL_REGS_BASE  (AVALANCHE_ICTRL_REGS_BASE + 0x80)
++
++
++/******************************************************************************
++ *  Avalanche Interrupt pacing register base (secondary)
++ ******************************************************************************/
++#define AVALANCHE_IPACE_REGS_BASE  (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
++
++
++
++/******************************************************************************
++ * Avalanche Interrupt Channel Control register base
++ *****************************************************************************/
++#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
++

 +
 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
 +{
 +
 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
 +{

-+  volatile unsigned long intsr1;    /* Interrupt Status/Set Register 1   */ /* 0x00 */      
-+  volatile unsigned long intsr2;    /* Interrupt Status/Set Register 2   */ /* 0x04 */
-+  volatile unsigned long unused1;                                           /* 0x08 */
-+  volatile unsigned long unused2;                                           /* 0x0C */
-+  volatile unsigned long intcr1;    /* Interrupt Clear Register 1        */ /* 0x10 */
-+  volatile unsigned long intcr2;    /* Interrupt Clear Register 2        */ /* 0x14 */
-+  volatile unsigned long unused3;                                           /* 0x18 */
-+  volatile unsigned long unused4;                                           /* 0x1C */
-+  volatile unsigned long intesr1;   /* Interrupt Enable (Set) Register 1 */ /* 0x20 */
-+  volatile unsigned long intesr2;   /* Interrupt Enable (Set) Register 2 */ /* 0x24 */
-+  volatile unsigned long unused5;                                           /* 0x28 */
-+  volatile unsigned long unused6;                                           /* 0x2C */
-+  volatile unsigned long intecr1;   /* Interrupt Enable Clear Register 1 */ /* 0x30 */
-+  volatile unsigned long intecr2;   /* Interrupt Enable Clear Register 2 */ /* 0x34 */
-+  volatile unsigned long unused7;                                           /* 0x38 */
-+  volatile unsigned long unused8;                                           /* 0x3c */
-+  volatile unsigned long pintir;    /* Priority Interrupt Index Register */ /* 0x40 */
-+  volatile unsigned long intmsr;    /* Priority Interrupt Mask Index Reg.*/ /* 0x44 */
-+  volatile unsigned long unused9;                                           /* 0x48 */
-+  volatile unsigned long unused10;                                          /* 0x4C */
-+  volatile unsigned long intpolr1;  /* Interrupt Polarity Mask register 1*/ /* 0x50 */
-+  volatile unsigned long intpolr2;  /* Interrupt Polarity Mask register 2*/ /* 0x54 */
++  volatile unsigned long intsr1;    /* Interrupt Status/Set Register 1   0x00 */
++  volatile unsigned long intsr2;    /* Interrupt Status/Set Register 2   0x04 */
++  volatile unsigned long unused1;                                      /*0x08 */
++  volatile unsigned long unused2;                                      /*0x0C */
++  volatile unsigned long intcr1;    /* Interrupt Clear Register 1        0x10 */
++  volatile unsigned long intcr2;    /* Interrupt Clear Register 2        0x14 */
++  volatile unsigned long unused3;                                      /*0x18 */
++  volatile unsigned long unused4;                                      /*0x1C */
++  volatile unsigned long intesr1;   /* Interrupt Enable (Set) Register 1 0x20 */
++  volatile unsigned long intesr2;   /* Interrupt Enable (Set) Register 2 0x24 */
++  volatile unsigned long unused5;                                      /*0x28 */
++  volatile unsigned long unused6;                                      /*0x2C */
++  volatile unsigned long intecr1;   /* Interrupt Enable Clear Register 1 0x30 */
++  volatile unsigned long intecr2;   /* Interrupt Enable Clear Register 2 0x34 */
++  volatile unsigned long unused7;                                     /* 0x38 */
++  volatile unsigned long unused8;                                     /* 0x3c */
++  volatile unsigned long pintir;    /* Priority Interrupt Index Register 0x40 */
++  volatile unsigned long intmsr;    /* Priority Interrupt Mask Index Reg 0x44 */
++  volatile unsigned long unused9;                                     /* 0x48 */
++  volatile unsigned long unused10;                                    /* 0x4C */
++  volatile unsigned long intpolr1;  /* Interrupt Polarity Mask register 10x50 */
++  volatile unsigned long intpolr2;  /* Interrupt Polarity Mask register 20x54 */
++  volatile unsigned long unused11;                                    /* 0x58 */
++  volatile unsigned long unused12;                                   /*0x5C */
++  volatile unsigned long inttypr1;  /* Interrupt Type     Mask register 10x60 */
++  volatile unsigned long inttypr2;  /* Interrupt Type     Mask register 20x64 */

 +};
 +
 +struct avalanche_exctrl_regs   /* Avalanche Exception control registers */
 +{
 +};
 +
 +struct avalanche_exctrl_regs   /* Avalanche Exception control registers */
 +{

-+  volatile unsigned long exsr;      /* Exceptions Status/Set register    */  /* 0x80 */
-+  volatile unsigned long reserved;                                           /* 0x84 */
-+  volatile unsigned long excr;      /* Exceptions Clear Register         */  /* 0x88 */
-+  volatile unsigned long reserved1;                                          /* 0x8c */
-+  volatile unsigned long exiesr;    /* Exceptions Interrupt Enable (set) */  /* 0x90 */
-+  volatile unsigned long reserved2;                                          /* 0x94 */
-+  volatile unsigned long exiecr;    /* Exceptions Interrupt Enable (clear)*/ /* 0x98 */
++  volatile unsigned long exsr;      /* Exceptions Status/Set register    0x80 */
++  volatile unsigned long reserved;                                     /*0x84 */
++  volatile unsigned long excr;      /* Exceptions Clear Register         0x88 */
++  volatile unsigned long reserved1;                                    /*0x8c */
++  volatile unsigned long exiesr;    /* Exceptions Interrupt Enable (set) 0x90 */
++  volatile unsigned long reserved2;                                    /*0x94 */
++  volatile unsigned long exiecr;    /* Exceptions Interrupt Enable(clear)0x98 */

 +};
 +};

++struct avalanche_ipace_regs
++{

 +
 +

++  volatile unsigned long ipacep;    /* Interrupt pacing register         0xa0 */
++  volatile unsigned long ipacemap;  /*Interrupt Pacing Map Register      0xa4 */
++  volatile unsigned long ipacemax;  /*Interrupt Pacing Max Register      0xa8 */
++};

 +struct avalanche_channel_int_number
 +{
 +struct avalanche_channel_int_number
 +{

-+  volatile unsigned long cintnr0;   /* Channel Interrupt Number Register */  /* 0x200 */
-+  volatile unsigned long cintnr1;   /* Channel Interrupt Number Register */  /* 0x204 */
-+  volatile unsigned long cintnr2;   /* Channel Interrupt Number Register */  /* 0x208 */
-+  volatile unsigned long cintnr3;   /* Channel Interrupt Number Register */  /* 0x20C */
-+  volatile unsigned long cintnr4;   /* Channel Interrupt Number Register */  /* 0x210 */
-+  volatile unsigned long cintnr5;   /* Channel Interrupt Number Register */  /* 0x214 */
-+  volatile unsigned long cintnr6;   /* Channel Interrupt Number Register */  /* 0x218 */
-+  volatile unsigned long cintnr7;   /* Channel Interrupt Number Register */  /* 0x21C */
-+  volatile unsigned long cintnr8;   /* Channel Interrupt Number Register */  /* 0x220 */
-+  volatile unsigned long cintnr9;   /* Channel Interrupt Number Register */  /* 0x224 */
-+  volatile unsigned long cintnr10;  /* Channel Interrupt Number Register */  /* 0x228 */
-+  volatile unsigned long cintnr11;  /* Channel Interrupt Number Register */  /* 0x22C */
-+  volatile unsigned long cintnr12;  /* Channel Interrupt Number Register */  /* 0x230 */
-+  volatile unsigned long cintnr13;  /* Channel Interrupt Number Register */  /* 0x234 */
-+  volatile unsigned long cintnr14;  /* Channel Interrupt Number Register */  /* 0x238 */
-+  volatile unsigned long cintnr15;  /* Channel Interrupt Number Register */  /* 0x23C */
-+  volatile unsigned long cintnr16;  /* Channel Interrupt Number Register */  /* 0x240 */
-+  volatile unsigned long cintnr17;  /* Channel Interrupt Number Register */  /* 0x244 */
-+  volatile unsigned long cintnr18;  /* Channel Interrupt Number Register */  /* 0x248 */
-+  volatile unsigned long cintnr19;  /* Channel Interrupt Number Register */  /* 0x24C */
-+  volatile unsigned long cintnr20;  /* Channel Interrupt Number Register */  /* 0x250 */
-+  volatile unsigned long cintnr21;  /* Channel Interrupt Number Register */  /* 0x254 */
-+  volatile unsigned long cintnr22;  /* Channel Interrupt Number Register */  /* 0x358 */
-+  volatile unsigned long cintnr23;  /* Channel Interrupt Number Register */  /* 0x35C */
-+  volatile unsigned long cintnr24;  /* Channel Interrupt Number Register */  /* 0x260 */
-+  volatile unsigned long cintnr25;  /* Channel Interrupt Number Register */  /* 0x264 */
-+  volatile unsigned long cintnr26;  /* Channel Interrupt Number Register */  /* 0x268 */
-+  volatile unsigned long cintnr27;  /* Channel Interrupt Number Register */  /* 0x26C */
-+  volatile unsigned long cintnr28;  /* Channel Interrupt Number Register */  /* 0x270 */
-+  volatile unsigned long cintnr29;  /* Channel Interrupt Number Register */  /* 0x274 */
-+  volatile unsigned long cintnr30;  /* Channel Interrupt Number Register */  /* 0x278 */
-+  volatile unsigned long cintnr31;  /* Channel Interrupt Number Register */  /* 0x27C */
-+  volatile unsigned long cintnr32;  /* Channel Interrupt Number Register */  /* 0x280 */
-+  volatile unsigned long cintnr33;  /* Channel Interrupt Number Register */  /* 0x284 */
-+  volatile unsigned long cintnr34;  /* Channel Interrupt Number Register */  /* 0x288 */
-+  volatile unsigned long cintnr35;  /* Channel Interrupt Number Register */  /* 0x28C */
-+  volatile unsigned long cintnr36;  /* Channel Interrupt Number Register */  /* 0x290 */
-+  volatile unsigned long cintnr37;  /* Channel Interrupt Number Register */  /* 0x294 */
-+  volatile unsigned long cintnr38;  /* Channel Interrupt Number Register */  /* 0x298 */
-+  volatile unsigned long cintnr39;  /* Channel Interrupt Number Register */  /* 0x29C */
++  volatile unsigned long cintnr0;   /* Channel Interrupt Number Register0x200 */
++  volatile unsigned long cintnr1;   /* Channel Interrupt Number Register0x204 */
++  volatile unsigned long cintnr2;   /* Channel Interrupt Number Register0x208 */
++  volatile unsigned long cintnr3;   /* Channel Interrupt Number Register0x20C */
++  volatile unsigned long cintnr4;   /* Channel Interrupt Number Register0x210 */
++  volatile unsigned long cintnr5;   /* Channel Interrupt Number Register0x214 */
++  volatile unsigned long cintnr6;   /* Channel Interrupt Number Register0x218 */
++  volatile unsigned long cintnr7;   /* Channel Interrupt Number Register0x21C */
++  volatile unsigned long cintnr8;   /* Channel Interrupt Number Register0x220 */
++  volatile unsigned long cintnr9;   /* Channel Interrupt Number Register0x224 */
++  volatile unsigned long cintnr10;  /* Channel Interrupt Number Register0x228 */
++  volatile unsigned long cintnr11;  /* Channel Interrupt Number Register0x22C */
++  volatile unsigned long cintnr12;  /* Channel Interrupt Number Register0x230 */
++  volatile unsigned long cintnr13;  /* Channel Interrupt Number Register0x234 */
++  volatile unsigned long cintnr14;  /* Channel Interrupt Number Register0x238 */
++  volatile unsigned long cintnr15;  /* Channel Interrupt Number Register0x23C */
++  volatile unsigned long cintnr16;  /* Channel Interrupt Number Register0x240 */
++  volatile unsigned long cintnr17;  /* Channel Interrupt Number Register0x244 */
++  volatile unsigned long cintnr18;  /* Channel Interrupt Number Register0x248 */
++  volatile unsigned long cintnr19;  /* Channel Interrupt Number Register0x24C */
++  volatile unsigned long cintnr20;  /* Channel Interrupt Number Register0x250 */
++  volatile unsigned long cintnr21;  /* Channel Interrupt Number Register0x254 */
++  volatile unsigned long cintnr22;  /* Channel Interrupt Number Register0x358 */
++  volatile unsigned long cintnr23;  /* Channel Interrupt Number Register0x35C */
++  volatile unsigned long cintnr24;  /* Channel Interrupt Number Register0x260 */
++  volatile unsigned long cintnr25;  /* Channel Interrupt Number Register0x264 */
++  volatile unsigned long cintnr26;  /* Channel Interrupt Number Register0x268 */
++  volatile unsigned long cintnr27;  /* Channel Interrupt Number Register0x26C */
++  volatile unsigned long cintnr28;  /* Channel Interrupt Number Register0x270 */
++  volatile unsigned long cintnr29;  /* Channel Interrupt Number Register0x274 */
++  volatile unsigned long cintnr30;  /* Channel Interrupt Number Register0x278 */
++  volatile unsigned long cintnr31;  /* Channel Interrupt Number Register0x27C */
++  volatile unsigned long cintnr32;  /* Channel Interrupt Number Register0x280 */
++  volatile unsigned long cintnr33;  /* Channel Interrupt Number Register0x284 */
++  volatile unsigned long cintnr34;  /* Channel Interrupt Number Register0x288 */
++  volatile unsigned long cintnr35;  /* Channel Interrupt Number Register0x28C */
++  volatile unsigned long cintnr36;  /* Channel Interrupt Number Register0x290 */
++  volatile unsigned long cintnr37;  /* Channel Interrupt Number Register0x294 */
++  volatile unsigned long cintnr38;  /* Channel Interrupt Number Register0x298 */
++  volatile unsigned long cintnr39;  /* Channel Interrupt Number Register0x29C */

 +};
 +
 +};
 +

-+struct avalanche_interrupt_line_to_channel 
++struct avalanche_interrupt_line_to_channel

 +{
 +  unsigned long int_line0;    /* Start of primary interrupts */
 +  unsigned long int_line1;
 +{
 +  unsigned long int_line0;    /* Start of primary interrupts */
 +  unsigned long int_line1;


@@ -3880,165 +3920,107 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_int.h linux-2.4.30.dev/inc
 +  unsigned long int_line8;
 +  unsigned long int_line9;
 +  unsigned long int_line10;
 +  unsigned long int_line8;
 +  unsigned long int_line9;
 +  unsigned long int_line10;

-+  unsigned long int_line11; 
-+  unsigned long int_line12; 
-+  unsigned long int_line13; 
-+  unsigned long int_line14; 
-+  unsigned long int_line15; 
-+  unsigned long int_line16; 
-+  unsigned long int_line17; 
-+  unsigned long int_line18; 
-+  unsigned long int_line19; 
-+  unsigned long int_line20; 
++  unsigned long int_line11;
++  unsigned long int_line12;
++  unsigned long int_line13;
++  unsigned long int_line14;
++  unsigned long int_line15;
++  unsigned long int_line16;
++  unsigned long int_line17;
++  unsigned long int_line18;
++  unsigned long int_line19;
++  unsigned long int_line20;

 +  unsigned long int_line21;
 +  unsigned long int_line21;

-+  unsigned long int_line22; 
-+  unsigned long int_line23; 
-+  unsigned long int_line24; 
-+  unsigned long int_line25; 
-+  unsigned long int_line26; 
-+  unsigned long int_line27; 
-+  unsigned long int_line28; 
-+  unsigned long int_line29; 
-+  unsigned long int_line30; 
-+  unsigned long int_line31; 
++  unsigned long int_line22;
++  unsigned long int_line23;
++  unsigned long int_line24;
++  unsigned long int_line25;
++  unsigned long int_line26;
++  unsigned long int_line27;
++  unsigned long int_line28;
++  unsigned long int_line29;
++  unsigned long int_line30;
++  unsigned long int_line31;

 +  unsigned long int_line32;
 +  unsigned long int_line32;

-+  unsigned long int_line33; 
-+  unsigned long int_line34; 
-+  unsigned long int_line35; 
-+  unsigned long int_line36; 
-+  unsigned long int_line37; 
-+  unsigned long int_line38; 
-+  unsigned long int_line39;  
++  unsigned long int_line33;
++  unsigned long int_line34;
++  unsigned long int_line35;
++  unsigned long int_line36;
++  unsigned long int_line37;
++  unsigned long int_line38;
++  unsigned long int_line39;

 +};
 +
 +};
 +

-+/* Interrupt Line #'s  (Avalanche peripherals) */
++
++/* Interrupt Line #'s  (Sangam peripherals) */

 +
 +/*------------------------------*/
 +
 +/*------------------------------*/

-+/* Avalanche primary interrupts */
++/* Sangam primary interrupts */

 +/*------------------------------*/
 +/*------------------------------*/

++

 +#define UNIFIED_SECONDARY_INTERRUPT  0
 +#define AVALANCHE_EXT_INT_0          1
 +#define AVALANCHE_EXT_INT_1          2
 +#define UNIFIED_SECONDARY_INTERRUPT  0
 +#define AVALANCHE_EXT_INT_0          1
 +#define AVALANCHE_EXT_INT_1          2

-+#define AVALANCHE_EXT_INT_2          3
-+#define AVALANCHE_EXT_INT_3          4
++/*  Line #3  Reserved               */
++/*  Line #4  Reserved               */

 +#define AVALANCHE_TIMER_0_INT        5
 +#define AVALANCHE_TIMER_1_INT        6
 +#define AVALANCHE_UART0_INT          7
 +#define AVALANCHE_UART1_INT          8
 +#define AVALANCHE_PDMA_INT0          9
 +#define AVALANCHE_PDMA_INT1          10
 +#define AVALANCHE_TIMER_0_INT        5
 +#define AVALANCHE_TIMER_1_INT        6
 +#define AVALANCHE_UART0_INT          7
 +#define AVALANCHE_UART1_INT          8
 +#define AVALANCHE_PDMA_INT0          9
 +#define AVALANCHE_PDMA_INT1          10

-+#define AVALANCHE_HDLC_TXA           11
-+#define AVALANCHE_HDLC_TXB           12
-+#define AVALANCHE_HDLC_RXA           13
-+#define AVALANCHE_HDLC_RXB           14
-+#define AVALANCHE_ATM_SAR_TXA        15
-+#define AVALANCHE_ATM_SAR_TXB        16
-+#define AVALANCHE_ATM_SAR_RXA        17
-+#define AVALANCHE_ATM_SAR_RXB        18
-+#define AVALANCHE_MAC_TXA            19
-+#define AVALANCHE_MAC_RXA            20
-+#define AVALANCHE_DSP_SUB0           21
-+#define AVALANCHE_DSP_SUB1           22
-+#define AVALANCHE_DES_INT            23
++/*  Line #11  Reserved               */
++/*  Line #12  Reserved               */
++/*  Line #13  Reserved               */
++/*  Line #14  Reserved               */
++#define AVALANCHE_ATM_SAR_INT        15
++/*  Line #16  Reserved               */
++/*  Line #17  Reserved               */
++/*  Line #18  Reserved               */
++#define AVALANCHE_MAC0_INT           19
++/*  Line #20  Reserved               */
++#define AVALANCHE_VLYNQ0_INT         21
++#define AVALANCHE_CODEC_WAKE_INT     22
++/*  Line #23  Reserved               */

 +#define AVALANCHE_USB_INT            24
 +#define AVALANCHE_USB_INT            24

-+#define AVALANCHE_PCI_INTA           25
-+#define AVALANCHE_PCI_INTB           26
-+#define AVALANCHE_PCI_INTC           27
-+/*  Line #28  Reserved               */
++#define AVALANCHE_VLYNQ1_INT         25
++/*  Line #26  Reserved               */
++/*  Line #27  Reserved               */
++#define AVALANCHE_MAC1_INT           28

 +#define AVALANCHE_I2CM_INT           29
 +#define AVALANCHE_PDMA_INT2          30
 +#define AVALANCHE_PDMA_INT3          31
 +#define AVALANCHE_I2CM_INT           29
 +#define AVALANCHE_PDMA_INT2          30
 +#define AVALANCHE_PDMA_INT3          31

-+#define AVALANCHE_CODEC              32
-+#define AVALANCHE_MAC_TXB            33
-+#define AVALANCHE_MAC_RXB            34
++/*  Line #32  Reserved               */
++/*  Line #33  Reserved               */
++/*  Line #34  Reserved               */

 +/*  Line #35  Reserved               */
 +/*  Line #36  Reserved               */
 +/*  Line #35  Reserved               */
 +/*  Line #36  Reserved               */

-+/*  Line #37  Reserved               */
-+/*  Line #38  Reserved               */
-+/*  Line #39  Reserved               */
-+
-+#define DEBUG_MISSED_INTS 1
-+
-+#ifdef DEBUG_MISSED_INTS
-+struct debug_missed_int
-+{
-+  unsigned int atm_sar_txa;
-+  unsigned int atm_sar_txb;
-+  unsigned int atm_sar_rxa;
-+  unsigned int atm_sar_rxb;
-+  unsigned int mac_txa;
-+  unsigned int mac_rxa;
-+  unsigned int mac_txb;
-+  unsigned int mac_rxb;
-+};
-+#endif /* DEBUG_MISSED_INTS */
++#define AVALANCHE_VDMA_VT_RX_INT     37
++#define AVALANCHE_VDMA_VT_TX_INT     38
++#define AVALANCHE_ADSLSS_INT         39

 +
 +/*-----------------------------------*/
 +
 +/*-----------------------------------*/

-+/* Avalanche Secondary Interrupts    */
++/* Sangam Secondary Interrupts    */

 +/*-----------------------------------*/
 +#define PRIMARY_INTS                 40
 +
 +/*-----------------------------------*/
 +#define PRIMARY_INTS                 40
 +

-+#define AVALANCHE_HDLC_STATUS        (0 + PRIMARY_INTS)
-+#define AVALANCHE_SAR_STATUS         (1 + PRIMARY_INTS)
-+/*  Line #02  Reserved               */
-+#define AVALANCHE_ETH_MACA_LNK_CHG   (3 + PRIMARY_INTS)
-+#define AVALANCHE_ETH_MACA_MGT       (4 + PRIMARY_INTS)
-+#define AVALANCHE_PCI_STATUS_INT     (5 + PRIMARY_INTS)
-+/*  Line #06  Reserved               */
-+#define AVALANCHE_EXTERN_MEM_INT     (7 + PRIMARY_INTS)
-+#define AVALANCHE_DSP_A_DOG          (8 + PRIMARY_INTS)
-+#define AVALANCHE_DSP_B_DOG          (9 + PRIMARY_INTS)
-+/*  Line #10-#20 Reserved            */
-+#define AVALANCHE_ETH_MACB_LNK_CHG   (21 + PRIMARY_INTS)
-+#define AVALANCHE_ETH_MACB_MGT       (22 + PRIMARY_INTS)
-+#define AVALANCHE_AAL2_STATUS        (23 + PRIMARY_INTS)
-+/*  Line #24-#31 Reserved            */
-+
-+#define AVALANCHEINT_UART0        LNXINTNUM(AVALANCHE_UART0_INT)
-+#define AVALANCHEINT_UART1        LNXINTNUM(AVALANCHE_UART1_INT)
-+#define SEADINT_UART0    3   /* TTYS0 interrupt on SEAD */
-+#define SEADINT_UART1    4   /* TTYS1 interrupt on SEAD */
-+
-+#ifdef JIMK_INT_CTRLR
-+/*-----------------------------------*/
-+/* Jim Kennedy's Interrupt Controller*/
-+/*-----------------------------------*/
-+
-+/* to clear the interrupt write the bit back to the status reg */
-+
-+#define JIMK_INT_STATUS (*(volatile unsigned int *)(0xA8612400))
-+#define JIMK_INT_MASK   (*(volatile unsigned int *)(0xA8612404))
-+#define JIMK_SAR_STATUS  (1<<0)
-+#define JIMK_SAR_TX_A    (1<<1)
-+#define JIMK_SAR_TX_B    (1<<2)
-+#define JIMK_SAR_RX_A    (1<<3)
-+#define JIMK_SAR_RX_B    (1<<4)
-+#define JIMK_AAL2_STATUS (1<<5)
-+#define JIMK_UART0_INT   (1<<11)
-+
-+#ifdef SEAD_USB_DEVELOPMENT
-+#define JIMK_USB_INT     (1<<0)
-+#endif /* SEAD_USB_DEVELOPMENT */
++#define EMIF_INT                    (7 + PRIMARY_INTS)

 +
 +

-+#endif /* JIMK_INT_CTRLR */

 +
 +extern void avalanche_int_set(int channel, int line);
 +
 +extern void avalanche_int_set(int channel, int line);

-+extern void avalancheint_init(void);
-+
-+
-+#endif /* !(_MIPS_AVALANCHEINT_H) */

 +
 +
 +
 +

-+
-+
-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_intc.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche_intc.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche_intc.h     2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,273 @@
-+ /*
-+ * Nitin Dhingra, iamnd@ti.com
-+ * Copyright (C) 2000 Texas Instruments Inc.
++#endif /* _AVALANCHE_INTC_H */
+diff -urN linux.old/include/asm-mips/ar7/avalanche_int.h linux.dev/include/asm-mips/ar7/avalanche_int.h
+--- linux.old/include/asm-mips/ar7/avalanche_int.h     1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/avalanche_int.h     2005-07-07 04:39:14.431224000 +0200
+@@ -0,0 +1,298 @@
++/* $Id$

 + *
 + *

++ * avalancheint.h
++ *
++ * Jeff Harrell, jharrell@ti.com
++ * Copyright (C) 2000,2001 Texas Instruments , Inc.

 + *
 + * ########################################################################
 + *
 + *
 + * ########################################################################
 + *


@@ -4057,26 +4039,25 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_intc.h linux-2.4.30.dev/in
 + *
 + * ########################################################################
 + *
 + *
 + * ########################################################################
 + *

-+ * Defines of the Sead board specific address-MAP, registers, etc.
++ * Defines for the AVALANCHE interrupt controller.

 + *
 + */
 + *
 + */

-+#ifndef _AVALANCHE_INTC_H
-+#define _AVALANCHE_INTC_H
++#ifndef _MIPS_AVALANCHEINT_H
++#define _MIPS_AVALANCHEINT_H

 +
 +

-+#define MIPS_EXCEPTION_OFFSET 8
++#include <linux/config.h>

 +
 +

-+/******************************************************************************
-+ Avalanche Interrupt number
-+******************************************************************************/
++/* Avalanche Interrupt number */

 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)

-+
-+/*******************************************************************************
-+*Linux Interrupt number
-+*******************************************************************************/
++/* Linux Interrupt number     */ 

 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)

++/* Number of IRQ supported on hw interrupt 0. */

 +
 +

++//#define SEADINT_UART0      3            /* TTYS0 interrupt on SEAD */
++//#define SEADINT_UART1      4            /* TTYS1 interrupt on SEAD */

 +
 +
 +
 +

++#define MIPS_EXCEPTION_OFFSET 8

 +#define AVALANCHE_INT_END_PRIMARY      (40 + MIPS_EXCEPTION_OFFSET)
 +#define AVALANCHE_INT_END_SECONDARY    (32 + MIPS_EXCEPTION_OFFSET)
 +
 +#define AVALANCHE_INT_END_PRIMARY      (40 + MIPS_EXCEPTION_OFFSET)
 +#define AVALANCHE_INT_END_SECONDARY    (32 + MIPS_EXCEPTION_OFFSET)
 +


@@ -4084,127 +4065,91 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_intc.h linux-2.4.30.dev/in
 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
 +
 +
 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
 +
 +

-+#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
-+                          AVINTNUM(AVALANCHE_INT_END_SECONDARY)  \
-+                                    + MIPS_EXCEPTION_OFFSET - 1) /* Suraj, check */
-+
-+
-+/*
-+ * Avalanche interrupt controller register base (primary)
-+ */
-+#define AVALANCHE_ICTRL_REGS_BASE  AVALANCHE_INTC_BASE
-+
-+/******************************************************************************
-+ * Avalanche exception controller register base (secondary)
-+ ******************************************************************************/
-+#define AVALANCHE_ECTRL_REGS_BASE  (AVALANCHE_ICTRL_REGS_BASE + 0x80)
-+
-+
-+/******************************************************************************
-+ *  Avalanche Interrupt pacing register base (secondary)
-+ ******************************************************************************/
-+#define AVALANCHE_IPACE_REGS_BASE  (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
-+
-+
-+
-+/******************************************************************************
-+ * Avalanche Interrupt Channel Control register base
-+ *****************************************************************************/
-+#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
-+
++#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + AVINTNUM(AVALANCHE_INT_END_SECONDARY)  \
++                     + MIPS_EXCEPTION_OFFSET - 1)

 +
 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
 +{
 +
 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
 +{

-+  volatile unsigned long intsr1;    /* Interrupt Status/Set Register 1   0x00 */
-+  volatile unsigned long intsr2;    /* Interrupt Status/Set Register 2   0x04 */
-+  volatile unsigned long unused1;                                      /*0x08 */
-+  volatile unsigned long unused2;                                      /*0x0C */
-+  volatile unsigned long intcr1;    /* Interrupt Clear Register 1        0x10 */
-+  volatile unsigned long intcr2;    /* Interrupt Clear Register 2        0x14 */
-+  volatile unsigned long unused3;                                      /*0x18 */
-+  volatile unsigned long unused4;                                      /*0x1C */
-+  volatile unsigned long intesr1;   /* Interrupt Enable (Set) Register 1 0x20 */
-+  volatile unsigned long intesr2;   /* Interrupt Enable (Set) Register 2 0x24 */
-+  volatile unsigned long unused5;                                      /*0x28 */
-+  volatile unsigned long unused6;                                      /*0x2C */
-+  volatile unsigned long intecr1;   /* Interrupt Enable Clear Register 1 0x30 */
-+  volatile unsigned long intecr2;   /* Interrupt Enable Clear Register 2 0x34 */
-+  volatile unsigned long unused7;                                     /* 0x38 */
-+  volatile unsigned long unused8;                                     /* 0x3c */
-+  volatile unsigned long pintir;    /* Priority Interrupt Index Register 0x40 */
-+  volatile unsigned long intmsr;    /* Priority Interrupt Mask Index Reg 0x44 */
-+  volatile unsigned long unused9;                                     /* 0x48 */
-+  volatile unsigned long unused10;                                    /* 0x4C */
-+  volatile unsigned long intpolr1;  /* Interrupt Polarity Mask register 10x50 */
-+  volatile unsigned long intpolr2;  /* Interrupt Polarity Mask register 20x54 */
-+  volatile unsigned long unused11;                                    /* 0x58 */
-+  volatile unsigned long unused12;                                   /*0x5C */
-+  volatile unsigned long inttypr1;  /* Interrupt Type     Mask register 10x60 */
-+  volatile unsigned long inttypr2;  /* Interrupt Type     Mask register 20x64 */
++  volatile unsigned long intsr1;    /* Interrupt Status/Set Register 1   */ /* 0x00 */      
++  volatile unsigned long intsr2;    /* Interrupt Status/Set Register 2   */ /* 0x04 */
++  volatile unsigned long unused1;                                           /* 0x08 */
++  volatile unsigned long unused2;                                           /* 0x0C */
++  volatile unsigned long intcr1;    /* Interrupt Clear Register 1        */ /* 0x10 */
++  volatile unsigned long intcr2;    /* Interrupt Clear Register 2        */ /* 0x14 */
++  volatile unsigned long unused3;                                           /* 0x18 */
++  volatile unsigned long unused4;                                           /* 0x1C */
++  volatile unsigned long intesr1;   /* Interrupt Enable (Set) Register 1 */ /* 0x20 */
++  volatile unsigned long intesr2;   /* Interrupt Enable (Set) Register 2 */ /* 0x24 */
++  volatile unsigned long unused5;                                           /* 0x28 */
++  volatile unsigned long unused6;                                           /* 0x2C */
++  volatile unsigned long intecr1;   /* Interrupt Enable Clear Register 1 */ /* 0x30 */
++  volatile unsigned long intecr2;   /* Interrupt Enable Clear Register 2 */ /* 0x34 */
++  volatile unsigned long unused7;                                           /* 0x38 */
++  volatile unsigned long unused8;                                           /* 0x3c */
++  volatile unsigned long pintir;    /* Priority Interrupt Index Register */ /* 0x40 */
++  volatile unsigned long intmsr;    /* Priority Interrupt Mask Index Reg.*/ /* 0x44 */
++  volatile unsigned long unused9;                                           /* 0x48 */
++  volatile unsigned long unused10;                                          /* 0x4C */
++  volatile unsigned long intpolr1;  /* Interrupt Polarity Mask register 1*/ /* 0x50 */
++  volatile unsigned long intpolr2;  /* Interrupt Polarity Mask register 2*/ /* 0x54 */

 +};
 +
 +struct avalanche_exctrl_regs   /* Avalanche Exception control registers */
 +{
 +};
 +
 +struct avalanche_exctrl_regs   /* Avalanche Exception control registers */
 +{

-+  volatile unsigned long exsr;      /* Exceptions Status/Set register    0x80 */
-+  volatile unsigned long reserved;                                     /*0x84 */
-+  volatile unsigned long excr;      /* Exceptions Clear Register         0x88 */
-+  volatile unsigned long reserved1;                                    /*0x8c */
-+  volatile unsigned long exiesr;    /* Exceptions Interrupt Enable (set) 0x90 */
-+  volatile unsigned long reserved2;                                    /*0x94 */
-+  volatile unsigned long exiecr;    /* Exceptions Interrupt Enable(clear)0x98 */
++  volatile unsigned long exsr;      /* Exceptions Status/Set register    */  /* 0x80 */
++  volatile unsigned long reserved;                                           /* 0x84 */
++  volatile unsigned long excr;      /* Exceptions Clear Register         */  /* 0x88 */
++  volatile unsigned long reserved1;                                          /* 0x8c */
++  volatile unsigned long exiesr;    /* Exceptions Interrupt Enable (set) */  /* 0x90 */
++  volatile unsigned long reserved2;                                          /* 0x94 */
++  volatile unsigned long exiecr;    /* Exceptions Interrupt Enable (clear)*/ /* 0x98 */

 +};
 +};

-+struct avalanche_ipace_regs
-+{

 +
 +

-+  volatile unsigned long ipacep;    /* Interrupt pacing register         0xa0 */
-+  volatile unsigned long ipacemap;  /*Interrupt Pacing Map Register      0xa4 */
-+  volatile unsigned long ipacemax;  /*Interrupt Pacing Max Register      0xa8 */
-+};

 +struct avalanche_channel_int_number
 +{
 +struct avalanche_channel_int_number
 +{

-+  volatile unsigned long cintnr0;   /* Channel Interrupt Number Register0x200 */
-+  volatile unsigned long cintnr1;   /* Channel Interrupt Number Register0x204 */
-+  volatile unsigned long cintnr2;   /* Channel Interrupt Number Register0x208 */
-+  volatile unsigned long cintnr3;   /* Channel Interrupt Number Register0x20C */
-+  volatile unsigned long cintnr4;   /* Channel Interrupt Number Register0x210 */
-+  volatile unsigned long cintnr5;   /* Channel Interrupt Number Register0x214 */
-+  volatile unsigned long cintnr6;   /* Channel Interrupt Number Register0x218 */
-+  volatile unsigned long cintnr7;   /* Channel Interrupt Number Register0x21C */
-+  volatile unsigned long cintnr8;   /* Channel Interrupt Number Register0x220 */
-+  volatile unsigned long cintnr9;   /* Channel Interrupt Number Register0x224 */
-+  volatile unsigned long cintnr10;  /* Channel Interrupt Number Register0x228 */
-+  volatile unsigned long cintnr11;  /* Channel Interrupt Number Register0x22C */
-+  volatile unsigned long cintnr12;  /* Channel Interrupt Number Register0x230 */
-+  volatile unsigned long cintnr13;  /* Channel Interrupt Number Register0x234 */
-+  volatile unsigned long cintnr14;  /* Channel Interrupt Number Register0x238 */
-+  volatile unsigned long cintnr15;  /* Channel Interrupt Number Register0x23C */
-+  volatile unsigned long cintnr16;  /* Channel Interrupt Number Register0x240 */
-+  volatile unsigned long cintnr17;  /* Channel Interrupt Number Register0x244 */
-+  volatile unsigned long cintnr18;  /* Channel Interrupt Number Register0x248 */
-+  volatile unsigned long cintnr19;  /* Channel Interrupt Number Register0x24C */
-+  volatile unsigned long cintnr20;  /* Channel Interrupt Number Register0x250 */
-+  volatile unsigned long cintnr21;  /* Channel Interrupt Number Register0x254 */
-+  volatile unsigned long cintnr22;  /* Channel Interrupt Number Register0x358 */
-+  volatile unsigned long cintnr23;  /* Channel Interrupt Number Register0x35C */
-+  volatile unsigned long cintnr24;  /* Channel Interrupt Number Register0x260 */
-+  volatile unsigned long cintnr25;  /* Channel Interrupt Number Register0x264 */
-+  volatile unsigned long cintnr26;  /* Channel Interrupt Number Register0x268 */
-+  volatile unsigned long cintnr27;  /* Channel Interrupt Number Register0x26C */
-+  volatile unsigned long cintnr28;  /* Channel Interrupt Number Register0x270 */
-+  volatile unsigned long cintnr29;  /* Channel Interrupt Number Register0x274 */
-+  volatile unsigned long cintnr30;  /* Channel Interrupt Number Register0x278 */
-+  volatile unsigned long cintnr31;  /* Channel Interrupt Number Register0x27C */
-+  volatile unsigned long cintnr32;  /* Channel Interrupt Number Register0x280 */
-+  volatile unsigned long cintnr33;  /* Channel Interrupt Number Register0x284 */
-+  volatile unsigned long cintnr34;  /* Channel Interrupt Number Register0x288 */
-+  volatile unsigned long cintnr35;  /* Channel Interrupt Number Register0x28C */
-+  volatile unsigned long cintnr36;  /* Channel Interrupt Number Register0x290 */
-+  volatile unsigned long cintnr37;  /* Channel Interrupt Number Register0x294 */
-+  volatile unsigned long cintnr38;  /* Channel Interrupt Number Register0x298 */
-+  volatile unsigned long cintnr39;  /* Channel Interrupt Number Register0x29C */
++  volatile unsigned long cintnr0;   /* Channel Interrupt Number Register */  /* 0x200 */
++  volatile unsigned long cintnr1;   /* Channel Interrupt Number Register */  /* 0x204 */
++  volatile unsigned long cintnr2;   /* Channel Interrupt Number Register */  /* 0x208 */
++  volatile unsigned long cintnr3;   /* Channel Interrupt Number Register */  /* 0x20C */
++  volatile unsigned long cintnr4;   /* Channel Interrupt Number Register */  /* 0x210 */
++  volatile unsigned long cintnr5;   /* Channel Interrupt Number Register */  /* 0x214 */
++  volatile unsigned long cintnr6;   /* Channel Interrupt Number Register */  /* 0x218 */
++  volatile unsigned long cintnr7;   /* Channel Interrupt Number Register */  /* 0x21C */
++  volatile unsigned long cintnr8;   /* Channel Interrupt Number Register */  /* 0x220 */
++  volatile unsigned long cintnr9;   /* Channel Interrupt Number Register */  /* 0x224 */
++  volatile unsigned long cintnr10;  /* Channel Interrupt Number Register */  /* 0x228 */
++  volatile unsigned long cintnr11;  /* Channel Interrupt Number Register */  /* 0x22C */
++  volatile unsigned long cintnr12;  /* Channel Interrupt Number Register */  /* 0x230 */
++  volatile unsigned long cintnr13;  /* Channel Interrupt Number Register */  /* 0x234 */
++  volatile unsigned long cintnr14;  /* Channel Interrupt Number Register */  /* 0x238 */
++  volatile unsigned long cintnr15;  /* Channel Interrupt Number Register */  /* 0x23C */
++  volatile unsigned long cintnr16;  /* Channel Interrupt Number Register */  /* 0x240 */
++  volatile unsigned long cintnr17;  /* Channel Interrupt Number Register */  /* 0x244 */
++  volatile unsigned long cintnr18;  /* Channel Interrupt Number Register */  /* 0x248 */
++  volatile unsigned long cintnr19;  /* Channel Interrupt Number Register */  /* 0x24C */
++  volatile unsigned long cintnr20;  /* Channel Interrupt Number Register */  /* 0x250 */
++  volatile unsigned long cintnr21;  /* Channel Interrupt Number Register */  /* 0x254 */
++  volatile unsigned long cintnr22;  /* Channel Interrupt Number Register */  /* 0x358 */
++  volatile unsigned long cintnr23;  /* Channel Interrupt Number Register */  /* 0x35C */
++  volatile unsigned long cintnr24;  /* Channel Interrupt Number Register */  /* 0x260 */
++  volatile unsigned long cintnr25;  /* Channel Interrupt Number Register */  /* 0x264 */
++  volatile unsigned long cintnr26;  /* Channel Interrupt Number Register */  /* 0x268 */
++  volatile unsigned long cintnr27;  /* Channel Interrupt Number Register */  /* 0x26C */
++  volatile unsigned long cintnr28;  /* Channel Interrupt Number Register */  /* 0x270 */
++  volatile unsigned long cintnr29;  /* Channel Interrupt Number Register */  /* 0x274 */
++  volatile unsigned long cintnr30;  /* Channel Interrupt Number Register */  /* 0x278 */
++  volatile unsigned long cintnr31;  /* Channel Interrupt Number Register */  /* 0x27C */
++  volatile unsigned long cintnr32;  /* Channel Interrupt Number Register */  /* 0x280 */
++  volatile unsigned long cintnr33;  /* Channel Interrupt Number Register */  /* 0x284 */
++  volatile unsigned long cintnr34;  /* Channel Interrupt Number Register */  /* 0x288 */
++  volatile unsigned long cintnr35;  /* Channel Interrupt Number Register */  /* 0x28C */
++  volatile unsigned long cintnr36;  /* Channel Interrupt Number Register */  /* 0x290 */
++  volatile unsigned long cintnr37;  /* Channel Interrupt Number Register */  /* 0x294 */
++  volatile unsigned long cintnr38;  /* Channel Interrupt Number Register */  /* 0x298 */
++  volatile unsigned long cintnr39;  /* Channel Interrupt Number Register */  /* 0x29C */

 +};
 +
 +};
 +

-+struct avalanche_interrupt_line_to_channel
++struct avalanche_interrupt_line_to_channel 

 +{
 +  unsigned long int_line0;    /* Start of primary interrupts */
 +  unsigned long int_line1;
 +{
 +  unsigned long int_line0;    /* Start of primary interrupts */
 +  unsigned long int_line1;


@@ -4217,100 +4162,160 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_intc.h linux-2.4.30.dev/in
 +  unsigned long int_line8;
 +  unsigned long int_line9;
 +  unsigned long int_line10;
 +  unsigned long int_line8;
 +  unsigned long int_line9;
 +  unsigned long int_line10;

-+  unsigned long int_line11;
-+  unsigned long int_line12;
-+  unsigned long int_line13;
-+  unsigned long int_line14;
-+  unsigned long int_line15;
-+  unsigned long int_line16;
-+  unsigned long int_line17;
-+  unsigned long int_line18;
-+  unsigned long int_line19;
-+  unsigned long int_line20;
++  unsigned long int_line11; 
++  unsigned long int_line12; 
++  unsigned long int_line13; 
++  unsigned long int_line14; 
++  unsigned long int_line15; 
++  unsigned long int_line16; 
++  unsigned long int_line17; 
++  unsigned long int_line18; 
++  unsigned long int_line19; 
++  unsigned long int_line20; 

 +  unsigned long int_line21;
 +  unsigned long int_line21;

-+  unsigned long int_line22;
-+  unsigned long int_line23;
-+  unsigned long int_line24;
-+  unsigned long int_line25;
-+  unsigned long int_line26;
-+  unsigned long int_line27;
-+  unsigned long int_line28;
-+  unsigned long int_line29;
-+  unsigned long int_line30;
-+  unsigned long int_line31;
++  unsigned long int_line22; 
++  unsigned long int_line23; 
++  unsigned long int_line24; 
++  unsigned long int_line25; 
++  unsigned long int_line26; 
++  unsigned long int_line27; 
++  unsigned long int_line28; 
++  unsigned long int_line29; 
++  unsigned long int_line30; 
++  unsigned long int_line31; 

 +  unsigned long int_line32;
 +  unsigned long int_line32;

-+  unsigned long int_line33;
-+  unsigned long int_line34;
-+  unsigned long int_line35;
-+  unsigned long int_line36;
-+  unsigned long int_line37;
-+  unsigned long int_line38;
-+  unsigned long int_line39;
++  unsigned long int_line33; 
++  unsigned long int_line34; 
++  unsigned long int_line35; 
++  unsigned long int_line36; 
++  unsigned long int_line37; 
++  unsigned long int_line38; 
++  unsigned long int_line39;  

 +};
 +
 +};
 +

-+
-+/* Interrupt Line #'s  (Sangam peripherals) */
++/* Interrupt Line #'s  (Avalanche peripherals) */

 +
 +/*------------------------------*/
 +
 +/*------------------------------*/

-+/* Sangam primary interrupts */
++/* Avalanche primary interrupts */

 +/*------------------------------*/
 +/*------------------------------*/

-+

 +#define UNIFIED_SECONDARY_INTERRUPT  0
 +#define AVALANCHE_EXT_INT_0          1
 +#define AVALANCHE_EXT_INT_1          2
 +#define UNIFIED_SECONDARY_INTERRUPT  0
 +#define AVALANCHE_EXT_INT_0          1
 +#define AVALANCHE_EXT_INT_1          2

-+/*  Line #3  Reserved               */
-+/*  Line #4  Reserved               */
++#define AVALANCHE_EXT_INT_2          3
++#define AVALANCHE_EXT_INT_3          4

 +#define AVALANCHE_TIMER_0_INT        5
 +#define AVALANCHE_TIMER_1_INT        6
 +#define AVALANCHE_UART0_INT          7
 +#define AVALANCHE_UART1_INT          8
 +#define AVALANCHE_PDMA_INT0          9
 +#define AVALANCHE_PDMA_INT1          10
 +#define AVALANCHE_TIMER_0_INT        5
 +#define AVALANCHE_TIMER_1_INT        6
 +#define AVALANCHE_UART0_INT          7
 +#define AVALANCHE_UART1_INT          8
 +#define AVALANCHE_PDMA_INT0          9
 +#define AVALANCHE_PDMA_INT1          10

-+/*  Line #11  Reserved               */
-+/*  Line #12  Reserved               */
-+/*  Line #13  Reserved               */
-+/*  Line #14  Reserved               */
-+#define AVALANCHE_ATM_SAR_INT        15
-+/*  Line #16  Reserved               */
-+/*  Line #17  Reserved               */
-+/*  Line #18  Reserved               */
-+#define AVALANCHE_MAC0_INT           19
-+/*  Line #20  Reserved               */
-+#define AVALANCHE_VLYNQ0_INT         21
-+#define AVALANCHE_CODEC_WAKE_INT     22
-+/*  Line #23  Reserved               */
++#define AVALANCHE_HDLC_TXA           11
++#define AVALANCHE_HDLC_TXB           12
++#define AVALANCHE_HDLC_RXA           13
++#define AVALANCHE_HDLC_RXB           14
++#define AVALANCHE_ATM_SAR_TXA        15
++#define AVALANCHE_ATM_SAR_TXB        16
++#define AVALANCHE_ATM_SAR_RXA        17
++#define AVALANCHE_ATM_SAR_RXB        18
++#define AVALANCHE_MAC_TXA            19
++#define AVALANCHE_MAC_RXA            20
++#define AVALANCHE_DSP_SUB0           21
++#define AVALANCHE_DSP_SUB1           22
++#define AVALANCHE_DES_INT            23

 +#define AVALANCHE_USB_INT            24
 +#define AVALANCHE_USB_INT            24

-+#define AVALANCHE_VLYNQ1_INT         25
-+/*  Line #26  Reserved               */
-+/*  Line #27  Reserved               */
-+#define AVALANCHE_MAC1_INT           28
++#define AVALANCHE_PCI_INTA           25
++#define AVALANCHE_PCI_INTB           26
++#define AVALANCHE_PCI_INTC           27
++/*  Line #28  Reserved               */

 +#define AVALANCHE_I2CM_INT           29
 +#define AVALANCHE_PDMA_INT2          30
 +#define AVALANCHE_PDMA_INT3          31
 +#define AVALANCHE_I2CM_INT           29
 +#define AVALANCHE_PDMA_INT2          30
 +#define AVALANCHE_PDMA_INT3          31

-+/*  Line #32  Reserved               */
-+/*  Line #33  Reserved               */
-+/*  Line #34  Reserved               */
++#define AVALANCHE_CODEC              32
++#define AVALANCHE_MAC_TXB            33
++#define AVALANCHE_MAC_RXB            34

 +/*  Line #35  Reserved               */
 +/*  Line #36  Reserved               */
 +/*  Line #35  Reserved               */
 +/*  Line #36  Reserved               */

-+#define AVALANCHE_VDMA_VT_RX_INT     37
-+#define AVALANCHE_VDMA_VT_TX_INT     38
-+#define AVALANCHE_ADSLSS_INT         39
++/*  Line #37  Reserved               */
++/*  Line #38  Reserved               */
++/*  Line #39  Reserved               */
++
++#define DEBUG_MISSED_INTS 1
++
++#ifdef DEBUG_MISSED_INTS
++struct debug_missed_int
++{
++  unsigned int atm_sar_txa;
++  unsigned int atm_sar_txb;
++  unsigned int atm_sar_rxa;
++  unsigned int atm_sar_rxb;
++  unsigned int mac_txa;
++  unsigned int mac_rxa;
++  unsigned int mac_txb;
++  unsigned int mac_rxb;
++};
++#endif /* DEBUG_MISSED_INTS */

 +
 +/*-----------------------------------*/
 +
 +/*-----------------------------------*/

-+/* Sangam Secondary Interrupts    */
++/* Avalanche Secondary Interrupts    */

 +/*-----------------------------------*/
 +#define PRIMARY_INTS                 40
 +
 +/*-----------------------------------*/
 +#define PRIMARY_INTS                 40
 +

-+#define EMIF_INT                    (7 + PRIMARY_INTS)
++#define AVALANCHE_HDLC_STATUS        (0 + PRIMARY_INTS)
++#define AVALANCHE_SAR_STATUS         (1 + PRIMARY_INTS)
++/*  Line #02  Reserved               */
++#define AVALANCHE_ETH_MACA_LNK_CHG   (3 + PRIMARY_INTS)
++#define AVALANCHE_ETH_MACA_MGT       (4 + PRIMARY_INTS)
++#define AVALANCHE_PCI_STATUS_INT     (5 + PRIMARY_INTS)
++/*  Line #06  Reserved               */
++#define AVALANCHE_EXTERN_MEM_INT     (7 + PRIMARY_INTS)
++#define AVALANCHE_DSP_A_DOG          (8 + PRIMARY_INTS)
++#define AVALANCHE_DSP_B_DOG          (9 + PRIMARY_INTS)
++/*  Line #10-#20 Reserved            */
++#define AVALANCHE_ETH_MACB_LNK_CHG   (21 + PRIMARY_INTS)
++#define AVALANCHE_ETH_MACB_MGT       (22 + PRIMARY_INTS)
++#define AVALANCHE_AAL2_STATUS        (23 + PRIMARY_INTS)
++/*  Line #24-#31 Reserved            */
++
++#define AVALANCHEINT_UART0        LNXINTNUM(AVALANCHE_UART0_INT)
++#define AVALANCHEINT_UART1        LNXINTNUM(AVALANCHE_UART1_INT)
++#define SEADINT_UART0    3   /* TTYS0 interrupt on SEAD */
++#define SEADINT_UART1    4   /* TTYS1 interrupt on SEAD */
++
++#ifdef JIMK_INT_CTRLR
++/*-----------------------------------*/
++/* Jim Kennedy's Interrupt Controller*/
++/*-----------------------------------*/
++
++/* to clear the interrupt write the bit back to the status reg */
++
++#define JIMK_INT_STATUS (*(volatile unsigned int *)(0xA8612400))
++#define JIMK_INT_MASK   (*(volatile unsigned int *)(0xA8612404))
++#define JIMK_SAR_STATUS  (1<<0)
++#define JIMK_SAR_TX_A    (1<<1)
++#define JIMK_SAR_TX_B    (1<<2)
++#define JIMK_SAR_RX_A    (1<<3)
++#define JIMK_SAR_RX_B    (1<<4)
++#define JIMK_AAL2_STATUS (1<<5)
++#define JIMK_UART0_INT   (1<<11)
++
++#ifdef SEAD_USB_DEVELOPMENT
++#define JIMK_USB_INT     (1<<0)
++#endif /* SEAD_USB_DEVELOPMENT */

 +
 +

++#endif /* JIMK_INT_CTRLR */

 +
 +extern void avalanche_int_set(int channel, int line);
 +
 +extern void avalanche_int_set(int channel, int line);

++extern void avalancheint_init(void);

 +
 +
 +
 +

-+#endif /* _AVALANCHE_INTC_H */
-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_prom.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche_prom.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche_prom.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche_prom.h     2005-06-14 15:36:59.000000000 +0200
++#endif /* !(_MIPS_AVALANCHEINT_H) */
++
++
++
++
+diff -urN linux.old/include/asm-mips/ar7/avalanche_prom.h linux.dev/include/asm-mips/ar7/avalanche_prom.h
+--- linux.old/include/asm-mips/ar7/avalanche_prom.h    1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/avalanche_prom.h    2005-07-07 04:39:14.431224000 +0200

 @@ -0,0 +1,54 @@
 +/* $Id$
 + *
 @@ -0,0 +1,54 @@
 +/* $Id$
 + *


@@ -4366,9 +4371,9 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_prom.h linux-2.4.30.dev/in
 +
 +#endif /* !(_MIPS_PROM_H) */
 +
 +
 +#endif /* !(_MIPS_PROM_H) */
 +

-diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_regs.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche_regs.h
---- linux-2.4.30/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche_regs.h     2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm-mips/ar7/avalanche_regs.h
+--- linux.old/include/asm-mips/ar7/avalanche_regs.h    1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/avalanche_regs.h    2005-07-07 04:39:14.433224000 +0200

 @@ -0,0 +1,567 @@
 +/* 
 + *  $Id$
 @@ -0,0 +1,567 @@
 +/* 
 + *  $Id$


@@ -4937,9 +4942,55 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_regs.h linux-2.4.30.dev/in
 +
 +
 +
 +
 +
 +

-diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx.h linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx.h
---- linux-2.4.30/include/asm-mips/ar7/tnetd73xx.h      1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx.h  2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_err.h linux.dev/include/asm-mips/ar7/tnetd73xx_err.h
+--- linux.old/include/asm-mips/ar7/tnetd73xx_err.h     1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h     2005-07-07 04:39:14.434224000 +0200
+@@ -0,0 +1,42 @@
++/******************************************************************************
++ * FILE PURPOSE:    TNETD73xx Error Definations Header File
++ ******************************************************************************
++ * FILE NAME:       tnetd73xx_err.h
++ *
++ * DESCRIPTION:     Error definations for TNETD73XX
++ *
++ * REVISION HISTORY:
++ * 27 Nov 02 - PSP TII  
++ *
++ * (C) Copyright 2002, Texas Instruments, Inc
++ *******************************************************************************/
++
++ 
++#ifndef __TNETD73XX_ERR_H__
++#define __TNETD73XX_ERR_H__
++
++typedef enum TNETD73XX_ERR_t
++{
++    TNETD73XX_ERR_OK        = 0,    /* OK or SUCCESS */
++    TNETD73XX_ERR_ERROR     = -1,   /* Unspecified/Generic ERROR */
++
++    /* Pointers and args */
++    TNETD73XX_ERR_INVARG        = -2,   /* Invaild argument to the call */
++    TNETD73XX_ERR_NULLPTR       = -3,   /* NULL pointer */
++    TNETD73XX_ERR_BADPTR        = -4,   /* Bad (out of mem) pointer */
++
++    /* Memory issues */
++    TNETD73XX_ERR_ALLOC_FAIL    = -10,  /* allocation failed */
++    TNETD73XX_ERR_FREE_FAIL     = -11,  /* free failed */
++    TNETD73XX_ERR_MEM_CORRUPT   = -12,  /* corrupted memory */
++    TNETD73XX_ERR_BUF_LINK      = -13,  /* buffer linking failed */
++
++    /* Device issues */
++    TNETD73XX_ERR_DEVICE_TIMEOUT    = -20,  /* device timeout on read/write */
++    TNETD73XX_ERR_DEVICE_MALFUNC    = -21,  /* device malfunction */
++
++    TNETD73XX_ERR_INVID     = -30   /* Invalid ID */
++
++} TNETD73XX_ERR;
++
++#endif /* __TNETD73XX_ERR_H__ */
+diff -urN linux.old/include/asm-mips/ar7/tnetd73xx.h linux.dev/include/asm-mips/ar7/tnetd73xx.h
+--- linux.old/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/tnetd73xx.h 2005-07-07 04:39:14.433224000 +0200

 @@ -0,0 +1,340 @@
 +/******************************************************************************
 + * FILE PURPOSE:    TNETD73xx Common Header File
 @@ -0,0 +1,340 @@
 +/******************************************************************************
 + * FILE PURPOSE:    TNETD73xx Common Header File


@@ -5281,55 +5332,9 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx.h linux-2.4.30.dev/include
 +
 +
 +#endif /* __TNETD73XX_H_ */
 +
 +
 +#endif /* __TNETD73XX_H_ */

-diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx_err.h linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx_err.h
---- linux-2.4.30/include/asm-mips/ar7/tnetd73xx_err.h  1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx_err.h      2005-06-14 15:36:59.000000000 +0200
-@@ -0,0 +1,42 @@
-+/******************************************************************************
-+ * FILE PURPOSE:    TNETD73xx Error Definations Header File
-+ ******************************************************************************
-+ * FILE NAME:       tnetd73xx_err.h
-+ *
-+ * DESCRIPTION:     Error definations for TNETD73XX
-+ *
-+ * REVISION HISTORY:
-+ * 27 Nov 02 - PSP TII  
-+ *
-+ * (C) Copyright 2002, Texas Instruments, Inc
-+ *******************************************************************************/
-+
-+ 
-+#ifndef __TNETD73XX_ERR_H__
-+#define __TNETD73XX_ERR_H__
-+
-+typedef enum TNETD73XX_ERR_t
-+{
-+    TNETD73XX_ERR_OK        = 0,    /* OK or SUCCESS */
-+    TNETD73XX_ERR_ERROR     = -1,   /* Unspecified/Generic ERROR */
-+
-+    /* Pointers and args */
-+    TNETD73XX_ERR_INVARG        = -2,   /* Invaild argument to the call */
-+    TNETD73XX_ERR_NULLPTR       = -3,   /* NULL pointer */
-+    TNETD73XX_ERR_BADPTR        = -4,   /* Bad (out of mem) pointer */
-+
-+    /* Memory issues */
-+    TNETD73XX_ERR_ALLOC_FAIL    = -10,  /* allocation failed */
-+    TNETD73XX_ERR_FREE_FAIL     = -11,  /* free failed */
-+    TNETD73XX_ERR_MEM_CORRUPT   = -12,  /* corrupted memory */
-+    TNETD73XX_ERR_BUF_LINK      = -13,  /* buffer linking failed */
-+
-+    /* Device issues */
-+    TNETD73XX_ERR_DEVICE_TIMEOUT    = -20,  /* device timeout on read/write */
-+    TNETD73XX_ERR_DEVICE_MALFUNC    = -21,  /* device malfunction */
-+
-+    TNETD73XX_ERR_INVID     = -30   /* Invalid ID */
-+
-+} TNETD73XX_ERR;
-+
-+#endif /* __TNETD73XX_ERR_H__ */
-diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx_misc.h linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx_misc.h
---- linux-2.4.30/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx_misc.h     2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_misc.h linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h
+--- linux.old/include/asm-mips/ar7/tnetd73xx_misc.h    1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h    2005-07-07 04:39:14.434224000 +0200

 @@ -0,0 +1,243 @@
 +/******************************************************************************
 + * FILE PURPOSE:    TNETD73xx Misc modules API Header
 @@ -0,0 +1,243 @@
 +/******************************************************************************
 + * FILE PURPOSE:    TNETD73xx Misc modules API Header


@@ -5574,9 +5579,9 @@ diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx_misc.h linux-2.4.30.dev/in
 +u32 tnetd73xx_get_revision(void);
 +
 +#endif /* __TNETD73XX_MISC_H__ */
 +u32 tnetd73xx_get_revision(void);
 +
 +#endif /* __TNETD73XX_MISC_H__ */

-diff -urN linux-2.4.30/include/asm-mips/io.h linux-2.4.30.dev/include/asm-mips/io.h
---- linux-2.4.30/include/asm-mips/io.h 2005-06-14 18:42:07.000000000 +0200
-+++ linux-2.4.30.dev/include/asm-mips/io.h     2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h
+--- linux.old/include/asm-mips/io.h    2005-07-07 05:38:31.416480768 +0200
++++ linux.dev/include/asm-mips/io.h    2005-07-07 04:39:14.434224000 +0200

 @@ -63,8 +63,12 @@
  #ifdef CONFIG_64BIT_PHYS_ADDR
  #define page_to_phys(page)    ((u64)(page - mem_map) << PAGE_SHIFT)
 @@ -63,8 +63,12 @@
  #ifdef CONFIG_64BIT_PHYS_ADDR
  #define page_to_phys(page)    ((u64)(page - mem_map) << PAGE_SHIFT)


@@ -5590,9 +5595,9 @@ diff -urN linux-2.4.30/include/asm-mips/io.h linux-2.4.30.dev/include/asm-mips/i
  
  #define IO_SPACE_LIMIT 0xffff
  
  
  #define IO_SPACE_LIMIT 0xffff
  

-diff -urN linux-2.4.30/include/asm-mips/irq.h linux-2.4.30.dev/include/asm-mips/irq.h
---- linux-2.4.30/include/asm-mips/irq.h        2005-06-14 18:42:07.000000000 +0200
-+++ linux-2.4.30.dev/include/asm-mips/irq.h    2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h
+--- linux.old/include/asm-mips/irq.h   2005-07-07 05:38:31.424479552 +0200
++++ linux.dev/include/asm-mips/irq.h   2005-07-07 04:39:14.435224000 +0200

 @@ -14,7 +14,12 @@
  #include <linux/config.h>
  #include <linux/linkage.h>
 @@ -14,7 +14,12 @@
  #include <linux/config.h>
  #include <linux/linkage.h>


@@ -5606,9 +5611,9 @@ diff -urN linux-2.4.30/include/asm-mips/irq.h linux-2.4.30.dev/include/asm-mips/
  
  #ifdef CONFIG_I8259
  static inline int irq_cannonicalize(int irq)
  
  #ifdef CONFIG_I8259
  static inline int irq_cannonicalize(int irq)

-diff -urN linux-2.4.30/include/asm-mips/page.h linux-2.4.30.dev/include/asm-mips/page.h
---- linux-2.4.30/include/asm-mips/page.h       2005-06-14 18:42:07.000000000 +0200
-+++ linux-2.4.30.dev/include/asm-mips/page.h   2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h
+--- linux.old/include/asm-mips/page.h  2005-07-07 05:38:31.426479248 +0200
++++ linux.dev/include/asm-mips/page.h  2005-07-07 04:39:14.435224000 +0200

 @@ -129,7 +129,11 @@
  
  #define __pa(x)               ((unsigned long) (x) - PAGE_OFFSET)
 @@ -129,7 +129,11 @@
  
  #define __pa(x)               ((unsigned long) (x) - PAGE_OFFSET)


@@ -5621,9 +5626,9 @@ diff -urN linux-2.4.30/include/asm-mips/page.h linux-2.4.30.dev/include/asm-mips
  #define VALID_PAGE(page)      ((page - mem_map) < max_mapnr)
  
  #define VM_DATA_DEFAULT_FLAGS  (VM_READ | VM_WRITE | VM_EXEC | \
  #define VALID_PAGE(page)      ((page - mem_map) < max_mapnr)
  
  #define VM_DATA_DEFAULT_FLAGS  (VM_READ | VM_WRITE | VM_EXEC | \

-diff -urN linux-2.4.30/include/asm-mips/pgtable-32.h linux-2.4.30.dev/include/asm-mips/pgtable-32.h
---- linux-2.4.30/include/asm-mips/pgtable-32.h 2005-06-14 18:42:07.000000000 +0200
-+++ linux-2.4.30.dev/include/asm-mips/pgtable-32.h     2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgtable-32.h
+--- linux.old/include/asm-mips/pgtable-32.h    2005-07-07 05:38:31.434478032 +0200
++++ linux.dev/include/asm-mips/pgtable-32.h    2005-07-07 04:39:14.435224000 +0200

 @@ -108,7 +108,18 @@
   * and a page entry and page directory to the page they refer to.
   */
 @@ -108,7 +108,18 @@
   * and a page entry and page directory to the page they refer to.
   */


@@ -5664,9 +5669,9 @@ diff -urN linux-2.4.30/include/asm-mips/pgtable-32.h linux-2.4.30.dev/include/as
  #define pte_page(x)  (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
  #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
  #else
  #define pte_page(x)  (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
  #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
  #else

-diff -urN linux-2.4.30/include/asm-mips/serial.h linux-2.4.30.dev/include/asm-mips/serial.h
---- linux-2.4.30/include/asm-mips/serial.h     2005-06-14 18:42:07.000000000 +0200
-+++ linux-2.4.30.dev/include/asm-mips/serial.h 2005-06-14 15:36:59.000000000 +0200
+diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
+--- linux.old/include/asm-mips/serial.h        2005-07-07 05:38:31.470472560 +0200
++++ linux.dev/include/asm-mips/serial.h        2005-07-07 04:39:14.436223000 +0200

 @@ -65,6 +65,15 @@
  
  #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
 @@ -65,6 +65,15 @@
  
  #define C_P(card,port) (((card)<<6|(port)<<3) + 1)


@@ -5691,3 +5696,15 @@ diff -urN linux-2.4.30/include/asm-mips/serial.h linux-2.4.30.dev/include/asm-mi
        ATLAS_SERIAL_PORT_DEFNS                 \
        AU1000_SERIAL_PORT_DEFNS                \
        COBALT_SERIAL_PORT_DEFNS                \
        ATLAS_SERIAL_PORT_DEFNS                 \
        AU1000_SERIAL_PORT_DEFNS                \
        COBALT_SERIAL_PORT_DEFNS                \

+diff -urN linux.old/Makefile linux.dev/Makefile
+--- linux.old/Makefile 2005-07-07 05:38:31.320495360 +0200
++++ linux.dev/Makefile 2005-07-07 04:39:14.501214000 +0200
+@@ -91,7 +91,7 @@
+ 
+ CPPFLAGS := -D__KERNEL__ -I$(HPATH)
+ 
+-CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
++CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
+         -fno-strict-aliasing -fno-common
+ ifndef CONFIG_FRAME_POINTER
+ CFLAGS += -fomit-frame-pointer