[ifxmips] add external irq

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@21201 3c298f89-4303-0410-b956-a3cf2f4a3e73

diff --git a/target/linux/ifxmips/files-2.6.30/arch/mips/include/asm/mach-ifxmips/ifxmips.h b/target/linux/ifxmips/files-2.6.30/arch/mips/include/asm/mach-ifxmips/ifxmips.h
index 7d5ae23..0cb909d 100644 (file)
--- a/target/linux/ifxmips/files-2.6.30/arch/mips/include/asm/mach-ifxmips/ifxmips.h
+++ b/target/linux/ifxmips/files-2.6.30/arch/mips/include/asm/mach-ifxmips/ifxmips.h
@@ -203,6 +203,23 @@
 
 #define IFXMIPS_ICU_OFFSET             (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR)
 
+/* EIU - external interrupt controller */
+
+/** EIU - base address */
+#define IFXMIPS_EIU_BASE_ADDR          0xBF101000
+/** EIU - control register */
+#define IFXMIPS_EIU_EXIN_C                     ((u32 *)(IFXMIPS_EIU_BASE_ADDR + 0x0000))
+/** EIU - interrupt node interrupt capture */
+#define IFXMIPS_EIU_INIC                       ((u32 *)(IFXMIPS_EIU_BASE_ADDR + 0x0004))
+/** EIU - interrupt node control */
+#define IFXMIPS_EIU_INC                                ((u32 *)(IFXMIPS_EIU_BASE_ADDR + 0x0008))
+/** EIU - interrupt node enable */
+#define IFXMIPS_EIU_INEN                       ((u32 *)(IFXMIPS_EIU_BASE_ADDR + 0x000C))
+/** NMI - control */
+#define IFXMIPS_NMI_CR                         ((u32 *)(IFXMIPS_EIU_BASE_ADDR + 0x00F0))
+/** NMI - status */
+#define IFXMIPS_NMI_SR                         (( u32 *)(IFXMIPS_EIU_BASE_ADDR + 0x00F4))
+
 
 /*------------ ETOP */
 

diff --git a/target/linux/ifxmips/files-2.6.30/arch/mips/include/asm/mach-ifxmips/ifxmips_irq.h b/target/linux/ifxmips/files-2.6.30/arch/mips/include/asm/mach-ifxmips/ifxmips_irq.h
index e6ca59b..3c4fb6b 100644 (file)
--- a/target/linux/ifxmips/files-2.6.30/arch/mips/include/asm/mach-ifxmips/ifxmips_irq.h
+++ b/target/linux/ifxmips/files-2.6.30/arch/mips/include/asm/mach-ifxmips/ifxmips_irq.h
@@ -72,6 +72,10 @@
 #define IFXMIPS_USB_INT                                (INT_NUM_IM4_IRL0 + 22)
 #define IFXMIPS_USB_OC_INT                     (INT_NUM_IM4_IRL0 + 23)
 
+#define IFXMIPS_EIU_IR0                                (INT_NUM_IM4_IRL0 + 30)
+#define IFXMIPS_EIU_IR1                                (INT_NUM_IM3_IRL0 + 31)
+#define IFXMIPS_EIU_IR2                                (INT_NUM_IM1_IRL0 + 26)
+
 
 extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);