kernel: backport some ssb changes to support a mac80211 update

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@26911 3c298f89-4303-0410-b956-a3cf2f4a3e73

diff --git a/target/linux/generic/patches-2.6.30/942-ssb_commit_settings_export.patch b/target/linux/generic/patches-2.6.30/942-ssb_commit_settings_export.patch
new file mode 100644 (file)
index 0000000..2bd5512
--- /dev/null
+++ b/target/linux/generic/patches-2.6.30/942-ssb_commit_settings_export.patch
@@ -0,0 +1,77 @@
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -476,30 +476,6 @@ static void ssb_pcie_mdio_write(struct s
+       pcicore_write32(pc, mdio_control, 0);
+ }
+ 
+-static void ssb_broadcast_value(struct ssb_device *dev,
+-                              u32 address, u32 data)
+-{
+-      /* This is used for both, PCI and ChipCommon core, so be careful. */
+-      BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
+-      BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
+-
+-      ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
+-      ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
+-      ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
+-      ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
+-}
+-
+-static void ssb_commit_settings(struct ssb_bus *bus)
+-{
+-      struct ssb_device *dev;
+-
+-      dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
+-      if (WARN_ON(!dev))
+-              return;
+-      /* This forces an update of the cached registers. */
+-      ssb_broadcast_value(dev, 0xFD8, 0);
+-}
+-
+ int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
+                                  struct ssb_device *dev)
+ {
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -1406,6 +1406,31 @@ error:
+ }
+ EXPORT_SYMBOL(ssb_bus_powerup);
+ 
++static void ssb_broadcast_value(struct ssb_device *dev,
++                              u32 address, u32 data)
++{
++      /* This is used for both, PCI and ChipCommon core, so be careful. */
++      BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
++      BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
++
++      ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
++      ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
++      ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
++      ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
++}
++
++void ssb_commit_settings(struct ssb_bus *bus)
++{
++      struct ssb_device *dev;
++
++      dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
++      if (WARN_ON(!dev))
++              return;
++      /* This forces an update of the cached registers. */
++      ssb_broadcast_value(dev, 0xFD8, 0);
++}
++EXPORT_SYMBOL(ssb_commit_settings);
++
+ u32 ssb_admatch_base(u32 adm)
+ {
+       u32 base = 0;
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -675,6 +675,7 @@ extern int ssb_bus_may_powerdown(struct 
+  * Otherwise static always-on powercontrol will be used. */
+ extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
+ 
++extern void ssb_commit_settings(struct ssb_bus *bus);
+ 
+ /* Various helper functions */
+ extern u32 ssb_admatch_base(u32 adm);

diff --git a/target/linux/generic/patches-2.6.31/942-ssb_commit_settings_export.patch b/target/linux/generic/patches-2.6.31/942-ssb_commit_settings_export.patch
new file mode 100644 (file)
index 0000000..2bd5512
--- /dev/null
+++ b/target/linux/generic/patches-2.6.31/942-ssb_commit_settings_export.patch
@@ -0,0 +1,77 @@
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -476,30 +476,6 @@ static void ssb_pcie_mdio_write(struct s
+       pcicore_write32(pc, mdio_control, 0);
+ }
+ 
+-static void ssb_broadcast_value(struct ssb_device *dev,
+-                              u32 address, u32 data)
+-{
+-      /* This is used for both, PCI and ChipCommon core, so be careful. */
+-      BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
+-      BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
+-
+-      ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
+-      ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
+-      ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
+-      ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
+-}
+-
+-static void ssb_commit_settings(struct ssb_bus *bus)
+-{
+-      struct ssb_device *dev;
+-
+-      dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
+-      if (WARN_ON(!dev))
+-              return;
+-      /* This forces an update of the cached registers. */
+-      ssb_broadcast_value(dev, 0xFD8, 0);
+-}
+-
+ int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
+                                  struct ssb_device *dev)
+ {
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -1406,6 +1406,31 @@ error:
+ }
+ EXPORT_SYMBOL(ssb_bus_powerup);
+ 
++static void ssb_broadcast_value(struct ssb_device *dev,
++                              u32 address, u32 data)
++{
++      /* This is used for both, PCI and ChipCommon core, so be careful. */
++      BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
++      BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
++
++      ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
++      ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
++      ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
++      ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
++}
++
++void ssb_commit_settings(struct ssb_bus *bus)
++{
++      struct ssb_device *dev;
++
++      dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
++      if (WARN_ON(!dev))
++              return;
++      /* This forces an update of the cached registers. */
++      ssb_broadcast_value(dev, 0xFD8, 0);
++}
++EXPORT_SYMBOL(ssb_commit_settings);
++
+ u32 ssb_admatch_base(u32 adm)
+ {
+       u32 base = 0;
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -675,6 +675,7 @@ extern int ssb_bus_may_powerdown(struct 
+  * Otherwise static always-on powercontrol will be used. */
+ extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
+ 
++extern void ssb_commit_settings(struct ssb_bus *bus);
+ 
+ /* Various helper functions */
+ extern u32 ssb_admatch_base(u32 adm);

diff --git a/target/linux/generic/patches-2.6.32/976-ssb_commit_settings_export.patch b/target/linux/generic/patches-2.6.32/976-ssb_commit_settings_export.patch
new file mode 100644 (file)
index 0000000..2bd5512
--- /dev/null
+++ b/target/linux/generic/patches-2.6.32/976-ssb_commit_settings_export.patch
@@ -0,0 +1,77 @@
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -476,30 +476,6 @@ static void ssb_pcie_mdio_write(struct s
+       pcicore_write32(pc, mdio_control, 0);
+ }
+ 
+-static void ssb_broadcast_value(struct ssb_device *dev,
+-                              u32 address, u32 data)
+-{
+-      /* This is used for both, PCI and ChipCommon core, so be careful. */
+-      BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
+-      BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
+-
+-      ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
+-      ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
+-      ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
+-      ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
+-}
+-
+-static void ssb_commit_settings(struct ssb_bus *bus)
+-{
+-      struct ssb_device *dev;
+-
+-      dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
+-      if (WARN_ON(!dev))
+-              return;
+-      /* This forces an update of the cached registers. */
+-      ssb_broadcast_value(dev, 0xFD8, 0);
+-}
+-
+ int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
+                                  struct ssb_device *dev)
+ {
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -1406,6 +1406,31 @@ error:
+ }
+ EXPORT_SYMBOL(ssb_bus_powerup);
+ 
++static void ssb_broadcast_value(struct ssb_device *dev,
++                              u32 address, u32 data)
++{
++      /* This is used for both, PCI and ChipCommon core, so be careful. */
++      BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
++      BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
++
++      ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
++      ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
++      ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
++      ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
++}
++
++void ssb_commit_settings(struct ssb_bus *bus)
++{
++      struct ssb_device *dev;
++
++      dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
++      if (WARN_ON(!dev))
++              return;
++      /* This forces an update of the cached registers. */
++      ssb_broadcast_value(dev, 0xFD8, 0);
++}
++EXPORT_SYMBOL(ssb_commit_settings);
++
+ u32 ssb_admatch_base(u32 adm)
+ {
+       u32 base = 0;
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -675,6 +675,7 @@ extern int ssb_bus_may_powerdown(struct 
+  * Otherwise static always-on powercontrol will be used. */
+ extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
+ 
++extern void ssb_commit_settings(struct ssb_bus *bus);
+ 
+ /* Various helper functions */
+ extern u32 ssb_admatch_base(u32 adm);

diff --git a/target/linux/generic/patches-2.6.36/942-ssb_commit_settings_export.patch b/target/linux/generic/patches-2.6.36/942-ssb_commit_settings_export.patch
new file mode 100644 (file)
index 0000000..6c68d86
--- /dev/null
+++ b/target/linux/generic/patches-2.6.36/942-ssb_commit_settings_export.patch
@@ -0,0 +1,77 @@
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -476,30 +476,6 @@ static void ssb_pcie_mdio_write(struct s
+       pcicore_write32(pc, mdio_control, 0);
+ }
+ 
+-static void ssb_broadcast_value(struct ssb_device *dev,
+-                              u32 address, u32 data)
+-{
+-      /* This is used for both, PCI and ChipCommon core, so be careful. */
+-      BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
+-      BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
+-
+-      ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
+-      ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
+-      ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
+-      ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
+-}
+-
+-static void ssb_commit_settings(struct ssb_bus *bus)
+-{
+-      struct ssb_device *dev;
+-
+-      dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
+-      if (WARN_ON(!dev))
+-              return;
+-      /* This forces an update of the cached registers. */
+-      ssb_broadcast_value(dev, 0xFD8, 0);
+-}
+-
+ int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
+                                  struct ssb_device *dev)
+ {
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -1331,6 +1331,31 @@ error:
+ }
+ EXPORT_SYMBOL(ssb_bus_powerup);
+ 
++static void ssb_broadcast_value(struct ssb_device *dev,
++                              u32 address, u32 data)
++{
++      /* This is used for both, PCI and ChipCommon core, so be careful. */
++      BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
++      BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
++
++      ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
++      ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
++      ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
++      ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
++}
++
++void ssb_commit_settings(struct ssb_bus *bus)
++{
++      struct ssb_device *dev;
++
++      dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
++      if (WARN_ON(!dev))
++              return;
++      /* This forces an update of the cached registers. */
++      ssb_broadcast_value(dev, 0xFD8, 0);
++}
++EXPORT_SYMBOL(ssb_commit_settings);
++
+ u32 ssb_admatch_base(u32 adm)
+ {
+       u32 base = 0;
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -518,6 +518,7 @@ extern int ssb_bus_may_powerdown(struct 
+  * Otherwise static always-on powercontrol will be used. */
+ extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
+ 
++extern void ssb_commit_settings(struct ssb_bus *bus);
+ 
+ /* Various helper functions */
+ extern u32 ssb_admatch_base(u32 adm);

diff --git a/target/linux/generic/patches-2.6.37/021-ssb_commit_settings_export.patch b/target/linux/generic/patches-2.6.37/021-ssb_commit_settings_export.patch
new file mode 100644 (file)
index 0000000..a0086ec
--- /dev/null
+++ b/target/linux/generic/patches-2.6.37/021-ssb_commit_settings_export.patch
@@ -0,0 +1,77 @@
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -476,30 +476,6 @@ static void ssb_pcie_mdio_write(struct s
+       pcicore_write32(pc, mdio_control, 0);
+ }
+ 
+-static void ssb_broadcast_value(struct ssb_device *dev,
+-                              u32 address, u32 data)
+-{
+-      /* This is used for both, PCI and ChipCommon core, so be careful. */
+-      BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
+-      BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
+-
+-      ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
+-      ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
+-      ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
+-      ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
+-}
+-
+-static void ssb_commit_settings(struct ssb_bus *bus)
+-{
+-      struct ssb_device *dev;
+-
+-      dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
+-      if (WARN_ON(!dev))
+-              return;
+-      /* This forces an update of the cached registers. */
+-      ssb_broadcast_value(dev, 0xFD8, 0);
+-}
+-
+ int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
+                                  struct ssb_device *dev)
+ {
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -1330,6 +1330,31 @@ error:
+ }
+ EXPORT_SYMBOL(ssb_bus_powerup);
+ 
++static void ssb_broadcast_value(struct ssb_device *dev,
++                              u32 address, u32 data)
++{
++      /* This is used for both, PCI and ChipCommon core, so be careful. */
++      BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
++      BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
++
++      ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
++      ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
++      ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
++      ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
++}
++
++void ssb_commit_settings(struct ssb_bus *bus)
++{
++      struct ssb_device *dev;
++
++      dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
++      if (WARN_ON(!dev))
++              return;
++      /* This forces an update of the cached registers. */
++      ssb_broadcast_value(dev, 0xFD8, 0);
++}
++EXPORT_SYMBOL(ssb_commit_settings);
++
+ u32 ssb_admatch_base(u32 adm)
+ {
+       u32 base = 0;
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -518,6 +518,7 @@ extern int ssb_bus_may_powerdown(struct 
+  * Otherwise static always-on powercontrol will be used. */
+ extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
+ 
++extern void ssb_commit_settings(struct ssb_bus *bus);
+ 
+ /* Various helper functions */
+ extern u32 ssb_admatch_base(u32 adm);

diff --git a/target/linux/generic/patches-2.6.38/021-ssb_commit_settings_export.patch b/target/linux/generic/patches-2.6.38/021-ssb_commit_settings_export.patch
new file mode 100644 (file)
index 0000000..a0086ec
--- /dev/null
+++ b/target/linux/generic/patches-2.6.38/021-ssb_commit_settings_export.patch
@@ -0,0 +1,77 @@
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -476,30 +476,6 @@ static void ssb_pcie_mdio_write(struct s
+       pcicore_write32(pc, mdio_control, 0);
+ }
+ 
+-static void ssb_broadcast_value(struct ssb_device *dev,
+-                              u32 address, u32 data)
+-{
+-      /* This is used for both, PCI and ChipCommon core, so be careful. */
+-      BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
+-      BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
+-
+-      ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
+-      ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
+-      ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
+-      ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
+-}
+-
+-static void ssb_commit_settings(struct ssb_bus *bus)
+-{
+-      struct ssb_device *dev;
+-
+-      dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
+-      if (WARN_ON(!dev))
+-              return;
+-      /* This forces an update of the cached registers. */
+-      ssb_broadcast_value(dev, 0xFD8, 0);
+-}
+-
+ int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
+                                  struct ssb_device *dev)
+ {
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -1330,6 +1330,31 @@ error:
+ }
+ EXPORT_SYMBOL(ssb_bus_powerup);
+ 
++static void ssb_broadcast_value(struct ssb_device *dev,
++                              u32 address, u32 data)
++{
++      /* This is used for both, PCI and ChipCommon core, so be careful. */
++      BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
++      BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
++
++      ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
++      ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
++      ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
++      ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
++}
++
++void ssb_commit_settings(struct ssb_bus *bus)
++{
++      struct ssb_device *dev;
++
++      dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
++      if (WARN_ON(!dev))
++              return;
++      /* This forces an update of the cached registers. */
++      ssb_broadcast_value(dev, 0xFD8, 0);
++}
++EXPORT_SYMBOL(ssb_commit_settings);
++
+ u32 ssb_admatch_base(u32 adm)
+ {
+       u32 base = 0;
+--- a/include/linux/ssb/ssb.h
++++ b/include/linux/ssb/ssb.h
+@@ -518,6 +518,7 @@ extern int ssb_bus_may_powerdown(struct 
+  * Otherwise static always-on powercontrol will be used. */
+ extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
+ 
++extern void ssb_commit_settings(struct ssb_bus *bus);
+ 
+ /* Various helper functions */
+ extern u32 ssb_admatch_base(u32 adm);