if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
return -EINVAL;
if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
return -EINVAL;
regoffset = RTL8366S_MIB_COUNTER_PORT_OFFSET * (port);
regoffset = RTL8366S_MIB_COUNTER_PORT_OFFSET * (port);
+ for (i = 0; i < counter; i++)
regoffset += mibLength[i];
regoffset += mibLength[i];
addr = RTL8366S_MIB_COUNTER_BASE + regoffset;
addr = RTL8366S_MIB_COUNTER_BASE + regoffset;
- vlan_data &= ~(vlan_data & bits);
vlan_data |= data;
err = rtl8366_smi_write_reg(smi, addr, vlan_data);
vlan_data |= data;
err = rtl8366_smi_write_reg(smi, addr, vlan_data);
rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
- data &= ~(data & RTL8366_CHIP_CTRL_VLAN);
if (enable)
data |= RTL8366_CHIP_CTRL_VLAN;
if (enable)
data |= RTL8366_CHIP_CTRL_VLAN;
+ else
+ data &= ~RTL8366_CHIP_CTRL_VLAN;
return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
}
return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
}
rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
}
return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
}
rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
- data &= ~(data & RTL8366_LED_BLINKRATE_MASK);
+ data &= ~RTL8366_LED_BLINKRATE_MASK;
data |= val->value.i;
rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
data |= val->value.i;
rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);