++#ifdef notdef
++#define CLEN 1499
++#define CBUFSIZ (CLEN+4)
++#define CNBUFS 5
++
++void testcrc32(void)
++{
++ uint j,k,l;
++ uint8 *buf;
++ uint len[CNBUFS];
++ uint32 crcr;
++ uint32 crc32tv[CNBUFS] =
++ {0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110};
++
++ ASSERT((buf = MALLOC(CBUFSIZ*CNBUFS)) != NULL);
++
++ /* step through all possible alignments */
++ for (l=0;l<=4;l++) {
++ for (j=0; j<CNBUFS; j++) {
++ len[j] = CLEN;
++ for (k=0; k<len[j]; k++)
++ *(buf + j*CBUFSIZ + (k+l)) = (j+k) & 0xff;
++ }
++
++ for (j=0; j<CNBUFS; j++) {
++ crcr = crc32(buf + j*CBUFSIZ + l, len[j], CRC32_INIT_VALUE);
++ ASSERT(crcr == crc32tv[j]);
++ }
++ }
++
++ MFREE(buf, CBUFSIZ*CNBUFS);
++ return;
++}
++#endif
++
++
++/*
++ * Advance from the current 1-byte tag/1-byte length/variable-length value
++ * triple, to the next, returning a pointer to the next.
++ * If the current or next TLV is invalid (does not fit in given buffer length),
++ * NULL is returned.
++ * *buflen is not modified if the TLV elt parameter is invalid, or is decremented
++ * by the TLV paramter's length if it is valid.
++ */
++bcm_tlv_t *
++bcm_next_tlv(bcm_tlv_t *elt, int *buflen)
++{
++ int len;
++
++ /* validate current elt */
++ if (!bcm_valid_tlv(elt, *buflen))
++ return NULL;
++
++ /* advance to next elt */
++ len = elt->len;
++ elt = (bcm_tlv_t*)(elt->data + len);
++ *buflen -= (2 + len);
++
++ /* validate next elt */
++ if (!bcm_valid_tlv(elt, *buflen))
++ return NULL;
++
++ return elt;
++}
++
++/*
++ * Traverse a string of 1-byte tag/1-byte length/variable-length value
++ * triples, returning a pointer to the substring whose first element
++ * matches tag
++ */
++bcm_tlv_t *
++bcm_parse_tlvs(void *buf, int buflen, uint key)
++{
++ bcm_tlv_t *elt;
++ int totlen;
++
++ elt = (bcm_tlv_t*)buf;
++ totlen = buflen;
++
++ /* find tagged parameter */
++ while (totlen >= 2) {
++ int len = elt->len;
++
++ /* validate remaining totlen */
++ if ((elt->id == key) && (totlen >= (len + 2)))
++ return (elt);
++
++ elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
++ totlen -= (len + 2);
++ }
++
++ return NULL;
++}
++
++/*
++ * Traverse a string of 1-byte tag/1-byte length/variable-length value
++ * triples, returning a pointer to the substring whose first element
++ * matches tag. Stop parsing when we see an element whose ID is greater
++ * than the target key.
++ */
++bcm_tlv_t *
++bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
++{
++ bcm_tlv_t *elt;
++ int totlen;
++
++ elt = (bcm_tlv_t*)buf;
++ totlen = buflen;
++
++ /* find tagged parameter */
++ while (totlen >= 2) {
++ uint id = elt->id;
++ int len = elt->len;
++
++ /* Punt if we start seeing IDs > than target key */
++ if (id > key)
++ return(NULL);
++
++ /* validate remaining totlen */
++ if ((id == key) && (totlen >= (len + 2)))
++ return (elt);
++
++ elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
++ totlen -= (len + 2);
++ }
++ return NULL;
++}
++/* routine to dump fields in a fileddesc structure */
++
++uint
++bcmdumpfields(readreg_rtn read_rtn, void *arg0, void *arg1, struct fielddesc *fielddesc_array, char *buf, uint32 bufsize)
++{
++ uint filled_len;
++ uint len;
++ struct fielddesc *cur_ptr;
++
++ filled_len = 0;
++ cur_ptr = fielddesc_array;
++
++ while (bufsize > (filled_len + 64)) {
++ if (cur_ptr->nameandfmt == NULL)
++ break;
++ len = sprintf(buf, cur_ptr->nameandfmt, read_rtn(arg0, arg1, cur_ptr->offset));
++ buf += len;
++ filled_len += len;
++ cur_ptr++;
++ }
++ return filled_len;
++}
++
++uint
++bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint buflen)
++{
++ uint len;
++
++ len = strlen(name) + 1;
++
++ if ((len + datalen) > buflen)
++ return 0;
++
++ strcpy(buf, name);
++
++ /* append data onto the end of the name string */
++ memcpy(&buf[len], data, datalen);
++ len += datalen;
++
++ return len;
++}
++
++/* Quarter dBm units to mW
++ * Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153
++ * Table is offset so the last entry is largest mW value that fits in
++ * a uint16.
++ */
++
++#define QDBM_OFFSET 153
++#define QDBM_TABLE_LEN 40
++
++/* Smallest mW value that will round up to the first table entry, QDBM_OFFSET.
++ * Value is ( mW(QDBM_OFFSET - 1) + mW(QDBM_OFFSET) ) / 2
++ */
++#define QDBM_TABLE_LOW_BOUND 6493
++
++/* Largest mW value that will round down to the last table entry,
++ * QDBM_OFFSET + QDBM_TABLE_LEN-1.
++ * Value is ( mW(QDBM_OFFSET + QDBM_TABLE_LEN - 1) + mW(QDBM_OFFSET + QDBM_TABLE_LEN) ) / 2.
++ */
++#define QDBM_TABLE_HIGH_BOUND 64938
++
++static const uint16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = {
++/* qdBm: +0 +1 +2 +3 +4 +5 +6 +7 */
++/* 153: */ 6683, 7079, 7499, 7943, 8414, 8913, 9441, 10000,
++/* 161: */ 10593, 11220, 11885, 12589, 13335, 14125, 14962, 15849,
++/* 169: */ 16788, 17783, 18836, 19953, 21135, 22387, 23714, 25119,
++/* 177: */ 26607, 28184, 29854, 31623, 33497, 35481, 37584, 39811,
++/* 185: */ 42170, 44668, 47315, 50119, 53088, 56234, 59566, 63096
++};
++
++uint16
++bcm_qdbm_to_mw(uint8 qdbm)
++{
++ uint factor = 1;
++ int idx = qdbm - QDBM_OFFSET;
++
++ if (idx > QDBM_TABLE_LEN) {
++ /* clamp to max uint16 mW value */
++ return 0xFFFF;
++ }
++
++ /* scale the qdBm index up to the range of the table 0-40
++ * where an offset of 40 qdBm equals a factor of 10 mW.
++ */
++ while (idx < 0) {
++ idx += 40;
++ factor *= 10;
++ }
++
++ /* return the mW value scaled down to the correct factor of 10,
++ * adding in factor/2 to get proper rounding. */
++ return ((nqdBm_to_mW_map[idx] + factor/2) / factor);
++}
++
++uint8
++bcm_mw_to_qdbm(uint16 mw)
++{
++ uint8 qdbm;
++ int offset;
++ uint mw_uint = mw;
++ uint boundary;
++
++ /* handle boundary case */
++ if (mw_uint <= 1)
++ return 0;
++
++ offset = QDBM_OFFSET;
++
++ /* move mw into the range of the table */
++ while (mw_uint < QDBM_TABLE_LOW_BOUND) {
++ mw_uint *= 10;
++ offset -= 40;
++ }
++
++ for (qdbm = 0; qdbm < QDBM_TABLE_LEN-1; qdbm++) {
++ boundary = nqdBm_to_mW_map[qdbm] + (nqdBm_to_mW_map[qdbm+1] - nqdBm_to_mW_map[qdbm])/2;
++ if (mw_uint < boundary) break;
++ }
++
++ qdbm += (uint8)offset;
++
++ return(qdbm);
++}
+diff -Naur linux.old/drivers/net/hnd/linux_osl.c linux.dev/drivers/net/hnd/linux_osl.c
+--- linux.old/drivers/net/hnd/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/hnd/linux_osl.c 2006-04-06 15:34:15.000000000 +0200
+@@ -0,0 +1,708 @@
++/*
++ * Linux OS Independent Layer
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ *
++ * $Id$
++ */
++
++#define LINUX_OSL
++
++#include <typedefs.h>
++#include <bcmendian.h>
++#include <linux/module.h>
++#include <linuxver.h>
++#include <osl.h>
++#include <bcmutils.h>
++#include <linux/delay.h>
++#ifdef mips
++#include <asm/paccess.h>
++#endif
++#include <pcicfg.h>
++
++#define PCI_CFG_RETRY 10
++
++#define OS_HANDLE_MAGIC 0x1234abcd
++#define BCM_MEM_FILENAME_LEN 24
++
++typedef struct bcm_mem_link {
++ struct bcm_mem_link *prev;
++ struct bcm_mem_link *next;
++ uint size;
++ int line;
++ char file[BCM_MEM_FILENAME_LEN];
++} bcm_mem_link_t;
++
++struct os_handle {
++ uint magic;
++ void *pdev;
++ uint malloced;
++ uint failed;
++ bcm_mem_link_t *dbgmem_list;
++};
++
++static int16 linuxbcmerrormap[] = \
++{ 0, /* 0 */
++ -EINVAL, /* BCME_ERROR */
++ -EINVAL, /* BCME_BADARG*/
++ -EINVAL, /* BCME_BADOPTION*/
++ -EINVAL, /* BCME_NOTUP */
++ -EINVAL, /* BCME_NOTDOWN */
++ -EINVAL, /* BCME_NOTAP */
++ -EINVAL, /* BCME_NOTSTA */
++ -EINVAL, /* BCME_BADKEYIDX */
++ -EINVAL, /* BCME_RADIOOFF */
++ -EINVAL, /* BCME_NOTBANDLOCKED */
++ -EINVAL, /* BCME_NOCLK */
++ -EINVAL, /* BCME_BADRATESET */
++ -EINVAL, /* BCME_BADBAND */
++ -E2BIG, /* BCME_BUFTOOSHORT */
++ -E2BIG, /* BCME_BUFTOOLONG */
++ -EBUSY, /* BCME_BUSY */
++ -EINVAL, /* BCME_NOTASSOCIATED */
++ -EINVAL, /* BCME_BADSSIDLEN */
++ -EINVAL, /* BCME_OUTOFRANGECHAN */
++ -EINVAL, /* BCME_BADCHAN */
++ -EFAULT, /* BCME_BADADDR */
++ -ENOMEM, /* BCME_NORESOURCE */
++ -EOPNOTSUPP, /* BCME_UNSUPPORTED */
++ -EMSGSIZE, /* BCME_BADLENGTH */
++ -EINVAL, /* BCME_NOTREADY */
++ -EPERM, /* BCME_NOTPERMITTED */
++ -ENOMEM, /* BCME_NOMEM */
++ -EINVAL, /* BCME_ASSOCIATED */
++ -ERANGE, /* BCME_RANGE */
++ -EINVAL /* BCME_NOTFOUND */
++};
++
++/* translate bcmerrors into linux errors*/
++int
++osl_error(int bcmerror)
++{
++ int abs_bcmerror;
++ int array_size = ARRAYSIZE(linuxbcmerrormap);
++
++ abs_bcmerror = ABS(bcmerror);
++
++ if (bcmerror > 0)
++ abs_bcmerror = 0;
++
++ else if (abs_bcmerror >= array_size)
++ abs_bcmerror = BCME_ERROR;
++
++ return linuxbcmerrormap[abs_bcmerror];
++}
++
++osl_t *
++osl_attach(void *pdev)
++{
++ osl_t *osh;
++
++ osh = kmalloc(sizeof(osl_t), GFP_ATOMIC);
++ ASSERT(osh);
++
++ /*
++ * check the cases where
++ * 1.Error code Added to bcmerror table, but forgot to add it to the OS
++ * dependent error code
++ * 2. Error code is added to the bcmerror table, but forgot to add the
++ * corresponding errorstring(dummy call to bcmerrorstr)
++ */
++ bcmerrorstr(0);
++ ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(linuxbcmerrormap) - 1));
++
++ osh->magic = OS_HANDLE_MAGIC;
++ osh->malloced = 0;
++ osh->failed = 0;
++ osh->dbgmem_list = NULL;
++ osh->pdev = pdev;
++
++ return osh;
++}
++
++void
++osl_detach(osl_t *osh)
++{
++ ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC));
++ kfree(osh);
++}
++
++void*
++osl_pktget(osl_t *osh, uint len, bool send)
++{
++ struct sk_buff *skb;
++
++ if ((skb = dev_alloc_skb(len)) == NULL)
++ return (NULL);
++
++ skb_put(skb, len);
++
++ /* ensure the cookie field is cleared */
++ PKTSETCOOKIE(skb, NULL);
++
++ return ((void*) skb);
++}
++
++void
++osl_pktfree(void *p)
++{
++ struct sk_buff *skb, *nskb;
++
++ skb = (struct sk_buff*) p;
++
++ /* perversion: we use skb->next to chain multi-skb packets */
++ while (skb) {
++ nskb = skb->next;
++ skb->next = NULL;
++ if (skb->destructor) {
++ /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if destructor exists */
++ dev_kfree_skb_any(skb);
++ } else {
++ /* can free immediately (even in_irq()) if destructor does not exist */
++ dev_kfree_skb(skb);
++ }
++ skb = nskb;
++ }
++}
++
++uint32
++osl_pci_read_config(osl_t *osh, uint offset, uint size)
++{
++ uint val;
++ uint retry=PCI_CFG_RETRY;
++
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++ /* only 4byte access supported */
++ ASSERT(size == 4);
++
++ do {
++ pci_read_config_dword(osh->pdev, offset, &val);
++ if (val != 0xffffffff)
++ break;
++ } while (retry--);
++
++
++ return (val);
++}
++
++void
++osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
++{
++ uint retry=PCI_CFG_RETRY;
++
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++ /* only 4byte access supported */
++ ASSERT(size == 4);
++
++ do {
++ pci_write_config_dword(osh->pdev, offset, val);
++ if (offset!=PCI_BAR0_WIN)
++ break;
++ if (osl_pci_read_config(osh,offset,size) == val)
++ break;
++ } while (retry--);
++
++}
++
++/* return bus # for the pci device pointed by osh->pdev */
++uint
++osl_pci_bus(osl_t *osh)
++{
++ ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
++
++ return ((struct pci_dev *)osh->pdev)->bus->number;
++}
++
++/* return slot # for the pci device pointed by osh->pdev */
++uint
++osl_pci_slot(osl_t *osh)
++{
++ ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
++
++ return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
++}
++
++static void
++osl_pcmcia_attr(osl_t *osh, uint offset, char *buf, int size, bool write)
++{
++}
++
++void
++osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size)
++{
++ osl_pcmcia_attr(osh, offset, (char *) buf, size, FALSE);
++}
++
++void
++osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size)
++{
++ osl_pcmcia_attr(osh, offset, (char *) buf, size, TRUE);
++}
++
++
++#ifdef BCMDBG_MEM
++
++void*
++osl_debug_malloc(osl_t *osh, uint size, int line, char* file)
++{
++ bcm_mem_link_t *p;
++ char* basename;
++
++ ASSERT(size);
++
++ if ((p = (bcm_mem_link_t*)osl_malloc(osh, sizeof(bcm_mem_link_t) + size)) == NULL)
++ return (NULL);
++
++ p->size = size;
++ p->line = line;
++
++ basename = strrchr(file, '/');
++ /* skip the '/' */
++ if (basename)
++ basename++;
++
++ if (!basename)
++ basename = file;
++
++ strncpy(p->file, basename, BCM_MEM_FILENAME_LEN);
++ p->file[BCM_MEM_FILENAME_LEN - 1] = '\0';
++
++ /* link this block */
++ p->prev = NULL;
++ p->next = osh->dbgmem_list;
++ if (p->next)
++ p->next->prev = p;
++ osh->dbgmem_list = p;
++
++ return p + 1;
++}
++
++void
++osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file)
++{
++ bcm_mem_link_t *p = (bcm_mem_link_t *)((int8*)addr - sizeof(bcm_mem_link_t));
++
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++ if (p->size == 0) {
++ printk("osl_debug_mfree: double free on addr 0x%x size %d at line %d file %s\n",
++ (uint)addr, size, line, file);
++ ASSERT(p->size);
++ return;
++ }
++
++ if (p->size != size) {
++ printk("osl_debug_mfree: dealloc size %d does not match alloc size %d on addr 0x%x at line %d file %s\n",
++ size, p->size, (uint)addr, line, file);
++ ASSERT(p->size == size);
++ return;
++ }
++
++ /* unlink this block */
++ if (p->prev)
++ p->prev->next = p->next;
++ if (p->next)
++ p->next->prev = p->prev;
++ if (osh->dbgmem_list == p)
++ osh->dbgmem_list = p->next;
++ p->next = p->prev = NULL;
++
++ osl_mfree(osh, p, size + sizeof(bcm_mem_link_t));
++}
++
++char*
++osl_debug_memdump(osl_t *osh, char *buf, uint sz)
++{
++ bcm_mem_link_t *p;
++ char *obuf;
++
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++ obuf = buf;
++
++ buf += sprintf(buf, " Address\tSize\tFile:line\n");
++ for (p = osh->dbgmem_list; p && ((buf - obuf) < (sz - 128)); p = p->next)
++ buf += sprintf(buf, "0x%08x\t%5d\t%s:%d\n",
++ (int)p + sizeof(bcm_mem_link_t), p->size, p->file, p->line);
++
++ return (obuf);
++}
++
++#endif /* BCMDBG_MEM */
++
++void*
++osl_malloc(osl_t *osh, uint size)
++{
++ void *addr;
++
++ /* only ASSERT if osh is defined */
++ if (osh)
++ ASSERT(osh->magic == OS_HANDLE_MAGIC);
++
++ if ((addr = kmalloc(size, GFP_ATOMIC)) == NULL) {
++ if(osh)
++ osh->failed++;
++ return (NULL);
++ }
++ if (osh)
++ osh->malloced += size;
++
++ return (addr);
++}
++
++void
++osl_mfree(osl_t *osh, void *addr, uint size)
++{
++ if (osh) {
++ ASSERT(osh->magic == OS_HANDLE_MAGIC);
++ osh->malloced -= size;
++ }
++ kfree(addr);
++}
++
++uint
++osl_malloced(osl_t *osh)
++{
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++ return (osh->malloced);
++}
++
++uint osl_malloc_failed(osl_t *osh)
++{
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++ return (osh->failed);
++}
++
++void*
++osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap)
++{
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++ return (pci_alloc_consistent(osh->pdev, size, (dma_addr_t*)pap));
++}
++
++void
++osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa)
++{
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++
++ pci_free_consistent(osh->pdev, size, va, (dma_addr_t)pa);
++}
++
++uint
++osl_dma_map(osl_t *osh, void *va, uint size, int direction)
++{
++ int dir;
++
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++ dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
++ return (pci_map_single(osh->pdev, va, size, dir));
++}
++
++void
++osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction)
++{
++ int dir;
++
++ ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
++ dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
++ pci_unmap_single(osh->pdev, (uint32)pa, size, dir);
++}
++
++#if defined(BINOSL)
++void
++osl_assert(char *exp, char *file, int line)
++{
++ char tempbuf[255];
++
++ sprintf(tempbuf, "assertion \"%s\" failed: file \"%s\", line %d\n", exp, file, line);
++ panic(tempbuf);
++}
++#endif /* BCMDBG || BINOSL */
++
++void
++osl_delay(uint usec)
++{
++ uint d;
++
++ while (usec > 0) {
++ d = MIN(usec, 1000);
++ udelay(d);
++ usec -= d;
++ }
++}
++
++/*
++ * BINOSL selects the slightly slower function-call-based binary compatible osl.
++ */
++#ifdef BINOSL
++
++int
++osl_printf(const char *format, ...)
++{
++ va_list args;
++ char buf[1024];
++ int len;
++
++ /* sprintf into a local buffer because there *is* no "vprintk()".. */
++ va_start(args, format);
++ len = vsprintf(buf, format, args);
++ va_end(args);
++
++ if (len > sizeof (buf)) {
++ printk("osl_printf: buffer overrun\n");
++ return (0);
++ }
++
++ return (printk(buf));
++}
++
++int
++osl_sprintf(char *buf, const char *format, ...)
++{
++ va_list args;
++ int rc;
++
++ va_start(args, format);
++ rc = vsprintf(buf, format, args);
++ va_end(args);
++ return (rc);
++}
++
++int
++osl_strcmp(const char *s1, const char *s2)
++{
++ return (strcmp(s1, s2));
++}
++
++int
++osl_strncmp(const char *s1, const char *s2, uint n)
++{
++ return (strncmp(s1, s2, n));
++}
++
++int
++osl_strlen(const char *s)
++{
++ return (strlen(s));
++}
++
++char*
++osl_strcpy(char *d, const char *s)
++{
++ return (strcpy(d, s));
++}
++
++char*
++osl_strncpy(char *d, const char *s, uint n)
++{
++ return (strncpy(d, s, n));
++}
++
++void
++bcopy(const void *src, void *dst, int len)
++{
++ memcpy(dst, src, len);
++}
++
++int
++bcmp(const void *b1, const void *b2, int len)
++{
++ return (memcmp(b1, b2, len));
++}
++
++void
++bzero(void *b, int len)
++{
++ memset(b, '\0', len);
++}
++
++uint32
++osl_readl(volatile uint32 *r)
++{
++ return (readl(r));
++}
++
++uint16
++osl_readw(volatile uint16 *r)
++{
++ return (readw(r));
++}
++
++uint8
++osl_readb(volatile uint8 *r)
++{
++ return (readb(r));
++}
++
++void
++osl_writel(uint32 v, volatile uint32 *r)
++{
++ writel(v, r);
++}
++
++void
++osl_writew(uint16 v, volatile uint16 *r)
++{
++ writew(v, r);
++}
++
++void
++osl_writeb(uint8 v, volatile uint8 *r)
++{
++ writeb(v, r);
++}
++
++void *
++osl_uncached(void *va)
++{
++#ifdef mips
++ return ((void*)KSEG1ADDR(va));
++#else
++ return ((void*)va);
++#endif
++}
++
++uint
++osl_getcycles(void)
++{
++ uint cycles;
++
++#if defined(mips)
++ cycles = read_c0_count() * 2;
++#elif defined(__i386__)
++ rdtscl(cycles);
++#else
++ cycles = 0;
++#endif
++ return cycles;
++}
++
++void *
++osl_reg_map(uint32 pa, uint size)
++{
++ return (ioremap_nocache((unsigned long)pa, (unsigned long)size));
++}
++
++void
++osl_reg_unmap(void *va)
++{
++ iounmap(va);
++}
++
++int
++osl_busprobe(uint32 *val, uint32 addr)
++{
++#ifdef mips
++ return get_dbe(*val, (uint32*)addr);
++#else
++ *val = readl(addr);
++ return 0;
++#endif
++}
++
++uchar*
++osl_pktdata(osl_t *osh, void *skb)
++{
++ return (((struct sk_buff*)skb)->data);
++}
++
++uint
++osl_pktlen(osl_t *osh, void *skb)
++{
++ return (((struct sk_buff*)skb)->len);
++}
++
++uint
++osl_pktheadroom(osl_t *osh, void *skb)
++{
++ return (uint) skb_headroom((struct sk_buff *) skb);
++}
++
++uint
++osl_pkttailroom(osl_t *osh, void *skb)
++{
++ return (uint) skb_tailroom((struct sk_buff *) skb);
++}
++
++void*
++osl_pktnext(osl_t *osh, void *skb)
++{
++ return (((struct sk_buff*)skb)->next);
++}
++
++void
++osl_pktsetnext(void *skb, void *x)
++{
++ ((struct sk_buff*)skb)->next = (struct sk_buff*)x;
++}
++
++void
++osl_pktsetlen(osl_t *osh, void *skb, uint len)
++{
++ __skb_trim((struct sk_buff*)skb, len);
++}
++
++uchar*
++osl_pktpush(osl_t *osh, void *skb, int bytes)
++{
++ return (skb_push((struct sk_buff*)skb, bytes));
++}
++
++uchar*
++osl_pktpull(osl_t *osh, void *skb, int bytes)
++{
++ return (skb_pull((struct sk_buff*)skb, bytes));
++}
++
++void*
++osl_pktdup(osl_t *osh, void *skb)
++{
++ return (skb_clone((struct sk_buff*)skb, GFP_ATOMIC));
++}
++
++void*
++osl_pktcookie(void *skb)
++{
++ return ((void*)((struct sk_buff*)skb)->csum);
++}
++
++void
++osl_pktsetcookie(void *skb, void *x)
++{
++ ((struct sk_buff*)skb)->csum = (uint)x;
++}
++
++void*
++osl_pktlink(void *skb)
++{
++ return (((struct sk_buff*)skb)->prev);
++}
++
++void
++osl_pktsetlink(void *skb, void *x)
++{
++ ((struct sk_buff*)skb)->prev = (struct sk_buff*)x;
++}
++
++uint
++osl_pktprio(void *skb)
++{
++ return (((struct sk_buff*)skb)->priority);
++}
++
++void
++osl_pktsetprio(void *skb, uint x)
++{
++ ((struct sk_buff*)skb)->priority = x;
++}
++
++
++#endif /* BINOSL */
+diff -Naur linux.old/drivers/net/hnd/sbutils.c linux.dev/drivers/net/hnd/sbutils.c
+--- linux.old/drivers/net/hnd/sbutils.c 1970-01-01 01:00:00.000000000 +0100
++++ linux.dev/drivers/net/hnd/sbutils.c 2006-04-06 15:34:15.000000000 +0200
+@@ -0,0 +1,2837 @@
++/*
++ * Misc utility routines for accessing chip-specific features
++ * of the SiliconBackplane-based Broadcom chips.
++ *
++ * Copyright 2005, Broadcom Corporation
++ * All Rights Reserved.
++ *
++ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
++ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
++ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
++ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
++ * $Id$
++ */
++
++#include <typedefs.h>
++#include <osl.h>
++#include <sbutils.h>
++#include <bcmutils.h>
++#include <bcmdevs.h>
++#include <sbconfig.h>
++#include <sbchipc.h>
++#include <sbpci.h>
++#include <sbpcie.h>
++#include <pcicfg.h>
++#include <sbpcmcia.h>
++#include <sbextif.h>
++#include <bcmsrom.h>
++
++/* debug/trace */
++#define SB_ERROR(args)
++
++
++typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
++typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
++typedef bool (*sb_intrsenabled_t)(void *intr_arg);
++
++/* misc sb info needed by some of the routines */
++typedef struct sb_info {
++
++ struct sb_pub sb; /* back plane public state(must be first field of sb_info */
++
++ void *osh; /* osl os handle */
++ void *sdh; /* bcmsdh handle */
++
++ void *curmap; /* current regs va */
++ void *regs[SB_MAXCORES]; /* other regs va */
++
++ uint curidx; /* current core index */
++ uint dev_coreid; /* the core provides driver functions */
++
++ bool memseg; /* flag to toggle MEM_SEG register */
++
++ uint gpioidx; /* gpio control core index */
++ uint gpioid; /* gpio control coretype */
++
++ uint numcores; /* # discovered cores */
++ uint coreid[SB_MAXCORES]; /* id of each core */
++
++ void *intr_arg; /* interrupt callback function arg */
++ sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
++ sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
++ sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
++
++} sb_info_t;
++
++/* local prototypes */
++static sb_info_t * BCMINIT(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
++ uint bustype, void *sdh, char **vars, int *varsz);
++static void BCMINIT(sb_scan)(sb_info_t *si);
++static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
++static uint _sb_coreidx(sb_info_t *si);
++static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
++static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
++static uint BCMINIT(sb_chip2numcores)(uint chip);
++static bool sb_ispcie(sb_info_t *si);
++static bool sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen);
++static int sb_pci_fixcfg(sb_info_t *si);
++
++/* routines to access mdio slave device registers */
++static int sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint readdr, uint val);
++static void BCMINIT(sb_war30841)(sb_info_t *si);
++
++/* delay needed between the mdio control/ mdiodata register data access */
++#define PR28829_DELAY() OSL_DELAY(10)
++
++
++/* global variable to indicate reservation/release of gpio's*/
++static uint32 sb_gpioreservation = 0;
++
++#define SB_INFO(sbh) (sb_info_t*)sbh
++#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
++#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
++#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
++#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
++#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
++#define BADIDX (SB_MAXCORES+1)
++#define NOREV -1
++
++#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
++#define PCIE(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCIE))
++
++/* sonicsrev */
++#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
++#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
++
++#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
++#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
++#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
++#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
++
++/*
++ * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
++ * after core switching to avoid invalid register accesss inside ISR.
++ */
++#define INTR_OFF(si, intr_val) \
++ if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
++ intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
++#define INTR_RESTORE(si, intr_val) \
++ if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
++ (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
++
++/* dynamic clock control defines */
++#define LPOMINFREQ 25000 /* low power oscillator min */
++#define LPOMAXFREQ 43000 /* low power oscillator max */
++#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
++#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
++#define PCIMINFREQ 25000000 /* 25 MHz */
++#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
++
++#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
++#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
++
++#define MIN_DUMPBUFLEN 32 /* debug */
++
++/* different register spaces to access thr'u pcie indirect access*/
++#define PCIE_CONFIGREGS 1
++#define PCIE_PCIEREGS 2
++
++/* GPIO Based LED powersave defines */
++#define DEFAULT_GPIO_ONTIME 10
++#define DEFAULT_GPIO_OFFTIME 90
++
++#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
++
++static uint32
++sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
++{
++ uint8 tmp;
++ uint32 val, intr_val = 0;
++
++
++ /*
++ * compact flash only has 11 bits address, while we needs 12 bits address.
++ * MEM_SEG will be OR'd with other 11 bits address in hardware,
++ * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
++ * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
++ */
++ if(si->memseg) {
++ INTR_OFF(si, intr_val);
++ tmp = 1;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
++ sbr = (uint32) ((uintptr) sbr & ~(1 << 11)); /* mask out bit 11*/
++ }
++
++ val = R_REG(sbr);
++
++ if(si->memseg) {
++ tmp = 0;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
++ INTR_RESTORE(si, intr_val);
++ }
++
++ return (val);
++}
++
++static void
++sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
++{
++ uint8 tmp;
++ volatile uint32 dummy;
++ uint32 intr_val = 0;
++
++
++ /*
++ * compact flash only has 11 bits address, while we needs 12 bits address.
++ * MEM_SEG will be OR'd with other 11 bits address in hardware,
++ * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
++ * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
++ */
++ if(si->memseg) {
++ INTR_OFF(si, intr_val);
++ tmp = 1;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
++ sbr = (uint32) ((uintptr) sbr & ~(1 << 11)); /* mask out bit 11*/
++ }
++
++ if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
++#ifdef IL_BIGENDIAN
++ dummy = R_REG(sbr);
++ W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
++ dummy = R_REG(sbr);
++ W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
++#else
++ dummy = R_REG(sbr);
++ W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
++ dummy = R_REG(sbr);
++ W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
++#endif
++ } else
++ W_REG(sbr, v);
++
++ if(si->memseg) {
++ tmp = 0;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
++ INTR_RESTORE(si, intr_val);
++ }
++}
++
++/*
++ * Allocate a sb handle.
++ * devid - pci device id (used to determine chip#)
++ * osh - opaque OS handle
++ * regs - virtual address of initial core registers
++ * bustype - pci/pcmcia/sb/sdio/etc
++ * vars - pointer to a pointer area for "environment" variables
++ * varsz - pointer to int to return the size of the vars
++ */
++sb_t *
++BCMINITFN(sb_attach)(uint devid, osl_t *osh, void *regs,
++ uint bustype, void *sdh, char **vars, int *varsz)
++{
++ sb_info_t *si;
++
++ /* alloc sb_info_t */
++ if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
++ SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
++ return (NULL);
++ }
++
++ if (BCMINIT(sb_doattach)(si, devid, osh, regs, bustype, sdh, vars, varsz) == NULL) {
++ MFREE(osh, si, sizeof (sb_info_t));
++ return (NULL);
++ }
++ return (sb_t *)si;
++}
++
++/* Using sb_kattach depends on SB_BUS support, either implicit */
++/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
++#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
++
++/* global kernel resource */
++static sb_info_t ksi;
++
++/* generic kernel variant of sb_attach() */
++sb_t *
++BCMINITFN(sb_kattach)()
++{
++ uint32 *regs;
++
++ if (ksi.curmap == NULL) {
++ uint32 cid;
++
++ regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
++ cid = R_REG((uint32 *)regs);
++ if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
++ ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
++ ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
++ uint32 *scc, val;
++
++ scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
++ val = R_REG(scc);
++ SB_ERROR((" initial scc = 0x%x\n", val));
++ val |= SCC_SS_XTAL;
++ W_REG(scc, val);
++ }
++
++ if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
++ SB_BUS, NULL, NULL, NULL) == NULL) {
++ return NULL;
++ }
++ }
++
++ return (sb_t *)&ksi;
++}
++#endif
++
++static sb_info_t *
++BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
++ uint bustype, void *sdh, char **vars, int *varsz)
++{
++ uint origidx;
++ chipcregs_t *cc;
++ sbconfig_t *sb;
++ uint32 w;
++
++ ASSERT(GOODREGS(regs));
++
++ bzero((uchar*)si, sizeof (sb_info_t));
++
++ si->sb.buscoreidx = si->gpioidx = BADIDX;
++
++ si->osh = osh;
++ si->curmap = regs;
++ si->sdh = sdh;
++
++ /* check to see if we are a sb core mimic'ing a pci core */
++ if (bustype == PCI_BUS) {
++ if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
++ bustype = SB_BUS;
++ else
++ bustype = PCI_BUS;
++ }
++
++ si->sb.bustype = bustype;
++ if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
++ SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
++ si->sb.bustype, BUSTYPE(si->sb.bustype)));
++ return NULL;
++ }
++
++ /* need to set memseg flag for CF card first before any sb registers access */
++ if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
++ si->memseg = TRUE;
++
++ /* kludge to enable the clock on the 4306 which lacks a slowclock */
++ if (BUSTYPE(si->sb.bustype) == PCI_BUS)
++ sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
++
++ if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
++ w = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, sizeof (uint32));
++ if (!GOODCOREADDR(w))
++ OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32), SB_ENUM_BASE);
++ }
++
++ /* initialize current core index value */
++ si->curidx = _sb_coreidx(si);
++
++ if (si->curidx == BADIDX) {
++ SB_ERROR(("sb_doattach: bad core index\n"));
++ return NULL;
++ }
++
++ /* get sonics backplane revision */
++ sb = REGS2SB(si->curmap);
++ si->sb.sonicsrev = (R_SBREG(si, &(sb)->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
++
++ /* keep and reuse the initial register mapping */
++ origidx = si->curidx;
++ if (BUSTYPE(si->sb.bustype) == SB_BUS)
++ si->regs[origidx] = regs;
++
++ /* is core-0 a chipcommon core? */
++ si->numcores = 1;
++ cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
++ if (sb_coreid(&si->sb) != SB_CC)
++ cc = NULL;
++
++ /* determine chip id and rev */
++ if (cc) {
++ /* chip common core found! */
++ si->sb.chip = R_REG(&cc->chipid) & CID_ID_MASK;
++ si->sb.chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
++ si->sb.chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
++ } else {
++ /* The only pcmcia chip without a chipcommon core is a 4301 */
++ if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
++ devid = BCM4301_DEVICE_ID;
++
++ /* no chip common core -- must convert device id to chip id */
++ if ((si->sb.chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
++ SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
++ sb_setcoreidx(&si->sb, origidx);
++ return NULL;
++ }
++ }
++
++ /* get chipcommon rev */
++ si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
++
++ /* determine numcores */
++ if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
++ si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
++ else
++ si->numcores = BCMINIT(sb_chip2numcores)(si->sb.chip);
++
++ /* return to original core */
++ sb_setcoreidx(&si->sb, origidx);
++
++ /* sanity checks */
++ ASSERT(si->sb.chip);
++
++ /* scan for cores */
++ BCMINIT(sb_scan)(si);
++
++ /* fixup necessary chip/core configurations */
++ if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
++ if (sb_pci_fixcfg(si)) {
++ SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
++ return NULL;
++ }
++ }
++
++ /* srom_var_init() depends on sb_scan() info */
++ if (srom_var_init(si, si->sb.bustype, si->curmap, osh, vars, varsz)) {
++ SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
++ return (NULL);
++ }
++
++ if (cc == NULL) {
++ /*
++ * The chip revision number is hardwired into all
++ * of the pci function config rev fields and is
++ * independent from the individual core revision numbers.
++ * For example, the "A0" silicon of each chip is chip rev 0.
++ * For PCMCIA we get it from the CIS instead.
++ */
++ if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
++ ASSERT(vars);
++ si->sb.chiprev = getintvar(*vars, "chiprev");
++ } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
++ w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
++ si->sb.chiprev = w & 0xff;
++ } else
++ si->sb.chiprev = 0;
++ }
++
++ if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
++ w = getintvar(*vars, "regwindowsz");
++ si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
++ }
++
++ /* gpio control core is required */
++ if (!GOODIDX(si->gpioidx)) {
++ SB_ERROR(("sb_doattach: gpio control core not found\n"));
++ return NULL;
++ }
++
++ /* get boardtype and boardrev */
++ switch (BUSTYPE(si->sb.bustype)) {
++ case PCI_BUS:
++ /* do a pci config read to get subsystem id and subvendor id */
++ w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
++ si->sb.boardvendor = w & 0xffff;
++ si->sb.boardtype = (w >> 16) & 0xffff;
++ break;
++
++ case PCMCIA_BUS:
++ case SDIO_BUS:
++ si->sb.boardvendor = getintvar(*vars, "manfid");
++ si->sb.boardtype = getintvar(*vars, "prodid");
++ break;
++
++ case SB_BUS:
++ case JTAG_BUS:
++ si->sb.boardvendor = VENDOR_BROADCOM;
++ if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
++ si->sb.boardtype = 0xffff;
++ break;
++ }
++
++ if (si->sb.boardtype == 0) {
++ SB_ERROR(("sb_doattach: unknown board type\n"));
++ ASSERT(si->sb.boardtype);
++ }
++
++ /* setup the GPIO based LED powersave register */
++ if (si->sb.ccrev >= 16) {
++ w = getintvar(*vars, "gpiotimerval");
++ if (!w)
++ w = DEFAULT_GPIOTIMERVAL;
++ sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
++ }
++
++
++ return (si);
++}
++
++uint
++sb_coreid(sb_t *sbh)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++
++ si = SB_INFO(sbh);
++ sb = REGS2SB(si->curmap);
++
++ return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
++}
++
++uint
++sb_coreidx(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->curidx);
++}
++
++/* return current index of core */
++static uint
++_sb_coreidx(sb_info_t *si)
++{
++ sbconfig_t *sb;
++ uint32 sbaddr = 0;
++
++ ASSERT(si);
++
++ switch (BUSTYPE(si->sb.bustype)) {
++ case SB_BUS:
++ sb = REGS2SB(si->curmap);
++ sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
++ break;
++
++ case PCI_BUS:
++ sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
++ break;
++
++ case PCMCIA_BUS: {
++ uint8 tmp = 0;
++
++ OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
++ sbaddr = (uint)tmp << 12;
++ OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
++ sbaddr |= (uint)tmp << 16;
++ OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
++ sbaddr |= (uint)tmp << 24;
++ break;
++ }
++
++#ifdef BCMJTAG
++ case JTAG_BUS:
++ sbaddr = (uint32)si->curmap;
++ break;
++#endif /* BCMJTAG */
++
++ default:
++ ASSERT(0);
++ }
++
++ if (!GOODCOREADDR(sbaddr))
++ return BADIDX;
++
++ return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
++}
++
++uint
++sb_corevendor(sb_t *sbh)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++
++ si = SB_INFO(sbh);
++ sb = REGS2SB(si->curmap);
++
++ return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
++}
++
++uint
++sb_corerev(sb_t *sbh)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++ uint sbidh;
++
++ si = SB_INFO(sbh);
++ sb = REGS2SB(si->curmap);
++ sbidh = R_SBREG(si, &(sb)->sbidhigh);
++
++ return (SBCOREREV(sbidh));
++}
++
++void *
++sb_osh(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return si->osh;
++}
++
++#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
++
++/* set/clear sbtmstatelow core-specific flags */
++uint32
++sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++ uint32 w;
++
++ si = SB_INFO(sbh);
++ sb = REGS2SB(si->curmap);
++
++ ASSERT((val & ~mask) == 0);
++ ASSERT((mask & ~SBTML_ALLOW) == 0);
++
++ /* mask and set */
++ if (mask || val) {
++ w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
++ W_SBREG(si, &sb->sbtmstatelow, w);
++ }
++
++ /* return the new value */
++ return (R_SBREG(si, &sb->sbtmstatelow) & SBTML_ALLOW);
++}
++
++/* set/clear sbtmstatehigh core-specific flags */
++uint32
++sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++ uint32 w;
++
++ si = SB_INFO(sbh);
++ sb = REGS2SB(si->curmap);
++
++ ASSERT((val & ~mask) == 0);
++ ASSERT((mask & ~SBTMH_FL_MASK) == 0);
++
++ /* mask and set */
++ if (mask || val) {
++ w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
++ W_SBREG(si, &sb->sbtmstatehigh, w);
++ }
++
++ /* return the new value */
++ return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
++}
++
++/* caller needs to take care of core-specific bist hazards */
++int
++sb_corebist(sb_t *sbh, uint coreid, uint coreunit)
++{
++ uint32 sblo;
++ uint coreidx;
++ sb_info_t *si;
++ int result = 0;
++
++ si = SB_INFO(sbh);
++
++ coreidx = sb_findcoreidx(si, coreid, coreunit);
++ if (!GOODIDX(coreidx))
++ result = BCME_ERROR;
++ else {
++ sblo = sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), 0, 0);
++ sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, (sblo | SBTML_FGC | SBTML_BE));
++
++ SPINWAIT(((sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTD) == 0), 100000);
++
++ if (sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTF)
++ result = BCME_ERROR;
++
++ sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, sblo);
++ }
++
++ return result;
++}
++
++bool
++sb_iscoreup(sb_t *sbh)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++
++ si = SB_INFO(sbh);
++ sb = REGS2SB(si->curmap);
++
++ return ((R_SBREG(si, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
++}
++
++/*
++ * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
++ * switch back to the original core, and return the new value.
++ */
++static uint
++sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
++{
++ uint origidx;
++ uint32 *r;
++ uint w;
++ uint intr_val = 0;
++
++ ASSERT(GOODIDX(coreidx));
++ ASSERT(regoff < SB_CORE_SIZE);
++ ASSERT((val & ~mask) == 0);
++
++ INTR_OFF(si, intr_val);
++
++ /* save current core index */
++ origidx = sb_coreidx(&si->sb);
++
++ /* switch core */
++ r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
++
++ /* mask and set */
++ if (mask || val) {
++ if (regoff >= SBCONFIGOFF) {
++ w = (R_SBREG(si, r) & ~mask) | val;
++ W_SBREG(si, r, w);
++ } else {
++ w = (R_REG(r) & ~mask) | val;
++ W_REG(r, w);
++ }
++ }
++
++ /* readback */
++ if (regoff >= SBCONFIGOFF)
++ w = R_SBREG(si, r);
++ else
++ w = R_REG(r);
++
++ /* restore core index */
++ if (origidx != coreidx)
++ sb_setcoreidx(&si->sb, origidx);
++
++ INTR_RESTORE(si, intr_val);
++ return (w);
++}
++
++#define DWORD_ALIGN(x) (x & ~(0x03))
++#define BYTE_POS(x) (x & 0x3)
++#define WORD_POS(x) (x & 0x1)
++
++#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
++#define WORD_SHIFT(x) (16 * WORD_POS(x))
++
++#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
++#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
++
++#define read_pci_cfg_byte(a) \
++ (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
++
++#define read_pci_cfg_write(a) \
++ (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
++
++
++/* return TRUE if requested capability exists in the PCI config space */
++static bool
++sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen)
++{
++ uint8 cap_id;
++ uint8 cap_ptr;
++ uint32 bufsize;
++ uint8 byte_val;
++
++ if (BUSTYPE(si->sb.bustype) != PCI_BUS)
++ return FALSE;
++
++ /* check for Header type 0*/
++ byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
++ if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
++ return FALSE;
++
++ /* check if the capability pointer field exists */
++ byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
++ if (!(byte_val & PCI_CAPPTR_PRESENT))
++ return FALSE;
++
++ cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
++ /* check if the capability pointer is 0x00 */
++ if (cap_ptr == 0x00)
++ return FALSE;
++
++
++ /* loop thr'u the capability list and see if the pcie capabilty exists */
++
++ cap_id = read_pci_cfg_byte(cap_ptr);
++
++ while (cap_id != req_cap_id) {
++ cap_ptr = read_pci_cfg_byte((cap_ptr+1));
++ if (cap_ptr == 0x00) break;
++ cap_id = read_pci_cfg_byte(cap_ptr);
++ }
++ if (cap_id != req_cap_id) {
++ return FALSE;
++ }
++ /* found the caller requested capability */
++ if ((buf != NULL) && (buflen != NULL)) {
++ bufsize = *buflen;
++ if (!bufsize) goto end;
++ *buflen = 0;
++ /* copy the cpability data excluding cap ID and next ptr */
++ cap_ptr += 2;
++ if ((bufsize + cap_ptr) > SZPCR)
++ bufsize = SZPCR - cap_ptr;
++ *buflen = bufsize;
++ while (bufsize--) {
++ *buf = read_pci_cfg_byte(cap_ptr);
++ cap_ptr++;
++ buf++;
++ }
++ }
++end:
++ return TRUE;
++}
++
++/* return TRUE if PCIE capability exists the pci config space */
++static bool
++sb_ispcie(sb_info_t *si)
++{
++ return(sb_find_pci_capability(si, PCI_CAP_PCIECAP_ID, NULL, NULL));
++}
++
++/* scan the sb enumerated space to identify all cores */
++static void
++BCMINITFN(sb_scan)(sb_info_t *si)
++{
++ uint origidx;
++ uint i;
++ bool pci;
++ bool pcie;
++ uint pciidx;
++ uint pcieidx;
++ uint pcirev;
++ uint pcierev;
++
++
++
++ /* numcores should already be set */
++ ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
++
++ /* save current core index */
++ origidx = sb_coreidx(&si->sb);
++
++ si->sb.buscorerev = NOREV;
++ si->sb.buscoreidx = BADIDX;
++
++ si->gpioidx = BADIDX;
++
++ pci = pcie = FALSE;
++ pcirev = pcierev = NOREV;
++ pciidx = pcieidx = BADIDX;
++
++ for (i = 0; i < si->numcores; i++) {
++ sb_setcoreidx(&si->sb, i);
++ si->coreid[i] = sb_coreid(&si->sb);
++
++ if (si->coreid[i] == SB_PCI) {
++ pciidx = i;
++ pcirev = sb_corerev(&si->sb);
++ pci = TRUE;
++ } else if (si->coreid[i] == SB_PCIE) {
++ pcieidx = i;
++ pcierev = sb_corerev(&si->sb);
++ pcie = TRUE;
++ } else if (si->coreid[i] == SB_PCMCIA) {
++ si->sb.buscorerev = sb_corerev(&si->sb);
++ si->sb.buscoretype = si->coreid[i];
++ si->sb.buscoreidx = i;
++ }
++ }
++ if (pci && pcie) {
++ if (sb_ispcie(si))
++ pci = FALSE;
++ else
++ pcie = FALSE;
++ }
++ if (pci) {
++ si->sb.buscoretype = SB_PCI;
++ si->sb.buscorerev = pcirev;
++ si->sb.buscoreidx = pciidx;
++ }
++ else if (pcie) {
++ si->sb.buscoretype = SB_PCIE;
++ si->sb.buscorerev = pcierev;
++ si->sb.buscoreidx = pcieidx;
++ }
++
++ /*
++ * Find the gpio "controlling core" type and index.
++ * Precedence:
++ * - if there's a chip common core - use that
++ * - else if there's a pci core (rev >= 2) - use that
++ * - else there had better be an extif core (4710 only)
++ */
++ if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
++ si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
++ si->gpioid = SB_CC;
++ } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
++ si->gpioidx = si->sb.buscoreidx;
++ si->gpioid = SB_PCI;
++ } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
++ si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
++ si->gpioid = SB_EXTIF;
++ } else
++ ASSERT(si->gpioidx != BADIDX);
++
++ /* return to original core index */
++ sb_setcoreidx(&si->sb, origidx);
++}
++
++/* may be called with core in reset */
++void
++sb_detach(sb_t *sbh)
++{
++ sb_info_t *si;
++ uint idx;
++
++ si = SB_INFO(sbh);
++
++ if (si == NULL)
++ return;
++
++ if (BUSTYPE(si->sb.bustype) == SB_BUS)
++ for (idx = 0; idx < SB_MAXCORES; idx++)
++ if (si->regs[idx]) {
++ REG_UNMAP(si->regs[idx]);
++ si->regs[idx] = NULL;
++ }
++
++ if (si != &ksi)
++ MFREE(si->osh, si, sizeof (sb_info_t));
++}
++
++/* use pci dev id to determine chip id for chips not having a chipcommon core */
++static uint
++BCMINITFN(sb_pcidev2chip)(uint pcidev)
++{
++ if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
++ return (BCM4710_DEVICE_ID);
++ if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
++ return (BCM4402_DEVICE_ID);
++ if (pcidev == BCM4401_ENET_ID)
++ return (BCM4402_DEVICE_ID);
++ if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
++ return (BCM4307_DEVICE_ID);
++ if (pcidev == BCM4301_DEVICE_ID)
++ return (BCM4301_DEVICE_ID);
++
++ return (0);
++}
++
++/* convert chip number to number of i/o cores */
++static uint
++BCMINITFN(sb_chip2numcores)(uint chip)
++{
++ if (chip == BCM4710_DEVICE_ID)
++ return (9);
++ if (chip == BCM4402_DEVICE_ID)
++ return (3);
++ if ((chip == BCM4301_DEVICE_ID) || (chip == BCM4307_DEVICE_ID))
++ return (5);
++ if (chip == BCM4306_DEVICE_ID) /* < 4306c0 */
++ return (6);
++ if (chip == BCM4704_DEVICE_ID)
++ return (9);
++ if (chip == BCM5365_DEVICE_ID)
++ return (7);
++
++ SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
++ ASSERT(0);
++ return (1);
++}
++
++/* return index of coreid or BADIDX if not found */
++static uint
++sb_findcoreidx( sb_info_t *si, uint coreid, uint coreunit)
++{
++ uint found;
++ uint i;
++
++ found = 0;
++
++ for (i = 0; i < si->numcores; i++)
++ if (si->coreid[i] == coreid) {
++ if (found == coreunit)
++ return (i);
++ found++;
++ }
++
++ return (BADIDX);
++}
++
++/*
++ * this function changes logical "focus" to the indiciated core,
++ * must be called with interrupt off.
++ * Moreover, callers should keep interrupts off during switching out of and back to d11 core
++ */
++void*
++sb_setcoreidx(sb_t *sbh, uint coreidx)
++{
++ sb_info_t *si;
++ uint32 sbaddr;
++ uint8 tmp;
++
++ si = SB_INFO(sbh);
++
++ if (coreidx >= si->numcores)
++ return (NULL);
++
++ /*
++ * If the user has provided an interrupt mask enabled function,
++ * then assert interrupts are disabled before switching the core.
++ */
++ ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
++
++ sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
++
++ switch (BUSTYPE(si->sb.bustype)) {
++ case SB_BUS:
++ /* map new one */
++ if (!si->regs[coreidx]) {
++ si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
++ ASSERT(GOODREGS(si->regs[coreidx]));
++ }
++ si->curmap = si->regs[coreidx];
++ break;
++
++ case PCI_BUS:
++ /* point bar0 window */
++ OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
++ break;
++
++ case PCMCIA_BUS:
++ tmp = (sbaddr >> 12) & 0x0f;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
++ tmp = (sbaddr >> 16) & 0xff;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
++ tmp = (sbaddr >> 24) & 0xff;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
++ break;
++#ifdef BCMJTAG
++ case JTAG_BUS:
++ /* map new one */
++ if (!si->regs[coreidx]) {
++ si->regs[coreidx] = (void *)sbaddr;
++ ASSERT(GOODREGS(si->regs[coreidx]));
++ }
++ si->curmap = si->regs[coreidx];
++ break;
++#endif /* BCMJTAG */
++ }
++
++ si->curidx = coreidx;
++
++ return (si->curmap);
++}
++
++/*
++ * this function changes logical "focus" to the indiciated core,
++ * must be called with interrupt off.
++ * Moreover, callers should keep interrupts off during switching out of and back to d11 core
++ */
++void*
++sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
++{
++ sb_info_t *si;
++ uint idx;
++
++ si = SB_INFO(sbh);
++ idx = sb_findcoreidx(si, coreid, coreunit);
++ if (!GOODIDX(idx))
++ return (NULL);
++
++ return (sb_setcoreidx(sbh, idx));
++}
++
++/* return chip number */
++uint
++BCMINITFN(sb_chip)(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->sb.chip);
++}
++
++/* return chip revision number */
++uint
++BCMINITFN(sb_chiprev)(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->sb.chiprev);
++}
++
++/* return chip common revision number */
++uint
++BCMINITFN(sb_chipcrev)(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->sb.ccrev);
++}
++
++/* return chip package option */
++uint
++BCMINITFN(sb_chippkg)(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->sb.chippkg);
++}
++
++/* return PCI core rev. */
++uint
++BCMINITFN(sb_pcirev)(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->sb.buscorerev);
++}
++
++bool
++BCMINITFN(sb_war16165)(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++
++ return (PCI(si) && (si->sb.buscorerev <= 10));
++}
++
++static void
++BCMINITFN(sb_war30841)(sb_info_t *si)
++{
++ sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
++ sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
++ sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
++}
++
++/* return PCMCIA core rev. */
++uint
++BCMINITFN(sb_pcmciarev)(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->sb.buscorerev);
++}
++
++/* return board vendor id */
++uint
++BCMINITFN(sb_boardvendor)(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->sb.boardvendor);
++}
++
++/* return boardtype */
++uint
++BCMINITFN(sb_boardtype)(sb_t *sbh)
++{
++ sb_info_t *si;
++ char *var;
++
++ si = SB_INFO(sbh);
++
++ if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
++ /* boardtype format is a hex string */
++ si->sb.boardtype = getintvar(NULL, "boardtype");
++
++ /* backward compatibility for older boardtype string format */
++ if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
++ if (!strcmp(var, "bcm94710dev"))
++ si->sb.boardtype = BCM94710D_BOARD;
++ else if (!strcmp(var, "bcm94710ap"))
++ si->sb.boardtype = BCM94710AP_BOARD;
++ else if (!strcmp(var, "bu4710"))
++ si->sb.boardtype = BU4710_BOARD;
++ else if (!strcmp(var, "bcm94702mn"))
++ si->sb.boardtype = BCM94702MN_BOARD;
++ else if (!strcmp(var, "bcm94710r1"))
++ si->sb.boardtype = BCM94710R1_BOARD;
++ else if (!strcmp(var, "bcm94710r4"))
++ si->sb.boardtype = BCM94710R4_BOARD;
++ else if (!strcmp(var, "bcm94702cpci"))
++ si->sb.boardtype = BCM94702CPCI_BOARD;
++ else if (!strcmp(var, "bcm95380_rr"))
++ si->sb.boardtype = BCM95380RR_BOARD;
++ }
++ }
++
++ return (si->sb.boardtype);
++}
++
++/* return bus type of sbh device */
++uint
++sb_bus(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ return (si->sb.bustype);
++}
++
++/* return bus core type */
++uint
++sb_buscoretype(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++
++ return (si->sb.buscoretype);
++}
++
++/* return bus core revision */
++uint
++sb_buscorerev(sb_t *sbh)
++{
++ sb_info_t *si;
++ si = SB_INFO(sbh);
++
++ return (si->sb.buscorerev);
++}
++
++/* return list of found cores */
++uint
++sb_corelist(sb_t *sbh, uint coreid[])
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++
++ bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
++ return (si->numcores);
++}
++
++/* return current register mapping */
++void *
++sb_coreregs(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++ ASSERT(GOODREGS(si->curmap));
++
++ return (si->curmap);
++}
++
++
++/* do buffered registers update */
++void
++sb_commit(sb_t *sbh)
++{
++ sb_info_t *si;
++ uint origidx;
++ uint intr_val = 0;
++
++ si = SB_INFO(sbh);
++
++ origidx = si->curidx;
++ ASSERT(GOODIDX(origidx));
++
++ INTR_OFF(si, intr_val);
++
++ /* switch over to chipcommon core if there is one, else use pci */
++ if (si->sb.ccrev != NOREV) {
++ chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
++
++ /* do the buffer registers update */
++ W_REG(&ccregs->broadcastaddress, SB_COMMIT);
++ W_REG(&ccregs->broadcastdata, 0x0);
++ } else if (PCI(si)) {
++ sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
++
++ /* do the buffer registers update */
++ W_REG(&pciregs->bcastaddr, SB_COMMIT);
++ W_REG(&pciregs->bcastdata, 0x0);
++ } else
++ ASSERT(0);
++
++ /* restore core index */
++ sb_setcoreidx(sbh, origidx);
++ INTR_RESTORE(si, intr_val);
++}
++
++/* reset and re-enable a core */
++void
++sb_core_reset(sb_t *sbh, uint32 bits)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++ volatile uint32 dummy;
++
++ si = SB_INFO(sbh);
++ ASSERT(GOODREGS(si->curmap));
++ sb = REGS2SB(si->curmap);
++
++ /*
++ * Must do the disable sequence first to work for arbitrary current core state.
++ */
++ sb_core_disable(sbh, bits);
++
++ /*
++ * Now do the initialization sequence.
++ */
++
++ /* set reset while enabling the clock and forcing them on throughout the core */
++ W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
++ dummy = R_SBREG(si, &sb->sbtmstatelow);
++ OSL_DELAY(1);
++
++ if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
++ W_SBREG(si, &sb->sbtmstatehigh, 0);
++ }
++ if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
++ AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
++ }
++
++ /* clear reset and allow it to propagate throughout the core */
++ W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
++ dummy = R_SBREG(si, &sb->sbtmstatelow);
++ OSL_DELAY(1);
++
++ /* leave clock enabled */
++ W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
++ dummy = R_SBREG(si, &sb->sbtmstatelow);
++ OSL_DELAY(1);
++}
++
++void
++sb_core_tofixup(sb_t *sbh)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++
++ si = SB_INFO(sbh);
++
++ if ( (BUSTYPE(si->sb.bustype) != PCI_BUS) || PCIE(si) || (PCI(si) && (si->sb.buscorerev >= 5)) )
++ return;
++
++ ASSERT(GOODREGS(si->curmap));
++ sb = REGS2SB(si->curmap);
++
++ if (BUSTYPE(si->sb.bustype) == SB_BUS) {
++ SET_SBREG(si, &sb->sbimconfiglow,
++ SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
++ (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
++ } else {
++ if (sb_coreid(sbh) == SB_PCI) {
++ SET_SBREG(si, &sb->sbimconfiglow,
++ SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
++ (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
++ } else {
++ SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
++ }
++ }
++
++ sb_commit(sbh);
++}
++
++/*
++ * Set the initiator timeout for the "master core".
++ * The master core is defined to be the core in control
++ * of the chip and so it issues accesses to non-memory
++ * locations (Because of dma *any* core can access memeory).
++ *
++ * The routine uses the bus to decide who is the master:
++ * SB_BUS => mips
++ * JTAG_BUS => chipc
++ * PCI_BUS => pci or pcie
++ * PCMCIA_BUS => pcmcia
++ * SDIO_BUS => pcmcia
++ *
++ * This routine exists so callers can disable initiator
++ * timeouts so accesses to very slow devices like otp
++ * won't cause an abort. The routine allows arbitrary
++ * settings of the service and request timeouts, though.
++ *
++ * Returns the timeout state before changing it or -1
++ * on error.
++ */
++
++#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
++
++uint32
++sb_set_initiator_to(sb_t *sbh, uint32 to)
++{
++ sb_info_t *si;
++ uint origidx, idx;
++ uint intr_val = 0;
++ uint32 tmp, ret = 0xffffffff;
++ sbconfig_t *sb;
++
++ si = SB_INFO(sbh);
++
++ if ((to & ~TO_MASK) != 0)
++ return ret;
++
++ /* Figure out the master core */
++ idx = BADIDX;
++ switch (BUSTYPE(si->sb.bustype)) {
++ case PCI_BUS:
++ idx = si->sb.buscoreidx;
++ break;
++ case JTAG_BUS:
++ idx = SB_CC_IDX;
++ break;
++ case PCMCIA_BUS:
++ case SDIO_BUS:
++ idx = sb_findcoreidx(si, SB_PCMCIA, 0);
++ break;
++ case SB_BUS:
++ if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
++ idx = sb_findcoreidx(si, SB_MIPS, 0);
++ break;
++ default:
++ ASSERT(0);
++ }
++ if (idx == BADIDX)
++ return ret;
++
++ INTR_OFF(si, intr_val);
++ origidx = sb_coreidx(sbh);
++
++ sb = REGS2SB(sb_setcoreidx(sbh, idx));
++
++ tmp = R_SBREG(si, &sb->sbimconfiglow);
++ ret = tmp & TO_MASK;
++ W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
++
++ sb_commit(sbh);
++ sb_setcoreidx(sbh, origidx);
++ INTR_RESTORE(si, intr_val);
++ return ret;
++}
++
++void
++sb_core_disable(sb_t *sbh, uint32 bits)
++{
++ sb_info_t *si;
++ volatile uint32 dummy;
++ uint32 rej;
++ sbconfig_t *sb;
++
++ si = SB_INFO(sbh);
++
++ ASSERT(GOODREGS(si->curmap));
++ sb = REGS2SB(si->curmap);
++
++ /* if core is already in reset, just return */
++ if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
++ return;
++
++ /* reject value changed between sonics 2.2 and 2.3 */
++ if (si->sb.sonicsrev == SONICS_2_2)
++ rej = (1 << SBTML_REJ_SHIFT);
++ else
++ rej = (2 << SBTML_REJ_SHIFT);
++
++ /* if clocks are not enabled, put into reset and return */
++ if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
++ goto disable;
++
++ /* set target reject and spin until busy is clear (preserve core-specific bits) */
++ OR_SBREG(si, &sb->sbtmstatelow, rej);
++ dummy = R_SBREG(si, &sb->sbtmstatelow);
++ OSL_DELAY(1);
++ SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
++
++ if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
++ OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
++ dummy = R_SBREG(si, &sb->sbimstate);
++ OSL_DELAY(1);
++ SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
++ }
++
++ /* set reset and reject while enabling the clocks */
++ W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
++ dummy = R_SBREG(si, &sb->sbtmstatelow);
++ OSL_DELAY(10);
++
++ /* don't forget to clear the initiator reject bit */
++ if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
++ AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
++
++disable:
++ /* leave reset and reject asserted */
++ W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
++ OSL_DELAY(1);
++}
++
++/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
++void
++sb_watchdog(sb_t *sbh, uint ticks)
++{
++ sb_info_t *si = SB_INFO(sbh);
++
++ /* instant NMI */
++ switch (si->gpioid) {
++ case SB_CC:
++ sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
++ break;
++ case SB_EXTIF:
++ sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
++ break;
++ }
++}
++
++/* initialize the pcmcia core */
++void
++sb_pcmcia_init(sb_t *sbh)
++{
++ sb_info_t *si;
++ uint8 cor;
++
++ si = SB_INFO(sbh);
++
++ /* enable d11 mac interrupts */
++ if (si->sb.chip == BCM4301_DEVICE_ID) {
++ /* Have to use FCR2 in 4301 */
++ OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
++ cor |= COR_IRQEN | COR_FUNEN;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
++ } else {
++ OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
++ cor |= COR_IRQEN | COR_FUNEN;
++ OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
++ }
++
++}
++
++
++/*
++ * Configure the pci core for pci client (NIC) action
++ * coremask is the bitvec of cores by index to be enabled.
++ */
++void
++sb_pci_setup(sb_t *sbh, uint coremask)
++{
++ sb_info_t *si;
++ sbconfig_t *sb;
++ sbpciregs_t *pciregs;
++ uint32 sbflag;
++ uint32 w;
++ uint idx;
++ int reg_val;
++
++ si = SB_INFO(sbh);
++
++ /* if not pci bus, we're done */
++ if (BUSTYPE(si->sb.bustype) != PCI_BUS)
++ return;
++
++ ASSERT(PCI(si) || PCIE(si));
++ ASSERT(si->sb.buscoreidx != BADIDX);
++
++ /* get current core index */
++ idx = si->curidx;
++
++ /* we interrupt on this backplane flag number */
++ ASSERT(GOODREGS(si->curmap));
++ sb = REGS2SB(si->curmap);
++ sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
++
++ /* switch over to pci core */
++ pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
++ sb = REGS2SB(pciregs);
++
++ /*
++ * Enable sb->pci interrupts. Assume
++ * PCI rev 2.3 support was added in pci core rev 6 and things changed..
++ */
++ if (PCIE(si) || (PCI(si) && ((si->sb.buscorerev) >= 6))) {
++ /* pci config write to set this core bit in PCIIntMask */
++ w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
++ w |= (coremask << PCI_SBIM_SHIFT);
++ OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
++ } else {
++ /* set sbintvec bit for our flag number */
++ OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
++ }
++
++ if (PCI(si)) {
++ OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
++ if (si->sb.buscorerev >= 11)
++ OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
++ if (si->sb.buscorerev < 5) {
++ SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
++ (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
++ sb_commit(sbh);
++ }
++ }
++
++ if (PCIE(si) && (si->sb.buscorerev == 0)) {
++ reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_TLP_WORKAROUNDSREG);
++ reg_val |= 0x8;
++ sb_pcie_writereg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_TLP_WORKAROUNDSREG, reg_val);
++
++ reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG);
++ reg_val &= ~(0x40);
++ sb_pcie_writereg(sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG, reg_val);
++
++ BCMINIT(sb_war30841)(si);
++ }
++
++ /* switch back to previous core */
++ sb_setcoreidx(sbh, idx);
++}
++
++uint32
++sb_base(uint32 admatch)
++{
++ uint32 base;
++ uint type;
++
++ type = admatch & SBAM_TYPE_MASK;
++ ASSERT(type < 3);
++
++ base = 0;
++
++ if (type == 0) {
++ base = admatch & SBAM_BASE0_MASK;
++ } else if (type == 1) {
++ ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
++ base = admatch & SBAM_BASE1_MASK;
++ } else if (type == 2) {
++ ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
++ base = admatch & SBAM_BASE2_MASK;
++ }
++
++ return (base);
++}
++
++uint32
++sb_size(uint32 admatch)
++{
++ uint32 size;
++ uint type;
++
++ type = admatch & SBAM_TYPE_MASK;
++ ASSERT(type < 3);
++
++ size = 0;
++
++ if (type == 0) {
++ size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
++ } else if (type == 1) {
++ ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
++ size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
++ } else if (type == 2) {
++ ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
++ size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
++ }
++
++ return (size);
++}
++
++/* return the core-type instantiation # of the current core */
++uint
++sb_coreunit(sb_t *sbh)
++{
++ sb_info_t *si;
++ uint idx;
++ uint coreid;
++ uint coreunit;
++ uint i;
++
++ si = SB_INFO(sbh);
++ coreunit = 0;
++
++ idx = si->curidx;
++
++ ASSERT(GOODREGS(si->curmap));
++ coreid = sb_coreid(sbh);
++
++ /* count the cores of our type */
++ for (i = 0; i < idx; i++)
++ if (si->coreid[i] == coreid)
++ coreunit++;
++
++ return (coreunit);
++}
++
++static INLINE uint32
++factor6(uint32 x)
++{
++ switch (x) {
++ case CC_F6_2: return 2;
++ case CC_F6_3: return 3;
++ case CC_F6_4: return 4;
++ case CC_F6_5: return 5;
++ case CC_F6_6: return 6;
++ case CC_F6_7: return 7;
++ default: return 0;
++ }
++}
++
++/* calculate the speed the SB would run at given a set of clockcontrol values */
++uint32
++sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
++{
++ uint32 n1, n2, clock, m1, m2, m3, mc;
++
++ n1 = n & CN_N1_MASK;
++ n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
++
++ if (pll_type == PLL_TYPE6) {
++ if (m & CC_T6_MMASK)
++ return CC_T6_M1;
++ else
++ return CC_T6_M0;
++ } else if ((pll_type == PLL_TYPE1) ||
++ (pll_type == PLL_TYPE3) ||
++ (pll_type == PLL_TYPE4) ||
++ (pll_type == PLL_TYPE7)) {
++ n1 = factor6(n1);
++ n2 += CC_F5_BIAS;
++ } else if (pll_type == PLL_TYPE2) {
++ n1 += CC_T2_BIAS;
++ n2 += CC_T2_BIAS;
++ ASSERT((n1 >= 2) && (n1 <= 7));
++ ASSERT((n2 >= 5) && (n2 <= 23));
++ } else if (pll_type == PLL_TYPE5) {
++ return (100000000);
++ } else
++ ASSERT(0);
++ /* PLL types 3 and 7 use BASE2 (25Mhz) */
++ if ((pll_type == PLL_TYPE3) ||
++ (pll_type == PLL_TYPE7)) {
++ clock = CC_CLOCK_BASE2 * n1 * n2;
++ }
++ else
++ clock = CC_CLOCK_BASE1 * n1 * n2;
++
++ if (clock == 0)
++ return 0;
++
++ m1 = m & CC_M1_MASK;
++ m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
++ m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
++ mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
++
++ if ((pll_type == PLL_TYPE1) ||
++ (pll_type == PLL_TYPE3) ||
++ (pll_type == PLL_TYPE4) ||
++ (pll_type == PLL_TYPE7)) {
++ m1 = factor6(m1);
++ if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
++ m2 += CC_F5_BIAS;
++ else
++ m2 = factor6(m2);
++ m3 = factor6(m3);
++
++ switch (mc) {
++ case CC_MC_BYPASS: return (clock);
++ case CC_MC_M1: return (clock / m1);
++ case CC_MC_M1M2: return (clock / (m1 * m2));
++ case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
++ case CC_MC_M1M3: return (clock / (m1 * m3));
++ default: return (0);
++ }
++ } else {
++ ASSERT(pll_type == PLL_TYPE2);
++
++ m1 += CC_T2_BIAS;
++ m2 += CC_T2M2_BIAS;
++ m3 += CC_T2_BIAS;
++ ASSERT((m1 >= 2) && (m1 <= 7));
++ ASSERT((m2 >= 3) && (m2 <= 10));
++ ASSERT((m3 >= 2) && (m3 <= 7));
++
++ if ((mc & CC_T2MC_M1BYP) == 0)
++ clock /= m1;
++ if ((mc & CC_T2MC_M2BYP) == 0)
++ clock /= m2;
++ if ((mc & CC_T2MC_M3BYP) == 0)
++ clock /= m3;
++
++ return(clock);
++ }
++}
++
++/* returns the current speed the SB is running at */
++uint32
++sb_clock(sb_t *sbh)
++{
++ sb_info_t *si;
++ extifregs_t *eir;
++ chipcregs_t *cc;
++ uint32 n, m;
++ uint idx;
++ uint32 pll_type, rate;
++ uint intr_val = 0;
++
++ si = SB_INFO(sbh);
++ idx = si->curidx;
++ pll_type = PLL_TYPE1;
++
++ INTR_OFF(si, intr_val);
++
++ /* switch to extif or chipc core */
++ if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
++ n = R_REG(&eir->clockcontrol_n);
++ m = R_REG(&eir->clockcontrol_sb);
++ } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
++ pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
++ n = R_REG(&cc->clockcontrol_n);
++ if (pll_type == PLL_TYPE6)
++ m = R_REG(&cc->clockcontrol_mips);
++ else if (pll_type == PLL_TYPE3)
++ {
++ // Added by Chen-I for 5365
++ if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
++ m = R_REG(&cc->clockcontrol_sb);
++ else
++ m = R_REG(&cc->clockcontrol_m2);
++ }
++ else
++ m = R_REG(&cc->clockcontrol_sb);
++ } else {
++ INTR_RESTORE(si, intr_val);
++ return 0;
++ }
++
++ // Added by Chen-I for 5365
++ if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
++ {
++ rate = 100000000;
++ }
++ else
++ {
++ /* calculate rate */
++ rate = sb_clock_rate(pll_type, n, m);
++ if (pll_type == PLL_TYPE3)
++ rate = rate / 2;
++ }
++
++ /* switch back to previous core */
++ sb_setcoreidx(sbh, idx);
++
++ INTR_RESTORE(si, intr_val);
++
++ return rate;
++}
++
++/* change logical "focus" to the gpio core for optimized access */
++void*
++sb_gpiosetcore(sb_t *sbh)
++{
++ sb_info_t *si;
++
++ si = SB_INFO(sbh);
++
++ return (sb_setcoreidx(sbh, si->gpioidx));
++}
++
++/* mask&set gpiocontrol bits */
++uint32
++sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
++{
++ sb_info_t *si;
++ uint regoff;
++
++ si = SB_INFO(sbh);
++ regoff = 0;
++
++ priority = GPIO_DRV_PRIORITY; /* compatibility hack */
++
++ /* gpios could be shared on router platforms */
++ if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
++ mask = priority ? (sb_gpioreservation & mask) :
++ ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
++ val &= mask;
++ }
++
++ switch (si->gpioid) {
++ case SB_CC:
++ regoff = OFFSETOF(chipcregs_t, gpiocontrol);
++ break;
++
++ case SB_PCI:
++ regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
++ break;
++
++ case SB_EXTIF:
++ return (0);
++ }
++
++ return (sb_corereg(si, si->gpioidx, regoff, mask, val));
++}
++
++/* mask&set gpio output enable bits */
++uint32
++sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
++{
++ sb_info_t *si;
++ uint regoff;
++
++ si = SB_INFO(sbh);
++ regoff = 0;
++
++ priority = GPIO_DRV_PRIORITY; /* compatibility hack */
++
++ /* gpios could be shared on router platforms */
++ if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
++ mask = priority ? (sb_gpioreservation & mask) :
++ ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
++ val &= mask;
++ }
++
++ switch (si->gpioid) {
++ case SB_CC:
++ regoff = OFFSETOF(chipcregs_t, gpioouten);
++ break;
++
++ case SB_PCI:
++ regoff = OFFSETOF(sbpciregs_t, gpioouten);
++ break;
++
++ case SB_EXTIF:
++ regoff = OFFSETOF(extifregs_t, gpio[0].outen);
++ break;
++ }
++
++ return (sb_corereg(si, si->gpioidx, regoff, mask, val));
++}
++
++/* mask&set gpio output bits */
++uint32
++sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
++{
++ sb_info_t *si;
++ uint regoff;
++
++ si = SB_INFO(sbh);
++ regoff = 0;
++
++ priority = GPIO_DRV_PRIORITY; /* compatibility hack */
++
++ /* gpios could be shared on router platforms */
++ if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
++ mask = priority ? (sb_gpioreservation & mask) :
++ ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
++ val &= mask;
++ }
++
++ switch (si->gpioid) {
++ case SB_CC:
++ regoff = OFFSETOF(chipcregs_t, gpioout);
++ break;
++
++ case SB_PCI:
++ regoff = OFFSETOF(sbpciregs_t, gpioout);
++ break;
++
++ case SB_EXTIF:
++ regoff = OFFSETOF(extifregs_t, gpio[0].out);
++ break;
++ }
++
++ return (sb_corereg(si, si->gpioidx, regoff, mask, val));
++}
projects / openwrt.git / commitdiff