ar71xx: reset the mdio bus on ar7241/ar7242
authornbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Sun, 28 Mar 2010 00:35:44 +0000 (00:35 +0000)
committernbd <nbd@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Sun, 28 Mar 2010 00:35:44 +0000 (00:35 +0000)
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20528 3c298f89-4303-0410-b956-a3cf2f4a3e73

target/linux/ar71xx/files/arch/mips/ar71xx/devices.c
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h

index a7714ee..f809dea 100644 (file)
@@ -436,9 +436,12 @@ void __init ar71xx_add_device_eth(unsigned int id)
                pdata->has_gbit = 1;
                break;
 
-       case AR71XX_SOC_AR7240:
        case AR71XX_SOC_AR7241:
        case AR71XX_SOC_AR7242:
+               ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
+               ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
+               /* fall through */
+       case AR71XX_SOC_AR7240:
                pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
                                      : ar724x_ddr_flush_ge0;
                pdata->set_pll =  id ? ar724x_set_pll_ge1
index 7a7d75c..c6a5a40 100644 (file)
@@ -427,6 +427,8 @@ void ar71xx_ddr_flush(u32 reg);
 #define RESET_MODULE_PCI_BUS           BIT(1)
 #define RESET_MODULE_PCI_CORE          BIT(0)
 
+#define AR724X_RESET_GE1_MDIO          BIT(23)
+#define AR724X_RESET_GE0_MDIO          BIT(22)
 #define AR724X_RESET_PCIE_PHY_SERIAL   BIT(10)
 #define AR724X_RESET_PCIE_PHY          BIT(7)
 #define AR724X_RESET_PCIE              BIT(6)
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