bcm63xx: add missing bits from extirq support
authorjogo <jogo@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Wed, 28 Mar 2012 20:42:15 +0000 (20:42 +0000)
committerjogo <jogo@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Wed, 28 Mar 2012 20:42:15 +0000 (20:42 +0000)
Add missing external IRQ code parts for older chips in the new code.

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31128 3c298f89-4303-0410-b956-a3cf2f4a3e73

target/linux/brcm63xx/patches-3.3/305-missing_ext_irq_bits.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.3/407-bcm6345_enet.patch
target/linux/brcm63xx/patches-3.3/408-6358-enet1-external-mii-clk.patch
target/linux/brcm63xx/patches-3.3/409-spi.patch

diff --git a/target/linux/brcm63xx/patches-3.3/305-missing_ext_irq_bits.patch b/target/linux/brcm63xx/patches-3.3/305-missing_ext_irq_bits.patch
new file mode 100644 (file)
index 0000000..a350c4d
--- /dev/null
@@ -0,0 +1,96 @@
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -45,8 +45,8 @@ static void __internal_irq_unmask_64(uns
+ #define is_ext_irq_cascaded   0
+ #define ext_irq_start         0
+ #define ext_irq_end           0
+-#define ext_irq_count         0
+-#define ext_irq_cfg_reg1      0
++#define ext_irq_count         4
++#define ext_irq_cfg_reg1      PERF_EXTIRQ_CFG_REG_6345
+ #define ext_irq_cfg_reg2      0
+ #endif
+ #ifdef CONFIG_BCM63XX_CPU_6348
+@@ -122,11 +122,15 @@ static void bcm63xx_init_irq(void)
+               irq_stat_addr += PERF_IRQSTAT_6338_REG;
+               irq_mask_addr += PERF_IRQMASK_6338_REG;
+               irq_bits = 32;
++              ext_irq_count = 4;
++              ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
+               break;
+       case BCM6345_CPU_ID:
+               irq_stat_addr += PERF_IRQSTAT_6345_REG;
+               irq_mask_addr += PERF_IRQMASK_6345_REG;
+               irq_bits = 32;
++              ext_irq_count = 4;
++              ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
+               break;
+       case BCM6348_CPU_ID:
+               irq_stat_addr += PERF_IRQSTAT_6348_REG;
+@@ -413,7 +417,8 @@ static int bcm63xx_external_irq_set_type
+       reg = bcm_perf_readl(regaddr);
+       irq %= 4;
+-      if (BCMCPU_IS_6348()) {
++      switch (bcm63xx_get_cpu_id()) {
++      case BCM6348_CPU_ID:
+               if (levelsense)
+                       reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
+               else
+@@ -426,9 +431,12 @@ static int bcm63xx_external_irq_set_type
+                       reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
+               else
+                       reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
+-      }
++              break;
+-      if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
++      case BCM6338_CPU_ID:
++      case BCM6345_CPU_ID:
++      case BCM6358_CPU_ID:
++      case BCM6368_CPU_ID:
+               if (levelsense)
+                       reg |= EXTIRQ_CFG_LEVELSENSE(irq);
+               else
+@@ -441,6 +449,9 @@ static int bcm63xx_external_irq_set_type
+                       reg |= EXTIRQ_CFG_BOTHEDGE(irq);
+               else
+                       reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
++              break;
++      default:
++              BUG();
+       }
+       bcm_perf_writel(reg, regaddr);
+--- a/arch/mips/bcm63xx/setup.c
++++ b/arch/mips/bcm63xx/setup.c
+@@ -71,6 +71,9 @@ void bcm63xx_machine_reboot(void)
+       case BCM6338_CPU_ID:
+               perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
+               break;
++      case BCM6345_CPU_ID:
++              perf_regs[0] = PERF_EXTIRQ_CFG_REG_6345;
++              break;
+       case BCM6348_CPU_ID:
+               perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348;
+               break;
+@@ -80,6 +83,9 @@ void bcm63xx_machine_reboot(void)
+       }
+       for (i = 0; i < 2; i++) {
++              if (!perf_regs[i])
++                      break;
++
+               reg = bcm_perf_readl(perf_regs[i]);
+               if (BCMCPU_IS_6348()) {
+                       reg &= ~EXTIRQ_CFG_MASK_ALL_6348;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -134,6 +134,7 @@
+ /* External Interrupt Configuration register */
+ #define PERF_EXTIRQ_CFG_REG_6338      0x14
++#define PERF_EXTIRQ_CFG_REG_6345      0x14
+ #define PERF_EXTIRQ_CFG_REG_6348      0x14
+ #define PERF_EXTIRQ_CFG_REG_6358      0x14
+ #define PERF_EXTIRQ_CFG_REG_6368      0x18
index 1f814ed..aac4de6 100644 (file)
@@ -25,7 +25,7 @@
                                        CKCTL_6345_ADSLPHY_EN)
  
  #define CKCTL_6348_ADSLPHY_EN         (1 << 0)
                                        CKCTL_6345_ADSLPHY_EN)
  
  #define CKCTL_6348_ADSLPHY_EN         (1 << 0)
-@@ -701,6 +700,39 @@
+@@ -702,6 +701,39 @@
  #define ENETSW_MIB_REG_COUNT          47
  
  
  #define ENETSW_MIB_REG_COUNT          47
  
  
index c1f044c..205be4b 100644 (file)
@@ -11,7 +11,7 @@
        bcm_gpio_writel(val, GPIO_MODE_REG);
 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
        bcm_gpio_writel(val, GPIO_MODE_REG);
 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -466,6 +466,8 @@
+@@ -467,6 +467,8 @@
  #define GPIO_MODE_6358_EXTRA_SPI_SS   (1 << 7)
  #define GPIO_MODE_6358_SERIAL_LED     (1 << 10)
  #define GPIO_MODE_6358_UTOPIA         (1 << 12)
  #define GPIO_MODE_6358_EXTRA_SPI_SS   (1 << 7)
  #define GPIO_MODE_6358_SERIAL_LED     (1 << 10)
  #define GPIO_MODE_6358_UTOPIA         (1 << 12)
index eea8082..e8d2dd7 100644 (file)
  #define BCM_6358_DSL_IRQ              (IRQ_INTERNAL_BASE + 29)
 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  #define BCM_6358_DSL_IRQ              (IRQ_INTERNAL_BASE + 29)
 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -1007,4 +1007,116 @@
+@@ -1008,4 +1008,116 @@
  #define M2M_SRCID_REG(x)              ((x) * 0x40 + 0x14)
  #define M2M_DSTID_REG(x)              ((x) * 0x40 + 0x18)
  
  #define M2M_SRCID_REG(x)              ((x) * 0x40 + 0x14)
  #define M2M_DSTID_REG(x)              ((x) * 0x40 + 0x18)
  
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