bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
/* disable all hardware blocks clock for now */
bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
/* disable all hardware blocks clock for now */
+ if (BCMCPU_IS_6338())
+ mask = CKCTL_6338_ALL_SAFE_EN;
+ else if (BCMCPU_IS_6345())
+ mask = CKCTL_6345_UART_EN;
+ else if (BCMCPU_IS_6348())
mask = CKCTL_6348_ALL_SAFE_EN;
else
/* BCMCPU_IS_6358() */
mask = CKCTL_6348_ALL_SAFE_EN;
else
/* BCMCPU_IS_6358() */
CKCTL_6338_SAR_EN | \
CKCTL_6338_SPI_EN)
CKCTL_6338_SAR_EN | \
CKCTL_6338_SPI_EN)
+#define CKCTL_6345_CPU_EN (1 << 0)
+#define CKCTL_6345_UART_EN (1 << 3)
+#define CKCTL_6345_ENET_EN (1 << 7)
+#define CKCTL_6345_USBH_EN (1 << 8)
+
#define CKCTL_6348_ADSLPHY_EN (1 << 0)
#define CKCTL_6348_MPI_EN (1 << 1)
#define CKCTL_6348_SDRAM_EN (1 << 2)
#define CKCTL_6348_ADSLPHY_EN (1 << 0)
#define CKCTL_6348_MPI_EN (1 << 1)
#define CKCTL_6348_SDRAM_EN (1 << 2)