--- /dev/null
+#
+# Copyright (C) 2007 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+# $Id: Makefile 7440 2007-06-02 02:22:01Z nbd $
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=bcm43xx-mac80211
+PKG_RELEASE:=1
+
+PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)
+
+include $(INCLUDE_DIR)/package.mk
+
+# This horrible, horrible hack is because I can't work out ow to add
+# CONFIG_* definitions to a kernel config from an external module dir.
+# It should come from a proper configuration based on the Kconfig in the src
+# directory.
+MAKE_CONFIGS=CONFIG_BCM43XX_MAC80211=m CONFIG_BCM43XX_MAC80211_PCI=y \
+ CONFIG_BCM43XX_MAC80211_DEBUG=y CONFIG_BCM43XX_MAC80211_DMA=y \
+ CONFIG_BCM43XX_MAC80211_PIO=y CONFIG_BCM43XX_MAC80211_DMA_AND_PIO_MODE=y
+
+BUILDFLAGS+=$(patsubst CONFIG_%, -DCONFIG_%, $(MAKE_CONFIGS))
+
+define KernelPackage/bcm43xx-mac80211
+ TITLE:=Broadcom 43xx wireless support
+ DESCRIPTION:=Kernel module for Broadcom 43xx wireless support (mac80211)
+ VERSION:=$(PKG_RELEASE)+$(LINUX_VERSION)-$(BOARD)-$(LINUX_RELEASE)
+ DEPENDS:=@LINUX_2_6 +kmod-mac80211
+ SUBMENU:=Wireless Drivers
+# AUTOLOAD:=$(call AutoLoad,30,bcm43xx-mac80211)
+ FILES:=$(PKG_BUILD_DIR)/bcm43xx-mac80211.$(LINUX_KMOD_SUFFIX)
+endef
+
+define Build/Prepare
+ mkdir -p $(PKG_BUILD_DIR)
+ $(CP) ./src/bcm43xx/* $(PKG_BUILD_DIR)/
+endef
+
+define Build/Compile
+ $(MAKE) $(MAKE_CONFIGS) -C "$(LINUX_DIR)" \
+ CROSS_COMPILE="$(TARGET_CROSS)" \
+ ARCH="$(LINUX_KARCH)" \
+ EXTRA_CFLAGS="$(BUILDFLAGS)" \
+ SUBDIRS="$(PKG_BUILD_DIR)" \
+ modules
+endef
+
+$(eval $(call KernelPackage,bcm43xx-mac80211))
--- /dev/null
+source "drivers/net/wireless/mac80211/bcm43xx/Kconfig"
--- /dev/null
+obj-$(CONFIG_BCM43XX_MAC80211) += bcm43xx/
--- /dev/null
+This directory contains IEEE 802.11 wireless LAN drivers that are using
+Devicescape IEEE 802.11 stack (net/mac80211).
--- /dev/null
+config BCM43XX_MAC80211
+ tristate "Broadcom BCM43xx wireless support (mac80211 stack)"
+ depends on MAC80211 && WLAN_80211 && EXPERIMENTAL
+ select FW_LOADER
+ select SSB
+ select HW_RANDOM
+ ---help---
+ This is an experimental driver for the Broadcom 43xx wireless chip,
+ found in the Apple Airport Extreme and various other devices.
+
+config BCM43XX_MAC80211_PCI
+ bool "BCM43xx PCI device support"
+ depends on BCM43XX_MAC80211 && PCI
+ select SSB_PCIHOST
+ select SSB_DRIVER_PCICORE
+ default y
+ ---help---
+ Broadcom 43xx PCI device support.
+
+ Say Y, if you have a BCM43xx device connected through the PCI bus.
+ Please note that most PC-CARD devices are (to the kernel) PCI devices,
+ too and not PCMCIA.
+ It's safe to select Y here, even if you don't have a BCM43xx PCI device.
+
+config BCM43XX_MAC80211_PCMCIA
+ bool "BCM43xx PCMCIA device support"
+ depends on BCM43XX_MAC80211 && PCMCIA
+ select SSB_PCMCIAHOST
+ ---help---
+ Broadcom 43xx PCMCIA device support.
+
+ Support for 16bit PCMCIA devices.
+ Please note that most PC-CARD devices are _NOT_ 16bit PCMCIA
+ devices, but 32bit CardBUS devices. CardBUS devices are supported
+ by "BCM43xx PCI device support".
+
+ With this config option you can drive bcm43xx cards in
+ CompactFlash formfactor in a PCMCIA adaptor.
+ CF bcm43xx cards can sometimes be found in handheld PCs.
+
+ It's safe to select Y here, even if you don't have a BCM43xx PCMCIA device.
+
+ If unsure, say N.
+
+config BCM43XX_MAC80211_DEBUG
+ bool "Broadcom BCM43xx debugging (RECOMMENDED)"
+ depends on BCM43XX_MAC80211
+ select SSB_DEBUG if !SSB_SILENT
+ default y
+ ---help---
+ Broadcom 43xx debugging messages.
+ Say Y, because the driver is still very experimental and
+ this will help you get it running.
+
+config BCM43XX_MAC80211_DMA
+ bool
+ depends on BCM43XX_MAC80211
+config BCM43XX_MAC80211_PIO
+ bool
+ depends on BCM43XX_MAC80211
+
+choice
+ prompt "BCM43xx data transfer mode"
+ depends on BCM43XX_MAC80211
+ default BCM43XX_MAC80211_DMA_AND_PIO_MODE
+
+config BCM43XX_MAC80211_DMA_AND_PIO_MODE
+ bool "DMA + PIO"
+ select BCM43XX_MAC80211_DMA
+ select BCM43XX_MAC80211_PIO
+ ---help---
+ Include both, Direct Memory Access (DMA) and Programmed I/O (PIO)
+ data transfer modes.
+ The actually used mode is selectable through the module
+ parameter "pio". If the module parameter is pio=0, DMA is used.
+ Otherwise PIO is used. DMA is default.
+
+ If unsure, choose this option.
+
+config BCM43XX_MAC80211_DMA_MODE
+ bool "DMA (Direct Memory Access) only"
+ select BCM43XX_MAC80211_DMA
+ ---help---
+ Only include Direct Memory Access (DMA).
+ This reduces the size of the driver module, by omitting the PIO code.
+
+config BCM43XX_MAC80211_PIO_MODE
+ bool "PIO (Programmed I/O) only"
+ select BCM43XX_MAC80211_PIO
+ ---help---
+ Only include Programmed I/O (PIO).
+ This reduces the size of the driver module, by omitting the DMA code.
+ Please note that PIO transfers are slow (compared to DMA).
+
+ Also note that not all devices of the 43xx series support PIO.
+ The 4306 (Apple Airport Extreme and others) supports PIO, while
+ the 4318 is known to _not_ support PIO.
+
+ Only use PIO, if DMA does not work for you.
+
+endchoice
--- /dev/null
+obj-$(CONFIG_BCM43XX_MAC80211) += bcm43xx-mac80211.o
+
+bcm43xx-mac80211-obj-$(CONFIG_BCM43XX_MAC80211_PCMCIA) += bcm43xx_pcmcia.o
+
+bcm43xx-mac80211-obj-$(CONFIG_BCM43XX_MAC80211_DEBUG) += bcm43xx_debugfs.o
+
+bcm43xx-mac80211-obj-$(CONFIG_BCM43XX_MAC80211_DMA) += bcm43xx_dma.o
+bcm43xx-mac80211-obj-$(CONFIG_BCM43XX_MAC80211_PIO) += bcm43xx_pio.o
+
+bcm43xx-mac80211-objs := bcm43xx_main.o \
+ bcm43xx_tables.o \
+ bcm43xx_phy.o \
+ bcm43xx_power.o \
+ bcm43xx_sysfs.o \
+ bcm43xx_leds.o \
+ bcm43xx_xmit.o \
+ bcm43xx_lo.o \
+ $(bcm43xx-mac80211-obj-y)
--- /dev/null
+#ifndef BCM43xx_H_
+#define BCM43xx_H_
+
+#include <linux/hw_random.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/stringify.h>
+#include <linux/netdevice.h>
+#include <linux/pci.h>
+#include <asm/atomic.h>
+#include <asm/io.h>
+
+#include <linux/ssb/ssb.h>
+#include <linux/ssb/ssb_driver_chipcommon.h>
+
+#include <linux/wireless.h>
+#include <net/mac80211.h>
+
+#include "bcm43xx_debugfs.h"
+#include "bcm43xx_leds.h"
+#include "bcm43xx_lo.h"
+#include "bcm43xx_phy.h"
+
+
+#define PFX KBUILD_MODNAME ": "
+
+#define BCM43xx_IRQWAIT_MAX_RETRIES 50
+
+#define BCM43xx_IO_SIZE 8192
+
+#define BCM43xx_RX_MAX_SSI 60
+
+/* MMIO offsets */
+#define BCM43xx_MMIO_DMA0_REASON 0x20
+#define BCM43xx_MMIO_DMA0_IRQ_MASK 0x24
+#define BCM43xx_MMIO_DMA1_REASON 0x28
+#define BCM43xx_MMIO_DMA1_IRQ_MASK 0x2C
+#define BCM43xx_MMIO_DMA2_REASON 0x30
+#define BCM43xx_MMIO_DMA2_IRQ_MASK 0x34
+#define BCM43xx_MMIO_DMA3_REASON 0x38
+#define BCM43xx_MMIO_DMA3_IRQ_MASK 0x3C
+#define BCM43xx_MMIO_DMA4_REASON 0x40
+#define BCM43xx_MMIO_DMA4_IRQ_MASK 0x44
+#define BCM43xx_MMIO_DMA5_REASON 0x48
+#define BCM43xx_MMIO_DMA5_IRQ_MASK 0x4C
+#define BCM43xx_MMIO_MACCTL 0x120
+#define BCM43xx_MMIO_STATUS_BITFIELD 0x120//TODO replace all instances by MACCTL
+#define BCM43xx_MMIO_STATUS2_BITFIELD 0x124
+#define BCM43xx_MMIO_GEN_IRQ_REASON 0x128
+#define BCM43xx_MMIO_GEN_IRQ_MASK 0x12C
+#define BCM43xx_MMIO_RAM_CONTROL 0x130
+#define BCM43xx_MMIO_RAM_DATA 0x134
+#define BCM43xx_MMIO_PS_STATUS 0x140
+#define BCM43xx_MMIO_RADIO_HWENABLED_HI 0x158
+#define BCM43xx_MMIO_SHM_CONTROL 0x160
+#define BCM43xx_MMIO_SHM_DATA 0x164
+#define BCM43xx_MMIO_SHM_DATA_UNALIGNED 0x166
+#define BCM43xx_MMIO_XMITSTAT_0 0x170
+#define BCM43xx_MMIO_XMITSTAT_1 0x174
+#define BCM43xx_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
+#define BCM43xx_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
+
+/* 32-bit DMA */
+#define BCM43xx_MMIO_DMA32_BASE0 0x200
+#define BCM43xx_MMIO_DMA32_BASE1 0x220
+#define BCM43xx_MMIO_DMA32_BASE2 0x240
+#define BCM43xx_MMIO_DMA32_BASE3 0x260
+#define BCM43xx_MMIO_DMA32_BASE4 0x280
+#define BCM43xx_MMIO_DMA32_BASE5 0x2A0
+/* 64-bit DMA */
+#define BCM43xx_MMIO_DMA64_BASE0 0x200
+#define BCM43xx_MMIO_DMA64_BASE1 0x240
+#define BCM43xx_MMIO_DMA64_BASE2 0x280
+#define BCM43xx_MMIO_DMA64_BASE3 0x2C0
+#define BCM43xx_MMIO_DMA64_BASE4 0x300
+#define BCM43xx_MMIO_DMA64_BASE5 0x340
+/* PIO */
+#define BCM43xx_MMIO_PIO1_BASE 0x300
+#define BCM43xx_MMIO_PIO2_BASE 0x310
+#define BCM43xx_MMIO_PIO3_BASE 0x320
+#define BCM43xx_MMIO_PIO4_BASE 0x330
+
+#define BCM43xx_MMIO_PHY_VER 0x3E0
+#define BCM43xx_MMIO_PHY_RADIO 0x3E2
+#define BCM43xx_MMIO_PHY0 0x3E6
+#define BCM43xx_MMIO_ANTENNA 0x3E8
+#define BCM43xx_MMIO_CHANNEL 0x3F0
+#define BCM43xx_MMIO_CHANNEL_EXT 0x3F4
+#define BCM43xx_MMIO_RADIO_CONTROL 0x3F6
+#define BCM43xx_MMIO_RADIO_DATA_HIGH 0x3F8
+#define BCM43xx_MMIO_RADIO_DATA_LOW 0x3FA
+#define BCM43xx_MMIO_PHY_CONTROL 0x3FC
+#define BCM43xx_MMIO_PHY_DATA 0x3FE
+#define BCM43xx_MMIO_MACFILTER_CONTROL 0x420
+#define BCM43xx_MMIO_MACFILTER_DATA 0x422
+#define BCM43xx_MMIO_RCMTA_COUNT 0x43C
+#define BCM43xx_MMIO_RADIO_HWENABLED_LO 0x49A
+#define BCM43xx_MMIO_GPIO_CONTROL 0x49C
+#define BCM43xx_MMIO_GPIO_MASK 0x49E
+#define BCM43xx_MMIO_TSF_0 0x632 /* core rev < 3 only */
+#define BCM43xx_MMIO_TSF_1 0x634 /* core rev < 3 only */
+#define BCM43xx_MMIO_TSF_2 0x636 /* core rev < 3 only */
+#define BCM43xx_MMIO_TSF_3 0x638 /* core rev < 3 only */
+#define BCM43xx_MMIO_RNG 0x65A
+#define BCM43xx_MMIO_POWERUP_DELAY 0x6A8
+
+/* SPROM boardflags_lo values */
+#define BCM43xx_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
+#define BCM43xx_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
+#define BCM43xx_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
+#define BCM43xx_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
+#define BCM43xx_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
+#define BCM43xx_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
+#define BCM43xx_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
+#define BCM43xx_BFL_ENETADM 0x0080 /* has ADMtek switch */
+#define BCM43xx_BFL_ENETVLAN 0x0100 /* can do vlan */
+#define BCM43xx_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
+#define BCM43xx_BFL_NOPCI 0x0400 /* leaves PCI floating */
+#define BCM43xx_BFL_FEM 0x0800 /* supports the Front End Module */
+#define BCM43xx_BFL_EXTLNA 0x1000 /* has an external LNA */
+#define BCM43xx_BFL_HGPA 0x2000 /* had high gain PA */
+#define BCM43xx_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
+#define BCM43xx_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
+
+/* GPIO register offset, in both ChipCommon and PCI core. */
+#define BCM43xx_GPIO_CONTROL 0x6c
+
+/* SHM Routing */
+enum {
+ BCM43xx_SHM_UCODE, /* Microcode memory */
+ BCM43xx_SHM_SHARED, /* Shared memory */
+ BCM43xx_SHM_SCRATCH, /* Scratch memory */
+ BCM43xx_SHM_HW, /* Internal hardware register */
+ BCM43xx_SHM_RCMTA, /* Receive match transmitter address (rev >= 5 only) */
+};
+/* SHM Routing modifiers */
+#define BCM43xx_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
+#define BCM43xx_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
+#define BCM43xx_SHM_AUTOINC_RW (BCM43xx_SHM_AUTOINC_R | \
+ BCM43xx_SHM_AUTOINC_W)
+
+/* Misc SHM_SHARED offsets */
+#define BCM43xx_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
+#define BCM43xx_SHM_SH_PCTLWDPOS 0x0008
+#define BCM43xx_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */
+#define BCM43xx_SHM_SH_PHYVER 0x0050 /* PHY version */
+#define BCM43xx_SHM_SH_PHYTYPE 0x0052 /* PHY type */
+#define BCM43xx_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */
+#define BCM43xx_SHM_SH_HOSTFLO 0x005E /* Hostflags for ucode options (low) */
+#define BCM43xx_SHM_SH_HOSTFHI 0x0060 /* Hostflags for ucode options (high) */
+#define BCM43xx_SHM_SH_RADAR 0x0066 /* Radar register */
+#define BCM43xx_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */
+#define BCM43xx_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */
+#define BCM43xx_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */
+#define BCM43xx_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5Ghz channel */
+#define BCM43xx_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */
+/* SHM_SHARED TX FIFO variables */
+#define BCM43xx_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */
+#define BCM43xx_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */
+#define BCM43xx_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */
+#define BCM43xx_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */
+/* SHM_SHARED background noise */
+#define BCM43xx_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */
+#define BCM43xx_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */
+#define BCM43xx_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */
+/* SHM_SHARED crypto engine */
+#define BCM43xx_SHM_SH_DEFAULTIV 0x003C /* Default IV location */
+#define BCM43xx_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */
+#define BCM43xx_SHM_SH_KTP 0x0056 /* Key table pointer */
+#define BCM43xx_SHM_SH_TKIPTSCTTAK 0x0318
+#define BCM43xx_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */
+#define BCM43xx_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */
+/* SHM_SHARED WME variables */
+#define BCM43xx_SHM_SH_EDCFSTAT 0x000E /* EDCF status */
+#define BCM43xx_SHM_SH_TXFCUR 0x0030 /* TXF current index */
+#define BCM43xx_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */
+/* SHM_SHARED powersave mode related */
+#define BCM43xx_SHM_SH_SLOTT 0x0010 /* Slot time */
+#define BCM43xx_SHM_SH_DTIMPER 0x0012 /* DTIM period */
+#define BCM43xx_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */
+/* SHM_SHARED beacon variables */
+#define BCM43xx_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
+#define BCM43xx_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
+#define BCM43xx_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
+#define BCM43xx_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */
+#define BCM43xx_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */
+#define BCM43xx_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */
+#define BCM43xx_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */
+/* SHM_SHARED ACK/CTS control */
+#define BCM43xx_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */
+/* SHM_SHARED probe response variables */
+#define BCM43xx_SHM_SH_PRSSID 0x0160 /* Probe Response SSID */
+#define BCM43xx_SHM_SH_PRSSIDLEN 0x0048 /* Probe Response SSID length */
+#define BCM43xx_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
+#define BCM43xx_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
+#define BCM43xx_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */
+/* SHM_SHARED rate tables */
+#define BCM43xx_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */
+#define BCM43xx_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */
+#define BCM43xx_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */
+#define BCM43xx_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */
+/* SHM_SHARED microcode soft registers */
+#define BCM43xx_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
+#define BCM43xx_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
+#define BCM43xx_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
+#define BCM43xx_SHM_SH_UCODETIME 0x0006 /* Microcode time */
+#define BCM43xx_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */
+#define BCM43xx_SHM_SH_UCODESTAT_INVALID 0
+#define BCM43xx_SHM_SH_UCODESTAT_INIT 1
+#define BCM43xx_SHM_SH_UCODESTAT_ACTIVE 2
+#define BCM43xx_SHM_SH_UCODESTAT_SUSP 3 /* suspended */
+#define BCM43xx_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */
+#define BCM43xx_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */
+#define BCM43xx_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
+#define BCM43xx_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
+
+/* SHM_SCRATCH offsets */
+#define BCM43xx_SHM_SC_MINCONT 0x0003 /* Minimum contention window */
+#define BCM43xx_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */
+#define BCM43xx_SHM_SC_CURCONT 0x0005 /* Current contention window */
+#define BCM43xx_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */
+#define BCM43xx_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */
+#define BCM43xx_SHM_SC_DTIMC 0x0008 /* Current DTIM count */
+#define BCM43xx_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */
+#define BCM43xx_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */
+#define BCM43xx_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */
+#define BCM43xx_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */
+
+
+/* Hardware Radio Enable masks */
+#define BCM43xx_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
+#define BCM43xx_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
+
+/* HostFlags. See bcm43xx_hf_read/write() */
+#define BCM43xx_HF_ANTDIVHELP 0x00000001 /* ucode antenna div helper */
+#define BCM43xx_HF_SYMW 0x00000002 /* G-PHY SYM workaround */
+#define BCM43xx_HF_RXPULLW 0x00000004 /* RX pullup workaround */
+#define BCM43xx_HF_CCKBOOST 0x00000008 /* 4dB CCK power boost (exclusive with OFDM boost) */
+#define BCM43xx_HF_BTCOEX 0x00000010 /* Bluetooth coexistance */
+#define BCM43xx_HF_GDCW 0x00000020 /* G-PHY DV canceller filter bw workaround */
+#define BCM43xx_HF_OFDMPABOOST 0x00000040 /* Enable PA gain boost for OFDM */
+#define BCM43xx_HF_ACPR 0x00000080 /* Disable for Japan, channel 14 */
+#define BCM43xx_HF_EDCF 0x00000100 /* on if WME and MAC suspended */
+#define BCM43xx_HF_TSSIRPSMW 0x00000200 /* TSSI reset PSM ucode workaround */
+#define BCM43xx_HF_DSCRQ 0x00000400 /* Disable slow clock request in ucode */
+#define BCM43xx_HF_ACIW 0x00000800 /* ACI workaround: shift bits by 2 on PHY CRS */
+#define BCM43xx_HF_2060W 0x00001000 /* 2060 radio workaround */
+#define BCM43xx_HF_RADARW 0x00002000 /* Radar workaround */
+#define BCM43xx_HF_USEDEFKEYS 0x00004000 /* Enable use of default keys */
+#define BCM43xx_HF_BT4PRIOCOEX 0x00010000 /* Bluetooth 2-priority coexistance */
+#define BCM43xx_HF_FWKUP 0x00020000 /* Fast wake-up ucode */
+#define BCM43xx_HF_VCORECALC 0x00040000 /* Force VCO recalculation when powering up synthpu */
+#define BCM43xx_HF_PCISCW 0x00080000 /* PCI slow clock workaround */
+#define BCM43xx_HF_4318TSSI 0x00200000 /* 4318 TSSI */
+#define BCM43xx_HF_FBCMCFIFO 0x00400000 /* Flush bcast/mcast FIFO immediately */
+#define BCM43xx_HF_HWPCTL 0x00800000 /* Enable hardwarre power control */
+#define BCM43xx_HF_BTCOEXALT 0x01000000 /* Bluetooth coexistance in alternate pins */
+#define BCM43xx_HF_TXBTCHECK 0x02000000 /* Bluetooth check during transmission */
+#define BCM43xx_HF_SKCFPUP 0x04000000 /* Skip CFP update */
+
+
+/* MacFilter offsets. */
+#define BCM43xx_MACFILTER_SELF 0x0000
+#define BCM43xx_MACFILTER_ASSOC 0x0003
+
+/* PowerControl */
+#define BCM43xx_PCTL_IN 0xB0
+#define BCM43xx_PCTL_OUT 0xB4
+#define BCM43xx_PCTL_OUTENABLE 0xB8
+#define BCM43xx_PCTL_XTAL_POWERUP 0x40
+#define BCM43xx_PCTL_PLL_POWERDOWN 0x80
+
+/* PowerControl Clock Modes */
+#define BCM43xx_PCTL_CLK_FAST 0x00
+#define BCM43xx_PCTL_CLK_SLOW 0x01
+#define BCM43xx_PCTL_CLK_DYNAMIC 0x02
+
+#define BCM43xx_PCTL_FORCE_SLOW 0x0800
+#define BCM43xx_PCTL_FORCE_PLL 0x1000
+#define BCM43xx_PCTL_DYN_XTAL 0x2000
+
+/* PHYVersioning */
+#define BCM43xx_PHYTYPE_A 0x00
+#define BCM43xx_PHYTYPE_B 0x01
+#define BCM43xx_PHYTYPE_G 0x02
+
+/* PHYRegisters */
+#define BCM43xx_PHY_ILT_A_CTRL 0x0072
+#define BCM43xx_PHY_ILT_A_DATA1 0x0073
+#define BCM43xx_PHY_ILT_A_DATA2 0x0074
+#define BCM43xx_PHY_G_LO_CONTROL 0x0810
+#define BCM43xx_PHY_ILT_G_CTRL 0x0472
+#define BCM43xx_PHY_ILT_G_DATA1 0x0473
+#define BCM43xx_PHY_ILT_G_DATA2 0x0474
+#define BCM43xx_PHY_A_PCTL 0x007B
+#define BCM43xx_PHY_G_PCTL 0x0029
+#define BCM43xx_PHY_A_CRS 0x0029
+#define BCM43xx_PHY_RADIO_BITFIELD 0x0401
+#define BCM43xx_PHY_G_CRS 0x0429
+#define BCM43xx_PHY_NRSSILT_CTRL 0x0803
+#define BCM43xx_PHY_NRSSILT_DATA 0x0804
+
+/* RadioRegisters */
+#define BCM43xx_RADIOCTL_ID 0x01
+
+/* MAC Control bitfield */
+#define BCM43xx_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
+#define BCM43xx_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
+#define BCM43xx_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
+#define BCM43xx_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
+#define BCM43xx_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */
+#define BCM43xx_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
+#define BCM43xx_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */
+#define BCM43xx_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */
+#define BCM43xx_MACCTL_BE 0x00010000 /* Big Endian mode */
+#define BCM43xx_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
+#define BCM43xx_MACCTL_AP 0x00040000 /* AccessPoint mode */
+#define BCM43xx_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
+#define BCM43xx_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
+#define BCM43xx_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */
+#define BCM43xx_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
+#define BCM43xx_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
+#define BCM43xx_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
+#define BCM43xx_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
+#define BCM43xx_MACCTL_AWAKE 0x04000000 /* Device is awake */
+#define BCM43xx_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */
+#define BCM43xx_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
+#define BCM43xx_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */
+#define BCM43xx_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */
+#define BCM43xx_MACCTL_GMODE 0x80000000 /* G Mode */
+
+/* StatusBitField *///FIXME rename these all
+#define BCM43xx_SBF_MAC_ENABLED 0x00000001
+#define BCM43xx_SBF_2 0x00000002 /*FIXME: fix name*/
+#define BCM43xx_SBF_CORE_READY 0x00000004
+#define BCM43xx_SBF_400 0x00000400 /*FIXME: fix name*/
+#define BCM43xx_SBF_4000 0x00004000 /*FIXME: fix name*/
+#define BCM43xx_SBF_8000 0x00008000 /*FIXME: fix name*/
+#define BCM43xx_SBF_XFER_REG_BYTESWAP 0x00010000
+#define BCM43xx_SBF_MODE_NOTADHOC 0x00020000
+#define BCM43xx_SBF_MODE_AP 0x00040000
+#define BCM43xx_SBF_RADIOREG_LOCK 0x00080000
+#define BCM43xx_SBF_MODE_MONITOR 0x00400000
+#define BCM43xx_SBF_MODE_PROMISC 0x01000000
+#define BCM43xx_SBF_PS1 0x02000000
+#define BCM43xx_SBF_PS2 0x04000000
+#define BCM43xx_SBF_NO_SSID_BCAST 0x08000000
+#define BCM43xx_SBF_TIME_UPDATE 0x10000000
+#define BCM43xx_SBF_80000000 0x80000000 /*FIXME: fix name*/
+
+/* 802.11 core specific TM State Low flags */
+#define BCM43xx_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
+#define BCM43xx_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select */
+#define BCM43xx_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */
+#define BCM43xx_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
+#define BCM43xx_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
+
+/* 802.11 core specific TM State High flags */
+#define BCM43xx_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5)*/
+#define BCM43xx_TMSHIGH_APHY 0x00020000 /* A-PHY available (rev >= 5) */
+#define BCM43xx_TMSHIGH_GPHY 0x00010000 /* G-PHY available (rev >= 5) */
+
+/* Generic-Interrupt reasons. */
+#define BCM43xx_IRQ_MAC_SUSPENDED 0x00000001
+#define BCM43xx_IRQ_BEACON 0x00000002
+#define BCM43xx_IRQ_TBTT_INDI 0x00000004
+#define BCM43xx_IRQ_BEACON_TX_OK 0x00000008
+#define BCM43xx_IRQ_BEACON_CANCEL 0x00000010
+#define BCM43xx_IRQ_ATIM_END 0x00000020
+#define BCM43xx_IRQ_PMQ 0x00000040
+#define BCM43xx_IRQ_PIO_WORKAROUND 0x00000100
+#define BCM43xx_IRQ_MAC_TXERR 0x00000200
+#define BCM43xx_IRQ_PHY_TXERR 0x00000800
+#define BCM43xx_IRQ_PMEVENT 0x00001000
+#define BCM43xx_IRQ_TIMER0 0x00002000
+#define BCM43xx_IRQ_TIMER1 0x00004000
+#define BCM43xx_IRQ_DMA 0x00008000
+#define BCM43xx_IRQ_TXFIFO_FLUSH_OK 0x00010000
+#define BCM43xx_IRQ_CCA_MEASURE_OK 0x00020000
+#define BCM43xx_IRQ_NOISESAMPLE_OK 0x00040000
+#define BCM43xx_IRQ_UCODE_DEBUG 0x08000000
+#define BCM43xx_IRQ_RFKILL 0x10000000
+#define BCM43xx_IRQ_TX_OK 0x20000000
+#define BCM43xx_IRQ_PHY_G_CHANGED 0x40000000
+#define BCM43xx_IRQ_TIMEOUT 0x80000000
+
+#define BCM43xx_IRQ_ALL 0xFFFFFFFF
+#define BCM43xx_IRQ_MASKTEMPLATE (BCM43xx_IRQ_MAC_SUSPENDED | \
+ BCM43xx_IRQ_BEACON | \
+ BCM43xx_IRQ_TBTT_INDI | \
+ BCM43xx_IRQ_ATIM_END | \
+ BCM43xx_IRQ_PMQ | \
+ BCM43xx_IRQ_MAC_TXERR | \
+ BCM43xx_IRQ_PHY_TXERR | \
+ BCM43xx_IRQ_DMA | \
+ BCM43xx_IRQ_TXFIFO_FLUSH_OK | \
+ BCM43xx_IRQ_NOISESAMPLE_OK | \
+ BCM43xx_IRQ_UCODE_DEBUG | \
+ BCM43xx_IRQ_RFKILL | \
+ BCM43xx_IRQ_TX_OK)
+
+/* Device specific rate values.
+ * The actual values defined here are (rate_in_mbps * 2).
+ * Some code depends on this. Don't change it. */
+#define BCM43xx_CCK_RATE_1MB 0x02
+#define BCM43xx_CCK_RATE_2MB 0x04
+#define BCM43xx_CCK_RATE_5MB 0x0B
+#define BCM43xx_CCK_RATE_11MB 0x16
+#define BCM43xx_OFDM_RATE_6MB 0x0C
+#define BCM43xx_OFDM_RATE_9MB 0x12
+#define BCM43xx_OFDM_RATE_12MB 0x18
+#define BCM43xx_OFDM_RATE_18MB 0x24
+#define BCM43xx_OFDM_RATE_24MB 0x30
+#define BCM43xx_OFDM_RATE_36MB 0x48
+#define BCM43xx_OFDM_RATE_48MB 0x60
+#define BCM43xx_OFDM_RATE_54MB 0x6C
+/* Convert a bcm43xx rate value to a rate in 100kbps */
+#define BCM43xx_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
+
+
+#define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7
+#define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4
+
+/* Max size of a security key */
+#define BCM43xx_SEC_KEYSIZE 16
+/* Security algorithms. */
+enum {
+ BCM43xx_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
+ BCM43xx_SEC_ALGO_WEP40,
+ BCM43xx_SEC_ALGO_TKIP,
+ BCM43xx_SEC_ALGO_AES,
+ BCM43xx_SEC_ALGO_WEP104,
+ BCM43xx_SEC_ALGO_AES_LEGACY,
+};
+
+
+#ifdef assert
+# undef assert
+#endif
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+# define assert(expr) \
+ do { \
+ if (unlikely(!(expr))) { \
+ printk(KERN_ERR PFX "ASSERTION FAILED (%s) at: %s:%d:%s()\n", \
+ #expr, __FILE__, __LINE__, __FUNCTION__); \
+ } \
+ } while (0)
+# define BCM43xx_DEBUG 1
+#else
+# define assert(expr) do { /* nothing */ } while (0)
+# define BCM43xx_DEBUG 0
+#endif
+
+/* rate limited printk(). */
+#ifdef printkl
+# undef printkl
+#endif
+#define printkl(f, x...) do { if (printk_ratelimit()) printk(f ,##x); } while (0)
+/* rate limited printk() for debugging */
+#ifdef dprintkl
+# undef dprintkl
+#endif
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+# define dprintkl printkl
+#else
+# define dprintkl(f, x...) do { /* nothing */ } while (0)
+#endif
+
+/* debugging printk() */
+#ifdef dprintk
+# undef dprintk
+#endif
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+# define dprintk(f, x...) do { printk(f ,##x); } while (0)
+#else
+# define dprintk(f, x...) do { /* nothing */ } while (0)
+#endif
+
+
+struct net_device;
+struct pci_dev;
+struct bcm43xx_dmaring;
+struct bcm43xx_pioqueue;
+
+struct bcm43xx_initval {
+ u16 offset;
+ u16 size;
+ u32 value;
+} __attribute__((__packed__));
+
+#define BCM43xx_PHYMODE(phytype) (1 << (phytype))
+#define BCM43xx_PHYMODE_A BCM43xx_PHYMODE(BCM43xx_PHYTYPE_A)
+#define BCM43xx_PHYMODE_B BCM43xx_PHYMODE(BCM43xx_PHYTYPE_B)
+#define BCM43xx_PHYMODE_G BCM43xx_PHYMODE(BCM43xx_PHYTYPE_G)
+
+struct bcm43xx_phy {
+ /* Possible PHYMODEs on this PHY */
+ u8 possible_phymodes;
+ /* GMODE bit enabled? */
+ u8 gmode;
+ /* Possible ieee80211 subsystem hwmodes for this PHY.
+ * Which mode is selected, depends on thr GMODE enabled bit */
+#define BCM43xx_MAX_PHYHWMODES 2
+ struct ieee80211_hw_mode hwmodes[BCM43xx_MAX_PHYHWMODES];
+
+ /* Analog Type */
+ u8 analog;
+ /* BCM43xx_PHYTYPE_ */
+ u8 type;
+ /* PHY revision number. */
+ u8 rev;
+
+ /* Radio versioning */
+ u16 radio_manuf; /* Radio manufacturer */
+ u16 radio_ver; /* Radio version */
+ u8 radio_rev; /* Radio revision */
+
+ u8 radio_on:1; /* Radio switched on/off */
+ u8 locked:1; /* Only used in bcm43xx_phy_{un}lock() */
+ u8 dyn_tssi_tbl:1; /* tssi2dbm is kmalloc()ed. */
+
+ /* ACI (adjacent channel interference) flags. */
+ u8 aci_enable:1;
+ u8 aci_wlan_automatic:1;
+ u8 aci_hw_rssi:1;
+
+ u16 minlowsig[2];
+ u16 minlowsigpos[2];
+
+ /* TSSI to dBm table in use */
+ const s8 *tssi2dbm;
+ /* Target idle TSSI */
+ int tgt_idle_tssi;
+ /* Current idle TSSI */
+ int cur_idle_tssi;
+
+ /* LocalOscillator control values. */
+ struct bcm43xx_txpower_lo_control *lo_control;
+ /* Values from bcm43xx_calc_loopback_gain() */
+ s16 max_lb_gain; /* Maximum Loopback gain in hdB */
+ s16 trsw_rx_gain; /* TRSW RX gain in hdB */
+ s16 lna_lod_gain; /* LNA lod */
+ s16 lna_gain; /* LNA */
+ s16 pga_gain; /* PGA */
+
+ /* PHY lock for core.rev < 3
+ * This lock is only used by bcm43xx_phy_{un}lock()
+ */
+ spinlock_t lock;
+
+ /* Desired TX power level (in dBm).
+ * This is set by the user and adjusted in bcm43xx_phy_xmitpower(). */
+ u8 power_level;
+ /* TX Power control values. */
+ /* B/G PHY */
+ struct {
+ /* Current Radio Attenuation for TXpower recalculation. */
+ u16 rfatt;
+ /* Current Baseband Attenuation for TXpower recalculation. */
+ u16 bbatt;
+ /* Current TXpower control value for TXpower recalculation. */
+ u16 txctl1;
+ };
+ /* A PHY */
+ struct {
+ u16 txpwr_offset;
+ };
+
+ /* Current Interference Mitigation mode */
+ int interfmode;
+ /* Stack of saved values from the Interference Mitigation code.
+ * Each value in the stack is layed out as follows:
+ * bit 0-11: offset
+ * bit 12-15: register ID
+ * bit 16-32: value
+ * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
+ */
+#define BCM43xx_INTERFSTACK_SIZE 26
+ u32 interfstack[BCM43xx_INTERFSTACK_SIZE];//FIXME: use a data structure
+
+ /* Saved values from the NRSSI Slope calculation */
+ s16 nrssi[2];
+ s32 nrssislope;
+ /* In memory nrssi lookup table. */
+ s8 nrssi_lt[64];
+
+ /* current channel */
+ u8 channel;
+
+ u16 lofcal;
+
+ u16 initval;//FIXME rename?
+};
+
+/* Data structures for DMA transmission, per 80211 core. */
+struct bcm43xx_dma {
+ struct bcm43xx_dmaring *tx_ring0;
+ struct bcm43xx_dmaring *tx_ring1;
+ struct bcm43xx_dmaring *tx_ring2;
+ struct bcm43xx_dmaring *tx_ring3;
+ struct bcm43xx_dmaring *tx_ring4;
+ struct bcm43xx_dmaring *tx_ring5;
+
+ struct bcm43xx_dmaring *rx_ring0;
+ struct bcm43xx_dmaring *rx_ring3; /* only available on core.rev < 5 */
+};
+
+/* Data structures for PIO transmission, per 80211 core. */
+struct bcm43xx_pio {
+ struct bcm43xx_pioqueue *queue0;
+ struct bcm43xx_pioqueue *queue1;
+ struct bcm43xx_pioqueue *queue2;
+ struct bcm43xx_pioqueue *queue3;
+};
+
+/* Context information for a noise calculation (Link Quality). */
+struct bcm43xx_noise_calculation {
+ u8 channel_at_start;
+ u8 calculation_running:1;
+ u8 nr_samples;
+ s8 samples[8][4];
+};
+
+struct bcm43xx_stats {
+ u8 link_noise;
+ /* Store the last TX/RX times here for updating the leds. */
+ unsigned long last_tx;
+ unsigned long last_rx;
+};
+
+struct bcm43xx_key {
+ u8 enabled;
+ u8 algorithm;
+ u8 address[6];
+};
+
+struct bcm43xx_wldev;
+
+/* Data structure for the WLAN parts (802.11 cores) of the bcm43xx chip. */
+struct bcm43xx_wl {
+ /* Pointer to the active wireless device on this chip */
+ struct bcm43xx_wldev *current_dev;
+ /* Pointer to the ieee80211 hardware data structure */
+ struct ieee80211_hw *hw;
+
+ spinlock_t irq_lock;
+ struct mutex mutex;
+ spinlock_t leds_lock;
+
+ /* We can only have one operating interface (802.11 core)
+ * at a time. General information about this interface follows.
+ */
+
+ /* Opaque ID of the operating interface (!= monitor
+ * interface) from the ieee80211 subsystem.
+ * Do not modify.
+ */
+ int if_id;
+ /* MAC address. */
+ u8 *mac_addr;
+ /* Current BSSID (if any). */
+ u8 *bssid;
+ /* Interface type. (IEEE80211_IF_TYPE_XXX) */
+ int if_type;
+ /* Counter of active monitor interfaces. */
+ int monitor;
+ /* Is the card operating in AP, STA or IBSS mode? */
+ unsigned int operating:1;
+ /* Promisc mode active?
+ * Note that (monitor != 0) implies promisc.
+ */
+ unsigned int promisc:1;
+ /* Stats about the wireless interface */
+ struct ieee80211_low_level_stats ieee_stats;
+
+ struct hwrng rng;
+ u8 rng_initialized;
+ char rng_name[30 + 1];
+
+ /* List of all wireless devices on this chip */
+ struct list_head devlist;
+ u8 nr_devs;
+};
+
+/* Pointers to the firmware data and meta information about it. */
+struct bcm43xx_firmware {
+ /* Microcode */
+ const struct firmware *ucode;
+ /* PCM code */
+ const struct firmware *pcm;
+ /* Initial MMIO values 0 */
+ const struct firmware *initvals0;
+ /* Initial MMIO values 1 */
+ const struct firmware *initvals1;
+ /* Firmware revision */
+ u16 rev;
+ /* Firmware patchlevel */
+ u16 patch;
+};
+
+/* Device (802.11 core) initialization status. */
+enum {
+ BCM43xx_STAT_UNINIT, /* Uninitialized. */
+ BCM43xx_STAT_INITIALIZING, /* bcm43xx_wireless_core_init() in progress. */
+ BCM43xx_STAT_INITIALIZED, /* Initialized. Note that this doesn't mean it's started. */
+};
+#define bcm43xx_status(bcm) atomic_read(&(bcm)->init_status)
+#define bcm43xx_set_status(bcm, stat) do { \
+ atomic_set(&(bcm)->init_status, (stat)); \
+ smp_wmb(); \
+ } while (0)
+
+/* XXX--- HOW LOCKING WORKS IN BCM43xx ---XXX
+ *
+ * You should always acquire both, wl->mutex and wl->irq_lock unless:
+ * - You don't need to acquire wl->irq_lock, if the interface is stopped.
+ * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
+ * and packet TX path (and _ONLY_ there.)
+ */
+
+/* Data structure for one wireless device (802.11 core) */
+struct bcm43xx_wldev {
+ struct ssb_device *dev;
+ struct bcm43xx_wl *wl;
+
+ /* Driver initialization status BCM43xx_STAT_*** */
+ atomic_t init_status;
+ /* Interface started? (bcm43xx_wireless_core_start()) */
+ u8 started;
+
+ u16 was_initialized:1, /* for suspend/resume. */
+ was_started:1, /* for suspend/resume. */
+ __using_pio:1, /* Internal, use bcm43xx_using_pio(). */
+ bad_frames_preempt:1, /* Use "Bad Frames Preemption" (default off) */
+ reg124_set_0x4:1, /* Some variable to keep track of IRQ stuff. */
+ short_preamble:1, /* TRUE, if short preamble is enabled. */
+ short_slot:1, /* TRUE, if short slot timing is enabled. */
+ radio_hw_enable:1; /* saved state of radio hardware enabled state */
+
+ /* PHY/Radio device. */
+ struct bcm43xx_phy phy;
+ union {
+ /* DMA engines. */
+ struct bcm43xx_dma dma;
+ /* PIO engines. */
+ struct bcm43xx_pio pio;
+ };
+
+ /* Various statistics about the physical device. */
+ struct bcm43xx_stats stats;
+
+#define BCM43xx_NR_LEDS 4
+ struct bcm43xx_led leds[BCM43xx_NR_LEDS];
+
+ /* Reason code of the last interrupt. */
+ u32 irq_reason;
+ u32 dma_reason[6];
+ /* saved irq enable/disable state bitfield. */
+ u32 irq_savedstate;
+ /* Link Quality calculation context. */
+ struct bcm43xx_noise_calculation noisecalc;
+ /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
+ int mac_suspended;
+
+ /* Interrupt Service Routine tasklet (bottom-half) */
+ struct tasklet_struct isr_tasklet;
+
+ /* Periodic tasks */
+ struct delayed_work periodic_work;
+ unsigned int periodic_state;
+
+ struct work_struct restart_work;
+
+ /* encryption/decryption */
+ u16 ktp; /* Key table pointer */
+ u8 max_nr_keys;
+ struct bcm43xx_key key[58];
+
+ /* Cached beacon template while uploading the template. */
+ struct sk_buff *cached_beacon;
+
+ /* Firmware data */
+ struct bcm43xx_firmware fw;
+
+ /* Devicelist in struct bcm43xx_wl (all 802.11 cores) */
+ struct list_head list;
+
+ /* Debugging stuff follows. */
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+ struct bcm43xx_dfsentry *dfsentry;
+#endif
+};
+
+
+static inline
+struct bcm43xx_wl * hw_to_bcm43xx_wl(struct ieee80211_hw *hw)
+{
+ return hw->priv;
+}
+
+/* Helper function, which returns a boolean.
+ * TRUE, if PIO is used; FALSE, if DMA is used.
+ */
+#if defined(CONFIG_BCM43XX_MAC80211_DMA) && defined(CONFIG_BCM43XX_MAC80211_PIO)
+static inline
+int bcm43xx_using_pio(struct bcm43xx_wldev *dev)
+{
+ return dev->__using_pio;
+}
+#elif defined(CONFIG_BCM43XX_MAC80211_DMA)
+static inline
+int bcm43xx_using_pio(struct bcm43xx_wldev *dev)
+{
+ return 0;
+}
+#elif defined(CONFIG_BCM43XX_MAC80211_PIO)
+static inline
+int bcm43xx_using_pio(struct bcm43xx_wldev *dev)
+{
+ return 1;
+}
+#else
+# error "Using neither DMA nor PIO? Confused..."
+#endif
+
+
+static inline
+struct bcm43xx_wldev * dev_to_bcm43xx_wldev(struct device *dev)
+{
+ struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
+ return ssb_get_drvdata(ssb_dev);
+}
+
+/* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
+static inline
+int bcm43xx_is_mode(struct bcm43xx_wl *wl, int type)
+{
+ if (type == IEEE80211_IF_TYPE_MNTR)
+ return !!(wl->monitor);
+ return (wl->operating &&
+ wl->if_type == type);
+}
+
+static inline
+u16 bcm43xx_read16(struct bcm43xx_wldev *dev, u16 offset)
+{
+ return ssb_read16(dev->dev, offset);
+}
+
+static inline
+void bcm43xx_write16(struct bcm43xx_wldev *dev, u16 offset, u16 value)
+{
+ ssb_write16(dev->dev, offset, value);
+}
+
+static inline
+u32 bcm43xx_read32(struct bcm43xx_wldev *dev, u16 offset)
+{
+ return ssb_read32(dev->dev, offset);
+}
+
+static inline
+void bcm43xx_write32(struct bcm43xx_wldev *dev, u16 offset, u32 value)
+{
+ ssb_write32(dev->dev, offset, value);
+}
+
+/** Limit a value between two limits */
+#ifdef limit_value
+# undef limit_value
+#endif
+#define limit_value(value, min, max) \
+ ({ \
+ typeof(value) __value = (value); \
+ typeof(value) __min = (min); \
+ typeof(value) __max = (max); \
+ if (__value < __min) \
+ __value = __min; \
+ else if (__value > __max) \
+ __value = __max; \
+ __value; \
+ })
+
+#endif /* BCM43xx_H_ */
--- /dev/null
+/*
+
+ Broadcom BCM43xx wireless driver
+
+ debugfs driver debugging code
+
+ Copyright (c) 2005 Michael Buesch <mb@bu3sch.de>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING. If not, write to
+ the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+ Boston, MA 02110-1301, USA.
+
+*/
+
+
+
+#include <linux/fs.h>
+#include <linux/debugfs.h>
+#include <linux/slab.h>
+#include <linux/netdevice.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+
+#include "bcm43xx.h"
+#include "bcm43xx_main.h"
+#include "bcm43xx_debugfs.h"
+#include "bcm43xx_dma.h"
+#include "bcm43xx_pio.h"
+#include "bcm43xx_xmit.h"
+
+#define REALLY_BIG_BUFFER_SIZE (1024*256)
+
+static struct bcm43xx_debugfs fs;
+static char big_buffer[1024*256];
+static DEFINE_MUTEX(big_buffer_mutex);
+
+
+static ssize_t write_file_dummy(struct file *file, const char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ return count;
+}
+
+static int open_file_generic(struct inode *inode, struct file *file)
+{
+ file->private_data = inode->i_private;
+ return 0;
+}
+
+#define fappend(fmt, x...) pos += snprintf(buf + pos, len - pos, fmt , ##x)
+
+static ssize_t drvinfo_read_file(struct file *file, char __user *userbuf,
+ size_t count, loff_t *ppos)
+{
+ const size_t len = ARRAY_SIZE(big_buffer);
+ char *buf = big_buffer;
+ size_t pos = 0;
+ ssize_t res;
+
+ mutex_lock(&big_buffer_mutex);
+ /* This is where the information is written to the "driver" file */
+ fappend(KBUILD_MODNAME " driver\n");
+ fappend("Compiled at: %s %s\n", __DATE__, __TIME__);
+ res = simple_read_from_buffer(userbuf, count, ppos, buf, pos);
+ mutex_unlock(&big_buffer_mutex);
+
+ return res;
+}
+
+static ssize_t tsf_read_file(struct file *file, char __user *userbuf,
+ size_t count, loff_t *ppos)
+{
+ struct bcm43xx_wldev *dev = file->private_data;
+ const size_t len = ARRAY_SIZE(big_buffer);
+ char *buf = big_buffer;
+ size_t pos = 0;
+ ssize_t res;
+ unsigned long flags;
+ u64 tsf;
+
+ mutex_lock(&big_buffer_mutex);
+ mutex_lock(&dev->wl->mutex);
+ spin_lock_irqsave(&dev->wl->irq_lock, flags);
+ if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED) {
+ fappend("Board not initialized.\n");
+ goto out;
+ }
+ bcm43xx_tsf_read(dev, &tsf);
+ fappend("0x%08x%08x\n",
+ (unsigned int)((tsf & 0xFFFFFFFF00000000ULL) >> 32),
+ (unsigned int)(tsf & 0xFFFFFFFFULL));
+
+out:
+ spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+ mutex_unlock(&dev->wl->mutex);
+ res = simple_read_from_buffer(userbuf, count, ppos, buf, pos);
+ mutex_unlock(&big_buffer_mutex);
+
+ return res;
+}
+
+static ssize_t tsf_write_file(struct file *file, const char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ struct bcm43xx_wldev *dev = file->private_data;
+ char *buf = big_buffer;
+ ssize_t buf_size;
+ ssize_t res;
+ unsigned long flags;
+ u64 tsf;
+
+ mutex_lock(&big_buffer_mutex);
+ buf_size = min(count, ARRAY_SIZE(big_buffer) - 1);
+ if (copy_from_user(buf, user_buf, buf_size)) {
+ res = -EFAULT;
+ goto out_unlock_bb;
+ }
+ mutex_lock(&dev->wl->mutex);
+ spin_lock_irqsave(&dev->wl->irq_lock, flags);
+ if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED) {
+ printk(KERN_INFO PFX "debugfs: Board not initialized.\n");
+ res = -EFAULT;
+ goto out_unlock;
+ }
+ if (sscanf(buf, "%llu", (unsigned long long *)(&tsf)) != 1) {
+ printk(KERN_INFO PFX "debugfs: invalid values for \"tsf\"\n");
+ res = -EINVAL;
+ goto out_unlock;
+ }
+ bcm43xx_tsf_write(dev, tsf);
+ mmiowb();
+ res = buf_size;
+
+out_unlock:
+ spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+ mutex_unlock(&dev->wl->mutex);
+out_unlock_bb:
+ mutex_unlock(&big_buffer_mutex);
+
+ return res;
+}
+
+static ssize_t txstat_read_file(struct file *file, char __user *userbuf,
+ size_t count, loff_t *ppos)
+{
+ struct bcm43xx_wldev *dev = file->private_data;
+ struct bcm43xx_dfsentry *e = dev->dfsentry;
+ struct bcm43xx_txstatus_log *log = &e->txstatlog;
+ unsigned long flags;
+ char *buf = log->printbuf;
+ const size_t len = ARRAY_SIZE(log->printbuf);
+ size_t pos = 0;
+ ssize_t res;
+ int i, idx;
+ struct bcm43xx_txstatus *stat;
+
+ mutex_lock(&big_buffer_mutex);
+ spin_lock_irqsave(&log->lock, flags);
+ if (!log->printing) {
+ log->printing = 1;
+ fappend("bcm43xx TX status reports:\n\n"
+ "index | cookie | seq | phy_stat | frame_count | "
+ "rts_count | supp_reason | pm_indicated | "
+ "intermediate | for_ampdu | acked\n"
+ "---\n");
+ i = log->end + 1;
+ idx = 0;
+ while (1) {
+ if (i == BCM43xx_NR_LOGGED_TXSTATUS)
+ i = 0;
+ stat = &(log->log[i]);
+ if (stat->cookie) {
+ fappend("%03d | "
+ "0x%04X | 0x%04X | 0x%02X | "
+ "0x%X | 0x%X | "
+ "%u | %u | "
+ "%u | %u | %u\n",
+ idx,
+ stat->cookie, stat->seq, stat->phy_stat,
+ stat->frame_count, stat->rts_count,
+ stat->supp_reason, stat->pm_indicated,
+ stat->intermediate, stat->for_ampdu,
+ stat->acked);
+ idx++;
+ }
+ if (i == log->end)
+ break;
+ i++;
+ }
+ log->buf_avail = pos;
+ }
+ memcpy(big_buffer, buf,
+ min(log->buf_avail, ARRAY_SIZE(big_buffer)));
+ spin_unlock_irqrestore(&log->lock, flags);
+
+ res = simple_read_from_buffer(userbuf, count, ppos,
+ big_buffer,
+ log->buf_avail);
+ if (*ppos == log->buf_avail) {
+ spin_lock_irqsave(&log->lock, flags);
+ log->printing = 0;
+ spin_unlock_irqrestore(&log->lock, flags);
+ }
+ mutex_unlock(&big_buffer_mutex);
+
+ return res;
+}
+
+static ssize_t restart_write_file(struct file *file, const char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ struct bcm43xx_wldev *dev = file->private_data;
+ char *buf = big_buffer;
+ ssize_t buf_size;
+ ssize_t res;
+ unsigned long flags;
+
+ mutex_lock(&big_buffer_mutex);
+ buf_size = min(count, ARRAY_SIZE(big_buffer) - 1);
+ if (copy_from_user(buf, user_buf, buf_size)) {
+ res = -EFAULT;
+ goto out_unlock_bb;
+ }
+ mutex_lock(&dev->wl->mutex);
+ spin_lock_irqsave(&dev->wl->irq_lock, flags);
+ if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED) {
+ printk(KERN_INFO PFX "debugfs: Board not initialized.\n");
+ res = -EFAULT;
+ goto out_unlock;
+ }
+ if (count > 0 && buf[0] == '1') {
+ bcm43xx_controller_restart(dev, "manually restarted");
+ res = count;
+ } else
+ res = -EINVAL;
+
+out_unlock:
+ spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+ mutex_unlock(&dev->wl->mutex);
+out_unlock_bb:
+ mutex_unlock(&big_buffer_mutex);
+
+ return res;
+}
+
+#undef fappend
+
+
+static struct file_operations drvinfo_fops = {
+ .read = drvinfo_read_file,
+ .write = write_file_dummy,
+ .open = open_file_generic,
+};
+
+static struct file_operations tsf_fops = {
+ .read = tsf_read_file,
+ .write = tsf_write_file,
+ .open = open_file_generic,
+};
+
+static struct file_operations txstat_fops = {
+ .read = txstat_read_file,
+ .write = write_file_dummy,
+ .open = open_file_generic,
+};
+
+static struct file_operations restart_fops = {
+ .write = restart_write_file,
+ .open = open_file_generic,
+};
+
+
+void bcm43xx_debugfs_add_device(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_dfsentry *e;
+ struct bcm43xx_txstatus_log *log;
+ char devdir[16];
+
+ assert(dev);
+ e = kzalloc(sizeof(*e), GFP_KERNEL);
+ if (!e) {
+ printk(KERN_ERR PFX "out of memory\n");
+ return;
+ }
+ e->dev = dev;
+ log = &e->txstatlog;
+ log->log = kcalloc(BCM43xx_NR_LOGGED_TXSTATUS,
+ sizeof(struct bcm43xx_txstatus),
+ GFP_KERNEL);
+ if (!log->log) {
+ printk(KERN_ERR PFX "debugfs txstatus log OOM\n");
+ kfree(e);
+ return;
+ }
+ log->end = -1;
+ spin_lock_init(&log->lock);
+
+ dev->dfsentry = e;
+
+ snprintf(devdir, sizeof(devdir), "%s", wiphy_name(dev->wl->hw->wiphy));
+ e->subdir = debugfs_create_dir(devdir, fs.root);
+ e->dentry_tsf = debugfs_create_file("tsf", 0666, e->subdir,
+ dev, &tsf_fops);
+ if (!e->dentry_tsf)
+ printk(KERN_ERR PFX "debugfs: creating \"tsf\" for \"%s\" failed!\n", devdir);
+ e->dentry_txstat = debugfs_create_file("tx_status", 0444, e->subdir,
+ dev, &txstat_fops);
+ if (!e->dentry_txstat)
+ printk(KERN_ERR PFX "debugfs: creating \"tx_status\" for \"%s\" failed!\n", devdir);
+ e->dentry_restart = debugfs_create_file("restart", 0222, e->subdir,
+ dev, &restart_fops);
+ if (!e->dentry_restart)
+ printk(KERN_ERR PFX "debugfs: creating \"restart\" for \"%s\" failed!\n", devdir);
+}
+
+void bcm43xx_debugfs_remove_device(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_dfsentry *e;
+
+ if (!dev)
+ return;
+
+ e = dev->dfsentry;
+ assert(e);
+ debugfs_remove(e->dentry_tsf);
+ debugfs_remove(e->dentry_txstat);
+ debugfs_remove(e->dentry_restart);
+ debugfs_remove(e->subdir);
+ kfree(e->txstatlog.log);
+ kfree(e);
+}
+
+void bcm43xx_debugfs_log_txstat(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_txstatus *status)
+{
+ struct bcm43xx_dfsentry *e = dev->dfsentry;
+ struct bcm43xx_txstatus_log *log;
+ struct bcm43xx_txstatus *cur;
+ int i;
+
+ log = &e->txstatlog;
+ assert(irqs_disabled());
+ spin_lock(&log->lock);
+ i = log->end + 1;
+ if (i == BCM43xx_NR_LOGGED_TXSTATUS)
+ i = 0;
+ log->end = i;
+ cur = &(log->log[i]);
+ memcpy(cur, status, sizeof(*cur));
+ spin_unlock(&log->lock);
+}
+
+void bcm43xx_debugfs_init(void)
+{
+ memset(&fs, 0, sizeof(fs));
+ fs.root = debugfs_create_dir(KBUILD_MODNAME, NULL);
+ if (!fs.root)
+ printk(KERN_ERR PFX "debugfs: creating \"" KBUILD_MODNAME "\" subdir failed!\n");
+ fs.dentry_driverinfo = debugfs_create_file("driver", 0444, fs.root, NULL, &drvinfo_fops);
+ if (!fs.dentry_driverinfo)
+ printk(KERN_ERR PFX "debugfs: creating \"" KBUILD_MODNAME "/driver\" failed!\n");
+}
+
+void bcm43xx_debugfs_exit(void)
+{
+ debugfs_remove(fs.dentry_driverinfo);
+ debugfs_remove(fs.root);
+}
+
+void bcm43xx_printk_dump(const char *data,
+ size_t size,
+ const char *description)
+{
+ unsigned int i;
+ char c;
+
+ printk(KERN_INFO PFX "Data dump (%s, %lu bytes):",
+ description, (unsigned long)size);
+ for (i = 0; i < size; i++) {
+ c = data[i];
+ if (i % 8 == 0)
+ printk("\n" KERN_INFO PFX "0x%08x: 0x%02x, ", i, c & 0xff);
+ else
+ printk("0x%02x, ", c & 0xff);
+ }
+ printk("\n");
+}
+
+void bcm43xx_printk_bitdump(const unsigned char *data,
+ size_t bytes, int msb_to_lsb,
+ const char *description)
+{
+ unsigned int i;
+ int j;
+ const unsigned char *d;
+
+ printk(KERN_INFO PFX "*** Bitdump (%s, %lu bytes, %s) ***",
+ description, (unsigned long)bytes,
+ msb_to_lsb ? "MSB to LSB" : "LSB to MSB");
+ for (i = 0; i < bytes; i++) {
+ d = data + i;
+ if (i % 8 == 0)
+ printk("\n" KERN_INFO PFX "0x%08x: ", i);
+ if (msb_to_lsb) {
+ for (j = 7; j >= 0; j--) {
+ if (*d & (1 << j))
+ printk("1");
+ else
+ printk("0");
+ }
+ } else {
+ for (j = 0; j < 8; j++) {
+ if (*d & (1 << j))
+ printk("1");
+ else
+ printk("0");
+ }
+ }
+ printk(" ");
+ }
+ printk("\n");
+}
--- /dev/null
+#ifndef BCM43xx_DEBUGFS_H_
+#define BCM43xx_DEBUGFS_H_
+
+struct bcm43xx_wldev;
+struct bcm43xx_txstatus;
+
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+
+struct dentry;
+
+#define BCM43xx_NR_LOGGED_TXSTATUS 100
+
+struct bcm43xx_txstatus_log {
+ struct bcm43xx_txstatus *log;
+ int end;
+ int printing;
+ char printbuf[(BCM43xx_NR_LOGGED_TXSTATUS * 70) + 200];
+ size_t buf_avail;
+ spinlock_t lock;
+};
+
+struct bcm43xx_dfsentry {
+ struct dentry *subdir;
+ struct dentry *dentry_tsf;
+ struct dentry *dentry_txstat;
+ struct dentry *dentry_restart;
+
+ struct bcm43xx_wldev *dev;
+
+ struct bcm43xx_txstatus_log txstatlog;
+};
+
+struct bcm43xx_debugfs {
+ struct dentry *root;
+ struct dentry *dentry_driverinfo;
+};
+
+void bcm43xx_debugfs_init(void);
+void bcm43xx_debugfs_exit(void);
+void bcm43xx_debugfs_add_device(struct bcm43xx_wldev *dev);
+void bcm43xx_debugfs_remove_device(struct bcm43xx_wldev *dev);
+void bcm43xx_debugfs_log_txstat(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_txstatus *status);
+
+/* Debug helper: Dump binary data through printk. */
+void bcm43xx_printk_dump(const char *data,
+ size_t size,
+ const char *description);
+/* Debug helper: Dump bitwise binary data through printk. */
+void bcm43xx_printk_bitdump(const unsigned char *data,
+ size_t bytes, int msb_to_lsb,
+ const char *description);
+#define bcm43xx_printk_bitdumpt(pointer, msb_to_lsb, description) \
+ do { \
+ bcm43xx_printk_bitdump((const unsigned char *)(pointer), \
+ sizeof(*(pointer)), \
+ (msb_to_lsb), \
+ (description)); \
+ } while (0)
+
+#else /* CONFIG_BCM43XX_MAC80211_DEBUG*/
+
+static inline
+void bcm43xx_debugfs_init(void) { }
+static inline
+void bcm43xx_debugfs_exit(void) { }
+static inline
+void bcm43xx_debugfs_add_device(struct bcm43xx_wldev *dev) { }
+static inline
+void bcm43xx_debugfs_remove_device(struct bcm43xx_wldev *dev) { }
+static inline
+void bcm43xx_debugfs_log_txstat(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_txstatus *status) { }
+
+static inline
+void bcm43xx_printk_dump(const char *data,
+ size_t size,
+ const char *description)
+{
+}
+static inline
+void bcm43xx_printk_bitdump(const unsigned char *data,
+ size_t bytes, int msb_to_lsb,
+ const char *description)
+{
+}
+#define bcm43xx_printk_bitdumpt(pointer, msb_to_lsb, description) do { /* nothing */ } while (0)
+
+#endif /* CONFIG_BCM43XX_MAC80211_DEBUG*/
+
+/* Ugly helper macros to make incomplete code more verbose on runtime */
+#ifdef TODO
+# undef TODO
+#endif
+#define TODO() \
+ do { \
+ printk(KERN_INFO PFX "TODO: Incomplete code in %s() at %s:%d\n", \
+ __FUNCTION__, __FILE__, __LINE__); \
+ } while (0)
+
+#ifdef FIXME
+# undef FIXME
+#endif
+#define FIXME() \
+ do { \
+ printk(KERN_INFO PFX "FIXME: Possibly broken code in %s() at %s:%d\n", \
+ __FUNCTION__, __FILE__, __LINE__); \
+ } while (0)
+
+#endif /* BCM43xx_DEBUGFS_H_ */
--- /dev/null
+/*
+
+ Broadcom BCM43xx wireless driver
+
+ DMA ringbuffer and descriptor allocation/management
+
+ Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
+
+ Some code in this file is derived from the b44.c driver
+ Copyright (C) 2002 David S. Miller
+ Copyright (C) Pekka Pietikainen
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING. If not, write to
+ the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+ Boston, MA 02110-1301, USA.
+
+*/
+
+#include "bcm43xx.h"
+#include "bcm43xx_dma.h"
+#include "bcm43xx_main.h"
+#include "bcm43xx_debugfs.h"
+#include "bcm43xx_power.h"
+#include "bcm43xx_xmit.h"
+
+#include <linux/dma-mapping.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/skbuff.h>
+
+
+/* 32bit DMA ops. */
+static
+struct bcm43xx_dmadesc_generic * op32_idx2desc(struct bcm43xx_dmaring *ring,
+ int slot,
+ struct bcm43xx_dmadesc_meta **meta)
+{
+ struct bcm43xx_dmadesc32 *desc;
+
+ *meta = &(ring->meta[slot]);
+ desc = ring->descbase;
+ desc = &(desc[slot]);
+
+ return (struct bcm43xx_dmadesc_generic *)desc;
+}
+
+static void op32_fill_descriptor(struct bcm43xx_dmaring *ring,
+ struct bcm43xx_dmadesc_generic *desc,
+ dma_addr_t dmaaddr, u16 bufsize,
+ int start, int end, int irq)
+{
+ struct bcm43xx_dmadesc32 *descbase = ring->descbase;
+ int slot;
+ u32 ctl;
+ u32 addr;
+ u32 addrext;
+
+ slot = (int)(&(desc->dma32) - descbase);
+ assert(slot >= 0 && slot < ring->nr_slots);
+
+ addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
+ addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK)
+ >> SSB_DMA_TRANSLATION_SHIFT;
+ addr |= ssb_dma_translation(ring->dev->dev);
+ ctl = (bufsize - ring->frameoffset)
+ & BCM43xx_DMA32_DCTL_BYTECNT;
+ if (slot == ring->nr_slots - 1)
+ ctl |= BCM43xx_DMA32_DCTL_DTABLEEND;
+ if (start)
+ ctl |= BCM43xx_DMA32_DCTL_FRAMESTART;
+ if (end)
+ ctl |= BCM43xx_DMA32_DCTL_FRAMEEND;
+ if (irq)
+ ctl |= BCM43xx_DMA32_DCTL_IRQ;
+ ctl |= (addrext << BCM43xx_DMA32_DCTL_ADDREXT_SHIFT)
+ & BCM43xx_DMA32_DCTL_ADDREXT_MASK;
+
+ desc->dma32.control = cpu_to_le32(ctl);
+ desc->dma32.address = cpu_to_le32(addr);
+}
+
+static void op32_poke_tx(struct bcm43xx_dmaring *ring, int slot)
+{
+ bcm43xx_dma_write(ring, BCM43xx_DMA32_TXINDEX,
+ (u32)(slot * sizeof(struct bcm43xx_dmadesc32)));
+}
+
+static void op32_tx_suspend(struct bcm43xx_dmaring *ring)
+{
+ bcm43xx_dma_write(ring, BCM43xx_DMA32_TXCTL,
+ bcm43xx_dma_read(ring, BCM43xx_DMA32_TXCTL)
+ | BCM43xx_DMA32_TXSUSPEND);
+}
+
+static void op32_tx_resume(struct bcm43xx_dmaring *ring)
+{
+ bcm43xx_dma_write(ring, BCM43xx_DMA32_TXCTL,
+ bcm43xx_dma_read(ring, BCM43xx_DMA32_TXCTL)
+ & ~BCM43xx_DMA32_TXSUSPEND);
+}
+
+static int op32_get_current_rxslot(struct bcm43xx_dmaring *ring)
+{
+ u32 val;
+
+ val = bcm43xx_dma_read(ring, BCM43xx_DMA32_RXSTATUS);
+ val &= BCM43xx_DMA32_RXDPTR;
+
+ return (val / sizeof(struct bcm43xx_dmadesc32));
+}
+
+static void op32_set_current_rxslot(struct bcm43xx_dmaring *ring,
+ int slot)
+{
+ bcm43xx_dma_write(ring, BCM43xx_DMA32_RXINDEX,
+ (u32)(slot * sizeof(struct bcm43xx_dmadesc32)));
+}
+
+static const struct bcm43xx_dma_ops dma32_ops = {
+ .idx2desc = op32_idx2desc,
+ .fill_descriptor = op32_fill_descriptor,
+ .poke_tx = op32_poke_tx,
+ .tx_suspend = op32_tx_suspend,
+ .tx_resume = op32_tx_resume,
+ .get_current_rxslot = op32_get_current_rxslot,
+ .set_current_rxslot = op32_set_current_rxslot,
+};
+
+/* 64bit DMA ops. */
+static
+struct bcm43xx_dmadesc_generic * op64_idx2desc(struct bcm43xx_dmaring *ring,
+ int slot,
+ struct bcm43xx_dmadesc_meta **meta)
+{
+ struct bcm43xx_dmadesc64 *desc;
+
+ *meta = &(ring->meta[slot]);
+ desc = ring->descbase;
+ desc = &(desc[slot]);
+
+ return (struct bcm43xx_dmadesc_generic *)desc;
+}
+
+static void op64_fill_descriptor(struct bcm43xx_dmaring *ring,
+ struct bcm43xx_dmadesc_generic *desc,
+ dma_addr_t dmaaddr, u16 bufsize,
+ int start, int end, int irq)
+{
+ struct bcm43xx_dmadesc64 *descbase = ring->descbase;
+ int slot;
+ u32 ctl0 = 0, ctl1 = 0;
+ u32 addrlo, addrhi;
+ u32 addrext;
+
+ slot = (int)(&(desc->dma64) - descbase);
+ assert(slot >= 0 && slot < ring->nr_slots);
+
+ addrlo = (u32)(dmaaddr & 0xFFFFFFFF);
+ addrhi = (((u64)dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
+ addrext = (((u64)dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
+ >> SSB_DMA_TRANSLATION_SHIFT;
+ addrhi |= ssb_dma_translation(ring->dev->dev);
+ if (slot == ring->nr_slots - 1)
+ ctl0 |= BCM43xx_DMA64_DCTL0_DTABLEEND;
+ if (start)
+ ctl0 |= BCM43xx_DMA64_DCTL0_FRAMESTART;
+ if (end)
+ ctl0 |= BCM43xx_DMA64_DCTL0_FRAMEEND;
+ if (irq)
+ ctl0 |= BCM43xx_DMA64_DCTL0_IRQ;
+ ctl1 |= (bufsize - ring->frameoffset)
+ & BCM43xx_DMA64_DCTL1_BYTECNT;
+ ctl1 |= (addrext << BCM43xx_DMA64_DCTL1_ADDREXT_SHIFT)
+ & BCM43xx_DMA64_DCTL1_ADDREXT_MASK;
+
+ desc->dma64.control0 = cpu_to_le32(ctl0);
+ desc->dma64.control1 = cpu_to_le32(ctl1);
+ desc->dma64.address_low = cpu_to_le32(addrlo);
+ desc->dma64.address_high = cpu_to_le32(addrhi);
+}
+
+static void op64_poke_tx(struct bcm43xx_dmaring *ring, int slot)
+{
+ bcm43xx_dma_write(ring, BCM43xx_DMA64_TXINDEX,
+ (u32)(slot * sizeof(struct bcm43xx_dmadesc64)));
+}
+
+static void op64_tx_suspend(struct bcm43xx_dmaring *ring)
+{
+ bcm43xx_dma_write(ring, BCM43xx_DMA64_TXCTL,
+ bcm43xx_dma_read(ring, BCM43xx_DMA64_TXCTL)
+ | BCM43xx_DMA64_TXSUSPEND);
+}
+
+static void op64_tx_resume(struct bcm43xx_dmaring *ring)
+{
+ bcm43xx_dma_write(ring, BCM43xx_DMA64_TXCTL,
+ bcm43xx_dma_read(ring, BCM43xx_DMA64_TXCTL)
+ & ~BCM43xx_DMA64_TXSUSPEND);
+}
+
+static int op64_get_current_rxslot(struct bcm43xx_dmaring *ring)
+{
+ u32 val;
+
+ val = bcm43xx_dma_read(ring, BCM43xx_DMA64_RXSTATUS);
+ val &= BCM43xx_DMA64_RXSTATDPTR;
+
+ return (val / sizeof(struct bcm43xx_dmadesc64));
+}
+
+static void op64_set_current_rxslot(struct bcm43xx_dmaring *ring,
+ int slot)
+{
+ bcm43xx_dma_write(ring, BCM43xx_DMA64_RXINDEX,
+ (u32)(slot * sizeof(struct bcm43xx_dmadesc64)));
+}
+
+static const struct bcm43xx_dma_ops dma64_ops = {
+ .idx2desc = op64_idx2desc,
+ .fill_descriptor = op64_fill_descriptor,
+ .poke_tx = op64_poke_tx,
+ .tx_suspend = op64_tx_suspend,
+ .tx_resume = op64_tx_resume,
+ .get_current_rxslot = op64_get_current_rxslot,
+ .set_current_rxslot = op64_set_current_rxslot,
+};
+
+
+static inline int free_slots(struct bcm43xx_dmaring *ring)
+{
+ return (ring->nr_slots - ring->used_slots);
+}
+
+static inline int next_slot(struct bcm43xx_dmaring *ring, int slot)
+{
+ assert(slot >= -1 && slot <= ring->nr_slots - 1);
+ if (slot == ring->nr_slots - 1)
+ return 0;
+ return slot + 1;
+}
+
+static inline int prev_slot(struct bcm43xx_dmaring *ring, int slot)
+{
+ assert(slot >= 0 && slot <= ring->nr_slots - 1);
+ if (slot == 0)
+ return ring->nr_slots - 1;
+ return slot - 1;
+}
+
+/* Request a slot for usage. */
+static inline
+int request_slot(struct bcm43xx_dmaring *ring)
+{
+ int slot;
+
+ assert(ring->tx);
+ assert(!ring->stopped);
+ assert(free_slots(ring) != 0);
+
+ slot = next_slot(ring, ring->current_slot);
+ ring->current_slot = slot;
+ ring->used_slots++;
+
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+ if (ring->used_slots > ring->max_used_slots)
+ ring->max_used_slots = ring->used_slots;
+#endif /* CONFIG_BCM43XX_MAC80211_DEBUG*/
+
+ return slot;
+}
+
+/* Return a slot to the free slots. */
+static inline
+void return_slot(struct bcm43xx_dmaring *ring, int slot)
+{
+ assert(ring->tx);
+
+ ring->used_slots--;
+}
+
+u16 bcm43xx_dmacontroller_base(int dma64bit, int controller_idx)
+{
+ static const u16 map64[] = {
+ BCM43xx_MMIO_DMA64_BASE0,
+ BCM43xx_MMIO_DMA64_BASE1,
+ BCM43xx_MMIO_DMA64_BASE2,
+ BCM43xx_MMIO_DMA64_BASE3,
+ BCM43xx_MMIO_DMA64_BASE4,
+ BCM43xx_MMIO_DMA64_BASE5,
+ };
+ static const u16 map32[] = {
+ BCM43xx_MMIO_DMA32_BASE0,
+ BCM43xx_MMIO_DMA32_BASE1,
+ BCM43xx_MMIO_DMA32_BASE2,
+ BCM43xx_MMIO_DMA32_BASE3,
+ BCM43xx_MMIO_DMA32_BASE4,
+ BCM43xx_MMIO_DMA32_BASE5,
+ };
+
+ if (dma64bit) {
+ assert(controller_idx >= 0 &&
+ controller_idx < ARRAY_SIZE(map64));
+ return map64[controller_idx];
+ }
+ assert(controller_idx >= 0 &&
+ controller_idx < ARRAY_SIZE(map32));
+ return map32[controller_idx];
+}
+
+static inline
+dma_addr_t map_descbuffer(struct bcm43xx_dmaring *ring,
+ unsigned char *buf,
+ size_t len,
+ int tx)
+{
+ dma_addr_t dmaaddr;
+
+ if (tx) {
+ dmaaddr = dma_map_single(ring->dev->dev->dev,
+ buf, len,
+ DMA_TO_DEVICE);
+ } else {
+ dmaaddr = dma_map_single(ring->dev->dev->dev,
+ buf, len,
+ DMA_FROM_DEVICE);
+ }
+
+ return dmaaddr;
+}
+
+static inline
+void unmap_descbuffer(struct bcm43xx_dmaring *ring,
+ dma_addr_t addr,
+ size_t len,
+ int tx)
+{
+ if (tx) {
+ dma_unmap_single(ring->dev->dev->dev,
+ addr, len,
+ DMA_TO_DEVICE);
+ } else {
+ dma_unmap_single(ring->dev->dev->dev,
+ addr, len,
+ DMA_FROM_DEVICE);
+ }
+}
+
+static inline
+void sync_descbuffer_for_cpu(struct bcm43xx_dmaring *ring,
+ dma_addr_t addr,
+ size_t len)
+{
+ assert(!ring->tx);
+
+ dma_sync_single_for_cpu(ring->dev->dev->dev,
+ addr, len, DMA_FROM_DEVICE);
+}
+
+static inline
+void sync_descbuffer_for_device(struct bcm43xx_dmaring *ring,
+ dma_addr_t addr,
+ size_t len)
+{
+ assert(!ring->tx);
+
+ dma_sync_single_for_device(ring->dev->dev->dev,
+ addr, len, DMA_FROM_DEVICE);
+}
+
+static inline
+void free_descriptor_buffer(struct bcm43xx_dmaring *ring,
+ struct bcm43xx_dmadesc_meta *meta,
+ int irq_context)
+{
+ if (meta->skb) {
+ if (irq_context)
+ dev_kfree_skb_irq(meta->skb);
+ else
+ dev_kfree_skb(meta->skb);
+ meta->skb = NULL;
+ }
+}
+
+static int alloc_ringmemory(struct bcm43xx_dmaring *ring)
+{
+ struct device *dev = ring->dev->dev->dev;
+
+ ring->descbase = dma_alloc_coherent(dev, BCM43xx_DMA_RINGMEMSIZE,
+ &(ring->dmabase), GFP_KERNEL);
+ if (!ring->descbase) {
+ printk(KERN_ERR PFX "DMA ringmemory allocation failed\n");
+ return -ENOMEM;
+ }
+ memset(ring->descbase, 0, BCM43xx_DMA_RINGMEMSIZE);
+
+ return 0;
+}
+
+static void free_ringmemory(struct bcm43xx_dmaring *ring)
+{
+ struct device *dev = ring->dev->dev->dev;
+
+ dma_free_coherent(dev, BCM43xx_DMA_RINGMEMSIZE,
+ ring->descbase, ring->dmabase);
+}
+
+/* Reset the RX DMA channel */
+int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_wldev *dev,
+ u16 mmio_base, int dma64)
+{
+ int i;
+ u32 value;
+ u16 offset;
+
+ offset = dma64 ? BCM43xx_DMA64_RXCTL : BCM43xx_DMA32_RXCTL;
+ bcm43xx_write32(dev, mmio_base + offset, 0);
+ for (i = 0; i < 1000; i++) {
+ offset = dma64 ? BCM43xx_DMA64_RXSTATUS : BCM43xx_DMA32_RXSTATUS;
+ value = bcm43xx_read32(dev, mmio_base + offset);
+ if (dma64) {
+ value &= BCM43xx_DMA64_RXSTAT;
+ if (value == BCM43xx_DMA64_RXSTAT_DISABLED) {
+ i = -1;
+ break;
+ }
+ } else {
+ value &= BCM43xx_DMA32_RXSTATE;
+ if (value == BCM43xx_DMA32_RXSTAT_DISABLED) {
+ i = -1;
+ break;
+ }
+ }
+ udelay(10);
+ }
+ if (i != -1) {
+ printk(KERN_ERR PFX "Error: Wait on DMA RX status timed out.\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+/* Reset the RX DMA channel */
+int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_wldev *dev,
+ u16 mmio_base, int dma64)
+{
+ int i;
+ u32 value;
+ u16 offset;
+
+ for (i = 0; i < 1000; i++) {
+ offset = dma64 ? BCM43xx_DMA64_TXSTATUS : BCM43xx_DMA32_TXSTATUS;
+ value = bcm43xx_read32(dev, mmio_base + offset);
+ if (dma64) {
+ value &= BCM43xx_DMA64_TXSTAT;
+ if (value == BCM43xx_DMA64_TXSTAT_DISABLED ||
+ value == BCM43xx_DMA64_TXSTAT_IDLEWAIT ||
+ value == BCM43xx_DMA64_TXSTAT_STOPPED)
+ break;
+ } else {
+ value &= BCM43xx_DMA32_TXSTATE;
+ if (value == BCM43xx_DMA32_TXSTAT_DISABLED ||
+ value == BCM43xx_DMA32_TXSTAT_IDLEWAIT ||
+ value == BCM43xx_DMA32_TXSTAT_STOPPED)
+ break;
+ }
+ udelay(10);
+ }
+ offset = dma64 ? BCM43xx_DMA64_TXCTL : BCM43xx_DMA32_TXCTL;
+ bcm43xx_write32(dev, mmio_base + offset, 0);
+ for (i = 0; i < 1000; i++) {
+ offset = dma64 ? BCM43xx_DMA64_TXSTATUS : BCM43xx_DMA32_TXSTATUS;
+ value = bcm43xx_read32(dev, mmio_base + offset);
+ if (dma64) {
+ value &= BCM43xx_DMA64_TXSTAT;
+ if (value == BCM43xx_DMA64_TXSTAT_DISABLED) {
+ i = -1;
+ break;
+ }
+ } else {
+ value &= BCM43xx_DMA32_TXSTATE;
+ if (value == BCM43xx_DMA32_TXSTAT_DISABLED) {
+ i = -1;
+ break;
+ }
+ }
+ udelay(10);
+ }
+ if (i != -1) {
+ printk(KERN_ERR PFX "Error: Wait on DMA TX status timed out.\n");
+ return -ENODEV;
+ }
+ /* ensure the reset is completed. */
+ udelay(300);
+
+ return 0;
+}
+
+static int setup_rx_descbuffer(struct bcm43xx_dmaring *ring,
+ struct bcm43xx_dmadesc_generic *desc,
+ struct bcm43xx_dmadesc_meta *meta,
+ gfp_t gfp_flags)
+{
+ struct bcm43xx_rxhdr_fw4 *rxhdr;
+ struct bcm43xx_hwtxstatus *txstat;
+ dma_addr_t dmaaddr;
+ struct sk_buff *skb;
+
+ assert(!ring->tx);
+
+ skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
+ if (unlikely(!skb))
+ return -ENOMEM;
+ dmaaddr = map_descbuffer(ring, skb->data,
+ ring->rx_buffersize, 0);
+ if (dma_mapping_error(dmaaddr)) {
+ /* ugh. try to realloc in zone_dma */
+ gfp_flags |= GFP_DMA;
+
+ dev_kfree_skb_any(skb);
+
+ skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
+ if (unlikely(!skb))
+ return -ENOMEM;
+ dmaaddr = map_descbuffer(ring, skb->data,
+ ring->rx_buffersize, 0);
+ }
+
+ if (dma_mapping_error(dmaaddr)) {
+ dev_kfree_skb_any(skb);
+ return -EIO;
+ }
+
+ meta->skb = skb;
+ meta->dmaaddr = dmaaddr;
+ ring->ops->fill_descriptor(ring, desc, dmaaddr,
+ ring->rx_buffersize, 0, 0, 0);
+
+ rxhdr = (struct bcm43xx_rxhdr_fw4 *)(skb->data);
+ rxhdr->frame_len = 0;
+ txstat = (struct bcm43xx_hwtxstatus *)(skb->data);
+ txstat->cookie = 0;
+
+ return 0;
+}
+
+/* Allocate the initial descbuffers.
+ * This is used for an RX ring only.
+ */
+static int alloc_initial_descbuffers(struct bcm43xx_dmaring *ring)
+{
+ int i, err = -ENOMEM;
+ struct bcm43xx_dmadesc_generic *desc;
+ struct bcm43xx_dmadesc_meta *meta;
+
+ for (i = 0; i < ring->nr_slots; i++) {
+ desc = ring->ops->idx2desc(ring, i, &meta);
+
+ err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
+ if (err) {
+ printk(KERN_ERR PFX "Failed to allocate initial descbuffers\n");
+ goto err_unwind;
+ }
+ }
+ mb();
+ ring->used_slots = ring->nr_slots;
+ err = 0;
+out:
+ return err;
+
+err_unwind:
+ for (i--; i >= 0; i--) {
+ desc = ring->ops->idx2desc(ring, i, &meta);
+
+ unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
+ dev_kfree_skb(meta->skb);
+ }
+ goto out;
+}
+
+/* Do initial setup of the DMA controller.
+ * Reset the controller, write the ring busaddress
+ * and switch the "enable" bit on.
+ */
+static int dmacontroller_setup(struct bcm43xx_dmaring *ring)
+{
+ int err = 0;
+ u32 value;
+ u32 addrext;
+ u32 trans = ssb_dma_translation(ring->dev->dev);
+
+ if (ring->tx) {
+ if (ring->dma64) {
+ u64 ringbase = (u64)(ring->dmabase);
+
+ addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
+ >> SSB_DMA_TRANSLATION_SHIFT;
+ value = BCM43xx_DMA64_TXENABLE;
+ value |= (addrext << BCM43xx_DMA64_TXADDREXT_SHIFT)
+ & BCM43xx_DMA64_TXADDREXT_MASK;
+ bcm43xx_dma_write(ring, BCM43xx_DMA64_TXCTL, value);
+ bcm43xx_dma_write(ring, BCM43xx_DMA64_TXRINGLO,
+ (ringbase & 0xFFFFFFFF));
+ bcm43xx_dma_write(ring, BCM43xx_DMA64_TXRINGHI,
+ ((ringbase >> 32) & ~SSB_DMA_TRANSLATION_MASK)
+ | trans);
+ } else {
+ u32 ringbase = (u32)(ring->dmabase);
+
+ addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
+ >> SSB_DMA_TRANSLATION_SHIFT;
+ value = BCM43xx_DMA32_TXENABLE;
+ value |= (addrext << BCM43xx_DMA32_TXADDREXT_SHIFT)
+ & BCM43xx_DMA32_TXADDREXT_MASK;
+ bcm43xx_dma_write(ring, BCM43xx_DMA32_TXCTL, value);
+ bcm43xx_dma_write(ring, BCM43xx_DMA32_TXRING,
+ (ringbase & ~SSB_DMA_TRANSLATION_MASK)
+ | trans);
+ }
+ } else {
+ err = alloc_initial_descbuffers(ring);
+ if (err)
+ goto out;
+ if (ring->dma64) {
+ u64 ringbase = (u64)(ring->dmabase);
+
+ addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
+ >> SSB_DMA_TRANSLATION_SHIFT;
+ value = (ring->frameoffset << BCM43xx_DMA64_RXFROFF_SHIFT);
+ value |= BCM43xx_DMA64_RXENABLE;
+ value |= (addrext << BCM43xx_DMA64_RXADDREXT_SHIFT)
+ & BCM43xx_DMA64_RXADDREXT_MASK;
+ bcm43xx_dma_write(ring, BCM43xx_DMA64_RXCTL, value);
+ bcm43xx_dma_write(ring, BCM43xx_DMA64_RXRINGLO,
+ (ringbase & 0xFFFFFFFF));
+ bcm43xx_dma_write(ring, BCM43xx_DMA64_RXRINGHI,
+ ((ringbase >> 32) & ~SSB_DMA_TRANSLATION_MASK)
+ | trans);
+ bcm43xx_dma_write(ring, BCM43xx_DMA64_RXINDEX, 200);
+ } else {
+ u32 ringbase = (u32)(ring->dmabase);
+
+ addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
+ >> SSB_DMA_TRANSLATION_SHIFT;
+ value = (ring->frameoffset << BCM43xx_DMA32_RXFROFF_SHIFT);
+ value |= BCM43xx_DMA32_RXENABLE;
+ value |= (addrext << BCM43xx_DMA32_RXADDREXT_SHIFT)
+ & BCM43xx_DMA32_RXADDREXT_MASK;
+ bcm43xx_dma_write(ring, BCM43xx_DMA32_RXCTL, value);
+ bcm43xx_dma_write(ring, BCM43xx_DMA32_RXRING,
+ (ringbase & ~SSB_DMA_TRANSLATION_MASK)
+ | trans);
+ bcm43xx_dma_write(ring, BCM43xx_DMA32_RXINDEX, 200);
+ }
+ }
+
+out:
+ return err;
+}
+
+/* Shutdown the DMA controller. */
+static void dmacontroller_cleanup(struct bcm43xx_dmaring *ring)
+{
+ if (ring->tx) {
+ bcm43xx_dmacontroller_tx_reset(ring->dev, ring->mmio_base, ring->dma64);
+ if (ring->dma64) {
+ bcm43xx_dma_write(ring, BCM43xx_DMA64_TXRINGLO, 0);
+ bcm43xx_dma_write(ring, BCM43xx_DMA64_TXRINGHI, 0);
+ } else
+ bcm43xx_dma_write(ring, BCM43xx_DMA32_TXRING, 0);
+ } else {
+ bcm43xx_dmacontroller_rx_reset(ring->dev, ring->mmio_base, ring->dma64);
+ if (ring->dma64) {
+ bcm43xx_dma_write(ring, BCM43xx_DMA64_RXRINGLO, 0);
+ bcm43xx_dma_write(ring, BCM43xx_DMA64_RXRINGHI, 0);
+ } else
+ bcm43xx_dma_write(ring, BCM43xx_DMA32_RXRING, 0);
+ }
+}
+
+static void free_all_descbuffers(struct bcm43xx_dmaring *ring)
+{
+ struct bcm43xx_dmadesc_generic *desc;
+ struct bcm43xx_dmadesc_meta *meta;
+ int i;
+
+ if (!ring->used_slots)
+ return;
+ for (i = 0; i < ring->nr_slots; i++) {
+ desc = ring->ops->idx2desc(ring, i, &meta);
+
+ if (!meta->skb) {
+ assert(ring->tx);
+ continue;
+ }
+ if (ring->tx) {
+ unmap_descbuffer(ring, meta->dmaaddr,
+ meta->skb->len, 1);
+ } else {
+ unmap_descbuffer(ring, meta->dmaaddr,
+ ring->rx_buffersize, 0);
+ }
+ free_descriptor_buffer(ring, meta, 0);
+ }
+}
+
+static u64 supported_dma_mask(struct bcm43xx_wldev *dev)
+{
+ u32 tmp;
+ u16 mmio_base;
+
+ tmp = bcm43xx_read32(dev, SSB_TMSHIGH);
+ if (tmp & SSB_TMSHIGH_DMA64)
+ return DMA_64BIT_MASK;
+ mmio_base = bcm43xx_dmacontroller_base(0, 0);
+ bcm43xx_write32(dev,
+ mmio_base + BCM43xx_DMA32_TXCTL,
+ BCM43xx_DMA32_TXADDREXT_MASK);
+ tmp = bcm43xx_read32(dev,
+ mmio_base + BCM43xx_DMA32_TXCTL);
+ if (tmp & BCM43xx_DMA32_TXADDREXT_MASK)
+ return DMA_32BIT_MASK;
+
+ return DMA_30BIT_MASK;
+}
+
+/* Main initialization function. */
+static
+struct bcm43xx_dmaring * bcm43xx_setup_dmaring(struct bcm43xx_wldev *dev,
+ int controller_index,
+ int for_tx,
+ int dma64)
+{
+ struct bcm43xx_dmaring *ring;
+ int err;
+ int nr_slots;
+ dma_addr_t dma_test;
+
+ ring = kzalloc(sizeof(*ring), GFP_KERNEL);
+ if (!ring)
+ goto out;
+
+ nr_slots = BCM43xx_RXRING_SLOTS;
+ if (for_tx)
+ nr_slots = BCM43xx_TXRING_SLOTS;
+
+ ring->meta = kcalloc(nr_slots, sizeof(struct bcm43xx_dmadesc_meta),
+ GFP_KERNEL);
+ if (!ring->meta)
+ goto err_kfree_ring;
+ if (for_tx) {
+ ring->txhdr_cache = kcalloc(nr_slots,
+ sizeof(struct bcm43xx_txhdr_fw4),
+ GFP_KERNEL);
+ if (!ring->txhdr_cache)
+ goto err_kfree_meta;
+
+ /* test for ability to dma to txhdr_cache */
+ dma_test = dma_map_single(dev->dev->dev,
+ ring->txhdr_cache, sizeof(struct bcm43xx_txhdr_fw4),
+ DMA_TO_DEVICE);
+
+ if (dma_mapping_error(dma_test)) {
+ /* ugh realloc */
+ kfree(ring->txhdr_cache);
+ ring->txhdr_cache = kcalloc(nr_slots,
+ sizeof(struct bcm43xx_txhdr_fw4),
+ GFP_KERNEL | GFP_DMA);
+ if (!ring->txhdr_cache)
+ goto err_kfree_meta;
+
+ dma_test = dma_map_single(dev->dev->dev,
+ ring->txhdr_cache, sizeof(struct bcm43xx_txhdr_fw4),
+ DMA_TO_DEVICE);
+
+ if (dma_mapping_error(dma_test))
+ goto err_kfree_txhdr_cache;
+ }
+
+ dma_unmap_single(dev->dev->dev,
+ dma_test, sizeof(struct bcm43xx_txhdr_fw4),
+ DMA_TO_DEVICE);
+ }
+
+ ring->dev = dev;
+ ring->nr_slots = nr_slots;
+ ring->mmio_base = bcm43xx_dmacontroller_base(dma64, controller_index);
+ ring->index = controller_index;
+ ring->dma64 = !!dma64;
+ if (dma64)
+ ring->ops = &dma64_ops;
+ else
+ ring->ops = &dma32_ops;
+ if (for_tx) {
+ ring->tx = 1;
+ ring->current_slot = -1;
+ } else {
+ if (ring->index == 0) {
+ ring->rx_buffersize = BCM43xx_DMA0_RX_BUFFERSIZE;
+ ring->frameoffset = BCM43xx_DMA0_RX_FRAMEOFFSET;
+ } else if (ring->index == 3) {
+ ring->rx_buffersize = BCM43xx_DMA3_RX_BUFFERSIZE;
+ ring->frameoffset = BCM43xx_DMA3_RX_FRAMEOFFSET;
+ } else
+ assert(0);
+ }
+
+ err = alloc_ringmemory(ring);
+ if (err)
+ goto err_kfree_txhdr_cache;
+ err = dmacontroller_setup(ring);
+ if (err)
+ goto err_free_ringmemory;
+
+out:
+ return ring;
+
+err_free_ringmemory:
+ free_ringmemory(ring);
+err_kfree_txhdr_cache:
+ kfree(ring->txhdr_cache);
+err_kfree_meta:
+ kfree(ring->meta);
+err_kfree_ring:
+ kfree(ring);
+ ring = NULL;
+ goto out;
+}
+
+/* Main cleanup function. */
+static void bcm43xx_destroy_dmaring(struct bcm43xx_dmaring *ring)
+{
+ if (!ring)
+ return;
+
+ dprintk(KERN_INFO PFX "DMA-%s 0x%04X (%s) max used slots: %d/%d\n",
+ (ring->dma64) ? "64" : "32",
+ ring->mmio_base,
+ (ring->tx) ? "TX" : "RX",
+ ring->max_used_slots, ring->nr_slots);
+ /* Device IRQs are disabled prior entering this function,
+ * so no need to take care of concurrency with rx handler stuff.
+ */
+ dmacontroller_cleanup(ring);
+ free_all_descbuffers(ring);
+ free_ringmemory(ring);
+
+ kfree(ring->txhdr_cache);
+ kfree(ring->meta);
+ kfree(ring);
+}
+
+void bcm43xx_dma_free(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_dma *dma;
+
+ if (bcm43xx_using_pio(dev))
+ return;
+ dma = &dev->dma;
+
+ bcm43xx_destroy_dmaring(dma->rx_ring3);
+ dma->rx_ring3 = NULL;
+ bcm43xx_destroy_dmaring(dma->rx_ring0);
+ dma->rx_ring0 = NULL;
+
+ bcm43xx_destroy_dmaring(dma->tx_ring5);
+ dma->tx_ring5 = NULL;
+ bcm43xx_destroy_dmaring(dma->tx_ring4);
+ dma->tx_ring4 = NULL;
+ bcm43xx_destroy_dmaring(dma->tx_ring3);
+ dma->tx_ring3 = NULL;
+ bcm43xx_destroy_dmaring(dma->tx_ring2);
+ dma->tx_ring2 = NULL;
+ bcm43xx_destroy_dmaring(dma->tx_ring1);
+ dma->tx_ring1 = NULL;
+ bcm43xx_destroy_dmaring(dma->tx_ring0);
+ dma->tx_ring0 = NULL;
+}
+
+int bcm43xx_dma_init(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_dma *dma = &dev->dma;
+ struct bcm43xx_dmaring *ring;
+ int err;
+ u64 dmamask;
+ int dma64 = 0;
+
+ dmamask = supported_dma_mask(dev);
+ if (dmamask == DMA_64BIT_MASK)
+ dma64 = 1;
+
+ err = ssb_dma_set_mask(dev->dev, dmamask);
+ if (err) {
+#ifdef BCM43XX_MAC80211_PIO
+ printk(KERN_WARNING PFX "DMA for this device not supported. "
+ "Falling back to PIO\n");
+ dev->__using_pio = 1;
+ return -EAGAIN;
+#else
+ printk(KERN_ERR PFX "DMA for this device not supported and "
+ "no PIO support compiled in\n");
+ return -EOPNOTSUPP;
+#endif
+ }
+
+ err = -ENOMEM;
+ /* setup TX DMA channels. */
+ ring = bcm43xx_setup_dmaring(dev, 0, 1, dma64);
+ if (!ring)
+ goto out;
+ dma->tx_ring0 = ring;
+
+ ring = bcm43xx_setup_dmaring(dev, 1, 1, dma64);
+ if (!ring)
+ goto err_destroy_tx0;
+ dma->tx_ring1 = ring;
+
+ ring = bcm43xx_setup_dmaring(dev, 2, 1, dma64);
+ if (!ring)
+ goto err_destroy_tx1;
+ dma->tx_ring2 = ring;
+
+ ring = bcm43xx_setup_dmaring(dev, 3, 1, dma64);
+ if (!ring)
+ goto err_destroy_tx2;
+ dma->tx_ring3 = ring;
+
+ ring = bcm43xx_setup_dmaring(dev, 4, 1, dma64);
+ if (!ring)
+ goto err_destroy_tx3;
+ dma->tx_ring4 = ring;
+
+ ring = bcm43xx_setup_dmaring(dev, 5, 1, dma64);
+ if (!ring)
+ goto err_destroy_tx4;
+ dma->tx_ring5 = ring;
+
+ /* setup RX DMA channels. */
+ ring = bcm43xx_setup_dmaring(dev, 0, 0, dma64);
+ if (!ring)
+ goto err_destroy_tx5;
+ dma->rx_ring0 = ring;
+
+ if (dev->dev->id.revision < 5) {
+ ring = bcm43xx_setup_dmaring(dev, 3, 0, dma64);
+ if (!ring)
+ goto err_destroy_rx0;
+ dma->rx_ring3 = ring;
+ }
+
+ dprintk(KERN_INFO PFX "%d-bit DMA initialized\n",
+ (dmamask == DMA_64BIT_MASK) ? 64 :
+ (dmamask == DMA_32BIT_MASK) ? 32 : 30);
+ err = 0;
+out:
+ return err;
+
+err_destroy_rx0:
+ bcm43xx_destroy_dmaring(dma->rx_ring0);
+ dma->rx_ring0 = NULL;
+err_destroy_tx5:
+ bcm43xx_destroy_dmaring(dma->tx_ring5);
+ dma->tx_ring5 = NULL;
+err_destroy_tx4:
+ bcm43xx_destroy_dmaring(dma->tx_ring4);
+ dma->tx_ring4 = NULL;
+err_destroy_tx3:
+ bcm43xx_destroy_dmaring(dma->tx_ring3);
+ dma->tx_ring3 = NULL;
+err_destroy_tx2:
+ bcm43xx_destroy_dmaring(dma->tx_ring2);
+ dma->tx_ring2 = NULL;
+err_destroy_tx1:
+ bcm43xx_destroy_dmaring(dma->tx_ring1);
+ dma->tx_ring1 = NULL;
+err_destroy_tx0:
+ bcm43xx_destroy_dmaring(dma->tx_ring0);
+ dma->tx_ring0 = NULL;
+ goto out;
+}
+
+/* Generate a cookie for the TX header. */
+static u16 generate_cookie(struct bcm43xx_dmaring *ring,
+ int slot)
+{
+ u16 cookie = 0x1000;
+
+ /* Use the upper 4 bits of the cookie as
+ * DMA controller ID and store the slot number
+ * in the lower 12 bits.
+ * Note that the cookie must never be 0, as this
+ * is a special value used in RX path.
+ */
+ switch (ring->index) {
+ case 0:
+ cookie = 0xA000;
+ break;
+ case 1:
+ cookie = 0xB000;
+ break;
+ case 2:
+ cookie = 0xC000;
+ break;
+ case 3:
+ cookie = 0xD000;
+ break;
+ case 4:
+ cookie = 0xE000;
+ break;
+ case 5:
+ cookie = 0xF000;
+ break;
+ }
+ assert(((u16)slot & 0xF000) == 0x0000);
+ cookie |= (u16)slot;
+
+ return cookie;
+}
+
+/* Inspect a cookie and find out to which controller/slot it belongs. */
+static
+struct bcm43xx_dmaring * parse_cookie(struct bcm43xx_wldev *dev,
+ u16 cookie, int *slot)
+{
+ struct bcm43xx_dma *dma = &dev->dma;
+ struct bcm43xx_dmaring *ring = NULL;
+
+ switch (cookie & 0xF000) {
+ case 0xA000:
+ ring = dma->tx_ring0;
+ break;
+ case 0xB000:
+ ring = dma->tx_ring1;
+ break;
+ case 0xC000:
+ ring = dma->tx_ring2;
+ break;
+ case 0xD000:
+ ring = dma->tx_ring3;
+ break;
+ case 0xE000:
+ ring = dma->tx_ring4;
+ break;
+ case 0xF000:
+ ring = dma->tx_ring5;
+ break;
+ default:
+ assert(0);
+ }
+ *slot = (cookie & 0x0FFF);
+ assert(ring && *slot >= 0 && *slot < ring->nr_slots);
+
+ return ring;
+}
+
+static int dma_tx_fragment(struct bcm43xx_dmaring *ring,
+ struct sk_buff *skb,
+ struct ieee80211_tx_control *ctl)
+{
+ const struct bcm43xx_dma_ops *ops = ring->ops;
+ u8 *header;
+ int slot;
+ int err;
+ struct bcm43xx_dmadesc_generic *desc;
+ struct bcm43xx_dmadesc_meta *meta;
+ struct bcm43xx_dmadesc_meta *meta_hdr;
+ struct sk_buff *bounce_skb;
+
+#define SLOTS_PER_PACKET 2
+ assert(skb_shinfo(skb)->nr_frags == 0);
+
+ /* Get a slot for the header. */
+ slot = request_slot(ring);
+ desc = ops->idx2desc(ring, slot, &meta_hdr);
+ memset(meta_hdr, 0, sizeof(*meta_hdr));
+
+ header = &(ring->txhdr_cache[slot * sizeof(struct bcm43xx_txhdr_fw4)]);
+ bcm43xx_generate_txhdr(ring->dev, header,
+ skb->data, skb->len, ctl,
+ generate_cookie(ring, slot));
+
+ meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
+ sizeof(struct bcm43xx_txhdr_fw4), 1);
+ if (dma_mapping_error(meta_hdr->dmaaddr))
+ return -EIO;
+ ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
+ sizeof(struct bcm43xx_txhdr_fw4), 1, 0, 0);
+
+ /* Get a slot for the payload. */
+ slot = request_slot(ring);
+ desc = ops->idx2desc(ring, slot, &meta);
+ memset(meta, 0, sizeof(*meta));
+
+ memcpy(&meta->txstat.control, ctl, sizeof(*ctl));
+ meta->skb = skb;
+ meta->is_last_fragment = 1;
+
+ meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
+ /* create a bounce buffer in zone_dma on mapping failure. */
+ if (dma_mapping_error(meta->dmaaddr)) {
+ bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
+ if (!bounce_skb) {
+ err = -ENOMEM;
+ goto out_unmap_hdr;
+ }
+
+ memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
+ dev_kfree_skb_any(skb);
+ skb = bounce_skb;
+ meta->skb = skb;
+ meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
+ if (dma_mapping_error(meta->dmaaddr)) {
+ err = -EIO;
+ goto out_free_bounce;
+ }
+ }
+
+ ops->fill_descriptor(ring, desc, meta->dmaaddr,
+ skb->len, 0, 1, 1);
+
+ /* Now transfer the whole frame. */
+ wmb();
+ ops->poke_tx(ring, next_slot(ring, slot));
+ return 0;
+
+out_free_bounce:
+ dev_kfree_skb_any(skb);
+out_unmap_hdr:
+ unmap_descbuffer(ring, meta_hdr->dmaaddr,
+ sizeof(struct bcm43xx_txhdr_fw4), 1);
+ return err;
+}
+
+int bcm43xx_dma_tx(struct bcm43xx_wldev *dev,
+ struct sk_buff *skb,
+ struct ieee80211_tx_control *ctl)
+{
+ struct bcm43xx_dmaring *ring = dev->dma.tx_ring1;
+ int err = 0;
+
+ assert(ring->tx);
+ if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
+ /* This should never trigger, as we call
+ * ieee80211_stop_queue() when it's full.
+ */
+ printkl(KERN_ERR PFX "DMA queue overflow\n");
+ return NETDEV_TX_BUSY;
+ }
+
+ err = dma_tx_fragment(ring, skb, ctl);
+ if (unlikely(err)) {
+ printkl(KERN_ERR PFX "DMA tx mapping failure\n");
+ return NETDEV_TX_BUSY;
+ }
+
+ ring->nr_tx_packets++;
+ if (free_slots(ring) < SLOTS_PER_PACKET) {
+ /* FIXME: we currently only have one queue */
+ ieee80211_stop_queue(dev->wl->hw, 0);
+ ring->stopped = 1;
+ }
+
+ return 0;
+}
+
+void bcm43xx_dma_handle_txstatus(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_txstatus *status)
+{
+ const struct bcm43xx_dma_ops *ops;
+ struct bcm43xx_dmaring *ring;
+ struct bcm43xx_dmadesc_generic *desc;
+ struct bcm43xx_dmadesc_meta *meta;
+ int slot;
+
+ ring = parse_cookie(dev, status->cookie, &slot);
+ if (unlikely(!ring))
+ return;
+ assert(ring->tx);
+ ops = ring->ops;
+ while (1) {
+ assert(slot >= 0 && slot < ring->nr_slots);
+ desc = ops->idx2desc(ring, slot, &meta);
+
+ if (meta->skb)
+ unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
+ else
+ unmap_descbuffer(ring, meta->dmaaddr, sizeof(struct bcm43xx_txhdr_fw4), 1);
+
+ if (meta->is_last_fragment) {
+ assert(meta->skb);
+ /* Call back to inform the ieee80211 subsystem about the
+ * status of the transmission.
+ * Some fields of txstat are already filled in dma_tx().
+ */
+ if (status->acked)
+ meta->txstat.flags |= IEEE80211_TX_STATUS_ACK;
+ meta->txstat.retry_count = status->frame_count - 1;
+ ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb, &(meta->txstat));
+ /* skb is freed by ieee80211_tx_status_irqsafe() */
+ meta->skb = NULL;
+ } else {
+ /* No need to call free_descriptor_buffer here, as
+ * this is only the txhdr, which is not allocated.
+ */
+ assert(meta->skb == NULL);
+ }
+ /* Everything belonging to the slot is unmapped
+ * and freed, so we can return it.
+ */
+ return_slot(ring, slot);
+
+ if (meta->is_last_fragment)
+ break;
+ slot = next_slot(ring, slot);
+ }
+ dev->stats.last_tx = jiffies;
+ if (ring->stopped) {
+ assert(free_slots(ring) >= SLOTS_PER_PACKET);
+ /* FIXME: we currently only have one queue */
+ ieee80211_wake_queue(dev->wl->hw, 0);
+ ring->stopped = 0;
+ }
+}
+
+void bcm43xx_dma_get_tx_stats(struct bcm43xx_wldev *dev,
+ struct ieee80211_tx_queue_stats *stats)
+{
+ struct bcm43xx_dma *dma = &dev->dma;
+ struct bcm43xx_dmaring *ring;
+ struct ieee80211_tx_queue_stats_data *data;
+
+ ring = dma->tx_ring1;
+ data = &(stats->data[0]);
+ data->len = ring->used_slots / SLOTS_PER_PACKET;
+ data->limit = ring->nr_slots / SLOTS_PER_PACKET;
+ data->count = ring->nr_tx_packets;
+}
+
+static void dma_rx(struct bcm43xx_dmaring *ring,
+ int *slot)
+{
+ const struct bcm43xx_dma_ops *ops = ring->ops;
+ struct bcm43xx_dmadesc_generic *desc;
+ struct bcm43xx_dmadesc_meta *meta;
+ struct bcm43xx_rxhdr_fw4 *rxhdr;
+ struct sk_buff *skb;
+ u16 len;
+ int err;
+ dma_addr_t dmaaddr;
+
+ desc = ops->idx2desc(ring, *slot, &meta);
+
+ sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
+ skb = meta->skb;
+
+ if (ring->index == 3) {
+ /* We received an xmit status. */
+ struct bcm43xx_hwtxstatus *hw = (struct bcm43xx_hwtxstatus *)skb->data;
+ int i = 0;
+
+ while (hw->cookie == 0) {
+ if (i > 100)
+ break;
+ i++;
+ udelay(2);
+ barrier();
+ }
+ bcm43xx_handle_hwtxstatus(ring->dev, hw);
+ /* recycle the descriptor buffer. */
+ sync_descbuffer_for_device(ring, meta->dmaaddr, ring->rx_buffersize);
+
+ return;
+ }
+ rxhdr = (struct bcm43xx_rxhdr_fw4 *)skb->data;
+ len = le16_to_cpu(rxhdr->frame_len);
+ if (len == 0) {
+ int i = 0;
+
+ do {
+ udelay(2);
+ barrier();
+ len = le16_to_cpu(rxhdr->frame_len);
+ } while (len == 0 && i++ < 5);
+ if (unlikely(len == 0)) {
+ /* recycle the descriptor buffer. */
+ sync_descbuffer_for_device(ring, meta->dmaaddr,
+ ring->rx_buffersize);
+ goto drop;
+ }
+ }
+ if (unlikely(len > ring->rx_buffersize)) {
+ /* The data did not fit into one descriptor buffer
+ * and is split over multiple buffers.
+ * This should never happen, as we try to allocate buffers
+ * big enough. So simply ignore this packet.
+ */
+ int cnt = 0;
+ s32 tmp = len;
+
+ while (1) {
+ desc = ops->idx2desc(ring, *slot, &meta);
+ /* recycle the descriptor buffer. */
+ sync_descbuffer_for_device(ring, meta->dmaaddr,
+ ring->rx_buffersize);
+ *slot = next_slot(ring, *slot);
+ cnt++;
+ tmp -= ring->rx_buffersize;
+ if (tmp <= 0)
+ break;
+ }
+ printkl(KERN_ERR PFX "DMA RX buffer too small "
+ "(len: %u, buffer: %u, nr-dropped: %d)\n",
+ len, ring->rx_buffersize, cnt);
+ goto drop;
+ }
+
+ dmaaddr = meta->dmaaddr;
+ err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
+ if (unlikely(err)) {
+ dprintkl(KERN_ERR PFX "DMA RX: setup_rx_descbuffer() failed\n");
+ sync_descbuffer_for_device(ring, dmaaddr,
+ ring->rx_buffersize);
+ goto drop;
+ }
+
+ unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
+ skb_put(skb, len + ring->frameoffset);
+ skb_pull(skb, ring->frameoffset);
+
+ bcm43xx_rx(ring->dev, skb, rxhdr);
+drop:
+ return;
+}
+
+void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring)
+{
+ const struct bcm43xx_dma_ops *ops = ring->ops;
+ int slot, current_slot;
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+ int used_slots = 0;
+#endif
+
+ assert(!ring->tx);
+ current_slot = ops->get_current_rxslot(ring);
+ assert(current_slot >= 0 && current_slot < ring->nr_slots);
+
+ slot = ring->current_slot;
+ for ( ; slot != current_slot; slot = next_slot(ring, slot)) {
+ dma_rx(ring, &slot);
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+ if (++used_slots > ring->max_used_slots)
+ ring->max_used_slots = used_slots;
+#endif
+ }
+ ops->set_current_rxslot(ring, slot);
+ ring->current_slot = slot;
+}
+
+void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring)
+{
+ assert(ring->tx);
+ bcm43xx_power_saving_ctl_bits(ring->dev, -1, 1);
+ ring->ops->tx_suspend(ring);
+}
+
+void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring)
+{
+ assert(ring->tx);
+ ring->ops->tx_resume(ring);
+ bcm43xx_power_saving_ctl_bits(ring->dev, -1, -1);
+}
--- /dev/null
+#ifndef BCM43xx_DMA_H_
+#define BCM43xx_DMA_H_
+
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+#include <linux/linkage.h>
+#include <asm/atomic.h>
+
+#include "bcm43xx.h"
+
+
+/* DMA-Interrupt reasons. */
+#define BCM43xx_DMAIRQ_FATALMASK ((1 << 10) | (1 << 11) | (1 << 12) \
+ | (1 << 14) | (1 << 15))
+#define BCM43xx_DMAIRQ_NONFATALMASK (1 << 13)
+#define BCM43xx_DMAIRQ_RX_DONE (1 << 16)
+
+
+/*** 32-bit DMA Engine. ***/
+
+/* 32-bit DMA controller registers. */
+#define BCM43xx_DMA32_TXCTL 0x00
+#define BCM43xx_DMA32_TXENABLE 0x00000001
+#define BCM43xx_DMA32_TXSUSPEND 0x00000002
+#define BCM43xx_DMA32_TXLOOPBACK 0x00000004
+#define BCM43xx_DMA32_TXFLUSH 0x00000010
+#define BCM43xx_DMA32_TXADDREXT_MASK 0x00030000
+#define BCM43xx_DMA32_TXADDREXT_SHIFT 16
+#define BCM43xx_DMA32_TXRING 0x04
+#define BCM43xx_DMA32_TXINDEX 0x08
+#define BCM43xx_DMA32_TXSTATUS 0x0C
+#define BCM43xx_DMA32_TXDPTR 0x00000FFF
+#define BCM43xx_DMA32_TXSTATE 0x0000F000
+#define BCM43xx_DMA32_TXSTAT_DISABLED 0x00000000
+#define BCM43xx_DMA32_TXSTAT_ACTIVE 0x00001000
+#define BCM43xx_DMA32_TXSTAT_IDLEWAIT 0x00002000
+#define BCM43xx_DMA32_TXSTAT_STOPPED 0x00003000
+#define BCM43xx_DMA32_TXSTAT_SUSP 0x00004000
+#define BCM43xx_DMA32_TXERROR 0x000F0000
+#define BCM43xx_DMA32_TXERR_NOERR 0x00000000
+#define BCM43xx_DMA32_TXERR_PROT 0x00010000
+#define BCM43xx_DMA32_TXERR_UNDERRUN 0x00020000
+#define BCM43xx_DMA32_TXERR_BUFREAD 0x00030000
+#define BCM43xx_DMA32_TXERR_DESCREAD 0x00040000
+#define BCM43xx_DMA32_TXACTIVE 0xFFF00000
+#define BCM43xx_DMA32_RXCTL 0x10
+#define BCM43xx_DMA32_RXENABLE 0x00000001
+#define BCM43xx_DMA32_RXFROFF_MASK 0x000000FE
+#define BCM43xx_DMA32_RXFROFF_SHIFT 1
+#define BCM43xx_DMA32_RXDIRECTFIFO 0x00000100
+#define BCM43xx_DMA32_RXADDREXT_MASK 0x00030000
+#define BCM43xx_DMA32_RXADDREXT_SHIFT 16
+#define BCM43xx_DMA32_RXRING 0x14
+#define BCM43xx_DMA32_RXINDEX 0x18
+#define BCM43xx_DMA32_RXSTATUS 0x1C
+#define BCM43xx_DMA32_RXDPTR 0x00000FFF
+#define BCM43xx_DMA32_RXSTATE 0x0000F000
+#define BCM43xx_DMA32_RXSTAT_DISABLED 0x00000000
+#define BCM43xx_DMA32_RXSTAT_ACTIVE 0x00001000
+#define BCM43xx_DMA32_RXSTAT_IDLEWAIT 0x00002000
+#define BCM43xx_DMA32_RXSTAT_STOPPED 0x00003000
+#define BCM43xx_DMA32_RXERROR 0x000F0000
+#define BCM43xx_DMA32_RXERR_NOERR 0x00000000
+#define BCM43xx_DMA32_RXERR_PROT 0x00010000
+#define BCM43xx_DMA32_RXERR_OVERFLOW 0x00020000
+#define BCM43xx_DMA32_RXERR_BUFWRITE 0x00030000
+#define BCM43xx_DMA32_RXERR_DESCREAD 0x00040000
+#define BCM43xx_DMA32_RXACTIVE 0xFFF00000
+
+/* 32-bit DMA descriptor. */
+struct bcm43xx_dmadesc32 {
+ __le32 control;
+ __le32 address;
+} __attribute__((__packed__));
+#define BCM43xx_DMA32_DCTL_BYTECNT 0x00001FFF
+#define BCM43xx_DMA32_DCTL_ADDREXT_MASK 0x00030000
+#define BCM43xx_DMA32_DCTL_ADDREXT_SHIFT 16
+#define BCM43xx_DMA32_DCTL_DTABLEEND 0x10000000
+#define BCM43xx_DMA32_DCTL_IRQ 0x20000000
+#define BCM43xx_DMA32_DCTL_FRAMEEND 0x40000000
+#define BCM43xx_DMA32_DCTL_FRAMESTART 0x80000000
+
+
+
+/*** 64-bit DMA Engine. ***/
+
+/* 64-bit DMA controller registers. */
+#define BCM43xx_DMA64_TXCTL 0x00
+#define BCM43xx_DMA64_TXENABLE 0x00000001
+#define BCM43xx_DMA64_TXSUSPEND 0x00000002
+#define BCM43xx_DMA64_TXLOOPBACK 0x00000004
+#define BCM43xx_DMA64_TXFLUSH 0x00000010
+#define BCM43xx_DMA64_TXADDREXT_MASK 0x00030000
+#define BCM43xx_DMA64_TXADDREXT_SHIFT 16
+#define BCM43xx_DMA64_TXINDEX 0x04
+#define BCM43xx_DMA64_TXRINGLO 0x08
+#define BCM43xx_DMA64_TXRINGHI 0x0C
+#define BCM43xx_DMA64_TXSTATUS 0x10
+#define BCM43xx_DMA64_TXSTATDPTR 0x00001FFF
+#define BCM43xx_DMA64_TXSTAT 0xF0000000
+#define BCM43xx_DMA64_TXSTAT_DISABLED 0x00000000
+#define BCM43xx_DMA64_TXSTAT_ACTIVE 0x10000000
+#define BCM43xx_DMA64_TXSTAT_IDLEWAIT 0x20000000
+#define BCM43xx_DMA64_TXSTAT_STOPPED 0x30000000
+#define BCM43xx_DMA64_TXSTAT_SUSP 0x40000000
+#define BCM43xx_DMA64_TXERROR 0x14
+#define BCM43xx_DMA64_TXERRDPTR 0x0001FFFF
+#define BCM43xx_DMA64_TXERR 0xF0000000
+#define BCM43xx_DMA64_TXERR_NOERR 0x00000000
+#define BCM43xx_DMA64_TXERR_PROT 0x10000000
+#define BCM43xx_DMA64_TXERR_UNDERRUN 0x20000000
+#define BCM43xx_DMA64_TXERR_TRANSFER 0x30000000
+#define BCM43xx_DMA64_TXERR_DESCREAD 0x40000000
+#define BCM43xx_DMA64_TXERR_CORE 0x50000000
+#define BCM43xx_DMA64_RXCTL 0x20
+#define BCM43xx_DMA64_RXENABLE 0x00000001
+#define BCM43xx_DMA64_RXFROFF_MASK 0x000000FE
+#define BCM43xx_DMA64_RXFROFF_SHIFT 1
+#define BCM43xx_DMA64_RXDIRECTFIFO 0x00000100
+#define BCM43xx_DMA64_RXADDREXT_MASK 0x00030000
+#define BCM43xx_DMA64_RXADDREXT_SHIFT 16
+#define BCM43xx_DMA64_RXINDEX 0x24
+#define BCM43xx_DMA64_RXRINGLO 0x28
+#define BCM43xx_DMA64_RXRINGHI 0x2C
+#define BCM43xx_DMA64_RXSTATUS 0x30
+#define BCM43xx_DMA64_RXSTATDPTR 0x00001FFF
+#define BCM43xx_DMA64_RXSTAT 0xF0000000
+#define BCM43xx_DMA64_RXSTAT_DISABLED 0x00000000
+#define BCM43xx_DMA64_RXSTAT_ACTIVE 0x10000000
+#define BCM43xx_DMA64_RXSTAT_IDLEWAIT 0x20000000
+#define BCM43xx_DMA64_RXSTAT_STOPPED 0x30000000
+#define BCM43xx_DMA64_RXSTAT_SUSP 0x40000000
+#define BCM43xx_DMA64_RXERROR 0x34
+#define BCM43xx_DMA64_RXERRDPTR 0x0001FFFF
+#define BCM43xx_DMA64_RXERR 0xF0000000
+#define BCM43xx_DMA64_RXERR_NOERR 0x00000000
+#define BCM43xx_DMA64_RXERR_PROT 0x10000000
+#define BCM43xx_DMA64_RXERR_UNDERRUN 0x20000000
+#define BCM43xx_DMA64_RXERR_TRANSFER 0x30000000
+#define BCM43xx_DMA64_RXERR_DESCREAD 0x40000000
+#define BCM43xx_DMA64_RXERR_CORE 0x50000000
+
+/* 64-bit DMA descriptor. */
+struct bcm43xx_dmadesc64 {
+ __le32 control0;
+ __le32 control1;
+ __le32 address_low;
+ __le32 address_high;
+} __attribute__((__packed__));
+#define BCM43xx_DMA64_DCTL0_DTABLEEND 0x10000000
+#define BCM43xx_DMA64_DCTL0_IRQ 0x20000000
+#define BCM43xx_DMA64_DCTL0_FRAMEEND 0x40000000
+#define BCM43xx_DMA64_DCTL0_FRAMESTART 0x80000000
+#define BCM43xx_DMA64_DCTL1_BYTECNT 0x00001FFF
+#define BCM43xx_DMA64_DCTL1_ADDREXT_MASK 0x00030000
+#define BCM43xx_DMA64_DCTL1_ADDREXT_SHIFT 16
+
+
+
+struct bcm43xx_dmadesc_generic {
+ union {
+ struct bcm43xx_dmadesc32 dma32;
+ struct bcm43xx_dmadesc64 dma64;
+ } __attribute__((__packed__));
+} __attribute__((__packed__));
+
+
+/* Misc DMA constants */
+#define BCM43xx_DMA_RINGMEMSIZE PAGE_SIZE
+#define BCM43xx_DMA0_RX_FRAMEOFFSET 30
+#define BCM43xx_DMA3_RX_FRAMEOFFSET 0
+
+
+/* DMA engine tuning knobs */
+#define BCM43xx_TXRING_SLOTS 128
+#define BCM43xx_RXRING_SLOTS 64
+#define BCM43xx_DMA0_RX_BUFFERSIZE (2304 + 100)
+#define BCM43xx_DMA3_RX_BUFFERSIZE 16
+
+
+
+#ifdef CONFIG_BCM43XX_MAC80211_DMA
+
+
+struct sk_buff;
+struct bcm43xx_private;
+struct bcm43xx_txstatus;
+
+
+struct bcm43xx_dmadesc_meta {
+ /* The kernel DMA-able buffer. */
+ struct sk_buff *skb;
+ /* DMA base bus-address of the descriptor buffer. */
+ dma_addr_t dmaaddr;
+ /* ieee80211 TX status. Only used once per 802.11 frag. */
+ u8 is_last_fragment;
+ struct ieee80211_tx_status txstat;
+};
+
+struct bcm43xx_dmaring;
+
+/* Lowlevel DMA operations that differ between 32bit and 64bit DMA. */
+struct bcm43xx_dma_ops {
+ struct bcm43xx_dmadesc_generic * (*idx2desc)(struct bcm43xx_dmaring *ring,
+ int slot,
+ struct bcm43xx_dmadesc_meta **meta);
+ void (*fill_descriptor)(struct bcm43xx_dmaring *ring,
+ struct bcm43xx_dmadesc_generic *desc,
+ dma_addr_t dmaaddr, u16 bufsize,
+ int start, int end, int irq);
+ void (*poke_tx)(struct bcm43xx_dmaring *ring, int slot);
+ void (*tx_suspend)(struct bcm43xx_dmaring *ring);
+ void (*tx_resume)(struct bcm43xx_dmaring *ring);
+ int (*get_current_rxslot)(struct bcm43xx_dmaring *ring);
+ void (*set_current_rxslot)(struct bcm43xx_dmaring *ring, int slot);
+};
+
+struct bcm43xx_dmaring {
+ /* Lowlevel DMA ops. */
+ const struct bcm43xx_dma_ops *ops;
+ /* Kernel virtual base address of the ring memory. */
+ void *descbase;
+ /* Meta data about all descriptors. */
+ struct bcm43xx_dmadesc_meta *meta;
+ /* Cache of TX headers for each slot.
+ * This is to avoid an allocation on each TX.
+ * This is NULL for an RX ring.
+ */
+ u8 *txhdr_cache;
+ /* (Unadjusted) DMA base bus-address of the ring memory. */
+ dma_addr_t dmabase;
+ /* Number of descriptor slots in the ring. */
+ int nr_slots;
+ /* Number of used descriptor slots. */
+ int used_slots;
+ /* Currently used slot in the ring. */
+ int current_slot;
+ /* Total number of packets sent. Statistics only. */
+ unsigned int nr_tx_packets;
+ /* Frameoffset in octets. */
+ u32 frameoffset;
+ /* Descriptor buffer size. */
+ u16 rx_buffersize;
+ /* The MMIO base register of the DMA controller. */
+ u16 mmio_base;
+ /* DMA controller index number (0-5). */
+ int index;
+ /* Boolean. Is this a TX ring? */
+ u8 tx;
+ /* Boolean. 64bit DMA if true, 32bit DMA otherwise. */
+ u8 dma64;
+ /* Boolean. Is this ring stopped at ieee80211 level? */
+ u8 stopped;
+ struct bcm43xx_wldev *dev;
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+ /* Maximum number of used slots. */
+ int max_used_slots;
+#endif /* CONFIG_BCM43XX_MAC80211_DEBUG*/
+};
+
+
+static inline
+u32 bcm43xx_dma_read(struct bcm43xx_dmaring *ring,
+ u16 offset)
+{
+ return bcm43xx_read32(ring->dev, ring->mmio_base + offset);
+}
+
+static inline
+void bcm43xx_dma_write(struct bcm43xx_dmaring *ring,
+ u16 offset, u32 value)
+{
+ bcm43xx_write32(ring->dev, ring->mmio_base + offset, value);
+}
+
+
+int bcm43xx_dma_init(struct bcm43xx_wldev *dev);
+void bcm43xx_dma_free(struct bcm43xx_wldev *dev);
+
+int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_wldev *dev,
+ u16 dmacontroller_mmio_base,
+ int dma64);
+int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_wldev *dev,
+ u16 dmacontroller_mmio_base,
+ int dma64);
+
+u16 bcm43xx_dmacontroller_base(int dma64bit, int dmacontroller_idx);
+
+void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring);
+void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring);
+
+void bcm43xx_dma_get_tx_stats(struct bcm43xx_wldev *dev,
+ struct ieee80211_tx_queue_stats *stats);
+
+int bcm43xx_dma_tx(struct bcm43xx_wldev *dev,
+ struct sk_buff *skb,
+ struct ieee80211_tx_control *ctl);
+void bcm43xx_dma_handle_txstatus(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_txstatus *status);
+
+void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring);
+
+#else /* CONFIG_BCM43XX_MAC80211_DMA */
+
+
+static inline
+int bcm43xx_dma_init(struct bcm43xx_wldev *dev)
+{
+ return 0;
+}
+static inline
+void bcm43xx_dma_free(struct bcm43xx_wldev *dev)
+{
+}
+static inline
+int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_wldev *dev,
+ u16 dmacontroller_mmio_base,
+ int dma64)
+{
+ return 0;
+}
+static inline
+int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_wldev *dev,
+ u16 dmacontroller_mmio_base,
+ int dma64)
+{
+ return 0;
+}
+static inline
+void bcm43xx_dma_get_tx_stats(struct bcm43xx_wldev *dev,
+ struct ieee80211_tx_queue_stats *stats)
+{
+}
+static inline
+int bcm43xx_dma_tx(struct bcm43xx_wldev *dev,
+ struct sk_buff *skb,
+ struct ieee80211_tx_control *ctl)
+{
+ return 0;
+}
+static inline
+void bcm43xx_dma_handle_txstatus(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_txstatus *status)
+{
+}
+static inline
+void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring)
+{
+}
+static inline
+void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring)
+{
+}
+static inline
+void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring)
+{
+}
+
+#endif /* CONFIG_BCM43XX_MAC80211_DMA */
+#endif /* BCM43xx_DMA_H_ */
--- /dev/null
+/*
+
+ Broadcom BCM43xx wireless driver
+
+ Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
+ Stefano Brivio <st3@riseup.net>
+ Michael Buesch <mb@bu3sch.de>
+ Danny van Dyk <kugelfang@gentoo.org>
+ Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING. If not, write to
+ the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+ Boston, MA 02110-1301, USA.
+
+*/
+
+#include "bcm43xx_leds.h"
+#include "bcm43xx.h"
+#include "bcm43xx_main.h"
+
+static void bcm43xx_led_changestate(struct bcm43xx_led *led)
+{
+ struct bcm43xx_wldev *dev = led->dev;
+ const int index = bcm43xx_led_index(led);
+ const u16 mask = (1 << index);
+ u16 ledctl;
+
+ assert(index >= 0 && index < BCM43xx_NR_LEDS);
+ assert(led->blink_interval);
+ ledctl = bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_CONTROL);
+ ledctl = (ledctl & mask) ? (ledctl & ~mask) : (ledctl | mask);
+ bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_CONTROL, ledctl);
+}
+
+static void bcm43xx_led_blink(unsigned long d)
+{
+ struct bcm43xx_led *led = (struct bcm43xx_led *)d;
+ struct bcm43xx_wldev *dev = led->dev;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev->wl->leds_lock, flags);
+ if (led->blink_interval) {
+ bcm43xx_led_changestate(led);
+ mod_timer(&led->blink_timer, jiffies + led->blink_interval);
+ }
+ spin_unlock_irqrestore(&dev->wl->leds_lock, flags);
+}
+
+static void bcm43xx_led_blink_start(struct bcm43xx_led *led,
+ unsigned long interval)
+{
+ if (led->blink_interval)
+ return;
+ led->blink_interval = interval;
+ bcm43xx_led_changestate(led);
+ led->blink_timer.expires = jiffies + interval;
+ add_timer(&led->blink_timer);
+}
+
+static void bcm43xx_led_blink_stop(struct bcm43xx_led *led, int sync)
+{
+ struct bcm43xx_wldev *dev = led->dev;
+ const int index = bcm43xx_led_index(led);
+ u16 ledctl;
+
+ if (!led->blink_interval)
+ return;
+ if (unlikely(sync))
+ del_timer_sync(&led->blink_timer);
+ else
+ del_timer(&led->blink_timer);
+ led->blink_interval = 0;
+
+ /* Make sure the LED is turned off. */
+ assert(index >= 0 && index < BCM43xx_NR_LEDS);
+ ledctl = bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_CONTROL);
+ if (led->activelow)
+ ledctl |= (1 << index);
+ else
+ ledctl &= ~(1 << index);
+ bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_CONTROL, ledctl);
+}
+
+static void bcm43xx_led_init_hardcoded(struct bcm43xx_wldev *dev,
+ struct bcm43xx_led *led,
+ int led_index)
+{
+ struct ssb_bus *bus = dev->dev->bus;
+
+ /* This function is called, if the behaviour (and activelow)
+ * information for a LED is missing in the SPROM.
+ * We hardcode the behaviour values for various devices here.
+ * Note that the BCM43xx_LED_TEST_XXX behaviour values can
+ * be used to figure out which led is mapped to which index.
+ */
+
+ switch (led_index) {
+ case 0:
+ led->behaviour = BCM43xx_LED_ACTIVITY;
+ led->activelow = 1;
+ if (bus->board_vendor == PCI_VENDOR_ID_COMPAQ)
+ led->behaviour = BCM43xx_LED_RADIO_ALL;
+ break;
+ case 1:
+ led->behaviour = BCM43xx_LED_RADIO_B;
+ if (bus->board_vendor == PCI_VENDOR_ID_ASUSTEK)
+ led->behaviour = BCM43xx_LED_ASSOC;
+ break;
+ case 2:
+ led->behaviour = BCM43xx_LED_RADIO_A;
+ break;
+ case 3:
+ led->behaviour = BCM43xx_LED_OFF;
+ break;
+ default:
+ assert(0);
+ }
+}
+
+int bcm43xx_leds_init(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_led *led;
+ u8 sprom[4];
+ int i;
+
+ sprom[0] = dev->dev->bus->sprom.r1.gpio0;
+ sprom[1] = dev->dev->bus->sprom.r1.gpio1;
+ sprom[2] = dev->dev->bus->sprom.r1.gpio2;
+ sprom[3] = dev->dev->bus->sprom.r1.gpio3;
+
+ for (i = 0; i < BCM43xx_NR_LEDS; i++) {
+ led = &(dev->leds[i]);
+ led->dev = dev;
+ setup_timer(&led->blink_timer,
+ bcm43xx_led_blink,
+ (unsigned long)led);
+
+ if (sprom[i] == 0xFF) {
+ bcm43xx_led_init_hardcoded(dev, led, i);
+ } else {
+ led->behaviour = sprom[i] & BCM43xx_LED_BEHAVIOUR;
+ led->activelow = !!(sprom[i] & BCM43xx_LED_ACTIVELOW);
+ }
+ }
+
+ return 0;
+}
+
+void bcm43xx_leds_exit(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_led *led;
+ int i;
+
+ for (i = 0; i < BCM43xx_NR_LEDS; i++) {
+ led = &(dev->leds[i]);
+ bcm43xx_led_blink_stop(led, 1);
+ }
+ bcm43xx_leds_switch_all(dev, 0);
+}
+
+void bcm43xx_leds_update(struct bcm43xx_wldev *dev, int activity)
+{
+ struct bcm43xx_led *led;
+ struct bcm43xx_phy *phy = &dev->phy;
+ const int transferring = (jiffies - dev->stats.last_tx) < BCM43xx_LED_XFER_THRES;
+ int i, turn_on;
+ unsigned long interval = 0;
+ u16 ledctl;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev->wl->leds_lock, flags);
+ ledctl = bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_CONTROL);
+ for (i = 0; i < BCM43xx_NR_LEDS; i++) {
+ led = &(dev->leds[i]);
+
+ turn_on = 0;
+ switch (led->behaviour) {
+ case BCM43xx_LED_INACTIVE:
+ continue;
+ case BCM43xx_LED_OFF:
+ break;
+ case BCM43xx_LED_ON:
+ turn_on = 1;
+ break;
+ case BCM43xx_LED_ACTIVITY:
+ turn_on = activity;
+ break;
+ case BCM43xx_LED_RADIO_ALL:
+ turn_on = phy->radio_on && bcm43xx_is_hw_radio_enabled(dev);
+ break;
+ case BCM43xx_LED_RADIO_A:
+ turn_on = (phy->radio_on && bcm43xx_is_hw_radio_enabled(dev)
+ && phy->type == BCM43xx_PHYTYPE_A);
+ break;
+ case BCM43xx_LED_RADIO_B:
+ turn_on = (phy->radio_on && bcm43xx_is_hw_radio_enabled(dev) &&
+ (phy->type == BCM43xx_PHYTYPE_B ||
+ phy->type == BCM43xx_PHYTYPE_G));
+ break;
+ case BCM43xx_LED_MODE_BG:
+ if (phy->type == BCM43xx_PHYTYPE_G && bcm43xx_is_hw_radio_enabled(dev) &&
+ 1/*FIXME: using G rates.*/)
+ turn_on = 1;
+ break;
+ case BCM43xx_LED_TRANSFER:
+ if (transferring)
+ bcm43xx_led_blink_start(led, BCM43xx_LEDBLINK_MEDIUM);
+ else
+ bcm43xx_led_blink_stop(led, 0);
+ continue;
+ case BCM43xx_LED_APTRANSFER:
+ if (bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
+ if (transferring) {
+ interval = BCM43xx_LEDBLINK_FAST;
+ turn_on = 1;
+ }
+ } else {
+ turn_on = 1;
+ if (0/*TODO: not assoc*/)
+ interval = BCM43xx_LEDBLINK_SLOW;
+ else if (transferring)
+ interval = BCM43xx_LEDBLINK_FAST;
+ else
+ turn_on = 0;
+ }
+ if (turn_on)
+ bcm43xx_led_blink_start(led, interval);
+ else
+ bcm43xx_led_blink_stop(led, 0);
+ continue;
+ case BCM43xx_LED_WEIRD:
+ //TODO
+ break;
+ case BCM43xx_LED_ASSOC:
+ if (1/*dev->softmac->associated*/)
+ turn_on = 1;
+ break;
+#ifdef CONFIG_BCM43XX_DEBUG
+ case BCM43xx_LED_TEST_BLINKSLOW:
+ bcm43xx_led_blink_start(led, BCM43xx_LEDBLINK_SLOW);
+ continue;
+ case BCM43xx_LED_TEST_BLINKMEDIUM:
+ bcm43xx_led_blink_start(led, BCM43xx_LEDBLINK_MEDIUM);
+ continue;
+ case BCM43xx_LED_TEST_BLINKFAST:
+ bcm43xx_led_blink_start(led, BCM43xx_LEDBLINK_FAST);
+ continue;
+#endif /* CONFIG_BCM43XX_DEBUG */
+ default:
+ assert(0);
+ };
+
+ if (led->activelow)
+ turn_on = !turn_on;
+ if (turn_on)
+ ledctl |= (1 << i);
+ else
+ ledctl &= ~(1 << i);
+ }
+ bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_CONTROL, ledctl);
+ spin_unlock_irqrestore(&dev->wl->leds_lock, flags);
+}
+
+void bcm43xx_leds_switch_all(struct bcm43xx_wldev *dev, int on)
+{
+ struct bcm43xx_led *led;
+ u16 ledctl;
+ int i;
+ int bit_on;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev->wl->leds_lock, flags);
+ ledctl = bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_CONTROL);
+ for (i = 0; i < BCM43xx_NR_LEDS; i++) {
+ led = &(dev->leds[i]);
+ if (led->behaviour == BCM43xx_LED_INACTIVE)
+ continue;
+ if (on)
+ bit_on = led->activelow ? 0 : 1;
+ else
+ bit_on = led->activelow ? 1 : 0;
+ if (bit_on)
+ ledctl |= (1 << i);
+ else
+ ledctl &= ~(1 << i);
+ }
+ bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_CONTROL, ledctl);
+ spin_unlock_irqrestore(&dev->wl->leds_lock, flags);
+}
--- /dev/null
+#ifndef BCM43xx_LEDS_H_
+#define BCM43xx_LEDS_H_
+
+#include <linux/types.h>
+#include <linux/timer.h>
+
+
+struct bcm43xx_led {
+ u8 behaviour:7;
+ u8 activelow:1;
+
+ struct bcm43xx_wldev *dev;
+ struct timer_list blink_timer;
+ unsigned long blink_interval;
+};
+#define bcm43xx_led_index(led) ((int)((led) - (led)->dev->leds))
+
+/* Delay between state changes when blinking in jiffies */
+#define BCM43xx_LEDBLINK_SLOW (HZ / 1)
+#define BCM43xx_LEDBLINK_MEDIUM (HZ / 4)
+#define BCM43xx_LEDBLINK_FAST (HZ / 8)
+
+#define BCM43xx_LED_XFER_THRES (HZ / 100)
+
+#define BCM43xx_LED_BEHAVIOUR 0x7F
+#define BCM43xx_LED_ACTIVELOW 0x80
+enum { /* LED behaviour values */
+ BCM43xx_LED_OFF,
+ BCM43xx_LED_ON,
+ BCM43xx_LED_ACTIVITY,
+ BCM43xx_LED_RADIO_ALL,
+ BCM43xx_LED_RADIO_A,
+ BCM43xx_LED_RADIO_B,
+ BCM43xx_LED_MODE_BG,
+ BCM43xx_LED_TRANSFER,
+ BCM43xx_LED_APTRANSFER,
+ BCM43xx_LED_WEIRD,//FIXME
+ BCM43xx_LED_ASSOC,
+ BCM43xx_LED_INACTIVE,
+
+ /* Behaviour values for testing.
+ * With these values it is easier to figure out
+ * the real behaviour of leds, in case the SPROM
+ * is missing information.
+ */
+ BCM43xx_LED_TEST_BLINKSLOW,
+ BCM43xx_LED_TEST_BLINKMEDIUM,
+ BCM43xx_LED_TEST_BLINKFAST,
+};
+
+int bcm43xx_leds_init(struct bcm43xx_wldev *dev);
+void bcm43xx_leds_exit(struct bcm43xx_wldev *dev);
+void bcm43xx_leds_update(struct bcm43xx_wldev *dev, int activity);
+void bcm43xx_leds_switch_all(struct bcm43xx_wldev *dev, int on);
+
+#endif /* BCM43xx_LEDS_H_ */
--- /dev/null
+/*
+
+ Broadcom BCM43xx wireless driver
+
+ G PHY LO (LocalOscillator) Measuring and Control routines
+
+ Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
+ Copyright (c) 2005, 2006 Stefano Brivio <st3@riseup.net>
+ Copyright (c) 2005-2007 Michael Buesch <mb@bu3sch.de>
+ Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
+ Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING. If not, write to
+ the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+ Boston, MA 02110-1301, USA.
+
+*/
+
+#include "bcm43xx.h"
+#include "bcm43xx_lo.h"
+#include "bcm43xx_phy.h"
+#include "bcm43xx_main.h"
+
+#include <linux/delay.h>
+
+
+/* Write the LocalOscillator Control (adjust) value-pair. */
+static void bcm43xx_lo_write(struct bcm43xx_wldev *dev,
+ struct bcm43xx_loctl *control)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 value;
+ u16 reg;
+
+ if (BCM43xx_DEBUG) {
+ if (unlikely(abs(control->i) > 16 ||
+ abs(control->q) > 16)) {
+ printk(KERN_ERR PFX "ERROR: Invalid LO control pair "
+ "(I: %d, Q: %d)\n",
+ control->i, control->q);
+ dump_stack();
+ return;
+ }
+ }
+
+ value = (u8)(control->q);
+ value |= ((u8)(control->i)) << 8;
+
+ reg = (phy->type == BCM43xx_PHYTYPE_B) ? 0x002F : BCM43xx_PHY_LO_CTL;
+ bcm43xx_phy_write(dev, reg, value);
+}
+
+static inline
+void assert_rfatt_and_bbatt(const struct bcm43xx_rfatt *rfatt,
+ const struct bcm43xx_bbatt *bbatt)
+{
+ if (BCM43xx_DEBUG) {
+ int err = 0;
+
+ if (unlikely(rfatt->att >= 16)) {
+ dprintk(KERN_ERR PFX "ERROR: invalid rf_att: %u\n",
+ rfatt->att);
+ err = 1;
+ }
+ if (unlikely(bbatt->att >= 9)) {
+ dprintk(KERN_ERR PFX "ERROR: invalid bband_att: %u\n",
+ bbatt->att);
+ err = 1;
+ }
+ if (unlikely(err))
+ dump_stack();
+ }
+}
+
+static
+struct bcm43xx_loctl * bcm43xx_get_lo_g_ctl_nopadmix(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_rfatt *rfatt,
+ const struct bcm43xx_bbatt *bbatt)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+
+ assert_rfatt_and_bbatt(rfatt, bbatt);
+ return &(lo->no_padmix[bbatt->att][rfatt->att]);
+}
+
+struct bcm43xx_loctl * bcm43xx_get_lo_g_ctl(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_rfatt *rfatt,
+ const struct bcm43xx_bbatt *bbatt)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+ struct bcm43xx_loctl *ret;
+
+ assert_rfatt_and_bbatt(rfatt, bbatt);
+ if (rfatt->with_padmix)
+ ret = &(lo->with_padmix[bbatt->att][rfatt->att]);
+ else
+ ret = &(lo->no_padmix[bbatt->att][rfatt->att]);
+
+ return ret;
+}
+
+/* Call a function for every possible LO control value-pair. */
+static int bcm43xx_call_for_each_loctl(struct bcm43xx_wldev *dev,
+ int (*func)(struct bcm43xx_wldev *,
+ struct bcm43xx_loctl *))
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct bcm43xx_txpower_lo_control *ctl = phy->lo_control;
+ int i, j;
+ int err;
+
+ for (i = 0; i < BCM43xx_NR_BB; i++) {
+ for (j = 0; j < BCM43xx_NR_RF; j++) {
+ err = func(dev, &(ctl->with_padmix[i][j]));
+ if (unlikely(err))
+ return err;
+ }
+ }
+ for (i = 0; i < BCM43xx_NR_BB; i++) {
+ for (j = 0; j < BCM43xx_NR_RF; j++) {
+ err = func(dev, &(ctl->no_padmix[i][j]));
+ if (unlikely(err))
+ return err;
+ }
+ }
+
+ return 0;
+}
+
+static u16 lo_b_r15_loop(struct bcm43xx_wldev *dev)
+{
+ int i;
+ u16 ret = 0;
+
+ for (i = 0; i < 10; i++){
+ bcm43xx_phy_write(dev, 0x0015, 0xAFA0);
+ udelay(1);
+ bcm43xx_phy_write(dev, 0x0015, 0xEFA0);
+ udelay(10);
+ bcm43xx_phy_write(dev, 0x0015, 0xFFA0);
+ udelay(40);
+ ret += bcm43xx_phy_read(dev, 0x002C);
+ }
+
+ return ret;
+}
+
+void bcm43xx_lo_b_measure(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 regstack[12] = { 0 };
+ u16 mls;
+ u16 fval;
+ int i, j;
+
+ regstack[0] = bcm43xx_phy_read(dev, 0x0015);
+ regstack[1] = bcm43xx_radio_read16(dev, 0x0052) & 0xFFF0;
+
+ if (phy->radio_ver == 0x2053) {
+ regstack[2] = bcm43xx_phy_read(dev, 0x000A);
+ regstack[3] = bcm43xx_phy_read(dev, 0x002A);
+ regstack[4] = bcm43xx_phy_read(dev, 0x0035);
+ regstack[5] = bcm43xx_phy_read(dev, 0x0003);
+ regstack[6] = bcm43xx_phy_read(dev, 0x0001);
+ regstack[7] = bcm43xx_phy_read(dev, 0x0030);
+
+ regstack[8] = bcm43xx_radio_read16(dev, 0x0043);
+ regstack[9] = bcm43xx_radio_read16(dev, 0x007A);
+ regstack[10] = bcm43xx_read16(dev, 0x03EC);
+ regstack[11] = bcm43xx_radio_read16(dev, 0x0052) & 0x00F0;
+
+ bcm43xx_phy_write(dev, 0x0030, 0x00FF);
+ bcm43xx_write16(dev, 0x03EC, 0x3F3F);
+ bcm43xx_phy_write(dev, 0x0035, regstack[4] & 0xFF7F);
+ bcm43xx_radio_write16(dev, 0x007A, regstack[9] & 0xFFF0);
+ }
+ bcm43xx_phy_write(dev, 0x0015, 0xB000);
+ bcm43xx_phy_write(dev, 0x002B, 0x0004);
+
+ if (phy->radio_ver == 0x2053) {
+ bcm43xx_phy_write(dev, 0x002B, 0x0203);
+ bcm43xx_phy_write(dev, 0x002A, 0x08A3);
+ }
+
+ phy->minlowsig[0] = 0xFFFF;
+
+ for (i = 0; i < 4; i++) {
+ bcm43xx_radio_write16(dev, 0x0052, regstack[1] | i);
+ lo_b_r15_loop(dev);
+ }
+ for (i = 0; i < 10; i++) {
+ bcm43xx_radio_write16(dev, 0x0052, regstack[1] | i);
+ mls = lo_b_r15_loop(dev) / 10;
+ if (mls < phy->minlowsig[0]) {
+ phy->minlowsig[0] = mls;
+ phy->minlowsigpos[0] = i;
+ }
+ }
+ bcm43xx_radio_write16(dev, 0x0052, regstack[1] | phy->minlowsigpos[0]);
+
+ phy->minlowsig[1] = 0xFFFF;
+
+ for (i = -4; i < 5; i += 2) {
+ for (j = -4; j < 5; j += 2) {
+ if (j < 0)
+ fval = (0x0100 * i) + j + 0x0100;
+ else
+ fval = (0x0100 * i) + j;
+ bcm43xx_phy_write(dev, 0x002F, fval);
+ mls = lo_b_r15_loop(dev) / 10;
+ if (mls < phy->minlowsig[1]) {
+ phy->minlowsig[1] = mls;
+ phy->minlowsigpos[1] = fval;
+ }
+ }
+ }
+ phy->minlowsigpos[1] += 0x0101;
+
+ bcm43xx_phy_write(dev, 0x002F, phy->minlowsigpos[1]);
+ if (phy->radio_ver == 0x2053) {
+ bcm43xx_phy_write(dev, 0x000A, regstack[2]);
+ bcm43xx_phy_write(dev, 0x002A, regstack[3]);
+ bcm43xx_phy_write(dev, 0x0035, regstack[4]);
+ bcm43xx_phy_write(dev, 0x0003, regstack[5]);
+ bcm43xx_phy_write(dev, 0x0001, regstack[6]);
+ bcm43xx_phy_write(dev, 0x0030, regstack[7]);
+
+ bcm43xx_radio_write16(dev, 0x0043, regstack[8]);
+ bcm43xx_radio_write16(dev, 0x007A, regstack[9]);
+
+ bcm43xx_radio_write16(dev, 0x0052,
+ (bcm43xx_radio_read16(dev, 0x0052) & 0x000F)
+ | regstack[11]);
+
+ bcm43xx_write16(dev, 0x03EC, regstack[10]);
+ }
+ bcm43xx_phy_write(dev, 0x0015, regstack[0]);
+}
+
+static u16 lo_measure_feedthrough(struct bcm43xx_wldev *dev,
+ u16 lna, u16 pga, u16 trsw_rx)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 rfover;
+
+ if (phy->gmode) {
+ lna <<= BCM43xx_PHY_RFOVERVAL_LNA_SHIFT;
+ pga <<= BCM43xx_PHY_RFOVERVAL_PGA_SHIFT;
+
+ assert((lna & ~BCM43xx_PHY_RFOVERVAL_LNA) == 0);
+ assert((pga & ~BCM43xx_PHY_RFOVERVAL_PGA) == 0);
+/*FIXME This assertion fails assert((trsw_rx & ~(BCM43xx_PHY_RFOVERVAL_TRSWRX |
+ BCM43xx_PHY_RFOVERVAL_BW)) == 0);
+*/
+trsw_rx &= (BCM43xx_PHY_RFOVERVAL_TRSWRX | BCM43xx_PHY_RFOVERVAL_BW);
+
+ /* Construct the RF Override Value */
+ rfover = BCM43xx_PHY_RFOVERVAL_UNK;
+ rfover |= pga;
+ rfover |= lna;
+ rfover |= trsw_rx;
+ if ((dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_EXTLNA) &&
+ phy->rev > 6)
+ rfover |= BCM43xx_PHY_RFOVERVAL_EXTLNA;
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xE300);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, rfover);
+ udelay(10);
+ rfover |= BCM43xx_PHY_RFOVERVAL_BW_LBW;
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, rfover);
+ udelay(10);
+ rfover |= BCM43xx_PHY_RFOVERVAL_BW_LPF;
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, rfover);
+ udelay(10);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xF300);
+ } else {
+ pga |= BCM43xx_PHY_PGACTL_UNKNOWN;
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, pga);
+ udelay(10);
+ pga |= BCM43xx_PHY_PGACTL_LOWBANDW;
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, pga);
+ udelay(10);
+ pga |= BCM43xx_PHY_PGACTL_LPF;
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, pga);
+ }
+ udelay(21);
+
+ return bcm43xx_phy_read(dev, BCM43xx_PHY_LO_LEAKAGE);
+}
+
+/* TXCTL Register and Value Table.
+ * Returns the "TXCTL Register".
+ * "value" is the "TXCTL Value".
+ * "pad_mix_gain" is the PAD Mixer Gain.
+ */
+static u16 lo_txctl_register_table(struct bcm43xx_wldev *dev,
+ u16 *value, u16 *pad_mix_gain)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 reg, v, padmix;
+
+ if (phy->type == BCM43xx_PHYTYPE_B) {
+ v = 0x30;
+ if (phy->radio_rev <= 5) {
+ reg = 0x43;
+ padmix = 0;
+ } else {
+ reg = 0x52;
+ padmix = 5;
+ }
+ } else {
+ if (phy->rev >= 2 && phy->radio_rev == 8) {
+ reg = 0x43;
+ v = 0x10;
+ padmix = 2;
+ } else {
+ reg = 0x52;
+ v = 0x30;
+ padmix = 5;
+ }
+ }
+ if (value)
+ *value = v;
+ if (pad_mix_gain)
+ *pad_mix_gain = padmix;
+
+ return reg;
+}
+
+static void lo_measure_txctl_values(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+ u16 reg, mask;
+ u16 trsw_rx, pga;
+ u16 radio_pctl_reg;
+
+ static const u8 tx_bias_values[] = {
+ 0x09, 0x08, 0x0A, 0x01, 0x00,
+ 0x02, 0x05, 0x04, 0x06,
+ };
+ static const u8 tx_magn_values[] = {
+ 0x70, 0x40,
+ };
+
+ if (!has_loopback_gain(phy)) {
+ radio_pctl_reg = 6;
+ trsw_rx = 2;
+ pga = 0;
+ } else {
+ int lb_gain; /* Loopback gain (in dB) */
+
+ trsw_rx = 0;
+ lb_gain = phy->max_lb_gain / 2;
+ if (lb_gain > 10) {
+ radio_pctl_reg = 0;
+ pga = abs(10 - lb_gain) / 6;
+ pga = limit_value(pga, 0, 15);
+ } else {
+ int cmp_val;
+ int tmp;
+
+ pga = 0;
+ cmp_val = 0x24;
+ if ((phy->rev >= 2) &&
+ (phy->radio_ver == 0x2050) &&
+ (phy->radio_rev == 8))
+ cmp_val = 0x3C;
+ tmp = lb_gain;
+ if ((10 - lb_gain) < cmp_val)
+ tmp = (10 - lb_gain);
+ if (tmp < 0)
+ tmp += 6;
+ else
+ tmp += 3;
+ cmp_val /= 4;
+ tmp /= 4;
+ if (tmp >= cmp_val)
+ radio_pctl_reg = cmp_val;
+ else
+ radio_pctl_reg = tmp;
+ }
+ }
+ bcm43xx_radio_write16(dev, 0x43,
+ (bcm43xx_radio_read16(dev, 0x43)
+ & 0xFFF0) | radio_pctl_reg);
+ bcm43xx_phy_set_baseband_attenuation(dev, 2);
+
+ reg = lo_txctl_register_table(dev, &mask, NULL);
+ mask = ~mask;
+ bcm43xx_radio_write16(dev, reg,
+ bcm43xx_radio_read16(dev, reg)
+ & mask);
+
+ if (has_tx_magnification(phy)) {
+ int i, j;
+ int feedthrough;
+ int min_feedth = 0xFFFF;
+ u8 tx_magn, tx_bias;
+
+ for (i = 0; i < ARRAY_SIZE(tx_magn_values); i++) {
+ tx_magn = tx_magn_values[i];
+ bcm43xx_radio_write16(dev, 0x52,
+ (bcm43xx_radio_read16(dev, 0x52)
+ & 0xFF0F) | tx_magn);
+ for (j = 0; j < ARRAY_SIZE(tx_bias_values); j++) {
+ tx_bias = tx_bias_values[j];
+ bcm43xx_radio_write16(dev, 0x52,
+ (bcm43xx_radio_read16(dev, 0x52)
+ & 0xFFF0) | tx_bias);
+ feedthrough = lo_measure_feedthrough(dev, 0, pga, trsw_rx);
+ if (feedthrough < min_feedth) {
+ lo->tx_bias = tx_bias;
+ lo->tx_magn = tx_magn;
+ min_feedth = feedthrough;
+ }
+ if (lo->tx_bias == 0)
+ break;
+ }
+ bcm43xx_radio_write16(dev, 0x52,
+ (bcm43xx_radio_read16(dev, 0x52)
+ & 0xFF00) | lo->tx_bias | lo->tx_magn);
+ }
+ } else {
+ lo->tx_magn = 0; /* FIXME */
+ lo->tx_bias = 0;
+ bcm43xx_radio_write16(dev, 0x52,
+ bcm43xx_radio_read16(dev, 0x52)
+ & 0xFFF0); /* TX bias == 0 */
+ }
+}
+
+static void lo_read_power_vector(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+ u16 i;
+ u64 tmp;
+ u64 power_vector = 0;
+ int rf_offset, bb_offset;
+ struct bcm43xx_loctl *loctl;
+
+ for (i = 0; i < 8; i += 2) {
+ tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+ 0x310 + i);
+ /* Clear the top byte. We get holes in the bitmap... */
+ tmp &= 0xFF;
+ power_vector |= (tmp << (i * 8));
+ /* Clear the vector on the device. */
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+ 0x310 + i, 0);
+ }
+
+ if (power_vector)
+ lo->power_vector = power_vector;
+ power_vector = lo->power_vector;
+
+ for (i = 0; i < 64; i++) {
+ if (power_vector & ((u64)1ULL << i)) {
+ /* Now figure out which bcm43xx_loctl corresponds
+ * to this bit.
+ */
+ rf_offset = i / lo->rfatt_list.len;
+ bb_offset = i % lo->rfatt_list.len;//FIXME?
+ loctl = bcm43xx_get_lo_g_ctl(dev, &lo->rfatt_list.list[rf_offset],
+ &lo->bbatt_list.list[bb_offset]);
+ /* And mark it as "used", as the device told us
+ * through the bitmap it is using it.
+ */
+ loctl->used = 1;
+ }
+ }
+}
+
+/* 802.11/LO/GPHY/MeasuringGains */
+static void lo_measure_gain_values(struct bcm43xx_wldev *dev,
+ s16 max_rx_gain,
+ int use_trsw_rx)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 tmp;
+
+ if (max_rx_gain < 0)
+ max_rx_gain = 0;
+
+ if (has_loopback_gain(phy)) {
+ int trsw_rx = 0;
+ int trsw_rx_gain;
+
+ if (use_trsw_rx) {
+ trsw_rx_gain = phy->trsw_rx_gain / 2;
+ if (max_rx_gain >= trsw_rx_gain) {
+ trsw_rx_gain = max_rx_gain - trsw_rx_gain;
+ trsw_rx = 0x20;
+ }
+ } else
+ trsw_rx_gain = max_rx_gain;
+ if (trsw_rx_gain < 9) {
+ phy->lna_lod_gain = 0;
+ } else {
+ phy->lna_lod_gain = 1;
+ trsw_rx_gain -= 8;
+ }
+ trsw_rx_gain = limit_value(trsw_rx_gain, 0, 0x2D);
+ phy->pga_gain = trsw_rx_gain / 3;
+ if (phy->pga_gain >= 5) {
+ phy->pga_gain -= 5;
+ phy->lna_gain = 2;
+ } else
+ phy->lna_gain = 0;
+ } else {
+ phy->lna_gain = 0;
+ phy->trsw_rx_gain = 0x20;
+ if (max_rx_gain >= 0x14) {
+ phy->lna_lod_gain = 1;
+ phy->pga_gain = 2;
+ } else if (max_rx_gain >= 0x12) {
+ phy->lna_lod_gain = 1;
+ phy->pga_gain = 1;
+ } else if (max_rx_gain >= 0xF) {
+ phy->lna_lod_gain = 1;
+ phy->pga_gain = 0;
+ } else {
+ phy->lna_lod_gain = 0;
+ phy->pga_gain = 0;
+ }
+ }
+
+ tmp = bcm43xx_radio_read16(dev, 0x7A);
+ if (phy->lna_lod_gain == 0)
+ tmp &= ~0x0008;
+ else
+ tmp |= 0x0008;
+ bcm43xx_radio_write16(dev, 0x7A, tmp);
+}
+
+struct lo_g_saved_values {
+ u8 old_channel;
+
+ /* Core registers */
+ u16 reg_3F4;
+ u16 reg_3E2;
+
+ /* PHY registers */
+ u16 phy_lo_mask;
+ u16 phy_extg_01;
+ u16 phy_dacctl_hwpctl;
+ u16 phy_dacctl;
+ u16 phy_base_14;
+ u16 phy_hpwr_tssictl;
+ u16 phy_analogover;
+ u16 phy_analogoverval;
+ u16 phy_rfover;
+ u16 phy_rfoverval;
+ u16 phy_classctl;
+ u16 phy_base_3E;
+ u16 phy_crs0;
+ u16 phy_pgactl;
+ u16 phy_base_2A;
+ u16 phy_syncctl;
+ u16 phy_base_30;
+ u16 phy_base_06;
+
+ /* Radio registers */
+ u16 radio_43;
+ u16 radio_7A;
+ u16 radio_52;
+};
+
+static void lo_measure_setup(struct bcm43xx_wldev *dev,
+ struct lo_g_saved_values *sav)
+{
+ struct ssb_sprom *sprom = &dev->dev->bus->sprom;
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+ u16 tmp;
+
+ if (has_hardware_pctl(phy)) {
+ sav->phy_lo_mask = bcm43xx_phy_read(dev, BCM43xx_PHY_LO_MASK);
+ sav->phy_extg_01 = bcm43xx_phy_read(dev, BCM43xx_PHY_EXTG(0x01));
+ sav->phy_dacctl_hwpctl = bcm43xx_phy_read(dev, BCM43xx_PHY_DACCTL);
+ sav->phy_base_14 = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x14));
+ sav->phy_hpwr_tssictl = bcm43xx_phy_read(dev, BCM43xx_PHY_HPWR_TSSICTL);
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_HPWR_TSSICTL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_HPWR_TSSICTL)
+ | 0x100);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_EXTG(0x01),
+ bcm43xx_phy_read(dev, BCM43xx_PHY_EXTG(0x01))
+ | 0x40);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_DACCTL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_DACCTL)
+ | 0x40);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x14),
+ bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x14))
+ | 0x200);
+ }
+ if (phy->type == BCM43xx_PHYTYPE_B &&
+ phy->radio_ver == 0x2050 &&
+ phy->radio_rev < 6) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x16), 0x410);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x17), 0x820);
+ }
+ if (!lo->rebuild && has_hardware_pctl(phy))
+ lo_read_power_vector(dev);
+ if (phy->rev >= 2) {
+ sav->phy_analogover = bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVER);
+ sav->phy_analogoverval = bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVERVAL);
+ sav->phy_rfover = bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER);
+ sav->phy_rfoverval = bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL);
+ sav->phy_classctl = bcm43xx_phy_read(dev, BCM43xx_PHY_CLASSCTL);
+ sav->phy_base_3E = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x3E));
+ sav->phy_crs0 = bcm43xx_phy_read(dev, BCM43xx_PHY_CRS0);
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_CLASSCTL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_CLASSCTL)
+ & 0xFFFC);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_CRS0,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_CRS0)
+ & 0x7FFF);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVER)
+ | 0x0003);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVERVAL)
+ & 0xFFFC);
+ if (phy->type == BCM43xx_PHYTYPE_G) {
+ if ((phy->rev >= 7) &&
+ (sprom->r1.boardflags_lo & BCM43xx_BFL_EXTLNA)) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, 0x933);
+ } else {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, 0x133);
+ }
+ } else {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, 0);
+ }
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x3E), 0);
+ }
+ sav->reg_3F4 = bcm43xx_read16(dev, 0x3F4);
+ sav->reg_3E2 = bcm43xx_read16(dev, 0x3E2);
+ sav->radio_43 = bcm43xx_radio_read16(dev, 0x43);
+ sav->radio_7A = bcm43xx_radio_read16(dev, 0x7A);
+ sav->phy_pgactl = bcm43xx_phy_read(dev, BCM43xx_PHY_PGACTL);
+ sav->phy_base_2A = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x2A));
+ sav->phy_syncctl = bcm43xx_phy_read(dev, BCM43xx_PHY_SYNCCTL);
+ sav->phy_dacctl = bcm43xx_phy_read(dev, BCM43xx_PHY_DACCTL);
+
+ if (!has_tx_magnification(phy)) {
+ sav->radio_52 = bcm43xx_radio_read16(dev, 0x52);
+ sav->radio_52 &= 0x00F0;
+ }
+ if (phy->type == BCM43xx_PHYTYPE_B) {
+ sav->phy_base_30 = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x30));
+ sav->phy_base_06 = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x06));
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x30), 0x00FF);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x06), 0x3F3F);
+ } else {
+ bcm43xx_write16(dev, 0x3E2,
+ bcm43xx_read16(dev, 0x3E2)
+ | 0x8000);
+ }
+ bcm43xx_write16(dev, 0x3F4,
+ bcm43xx_read16(dev, 0x3F4)
+ & 0xF000);
+
+ tmp = (phy->type == BCM43xx_PHYTYPE_G) ? BCM43xx_PHY_LO_MASK : BCM43xx_PHY_BASE(0x2E);
+ bcm43xx_phy_write(dev, tmp, 0x007F);
+
+ tmp = sav->phy_syncctl;
+ bcm43xx_phy_write(dev, BCM43xx_PHY_SYNCCTL, tmp & 0xFF7F);
+ tmp = sav->radio_7A;
+ bcm43xx_radio_write16(dev, 0x007A, tmp & 0xFFF0);
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2A), 0x8A3);
+ if (phy->type == BCM43xx_PHYTYPE_G ||
+ (phy->type == BCM43xx_PHYTYPE_B &&
+ phy->radio_ver == 0x2050 &&
+ phy->radio_rev >= 6)) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2B), 0x1003);
+ } else
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2B), 0x0802);
+ if (phy->rev >= 2)
+ bcm43xx_dummy_transmission(dev);
+ bcm43xx_radio_selectchannel(dev, 6, 0);
+ bcm43xx_radio_read16(dev, 0x51); /* dummy read */
+ if (phy->type == BCM43xx_PHYTYPE_G)
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2F), 0);
+ if (lo->rebuild)
+ lo_measure_txctl_values(dev);
+ if (phy->type == BCM43xx_PHYTYPE_G && phy->rev >= 3) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, 0xC078);
+ } else {
+ if (phy->type == BCM43xx_PHYTYPE_B)
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2E), 0x8078);
+ else
+ bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, 0x8078);
+ }
+}
+
+static void lo_measure_restore(struct bcm43xx_wldev *dev,
+ struct lo_g_saved_values *sav)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+ u16 tmp;
+
+ if (phy->rev >= 2) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xE300);
+ tmp = (phy->pga_gain << 8);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, tmp | 0xA0);
+ udelay(5);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, tmp | 0xA2);
+ udelay(2);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, tmp | 0xA3);
+ } else {
+ tmp = (phy->pga_gain | 0xEFA0);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, tmp);
+ }
+ if (has_hardware_pctl(phy)) {
+ bcm43xx_gphy_dc_lt_init(dev);
+ } else {
+ if (lo->rebuild)
+ bcm43xx_lo_g_adjust_to(dev, 3, 2, 0);
+ else
+ bcm43xx_lo_g_adjust(dev);
+ }
+ if (phy->type == BCM43xx_PHYTYPE_G) {
+ if (phy->rev >= 3)
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2E), 0xC078);
+ else
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2E), 0x8078);
+ if (phy->rev >= 2)
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2F), 0x0202);
+ else
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2F), 0x0101);
+ }
+ bcm43xx_write16(dev, 0x3F4, sav->reg_3F4);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, sav->phy_pgactl);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2A), sav->phy_base_2A);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_SYNCCTL, sav->phy_syncctl);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_DACCTL, sav->phy_dacctl);
+ bcm43xx_radio_write16(dev, 0x43, sav->radio_43);
+ bcm43xx_radio_write16(dev, 0x7A, sav->radio_7A);
+ if (!has_tx_magnification(phy)) {
+ tmp = sav->radio_52;
+ bcm43xx_radio_write16(dev, 0x52,
+ (bcm43xx_radio_read16(dev, 0x52)
+ & 0xFF0F) | tmp);
+ }
+ bcm43xx_write16(dev, 0x3E2, sav->reg_3E2);
+ if (phy->type == BCM43xx_PHYTYPE_B &&
+ phy->radio_ver == 0x2050 &&
+ phy->radio_rev <= 5) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x30), sav->phy_base_30);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x06), sav->phy_base_06);
+ }
+ if (phy->rev >= 2) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER, sav->phy_analogover);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL, sav->phy_analogoverval);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_CLASSCTL, sav->phy_classctl);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, sav->phy_rfover);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, sav->phy_rfoverval);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x3E), sav->phy_base_3E);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_CRS0, sav->phy_crs0);
+ }
+ if (has_hardware_pctl(phy)) {
+ tmp = (sav->phy_lo_mask & 0xBFFF);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, tmp);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_EXTG(0x01), sav->phy_extg_01);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_DACCTL, sav->phy_dacctl_hwpctl);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x14), sav->phy_base_14);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_HPWR_TSSICTL, sav->phy_hpwr_tssictl);
+ }
+ bcm43xx_radio_selectchannel(dev, sav->old_channel, 1);
+}
+
+struct bcm43xx_lo_g_statemachine {
+ int current_state;
+ int nr_measured;
+ int state_val_multiplier;
+ u16 lowest_feedth;
+ struct bcm43xx_loctl min_loctl;
+};
+
+/* Loop over each possible value in this state. */
+static int lo_probe_possible_loctls(struct bcm43xx_wldev *dev,
+ struct bcm43xx_loctl *probe_loctl,
+ struct bcm43xx_lo_g_statemachine *d)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+ struct bcm43xx_loctl test_loctl;
+ struct bcm43xx_loctl orig_loctl;
+ struct bcm43xx_loctl prev_loctl = {
+ .i = -100,
+ .q = -100,
+ };
+ int i;
+ int begin, end;
+ int found_lower = 0;
+ u16 feedth;
+
+ static const struct bcm43xx_loctl modifiers[] = {
+ { .i = 1, .q = 1, },
+ { .i = 1, .q = 0, },
+ { .i = 1, .q = -1, },
+ { .i = 0, .q = -1, },
+ { .i = -1, .q = -1, },
+ { .i = -1, .q = 0, },
+ { .i = -1, .q = 1, },
+ { .i = 0, .q = 1, },
+ };
+
+ if (d->current_state == 0) {
+ begin = 1;
+ end = 8;
+ } else if (d->current_state % 2 == 0) {
+ begin = d->current_state - 1;
+ end = d->current_state + 1;
+ } else {
+ begin = d->current_state - 2;
+ end = d->current_state + 2;
+ }
+ if (begin < 1)
+ begin += 8;
+ if (end > 8)
+ end -= 8;
+
+ memcpy(&orig_loctl, probe_loctl, sizeof(struct bcm43xx_loctl));
+ i = begin;
+ d->current_state = i;
+ while (1) {
+ assert(i >= 1 && i <= 8);
+ memcpy(&test_loctl, &orig_loctl, sizeof(struct bcm43xx_loctl));
+ test_loctl.i += modifiers[i - 1].i * d->state_val_multiplier;
+ test_loctl.q += modifiers[i - 1].q * d->state_val_multiplier;
+ if ((test_loctl.i != prev_loctl.i ||
+ test_loctl.q != prev_loctl.q) &&
+ (abs(test_loctl.i) <= 16 &&
+ abs(test_loctl.q) <= 16)) {
+ bcm43xx_lo_write(dev, &test_loctl);
+ feedth = lo_measure_feedthrough(dev, phy->lna_gain,
+ phy->pga_gain,
+ phy->trsw_rx_gain);
+ if (feedth < d->lowest_feedth) {
+ memcpy(probe_loctl, &test_loctl, sizeof(struct bcm43xx_loctl));
+ found_lower = 1;
+ d->lowest_feedth = feedth;
+ if ((d->nr_measured < 2) &&
+ (!has_loopback_gain(phy) || lo->rebuild))
+ break;
+ }
+ }
+ memcpy(&prev_loctl, &test_loctl, sizeof(prev_loctl));
+ if (i == end)
+ break;
+ if (i == 8)
+ i = 1;
+ else
+ i++;
+ d->current_state = i;
+ }
+
+ return found_lower;
+}
+
+static void lo_probe_loctls_statemachine(struct bcm43xx_wldev *dev,
+ struct bcm43xx_loctl *loctl,
+ int *max_rx_gain)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+ struct bcm43xx_lo_g_statemachine d;
+ u16 feedth;
+ int found_lower;
+ struct bcm43xx_loctl probe_loctl;
+ int max_repeat = 1, repeat_cnt = 0;
+
+ d.nr_measured = 0;
+ d.state_val_multiplier = 1;
+ if (has_loopback_gain(phy) && !lo->rebuild)
+ d.state_val_multiplier = 3;
+
+ memcpy(&d.min_loctl, loctl, sizeof(struct bcm43xx_loctl));
+ if (has_loopback_gain(phy) && lo->rebuild)
+ max_repeat = 4;
+ do {
+ bcm43xx_lo_write(dev, &d.min_loctl);
+ feedth = lo_measure_feedthrough(dev, phy->lna_gain,
+ phy->pga_gain,
+ phy->trsw_rx_gain);
+ if (!lo->rebuild && feedth < 0x258) {
+ if (feedth >= 0x12C)
+ *max_rx_gain += 6;
+ else
+ *max_rx_gain += 3;
+ feedth = lo_measure_feedthrough(dev, phy->lna_gain,
+ phy->pga_gain,
+ phy->trsw_rx_gain);
+ }
+ d.lowest_feedth = feedth;
+
+ d.current_state = 0;
+ do {
+ assert(d.current_state >= 0 && d.current_state <= 8);
+ memcpy(&probe_loctl, &d.min_loctl, sizeof(struct bcm43xx_loctl));
+ found_lower = lo_probe_possible_loctls(dev, &probe_loctl, &d);
+ if (!found_lower)
+ break;
+ if ((probe_loctl.i == d.min_loctl.i) &&
+ (probe_loctl.q == d.min_loctl.q))
+ break;
+ memcpy(&d.min_loctl, &probe_loctl, sizeof(struct bcm43xx_loctl));
+ d.nr_measured++;
+ } while (d.nr_measured < 24);
+ memcpy(loctl, &d.min_loctl, sizeof(struct bcm43xx_loctl));
+
+ if (has_loopback_gain(phy)) {
+ if (d.lowest_feedth > 0x1194)
+ *max_rx_gain -= 6;
+ else if (d.lowest_feedth < 0x5DC)
+ *max_rx_gain += 3;
+ if (repeat_cnt == 0) {
+ if (d.lowest_feedth <= 0x5DC) {
+ d.state_val_multiplier = 1;
+ repeat_cnt++;
+ } else
+ d.state_val_multiplier = 2;
+ } else if (repeat_cnt == 2)
+ d.state_val_multiplier = 1;
+ }
+ lo_measure_gain_values(dev, *max_rx_gain, has_loopback_gain(phy));
+ } while (++repeat_cnt < max_repeat);
+}
+
+static void lo_measure(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+ struct bcm43xx_loctl loctl = {
+ .i = 0,
+ .q = 0,
+ };
+ struct bcm43xx_loctl *ploctl;
+ int max_rx_gain;
+ int rfidx, bbidx;
+
+ /* Values from the "TXCTL Register and Value Table" */
+ u16 txctl_reg;
+ u16 txctl_value;
+ u16 pad_mix_gain;
+
+ txctl_reg = lo_txctl_register_table(dev, &txctl_value, &pad_mix_gain);
+
+ for (rfidx = 0; rfidx < lo->rfatt_list.len; rfidx++) {
+
+ bcm43xx_radio_write16(dev, 0x43,
+ (bcm43xx_radio_read16(dev, 0x43)
+ & 0xFFF0) | lo->rfatt_list.list[rfidx].att);
+ bcm43xx_radio_write16(dev, txctl_reg,
+ (bcm43xx_radio_read16(dev, txctl_reg)
+ & ~txctl_value)
+ | (lo->rfatt_list.list[rfidx].with_padmix ? txctl_value : 0));
+
+ for (bbidx = 0; bbidx < lo->bbatt_list.len; bbidx++) {
+ if (lo->rebuild) {
+ ploctl = bcm43xx_get_lo_g_ctl_nopadmix(dev,
+ &lo->rfatt_list.list[rfidx],
+ &lo->bbatt_list.list[bbidx]);
+ } else {
+ ploctl = bcm43xx_get_lo_g_ctl(dev, &lo->rfatt_list.list[rfidx],
+ &lo->bbatt_list.list[bbidx]);
+ if (!ploctl->used)
+ continue;
+ }
+ memcpy(&loctl, ploctl, sizeof(loctl));
+
+ max_rx_gain = lo->rfatt_list.list[rfidx].att * 2;
+ max_rx_gain += lo->bbatt_list.list[bbidx].att / 2;
+ if (lo->rfatt_list.list[rfidx].with_padmix)
+ max_rx_gain -= pad_mix_gain;
+ if (has_loopback_gain(phy))
+ max_rx_gain += phy->max_lb_gain;
+ lo_measure_gain_values(dev, max_rx_gain, has_loopback_gain(phy));
+
+ bcm43xx_phy_set_baseband_attenuation(dev, lo->bbatt_list.list[bbidx].att);
+ lo_probe_loctls_statemachine(dev, &loctl, &max_rx_gain);
+ if (phy->type == BCM43xx_PHYTYPE_B) {
+ loctl.i++;
+ loctl.q++;
+ }
+ memcpy(ploctl, &loctl, sizeof(loctl));
+ }
+ }
+}
+
+#if BCM43xx_DEBUG
+static int do_validate_loctl(struct bcm43xx_wldev *dev,
+ struct bcm43xx_loctl *control)
+{
+ const int is_initializing = (bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZING);
+
+ if (unlikely(abs(control->i) > 16 ||
+ abs(control->q) > 16 ||
+ (is_initializing && control->used))) {
+ printk(KERN_ERR PFX "ERROR: LO control pair validation failed "
+ "(first: %d, second: %d, used %u)\n",
+ control->i, control->q, control->used);
+ }
+ return 0;
+}
+static void validate_all_loctls(struct bcm43xx_wldev *dev)
+{
+ bcm43xx_call_for_each_loctl(dev, do_validate_loctl);
+}
+#else /* BCM43xx_DEBUG */
+static inline void validate_all_loctls(struct bcm43xx_wldev *dev) { }
+#endif /* BCM43xx_DEBUG */
+
+void bcm43xx_lo_g_measure(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct lo_g_saved_values sav;
+
+ assert(phy->type == BCM43xx_PHYTYPE_B ||
+ phy->type == BCM43xx_PHYTYPE_G);
+
+ sav.old_channel = phy->channel;
+ lo_measure_setup(dev, &sav);
+ lo_measure(dev);
+ lo_measure_restore(dev, &sav);
+
+ validate_all_loctls(dev);
+
+ phy->lo_control->lo_measured = 1;
+ phy->lo_control->rebuild = 0;
+}
+
+void bcm43xx_lo_g_adjust(struct bcm43xx_wldev *dev)
+{
+ bcm43xx_lo_write(dev, bcm43xx_lo_g_ctl_current(dev));
+}
+
+static inline void fixup_rfatt_for_txctl1(struct bcm43xx_rfatt *rf,
+ u16 txctl1)
+{
+ if ((rf->att < 5) && (txctl1 & 0x0001))
+ rf->att = 4;
+}
+
+void bcm43xx_lo_g_adjust_to(struct bcm43xx_wldev *dev,
+ u16 rfatt, u16 bbatt, u16 txctl1)
+{
+ struct bcm43xx_rfatt rf;
+ struct bcm43xx_bbatt bb;
+ struct bcm43xx_loctl *loctl;
+
+ memset(&rf, 0, sizeof(rf));
+ memset(&bb, 0, sizeof(bb));
+ rf.att = rfatt;
+ bb.att = bbatt;
+ fixup_rfatt_for_txctl1(&rf, txctl1);
+ loctl = bcm43xx_get_lo_g_ctl(dev, &rf, &bb);
+ bcm43xx_lo_write(dev, loctl);
+}
+
+struct bcm43xx_loctl * bcm43xx_lo_g_ctl_current(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+ struct bcm43xx_rfatt rf;
+
+ memcpy(&rf, &lo->rfatt, sizeof(rf));
+ fixup_rfatt_for_txctl1(&rf, phy->txctl1);
+
+ return bcm43xx_get_lo_g_ctl(dev, &rf, &lo->bbatt);
+}
+
+static int do_mark_unused(struct bcm43xx_wldev *dev,
+ struct bcm43xx_loctl *control)
+{
+ control->used = 0;
+ return 0;
+}
+
+void bcm43xx_lo_g_ctl_mark_all_unused(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+
+ bcm43xx_call_for_each_loctl(dev, do_mark_unused);
+ lo->rebuild = 1;
+}
+
+void bcm43xx_lo_g_ctl_mark_cur_used(struct bcm43xx_wldev *dev)
+{
+ bcm43xx_lo_g_ctl_current(dev)->used = 1;
+}
--- /dev/null
+#ifndef BCM43xx_LO_H_
+#define BCM43xx_LO_H_
+
+#include "bcm43xx_phy.h"
+
+struct bcm43xx_wldev;
+
+/* Local Oscillator control value-pair. */
+struct bcm43xx_loctl {
+ /* Control values. */
+ s8 i;
+ s8 q;
+ /* "Used by hardware" flag. */
+ u8 used;
+};
+
+/* TX Power LO Control Array.
+ * Value-pairs to adjust the LocalOscillator are stored
+ * in this structure.
+ * There are two different set of values. One for "Flag is Set"
+ * and one for "Flag is Unset".
+ * By "Flag" the flag in struct bcm43xx_rfatt is meant.
+ * The Value arrays are two-dimensional. The first index
+ * is the baseband attenuation and the second index
+ * is the radio attenuation.
+ * Use bcm43xx_get_lo_g_ctl() to retrieve a value from the lists.
+ */
+struct bcm43xx_txpower_lo_control {
+#define BCM43xx_NR_BB 9
+#define BCM43xx_NR_RF 16
+ /* LO Control values, with PAD Mixer */
+ struct bcm43xx_loctl with_padmix[ BCM43xx_NR_BB ][ BCM43xx_NR_RF ];
+ /* LO Control values, without PAD Mixer */
+ struct bcm43xx_loctl no_padmix[ BCM43xx_NR_BB ][ BCM43xx_NR_RF ];
+
+ /* Flag to indicate a complete rebuild of the two tables above
+ * to the LO measuring code. */
+ u8 rebuild;
+
+ /* Lists of valid RF and BB attenuation values for this device. */
+ struct bcm43xx_rfatt_list rfatt_list;
+ struct bcm43xx_bbatt_list bbatt_list;
+
+ /* Current RF and BB attenuation and LO control values. */
+ struct bcm43xx_rfatt rfatt;
+ struct bcm43xx_bbatt bbatt;
+
+ /* Current TX Bias value */
+ u8 tx_bias;
+ /* Current TX Magnification Value (if used by the device) */
+ u8 tx_magn;
+
+ /* GPHY LO is measured. */
+ u8 lo_measured;
+
+ /* Saved device PowerVector */
+ u64 power_vector;
+};
+
+
+/* Measure the BPHY Local Oscillator. */
+void bcm43xx_lo_b_measure(struct bcm43xx_wldev *dev);
+/* Measure the BPHY/GPHY Local Oscillator. */
+void bcm43xx_lo_g_measure(struct bcm43xx_wldev *dev);
+
+/* Adjust the Local Oscillator to the saved attenuation
+ * and txctl values.
+ */
+void bcm43xx_lo_g_adjust(struct bcm43xx_wldev *dev);
+/* Adjust to specific values. */
+void bcm43xx_lo_g_adjust_to(struct bcm43xx_wldev *dev,
+ u16 rfatt, u16 bbatt, u16 txctl1);
+
+/* Returns the bcm43xx_lo_g_ctl corresponding to the current
+ * attenuation values.
+ */
+struct bcm43xx_loctl * bcm43xx_lo_g_ctl_current(struct bcm43xx_wldev *dev);
+/* Mark all possible bcm43xx_lo_g_ctl as "unused" */
+void bcm43xx_lo_g_ctl_mark_all_unused(struct bcm43xx_wldev *dev);
+/* Mark the bcm43xx_lo_g_ctl corresponding to the current
+ * attenuation values as used.
+ */
+void bcm43xx_lo_g_ctl_mark_cur_used(struct bcm43xx_wldev *dev);
+
+/* Get a reference to a LO Control value pair in the
+ * TX Power LO Control Array.
+ */
+struct bcm43xx_loctl * bcm43xx_get_lo_g_ctl(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_rfatt *rfatt,
+ const struct bcm43xx_bbatt *bbatt);
+
+#endif /* BCM43xx_LO_H_ */
--- /dev/null
+/*
+
+ Broadcom BCM43xx wireless driver
+
+ Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
+ Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
+ Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
+ Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
+ Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+ Some parts of the code in this file are derived from the ipw2200
+ driver Copyright(c) 2003 - 2004 Intel Corporation.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING. If not, write to
+ the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+ Boston, MA 02110-1301, USA.
+
+*/
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/moduleparam.h>
+#include <linux/if_arp.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#include <linux/firmware.h>
+#include <linux/wireless.h>
+#include <linux/workqueue.h>
+#include <linux/skbuff.h>
+#include <linux/dma-mapping.h>
+
+#include "bcm43xx.h"
+#include "bcm43xx_main.h"
+#include "bcm43xx_debugfs.h"
+#include "bcm43xx_phy.h"
+#include "bcm43xx_dma.h"
+#include "bcm43xx_pio.h"
+#include "bcm43xx_power.h"
+#include "bcm43xx_sysfs.h"
+#include "bcm43xx_xmit.h"
+#include "bcm43xx_sysfs.h"
+#include "bcm43xx_lo.h"
+#include "bcm43xx_pcmcia.h"
+
+
+MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
+MODULE_AUTHOR("Martin Langer");
+MODULE_AUTHOR("Stefano Brivio");
+MODULE_AUTHOR("Michael Buesch");
+MODULE_LICENSE("GPL");
+
+
+extern char *nvram_get(char *name);
+
+
+#if defined(CONFIG_BCM43XX_MAC80211_DMA) && defined(CONFIG_BCM43XX_MAC80211_PIO)
+static int modparam_pio;
+module_param_named(pio, modparam_pio, int, 0444);
+MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
+#elif defined(CONFIG_BCM43XX_MAC80211_DMA)
+# define modparam_pio 0
+#elif defined(CONFIG_BCM43XX_MAC80211_PIO)
+# define modparam_pio 1
+#endif
+
+static int modparam_bad_frames_preempt;
+module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
+MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
+
+static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
+module_param_named(short_retry, modparam_short_retry, int, 0444);
+MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
+
+static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
+module_param_named(long_retry, modparam_long_retry, int, 0444);
+MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
+
+static int modparam_noleds;
+module_param_named(noleds, modparam_noleds, int, 0444);
+MODULE_PARM_DESC(noleds, "Turn off all LED activity");
+
+static char modparam_fwpostfix[16];
+module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
+MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
+
+static int modparam_mon_keep_bad;
+module_param_named(mon_keep_bad, modparam_mon_keep_bad, int, 0444);
+MODULE_PARM_DESC(mon_keep_bad, "Keep bad frames in monitor mode");
+
+static int modparam_mon_keep_badplcp;
+module_param_named(mon_keep_badplcp, modparam_mon_keep_bad, int, 0444);
+MODULE_PARM_DESC(mon_keep_badplcp, "Keep frames with bad PLCP in monitor mode");
+
+
+static const struct ssb_device_id bcm43xx_ssb_tbl[] = {
+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, SSB_ANY_REV),
+ SSB_DEVTABLE_END
+};
+MODULE_DEVICE_TABLE(ssb, bcm43xx_ssb_tbl);
+
+
+/* Channel and ratetables are shared for all devices.
+ * They can't be const, because ieee80211 puts some precalculated
+ * data in there. This data is the same for all devices, so we don't
+ * get concurrency issues */
+#define RATETAB_ENT(_rateid, _flags) \
+ { \
+ .rate = BCM43xx_RATE_TO_BASE100KBPS(_rateid), \
+ .val = (_rateid), \
+ .val2 = (_rateid), \
+ .flags = (_flags), \
+ }
+static struct ieee80211_rate __bcm43xx_ratetable[] = {
+ RATETAB_ENT(BCM43xx_CCK_RATE_1MB, IEEE80211_RATE_CCK),
+ RATETAB_ENT(BCM43xx_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
+ RATETAB_ENT(BCM43xx_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
+ RATETAB_ENT(BCM43xx_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
+ RATETAB_ENT(BCM43xx_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
+ RATETAB_ENT(BCM43xx_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
+ RATETAB_ENT(BCM43xx_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
+ RATETAB_ENT(BCM43xx_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
+ RATETAB_ENT(BCM43xx_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
+ RATETAB_ENT(BCM43xx_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
+ RATETAB_ENT(BCM43xx_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
+ RATETAB_ENT(BCM43xx_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
+};
+#define bcm43xx_a_ratetable (__bcm43xx_ratetable + 4)
+#define bcm43xx_a_ratetable_size 8
+#define bcm43xx_b_ratetable (__bcm43xx_ratetable + 0)
+#define bcm43xx_b_ratetable_size 4
+#define bcm43xx_g_ratetable (__bcm43xx_ratetable + 0)
+#define bcm43xx_g_ratetable_size 12
+
+#define CHANTAB_ENT(_chanid, _freq) \
+ { \
+ .chan = (_chanid), \
+ .freq = (_freq), \
+ .val = (_chanid), \
+ .flag = IEEE80211_CHAN_W_SCAN | \
+ IEEE80211_CHAN_W_ACTIVE_SCAN | \
+ IEEE80211_CHAN_W_IBSS, \
+ .power_level = 0xFF, \
+ .antenna_max = 0xFF, \
+ }
+static struct ieee80211_channel bcm43xx_bg_chantable[] = {
+ CHANTAB_ENT(1, 2412),
+ CHANTAB_ENT(2, 2417),
+ CHANTAB_ENT(3, 2422),
+ CHANTAB_ENT(4, 2427),
+ CHANTAB_ENT(5, 2432),
+ CHANTAB_ENT(6, 2437),
+ CHANTAB_ENT(7, 2442),
+ CHANTAB_ENT(8, 2447),
+ CHANTAB_ENT(9, 2452),
+ CHANTAB_ENT(10, 2457),
+ CHANTAB_ENT(11, 2462),
+ CHANTAB_ENT(12, 2467),
+ CHANTAB_ENT(13, 2472),
+ CHANTAB_ENT(14, 2484),
+};
+#define bcm43xx_bg_chantable_size ARRAY_SIZE(bcm43xx_bg_chantable)
+static struct ieee80211_channel bcm43xx_a_chantable[] = {
+ CHANTAB_ENT(36, 5180),
+ CHANTAB_ENT(40, 5200),
+ CHANTAB_ENT(44, 5220),
+ CHANTAB_ENT(48, 5240),
+ CHANTAB_ENT(52, 5260),
+ CHANTAB_ENT(56, 5280),
+ CHANTAB_ENT(60, 5300),
+ CHANTAB_ENT(64, 5320),
+ CHANTAB_ENT(149, 5745),
+ CHANTAB_ENT(153, 5765),
+ CHANTAB_ENT(157, 5785),
+ CHANTAB_ENT(161, 5805),
+ CHANTAB_ENT(165, 5825),
+};
+#define bcm43xx_a_chantable_size ARRAY_SIZE(bcm43xx_a_chantable)
+
+
+static void bcm43xx_wireless_core_exit(struct bcm43xx_wldev *dev);
+static int bcm43xx_wireless_core_init(struct bcm43xx_wldev *dev);
+static void bcm43xx_wireless_core_stop(struct bcm43xx_wldev *dev);
+static int bcm43xx_wireless_core_start(struct bcm43xx_wldev *dev);
+
+
+static void bcm43xx_ram_write(struct bcm43xx_wldev *dev, u16 offset, u32 val)
+{
+ u32 status;
+
+ assert(offset % 4 == 0);
+
+ status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
+ if (status & BCM43xx_SBF_XFER_REG_BYTESWAP)
+ val = swab32(val);
+
+ bcm43xx_write32(dev, BCM43xx_MMIO_RAM_CONTROL, offset);
+ mmiowb();
+ bcm43xx_write32(dev, BCM43xx_MMIO_RAM_DATA, val);
+}
+
+static inline
+void bcm43xx_shm_control_word(struct bcm43xx_wldev *dev,
+ u16 routing, u16 offset)
+{
+ u32 control;
+
+ /* "offset" is the WORD offset. */
+
+ control = routing;
+ control <<= 16;
+ control |= offset;
+ bcm43xx_write32(dev, BCM43xx_MMIO_SHM_CONTROL, control);
+}
+
+u32 bcm43xx_shm_read32(struct bcm43xx_wldev *dev,
+ u16 routing, u16 offset)
+{
+ u32 ret;
+
+ if (routing == BCM43xx_SHM_SHARED) {
+ assert((offset & 0x0001) == 0);
+ if (offset & 0x0003) {
+ /* Unaligned access */
+ bcm43xx_shm_control_word(dev, routing, offset >> 2);
+ ret = bcm43xx_read16(dev,
+ BCM43xx_MMIO_SHM_DATA_UNALIGNED);
+ ret <<= 16;
+ bcm43xx_shm_control_word(dev, routing, (offset >> 2) + 1);
+ ret |= bcm43xx_read16(dev,
+ BCM43xx_MMIO_SHM_DATA);
+
+ return ret;
+ }
+ offset >>= 2;
+ }
+ bcm43xx_shm_control_word(dev, routing, offset);
+ ret = bcm43xx_read32(dev, BCM43xx_MMIO_SHM_DATA);
+
+ return ret;
+}
+
+u16 bcm43xx_shm_read16(struct bcm43xx_wldev *dev,
+ u16 routing, u16 offset)
+{
+ u16 ret;
+
+ if (routing == BCM43xx_SHM_SHARED) {
+ assert((offset & 0x0001) == 0);
+ if (offset & 0x0003) {
+ /* Unaligned access */
+ bcm43xx_shm_control_word(dev, routing, offset >> 2);
+ ret = bcm43xx_read16(dev,
+ BCM43xx_MMIO_SHM_DATA_UNALIGNED);
+
+ return ret;
+ }
+ offset >>= 2;
+ }
+ bcm43xx_shm_control_word(dev, routing, offset);
+ ret = bcm43xx_read16(dev, BCM43xx_MMIO_SHM_DATA);
+
+ return ret;
+}
+
+void bcm43xx_shm_write32(struct bcm43xx_wldev *dev,
+ u16 routing, u16 offset,
+ u32 value)
+{
+ if (routing == BCM43xx_SHM_SHARED) {
+ assert((offset & 0x0001) == 0);
+ if (offset & 0x0003) {
+ /* Unaligned access */
+ bcm43xx_shm_control_word(dev, routing, offset >> 2);
+ mmiowb();
+ bcm43xx_write16(dev, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
+ (value >> 16) & 0xffff);
+ mmiowb();
+ bcm43xx_shm_control_word(dev, routing, (offset >> 2) + 1);
+ mmiowb();
+ bcm43xx_write16(dev, BCM43xx_MMIO_SHM_DATA,
+ value & 0xffff);
+ return;
+ }
+ offset >>= 2;
+ }
+ bcm43xx_shm_control_word(dev, routing, offset);
+ mmiowb();
+ bcm43xx_write32(dev, BCM43xx_MMIO_SHM_DATA, value);
+}
+
+void bcm43xx_shm_write16(struct bcm43xx_wldev *dev,
+ u16 routing, u16 offset,
+ u16 value)
+{
+ if (routing == BCM43xx_SHM_SHARED) {
+ assert((offset & 0x0001) == 0);
+ if (offset & 0x0003) {
+ /* Unaligned access */
+ bcm43xx_shm_control_word(dev, routing, offset >> 2);
+ mmiowb();
+ bcm43xx_write16(dev, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
+ value);
+ return;
+ }
+ offset >>= 2;
+ }
+ bcm43xx_shm_control_word(dev, routing, offset);
+ mmiowb();
+ bcm43xx_write16(dev, BCM43xx_MMIO_SHM_DATA, value);
+}
+
+/* Read HostFlags */
+u32 bcm43xx_hf_read(struct bcm43xx_wldev *dev)
+{
+ u32 ret;
+
+ ret = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_HOSTFHI);
+ ret <<= 16;
+ ret |= bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_HOSTFLO);
+
+ return ret;
+}
+
+/* Write HostFlags */
+void bcm43xx_hf_write(struct bcm43xx_wldev *dev, u32 value)
+{
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_HOSTFLO,
+ (value & 0x0000FFFF));
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_HOSTFHI,
+ ((value & 0xFFFF0000) >> 16));
+}
+
+void bcm43xx_tsf_read(struct bcm43xx_wldev *dev, u64 *tsf)
+{
+ /* We need to be careful. As we read the TSF from multiple
+ * registers, we should take care of register overflows.
+ * In theory, the whole tsf read process should be atomic.
+ * We try to be atomic here, by restaring the read process,
+ * if any of the high registers changed (overflew).
+ */
+ if (dev->dev->id.revision >= 3) {
+ u32 low, high, high2;
+
+ do {
+ high = bcm43xx_read32(dev, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
+ low = bcm43xx_read32(dev, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
+ high2 = bcm43xx_read32(dev, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
+ } while (unlikely(high != high2));
+
+ *tsf = high;
+ *tsf <<= 32;
+ *tsf |= low;
+ } else {
+ u64 tmp;
+ u16 v0, v1, v2, v3;
+ u16 test1, test2, test3;
+
+ do {
+ v3 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_3);
+ v2 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_2);
+ v1 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_1);
+ v0 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_0);
+
+ test3 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_3);
+ test2 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_2);
+ test1 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_1);
+ } while (v3 != test3 || v2 != test2 || v1 != test1);
+
+ *tsf = v3;
+ *tsf <<= 48;
+ tmp = v2;
+ tmp <<= 32;
+ *tsf |= tmp;
+ tmp = v1;
+ tmp <<= 16;
+ *tsf |= tmp;
+ *tsf |= v0;
+ }
+}
+
+static void bcm43xx_time_lock(struct bcm43xx_wldev *dev)
+{
+ u32 status;
+
+ status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
+ status |= BCM43xx_SBF_TIME_UPDATE;
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, status);
+ mmiowb();
+}
+
+static void bcm43xx_time_unlock(struct bcm43xx_wldev *dev)
+{
+ u32 status;
+
+ status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
+ status &= ~BCM43xx_SBF_TIME_UPDATE;
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, status);
+}
+
+static void bcm43xx_tsf_write_locked(struct bcm43xx_wldev *dev, u64 tsf)
+{
+ /* Be careful with the in-progress timer.
+ * First zero out the low register, so we have a full
+ * register-overflow duration to complete the operation.
+ */
+ if (dev->dev->id.revision >= 3) {
+ u32 lo = (tsf & 0x00000000FFFFFFFFULL);
+ u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
+
+ bcm43xx_write32(dev, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
+ mmiowb();
+ bcm43xx_write32(dev, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
+ mmiowb();
+ bcm43xx_write32(dev, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
+ } else {
+ u16 v0 = (tsf & 0x000000000000FFFFULL);
+ u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
+ u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
+ u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
+
+ bcm43xx_write16(dev, BCM43xx_MMIO_TSF_0, 0);
+ mmiowb();
+ bcm43xx_write16(dev, BCM43xx_MMIO_TSF_3, v3);
+ mmiowb();
+ bcm43xx_write16(dev, BCM43xx_MMIO_TSF_2, v2);
+ mmiowb();
+ bcm43xx_write16(dev, BCM43xx_MMIO_TSF_1, v1);
+ mmiowb();
+ bcm43xx_write16(dev, BCM43xx_MMIO_TSF_0, v0);
+ }
+}
+
+void bcm43xx_tsf_write(struct bcm43xx_wldev *dev, u64 tsf)
+{
+ bcm43xx_time_lock(dev);
+ bcm43xx_tsf_write_locked(dev, tsf);
+ bcm43xx_time_unlock(dev);
+}
+
+static void bcm43xx_measure_channel_change_time(struct bcm43xx_wldev *dev)
+{
+ u64 start, stop;
+ unsigned long flags;
+ u8 oldchan, testchan;
+
+ /* We (ab)use the bcm43xx TSF timer to measure the time needed
+ * to switch channels. This information is handed over to
+ * the ieee80211 subsystem.
+ * Time is measured in microseconds.
+ */
+
+ spin_lock_irqsave(&dev->wl->irq_lock, flags);
+ oldchan = dev->phy.channel;
+ testchan = (oldchan == 6) ? 7 : 6;
+ bcm43xx_tsf_read(dev, &start);
+ bcm43xx_radio_selectchannel(dev, testchan, 0);
+ bcm43xx_tsf_read(dev, &stop);
+ bcm43xx_radio_selectchannel(dev, oldchan, 0);
+ spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+
+ assert(stop > start);
+ dev->wl->hw->channel_change_time = stop - start;
+}
+
+static
+void bcm43xx_macfilter_set(struct bcm43xx_wldev *dev,
+ u16 offset,
+ const u8 *mac)
+{
+ u16 data;
+
+ offset |= 0x0020;
+ bcm43xx_write16(dev, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
+
+ data = mac[0];
+ data |= mac[1] << 8;
+ bcm43xx_write16(dev, BCM43xx_MMIO_MACFILTER_DATA, data);
+ data = mac[2];
+ data |= mac[3] << 8;
+ bcm43xx_write16(dev, BCM43xx_MMIO_MACFILTER_DATA, data);
+ data = mac[4];
+ data |= mac[5] << 8;
+ bcm43xx_write16(dev, BCM43xx_MMIO_MACFILTER_DATA, data);
+}
+
+static void bcm43xx_macfilter_clear(struct bcm43xx_wldev *dev,
+ u16 offset)
+{
+ static const u8 zero_addr[ETH_ALEN] = { 0 };
+
+ bcm43xx_macfilter_set(dev, offset, zero_addr);
+}
+
+static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_wldev *dev)
+{
+ static const u8 zero_addr[ETH_ALEN] = { 0 };
+ const u8 *mac;
+ const u8 *bssid;
+ u8 mac_bssid[ETH_ALEN * 2];
+ int i;
+ u32 tmp;
+
+ bssid = dev->wl->bssid;
+ if (!bssid)
+ bssid = zero_addr;
+ mac = dev->wl->mac_addr;
+ if (!mac)
+ mac = zero_addr;
+
+ memcpy(mac_bssid, mac, ETH_ALEN);
+ memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
+
+ /* Write our MAC address and BSSID to template ram */
+ for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
+ tmp = (u32)(mac_bssid[i + 0]);
+ tmp |= (u32)(mac_bssid[i + 1]) << 8;
+ tmp |= (u32)(mac_bssid[i + 2]) << 16;
+ tmp |= (u32)(mac_bssid[i + 3]) << 24;
+ bcm43xx_ram_write(dev, 0x20 + i, tmp);
+ }
+}
+
+static void bcm43xx_set_slot_time(struct bcm43xx_wldev *dev, u16 slot_time)
+{
+ /* slot_time is in usec. */
+ if (dev->phy.type != BCM43xx_PHYTYPE_G)
+ return;
+ bcm43xx_write16(dev, 0x684, 510 + slot_time);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0010, slot_time);
+}
+
+static void bcm43xx_short_slot_timing_enable(struct bcm43xx_wldev *dev)
+{
+ bcm43xx_set_slot_time(dev, 9);
+ dev->short_slot = 1;
+}
+
+static void bcm43xx_short_slot_timing_disable(struct bcm43xx_wldev *dev)
+{
+ bcm43xx_set_slot_time(dev, 20);
+ dev->short_slot = 0;
+}
+
+/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
+ * Returns the _previously_ enabled IRQ mask.
+ */
+static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_wldev *dev, u32 mask)
+{
+ u32 old_mask;
+
+ old_mask = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_MASK);
+ bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
+
+ return old_mask;
+}
+
+/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
+ * Returns the _previously_ enabled IRQ mask.
+ */
+static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_wldev *dev, u32 mask)
+{
+ u32 old_mask;
+
+ old_mask = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_MASK);
+ bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
+
+ return old_mask;
+}
+
+/* Synchronize IRQ top- and bottom-half.
+ * IRQs must be masked before calling this.
+ * This must not be called with the irq_lock held.
+ */
+static void bcm43xx_synchronize_irq(struct bcm43xx_wldev *dev)
+{
+ synchronize_irq(dev->dev->irq);
+ tasklet_kill(&dev->isr_tasklet);
+}
+
+/* DummyTransmission function, as documented on
+ * http://bcm-specs.sipsolutions.net/DummyTransmission
+ */
+void bcm43xx_dummy_transmission(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ unsigned int i, max_loop;
+ u16 value;
+ u32 buffer[5] = {
+ 0x00000000,
+ 0x00D40000,
+ 0x00000000,
+ 0x01000000,
+ 0x00000000,
+ };
+
+ switch (phy->type) {
+ case BCM43xx_PHYTYPE_A:
+ max_loop = 0x1E;
+ buffer[0] = 0x000201CC;
+ break;
+ case BCM43xx_PHYTYPE_B:
+ case BCM43xx_PHYTYPE_G:
+ max_loop = 0xFA;
+ buffer[0] = 0x000B846E;
+ break;
+ default:
+ assert(0);
+ return;
+ }
+
+ for (i = 0; i < 5; i++)
+ bcm43xx_ram_write(dev, i * 4, buffer[i]);
+
+ bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
+
+ bcm43xx_write16(dev, 0x0568, 0x0000);
+ bcm43xx_write16(dev, 0x07C0, 0x0000);
+ value = ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0);
+ bcm43xx_write16(dev, 0x050C, value);
+ bcm43xx_write16(dev, 0x0508, 0x0000);
+ bcm43xx_write16(dev, 0x050A, 0x0000);
+ bcm43xx_write16(dev, 0x054C, 0x0000);
+ bcm43xx_write16(dev, 0x056A, 0x0014);
+ bcm43xx_write16(dev, 0x0568, 0x0826);
+ bcm43xx_write16(dev, 0x0500, 0x0000);
+ bcm43xx_write16(dev, 0x0502, 0x0030);
+
+ if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
+ bcm43xx_radio_write16(dev, 0x0051, 0x0017);
+ for (i = 0x00; i < max_loop; i++) {
+ value = bcm43xx_read16(dev, 0x050E);
+ if (value & 0x0080)
+ break;
+ udelay(10);
+ }
+ for (i = 0x00; i < 0x0A; i++) {
+ value = bcm43xx_read16(dev, 0x050E);
+ if (value & 0x0400)
+ break;
+ udelay(10);
+ }
+ for (i = 0x00; i < 0x0A; i++) {
+ value = bcm43xx_read16(dev, 0x0690);
+ if (!(value & 0x0100))
+ break;
+ udelay(10);
+ }
+ if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
+ bcm43xx_radio_write16(dev, 0x0051, 0x0037);
+}
+
+static void key_write(struct bcm43xx_wldev *dev,
+ u8 index, u8 algorithm, const u8 *key)
+{
+ unsigned int i;
+ u32 offset;
+ u16 value;
+ u16 kidx;
+
+ /* Key index/algo block */
+ kidx = bcm43xx_kidx_to_fw(dev, index);
+ value = ((kidx << 4) | algorithm);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_KEYIDXBLOCK +
+ (kidx * 2), value);
+
+ /* Write the key to the Key Table Pointer offset */
+ offset = dev->ktp + (index * BCM43xx_SEC_KEYSIZE);
+ for (i = 0; i < BCM43xx_SEC_KEYSIZE; i += 2) {
+ value = key[i];
+ value |= (u16)(key[i + 1]) << 8;
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+ offset + i, value);
+ }
+}
+
+static void keymac_write(struct bcm43xx_wldev *dev,
+ u8 index, const u8 *addr)
+{
+ u32 addrtmp[2];
+
+ assert(index >= 4 + 4);
+ memcpy(dev->key[index].address, addr, 6);
+ /* We have two default TX keys and two default RX keys.
+ * Physical mac 0 is mapped to physical key 8.
+ * So we must adjust the index here.
+ */
+ index -= 8;
+
+ addrtmp[0] = addr[0];
+ addrtmp[0] |= ((u32)(addr[1]) << 8);
+ addrtmp[0] |= ((u32)(addr[2]) << 16);
+ addrtmp[0] |= ((u32)(addr[3]) << 24);
+ addrtmp[1] = addr[4];
+ addrtmp[1] |= ((u32)(addr[5]) << 8);
+
+ if (dev->dev->id.revision >= 5) {
+ /* Receive match transmitter address mechanism */
+ bcm43xx_shm_write32(dev, BCM43xx_SHM_RCMTA,
+ (index * 2) + 0, addrtmp[0]);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_RCMTA,
+ (index * 2) + 1, addrtmp[1]);
+ } else {
+ /* RXE (Receive Engine) and
+ * PSM (Programmable State Machine) mechanism
+ */
+ if (index < 8) {
+ /* TODO write to RCM 16, 19, 22 and 25 */
+ TODO();
+ } else {
+ bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_PSM + (index * 6) + 0,
+ addrtmp[0]);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_PSM + (index * 6) + 4,
+ addrtmp[1]);
+ }
+ }
+}
+
+static void do_key_write(struct bcm43xx_wldev *dev,
+ u8 index, u8 algorithm,
+ const u8 *key, size_t key_len,
+ const u8 *mac_addr)
+{
+ u8 buf[BCM43xx_SEC_KEYSIZE];
+
+ assert(index < dev->max_nr_keys);
+ assert(key_len <= BCM43xx_SEC_KEYSIZE);
+
+ memset(buf, 0, sizeof(buf));
+ if (index >= 8)
+ keymac_write(dev, index, buf); /* First zero out mac. */
+ memcpy(buf, key, key_len);
+ key_write(dev, index, algorithm, buf);
+ if (index >= 8)
+ keymac_write(dev, index, mac_addr);
+
+ dev->key[index].algorithm = algorithm;
+}
+
+static int bcm43xx_key_write(struct bcm43xx_wldev *dev,
+ int index, u8 algorithm,
+ const u8 *key, size_t key_len,
+ const u8 *mac_addr,
+ struct ieee80211_key_conf *keyconf)
+{
+ int i;
+ int sta_keys_start;
+
+ if (key_len > BCM43xx_SEC_KEYSIZE)
+ return -EINVAL;
+ if (index < 0) {
+ /* Per station key with associated MAC address.
+ * Look if it already exists, if yes update, otherwise
+ * allocate a new key.
+ */
+ if (bcm43xx_new_kidx_api(dev))
+ sta_keys_start = 4;
+ else
+ sta_keys_start = 8;
+ for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
+ if (compare_ether_addr(dev->key[i].address, mac_addr) == 0) {
+ /* found existing */
+ index = i;
+ break;
+ }
+ }
+ if (index < 0) {
+ for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
+ if (!dev->key[i].enabled) {
+ /* found empty */
+ index = i;
+ break;
+ }
+ }
+ }
+ if (index < 0) {
+ dprintk(KERN_ERR PFX "Out of hw key memory\n");
+ return -ENOBUFS;
+ }
+ } else
+ assert(index <= 3);
+
+ do_key_write(dev, index, algorithm, key, key_len, mac_addr);
+ if ((index <= 3) && !bcm43xx_new_kidx_api(dev)) {
+ /* Default RX key */
+ assert(mac_addr == NULL);
+ do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
+ }
+ keyconf->hw_key_idx = index;
+
+ return 0;
+}
+
+static void bcm43xx_clear_keys(struct bcm43xx_wldev *dev)
+{
+ static const u8 zero[BCM43xx_SEC_KEYSIZE] = { 0 };
+ unsigned int i;
+
+ BUILD_BUG_ON(BCM43xx_SEC_KEYSIZE < ETH_ALEN);
+ for (i = 0; i < dev->max_nr_keys; i++) {
+ do_key_write(dev, i, BCM43xx_SEC_ALGO_NONE,
+ zero, BCM43xx_SEC_KEYSIZE,
+ zero);
+ dev->key[i].enabled = 0;
+ }
+}
+
+/* Turn the Analog ON/OFF */
+static void bcm43xx_switch_analog(struct bcm43xx_wldev *dev, int on)
+{
+ bcm43xx_write16(dev, BCM43xx_MMIO_PHY0, on ? 0 : 0xF4);
+}
+
+void bcm43xx_wireless_core_reset(struct bcm43xx_wldev *dev, u32 flags)
+{
+ u32 tmslow;
+ u32 macctl;
+
+ flags |= BCM43xx_TMSLOW_PHYCLKEN;
+ flags |= BCM43xx_TMSLOW_PHYRESET;
+ ssb_device_enable(dev->dev, flags);
+ msleep(2); /* Wait for the PLL to turn on. */
+
+ /* Now take the PHY out of Reset again */
+ tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
+ tmslow |= SSB_TMSLOW_FGC;
+ tmslow &= ~BCM43xx_TMSLOW_PHYRESET;
+ ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
+ ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
+ msleep(1);
+ tmslow &= ~SSB_TMSLOW_FGC;
+ ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
+ ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
+ msleep(1);
+
+ /* Turn Analog ON */
+ bcm43xx_switch_analog(dev, 1);
+
+ macctl = bcm43xx_read32(dev, BCM43xx_MMIO_MACCTL);
+ macctl &= ~BCM43xx_MACCTL_GMODE;
+ if (flags & BCM43xx_TMSLOW_GMODE)
+ macctl |= BCM43xx_MACCTL_GMODE;
+ macctl |= BCM43xx_MACCTL_IHR_ENABLED;
+ bcm43xx_write32(dev, BCM43xx_MMIO_MACCTL, macctl);
+}
+
+static void handle_irq_transmit_status(struct bcm43xx_wldev *dev)
+{
+ u32 v0, v1;
+ u16 tmp;
+ struct bcm43xx_txstatus stat;
+
+ while (1) {
+ v0 = bcm43xx_read32(dev, BCM43xx_MMIO_XMITSTAT_0);
+ if (!(v0 & 0x00000001))
+ break;
+ v1 = bcm43xx_read32(dev, BCM43xx_MMIO_XMITSTAT_1);
+
+ stat.cookie = (v0 >> 16);
+ stat.seq = (v1 & 0x0000FFFF);
+ stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
+ tmp = (v0 & 0x0000FFFF);
+ stat.frame_count = ((tmp & 0xF000) >> 12);
+ stat.rts_count = ((tmp & 0x0F00) >> 8);
+ stat.supp_reason = ((tmp & 0x001C) >> 2);
+ stat.pm_indicated = !!(tmp & 0x0080);
+ stat.intermediate = !!(tmp & 0x0040);
+ stat.for_ampdu = !!(tmp & 0x0020);
+ stat.acked = !!(tmp & 0x0002);
+
+ bcm43xx_handle_txstatus(dev, &stat);
+ }
+}
+
+static void drain_txstatus_queue(struct bcm43xx_wldev *dev)
+{
+ u32 dummy;
+
+ if (dev->dev->id.revision < 5)
+ return;
+ /* Read all entries from the microcode TXstatus FIFO
+ * and throw them away.
+ */
+ while (1) {
+ dummy = bcm43xx_read32(dev, BCM43xx_MMIO_XMITSTAT_0);
+ if (!(dummy & 0x00000001))
+ break;
+ dummy = bcm43xx_read32(dev, BCM43xx_MMIO_XMITSTAT_1);
+ }
+}
+
+static u32 bcm43xx_jssi_read(struct bcm43xx_wldev *dev)
+{
+ u32 val = 0;
+
+ val = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x08A);
+ val <<= 16;
+ val |= bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x088);
+
+ return val;
+}
+
+static void bcm43xx_jssi_write(struct bcm43xx_wldev *dev, u32 jssi)
+{
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x088,
+ (jssi & 0x0000FFFF));
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x08A,
+ (jssi & 0xFFFF0000) >> 16);
+}
+
+static void bcm43xx_generate_noise_sample(struct bcm43xx_wldev *dev)
+{
+ bcm43xx_jssi_write(dev, 0x7F7F7F7F);
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD,
+ bcm43xx_read32(dev, BCM43xx_MMIO_STATUS2_BITFIELD)
+ | (1 << 4));
+ assert(dev->noisecalc.channel_at_start == dev->phy.channel);
+}
+
+static void bcm43xx_calculate_link_quality(struct bcm43xx_wldev *dev)
+{
+ /* Top half of Link Quality calculation. */
+
+ if (dev->noisecalc.calculation_running)
+ return;
+ dev->noisecalc.channel_at_start = dev->phy.channel;
+ dev->noisecalc.calculation_running = 1;
+ dev->noisecalc.nr_samples = 0;
+
+ bcm43xx_generate_noise_sample(dev);
+}
+
+static void handle_irq_noise(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 tmp;
+ u8 noise[4];
+ u8 i, j;
+ s32 average;
+
+ /* Bottom half of Link Quality calculation. */
+
+ assert(dev->noisecalc.calculation_running);
+ if (dev->noisecalc.channel_at_start != phy->channel)
+ goto drop_calculation;
+ *((u32 *)noise) = cpu_to_le32(bcm43xx_jssi_read(dev));
+ if (noise[0] == 0x7F || noise[1] == 0x7F ||
+ noise[2] == 0x7F || noise[3] == 0x7F)
+ goto generate_new;
+
+ /* Get the noise samples. */
+ assert(dev->noisecalc.nr_samples < 8);
+ i = dev->noisecalc.nr_samples;
+ noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
+ noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
+ noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
+ noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
+ dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
+ dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
+ dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
+ dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
+ dev->noisecalc.nr_samples++;
+ if (dev->noisecalc.nr_samples == 8) {
+ /* Calculate the Link Quality by the noise samples. */
+ average = 0;
+ for (i = 0; i < 8; i++) {
+ for (j = 0; j < 4; j++)
+ average += dev->noisecalc.samples[i][j];
+ }
+ average /= (8 * 4);
+ average *= 125;
+ average += 64;
+ average /= 128;
+ tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x40C);
+ tmp = (tmp / 128) & 0x1F;
+ if (tmp >= 8)
+ average += 2;
+ else
+ average -= 25;
+ if (tmp == 8)
+ average -= 72;
+ else
+ average -= 48;
+
+ dev->stats.link_noise = average;
+drop_calculation:
+ dev->noisecalc.calculation_running = 0;
+ return;
+ }
+generate_new:
+ bcm43xx_generate_noise_sample(dev);
+}
+
+static void handle_irq_tbtt_indication(struct bcm43xx_wldev *dev)
+{
+ if (bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
+ ///TODO: PS TBTT
+ } else {
+ if (1/*FIXME: the last PSpoll frame was sent successfully */)
+ bcm43xx_power_saving_ctl_bits(dev, -1, -1);
+ }
+ dev->reg124_set_0x4 = 0;
+ if (bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
+ dev->reg124_set_0x4 = 1;
+}
+
+static void handle_irq_atim_end(struct bcm43xx_wldev *dev)
+{
+ if (!dev->reg124_set_0x4 /*FIXME rename this variable*/)
+ return;
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD,
+ bcm43xx_read32(dev, BCM43xx_MMIO_STATUS2_BITFIELD)
+ | 0x4);
+}
+
+static void handle_irq_pmq(struct bcm43xx_wldev *dev)
+{
+ u32 tmp;
+
+ //TODO: AP mode.
+
+ while (1) {
+ tmp = bcm43xx_read32(dev, BCM43xx_MMIO_PS_STATUS);
+ if (!(tmp & 0x00000008))
+ break;
+ }
+ /* 16bit write is odd, but correct. */
+ bcm43xx_write16(dev, BCM43xx_MMIO_PS_STATUS, 0x0002);
+}
+
+static void bcm43xx_write_template_common(struct bcm43xx_wldev *dev,
+ const u8* data, u16 size,
+ u16 ram_offset,
+ u16 shm_size_offset, u8 rate)
+{
+ u32 i, tmp;
+ struct bcm43xx_plcp_hdr4 plcp;
+
+ plcp.data = 0;
+ bcm43xx_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
+ bcm43xx_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
+ ram_offset += sizeof(u32);
+ /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
+ * So leave the first two bytes of the next write blank.
+ */
+ tmp = (u32)(data[0]) << 16;
+ tmp |= (u32)(data[1]) << 24;
+ bcm43xx_ram_write(dev, ram_offset, tmp);
+ ram_offset += sizeof(u32);
+ for (i = 2; i < size; i += sizeof(u32)) {
+ tmp = (u32)(data[i + 0]);
+ if (i + 1 < size)
+ tmp |= (u32)(data[i + 1]) << 8;
+ if (i + 2 < size)
+ tmp |= (u32)(data[i + 2]) << 16;
+ if (i + 3 < size)
+ tmp |= (u32)(data[i + 3]) << 24;
+ bcm43xx_ram_write(dev, ram_offset + i - 2, tmp);
+ }
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, shm_size_offset,
+ size + sizeof(struct bcm43xx_plcp_hdr6));
+}
+
+static void bcm43xx_write_beacon_template(struct bcm43xx_wldev *dev,
+ u16 ram_offset,
+ u16 shm_size_offset, u8 rate)
+{
+ int len;
+ const u8 *data;
+
+ assert(dev->cached_beacon);
+ len = min((size_t)dev->cached_beacon->len,
+ 0x200 - sizeof(struct bcm43xx_plcp_hdr6));
+ data = (const u8 *)(dev->cached_beacon->data);
+ bcm43xx_write_template_common(dev, data,
+ len, ram_offset,
+ shm_size_offset, rate);
+}
+
+static void bcm43xx_write_probe_resp_plcp(struct bcm43xx_wldev *dev,
+ u16 shm_offset, u16 size, u8 rate)
+{
+ struct bcm43xx_plcp_hdr4 plcp;
+ u32 tmp;
+ u16 packet_time;
+
+ plcp.data = 0;
+ bcm43xx_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
+ /*
+ * 144 + 48 + 10 = preamble + PLCP + SIFS,
+ * taken from mac80211 timings calculation.
+ *
+ * FIXME: long preamble assumed!
+ *
+ */
+ packet_time = 202 + (size + FCS_LEN) * 16 / rate;
+ if ((size + FCS_LEN) * 16 % rate >= rate / 2)
+ ++packet_time;
+
+ /* Write PLCP in two parts and timing for packet transfer */
+ tmp = le32_to_cpu(plcp.data);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, shm_offset,
+ tmp & 0xFFFF);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, shm_offset + 2,
+ tmp >> 16);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, shm_offset + 6,
+ packet_time);
+}
+
+/* Instead of using custom probe response template, this function
+ * just patches custom beacon template by:
+ * 1) Changing packet type
+ * 2) Patching duration field
+ * 3) Stripping TIM
+ */
+static u8 * bcm43xx_generate_probe_resp(struct bcm43xx_wldev *dev,
+ u16* dest_size, u8 rate)
+{
+ const u8 *src_data;
+ u8 *dest_data;
+ u16 src_size, elem_size, src_pos, dest_pos, tmp;
+
+ assert(dev->cached_beacon);
+ src_size = dev->cached_beacon->len;
+ src_data = (const u8*)dev->cached_beacon->data;
+
+ if (unlikely(src_size < 0x24)) {
+ dprintk(KERN_ERR PFX "bcm43xx_generate_probe_resp: "
+ "invalid beacon\n");
+ return NULL;
+ }
+
+ dest_data = kmalloc(src_size, GFP_ATOMIC);
+ if (unlikely(!dest_data))
+ return NULL;
+
+ /* 0x24 is offset of first variable-len Information-Element
+ * in beacon frame.
+ */
+ memcpy(dest_data, src_data, 0x24);
+ src_pos = dest_pos = 0x24;
+ for ( ; src_pos < src_size - 2; src_pos += elem_size) {
+ elem_size = src_data[src_pos + 1] + 2;
+ if (src_data[src_pos] != 0x05) { /* TIM */
+ memcpy(dest_data + dest_pos, src_data + src_pos,
+ elem_size);
+ dest_pos += elem_size;
+ }
+ }
+ *dest_size = dest_pos;
+
+ /* Set the frame control. */
+ dest_data[0] = (IEEE80211_FTYPE_MGMT |
+ IEEE80211_STYPE_PROBE_RESP);
+ dest_data[1] = 0;
+
+ /* Set the duration field.
+ *
+ * 144 + 48 + 10 = preamble + PLCP + SIFS,
+ * taken from mac80211 timings calculation.
+ *
+ * FIXME: long preamble assumed!
+ *
+ */
+ tmp = 202 + (14 + FCS_LEN) * 16 / rate;
+ if ((14 + FCS_LEN) * 16 % rate >= rate / 2)
+ ++tmp;
+
+ dest_data[2] = tmp & 0xFF;
+ dest_data[3] = (tmp >> 8) & 0xFF;
+
+ return dest_data;
+}
+
+static void bcm43xx_write_probe_resp_template(struct bcm43xx_wldev *dev,
+ u16 ram_offset,
+ u16 shm_size_offset, u8 rate)
+{
+ u8* probe_resp_data;
+ u16 size;
+
+ assert(dev->cached_beacon);
+ size = dev->cached_beacon->len;
+ probe_resp_data = bcm43xx_generate_probe_resp(dev, &size, rate);
+ if (unlikely(!probe_resp_data))
+ return;
+
+ /* Looks like PLCP headers plus packet timings are stored for
+ * all possible basic rates
+ */
+ bcm43xx_write_probe_resp_plcp(dev, 0x31A, size,
+ BCM43xx_CCK_RATE_1MB);
+ bcm43xx_write_probe_resp_plcp(dev, 0x32C, size,
+ BCM43xx_CCK_RATE_2MB);
+ bcm43xx_write_probe_resp_plcp(dev, 0x33E, size,
+ BCM43xx_CCK_RATE_5MB);
+ bcm43xx_write_probe_resp_plcp(dev, 0x350, size,
+ BCM43xx_CCK_RATE_11MB);
+
+ size = min((size_t)size,
+ 0x200 - sizeof(struct bcm43xx_plcp_hdr6));
+ bcm43xx_write_template_common(dev, probe_resp_data,
+ size, ram_offset,
+ shm_size_offset, rate);
+ kfree(probe_resp_data);
+}
+
+static int bcm43xx_refresh_cached_beacon(struct bcm43xx_wldev *dev,
+ struct sk_buff *beacon)
+{
+ if (dev->cached_beacon)
+ kfree_skb(dev->cached_beacon);
+ dev->cached_beacon = beacon;
+
+ return 0;
+}
+
+static void bcm43xx_update_templates(struct bcm43xx_wldev *dev)
+{
+ u32 status;
+
+ assert(dev->cached_beacon);
+
+ bcm43xx_write_beacon_template(dev, 0x68, 0x18,
+ BCM43xx_CCK_RATE_1MB);
+ bcm43xx_write_beacon_template(dev, 0x468, 0x1A,
+ BCM43xx_CCK_RATE_1MB);
+ bcm43xx_write_probe_resp_template(dev, 0x268, 0x4A,
+ BCM43xx_CCK_RATE_11MB);
+
+ status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS2_BITFIELD);
+ status |= 0x03;
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD, status);
+}
+
+static void bcm43xx_refresh_templates(struct bcm43xx_wldev *dev,
+ struct sk_buff *beacon)
+{
+ int err;
+
+ err = bcm43xx_refresh_cached_beacon(dev, beacon);
+ if (unlikely(err))
+ return;
+ bcm43xx_update_templates(dev);
+}
+
+static void bcm43xx_set_ssid(struct bcm43xx_wldev *dev,
+ const u8 *ssid, u8 ssid_len)
+{
+ u32 tmp;
+ u16 i, len;
+
+ len = min((u16)ssid_len, (u16)0x100);
+ for (i = 0; i < len; i += sizeof(u32)) {
+ tmp = (u32)(ssid[i + 0]);
+ if (i + 1 < len)
+ tmp |= (u32)(ssid[i + 1]) << 8;
+ if (i + 2 < len)
+ tmp |= (u32)(ssid[i + 2]) << 16;
+ if (i + 3 < len)
+ tmp |= (u32)(ssid[i + 3]) << 24;
+ bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED,
+ 0x380 + i, tmp);
+ }
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+ 0x48, len);
+}
+
+static void bcm43xx_set_beacon_int(struct bcm43xx_wldev *dev, u16 beacon_int)
+{
+ bcm43xx_time_lock(dev);
+ if (dev->dev->id.revision >= 3) {
+ bcm43xx_write32(dev, 0x188, (beacon_int << 16));
+ } else {
+ bcm43xx_write16(dev, 0x606, (beacon_int >> 6));
+ bcm43xx_write16(dev, 0x610, beacon_int);
+ }
+ bcm43xx_time_unlock(dev);
+}
+
+static void handle_irq_beacon(struct bcm43xx_wldev *dev)
+{
+ u32 status;
+
+ if (!bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
+ return;
+
+ dev->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
+ status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS2_BITFIELD);
+
+ if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
+ /* ACK beacon IRQ. */
+ bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON,
+ BCM43xx_IRQ_BEACON);
+ dev->irq_savedstate |= BCM43xx_IRQ_BEACON;
+ if (dev->cached_beacon)
+ kfree_skb(dev->cached_beacon);
+ dev->cached_beacon = NULL;
+ return;
+ }
+ if (!(status & 0x1)) {
+ bcm43xx_write_beacon_template(dev, 0x68, 0x18,
+ BCM43xx_CCK_RATE_1MB);
+ status |= 0x1;
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD,
+ status);
+ }
+ if (!(status & 0x2)) {
+ bcm43xx_write_beacon_template(dev, 0x468, 0x1A,
+ BCM43xx_CCK_RATE_1MB);
+ status |= 0x2;
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD,
+ status);
+ }
+}
+
+static void handle_irq_ucode_debug(struct bcm43xx_wldev *dev)
+{
+ //TODO
+}
+
+/* Interrupt handler bottom-half */
+static void bcm43xx_interrupt_tasklet(struct bcm43xx_wldev *dev)
+{
+ u32 reason;
+ u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
+ u32 merged_dma_reason = 0;
+ int i, activity = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev->wl->irq_lock, flags);
+
+ assert(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED);
+ assert(dev->started);
+
+ reason = dev->irq_reason;
+ for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
+ dma_reason[i] = dev->dma_reason[i];
+ merged_dma_reason |= dma_reason[i];
+ }
+
+ if (unlikely(reason & BCM43xx_IRQ_MAC_TXERR))
+ printkl(KERN_ERR PFX "MAC transmission error\n");
+
+ if (unlikely(reason & BCM43xx_IRQ_PHY_TXERR))
+ printkl(KERN_ERR PFX "PHY transmission error\n");
+
+ if (unlikely(merged_dma_reason & (BCM43xx_DMAIRQ_FATALMASK |
+ BCM43xx_DMAIRQ_NONFATALMASK))) {
+ if (merged_dma_reason & BCM43xx_DMAIRQ_FATALMASK) {
+ printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
+ "0x%08X, 0x%08X, 0x%08X, "
+ "0x%08X, 0x%08X, 0x%08X\n",
+ dma_reason[0], dma_reason[1],
+ dma_reason[2], dma_reason[3],
+ dma_reason[4], dma_reason[5]);
+ bcm43xx_controller_restart(dev, "DMA error");
+ mmiowb();
+ spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+ return;
+ }
+ if (merged_dma_reason & BCM43xx_DMAIRQ_NONFATALMASK) {
+ printkl(KERN_ERR PFX "DMA error: "
+ "0x%08X, 0x%08X, 0x%08X, "
+ "0x%08X, 0x%08X, 0x%08X\n",
+ dma_reason[0], dma_reason[1],
+ dma_reason[2], dma_reason[3],
+ dma_reason[4], dma_reason[5]);
+ }
+ }
+
+ if (unlikely(reason & BCM43xx_IRQ_UCODE_DEBUG))
+ handle_irq_ucode_debug(dev);
+ if (reason & BCM43xx_IRQ_TBTT_INDI)
+ handle_irq_tbtt_indication(dev);
+ if (reason & BCM43xx_IRQ_ATIM_END)
+ handle_irq_atim_end(dev);
+ if (reason & BCM43xx_IRQ_BEACON)
+ handle_irq_beacon(dev);
+ if (reason & BCM43xx_IRQ_PMQ)
+ handle_irq_pmq(dev);
+ if (reason & BCM43xx_IRQ_TXFIFO_FLUSH_OK)
+ ;/*TODO*/
+ if (reason & BCM43xx_IRQ_NOISESAMPLE_OK)
+ handle_irq_noise(dev);
+
+ /* Check the DMA reason registers for received data. */
+ if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
+ if (bcm43xx_using_pio(dev))
+ bcm43xx_pio_rx(dev->pio.queue0);
+ else
+ bcm43xx_dma_rx(dev->dma.rx_ring0);
+ /* We intentionally don't set "activity" to 1, here. */
+ }
+ assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
+ assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
+ if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
+ if (bcm43xx_using_pio(dev))
+ bcm43xx_pio_rx(dev->pio.queue3);
+ else
+ bcm43xx_dma_rx(dev->dma.rx_ring3);
+ activity = 1;
+ }
+ assert(!(dma_reason[4] & BCM43xx_DMAIRQ_RX_DONE));
+ assert(!(dma_reason[5] & BCM43xx_DMAIRQ_RX_DONE));
+
+ if (reason & BCM43xx_IRQ_TX_OK) {
+ handle_irq_transmit_status(dev);
+ activity = 1;
+ //TODO: In AP mode, this also causes sending of powersave responses.
+ }
+
+ if (!modparam_noleds)
+ bcm43xx_leds_update(dev, activity);
+ bcm43xx_interrupt_enable(dev, dev->irq_savedstate);
+ mmiowb();
+ spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+}
+
+static void pio_irq_workaround(struct bcm43xx_wldev *dev,
+ u16 base, int queueidx)
+{
+ u16 rxctl;
+
+ rxctl = bcm43xx_read16(dev, base + BCM43xx_PIO_RXCTL);
+ if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
+ dev->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
+ else
+ dev->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
+}
+
+static void bcm43xx_interrupt_ack(struct bcm43xx_wldev *dev, u32 reason)
+{
+ if (bcm43xx_using_pio(dev) &&
+ (dev->dev->id.revision < 3) &&
+ (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
+ /* Apply a PIO specific workaround to the dma_reasons */
+ pio_irq_workaround(dev, BCM43xx_MMIO_PIO1_BASE, 0);
+ pio_irq_workaround(dev, BCM43xx_MMIO_PIO2_BASE, 1);
+ pio_irq_workaround(dev, BCM43xx_MMIO_PIO3_BASE, 2);
+ pio_irq_workaround(dev, BCM43xx_MMIO_PIO4_BASE, 3);
+ }
+
+ bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
+
+ bcm43xx_write32(dev, BCM43xx_MMIO_DMA0_REASON,
+ dev->dma_reason[0]);
+ bcm43xx_write32(dev, BCM43xx_MMIO_DMA1_REASON,
+ dev->dma_reason[1]);
+ bcm43xx_write32(dev, BCM43xx_MMIO_DMA2_REASON,
+ dev->dma_reason[2]);
+ bcm43xx_write32(dev, BCM43xx_MMIO_DMA3_REASON,
+ dev->dma_reason[3]);
+ bcm43xx_write32(dev, BCM43xx_MMIO_DMA4_REASON,
+ dev->dma_reason[4]);
+ bcm43xx_write32(dev, BCM43xx_MMIO_DMA5_REASON,
+ dev->dma_reason[5]);
+}
+
+/* Interrupt handler top-half */
+static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id)
+{
+ irqreturn_t ret = IRQ_HANDLED;
+ struct bcm43xx_wldev *dev = dev_id;
+ u32 reason;
+
+ if (!dev)
+ return IRQ_NONE;
+
+ spin_lock(&dev->wl->irq_lock);
+
+ reason = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON);
+ if (reason == 0xffffffff) {
+ /* irq not for us (shared irq) */
+ ret = IRQ_NONE;
+ goto out;
+ }
+ reason &= bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_MASK);
+ if (!reason)
+ goto out;
+
+ assert(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED);
+ assert(dev->started);
+
+ dev->dma_reason[0] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA0_REASON)
+ & 0x0001DC00;
+ dev->dma_reason[1] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA1_REASON)
+ & 0x0000DC00;
+ dev->dma_reason[2] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA2_REASON)
+ & 0x0000DC00;
+ dev->dma_reason[3] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA3_REASON)
+ & 0x0001DC00;
+ dev->dma_reason[4] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA4_REASON)
+ & 0x0000DC00;
+ dev->dma_reason[5] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA5_REASON)
+ & 0x0000DC00;
+
+ bcm43xx_interrupt_ack(dev, reason);
+ /* disable all IRQs. They are enabled again in the bottom half. */
+ dev->irq_savedstate = bcm43xx_interrupt_disable(dev, BCM43xx_IRQ_ALL);
+ /* save the reason code and call our bottom half. */
+ dev->irq_reason = reason;
+ tasklet_schedule(&dev->isr_tasklet);
+out:
+ mmiowb();
+ spin_unlock(&dev->wl->irq_lock);
+
+ return ret;
+}
+
+static void bcm43xx_release_firmware(struct bcm43xx_wldev *dev)
+{
+ release_firmware(dev->fw.ucode);
+ dev->fw.ucode = NULL;
+ release_firmware(dev->fw.pcm);
+ dev->fw.pcm = NULL;
+ release_firmware(dev->fw.initvals0);
+ dev->fw.initvals0 = NULL;
+ release_firmware(dev->fw.initvals1);
+ dev->fw.initvals1 = NULL;
+}
+
+static int bcm43xx_request_firmware(struct bcm43xx_wldev *dev)
+{
+ u8 rev = dev->dev->id.revision;
+ int err = 0;
+ int nr;
+ char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
+
+ if (!dev->fw.ucode) {
+ snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
+ (rev >= 5 ? 5 : rev),
+ modparam_fwpostfix);
+ err = request_firmware(&dev->fw.ucode, buf, dev->dev->dev);
+ if (err) {
+ printk(KERN_ERR PFX
+ "Error: Microcode \"%s\" not available or load failed.\n",
+ buf);
+ goto error;
+ }
+ }
+
+ if (!dev->fw.pcm) {
+ snprintf(buf, ARRAY_SIZE(buf),
+ "bcm43xx_pcm%d%s.fw",
+ (rev < 5 ? 4 : 5),
+ modparam_fwpostfix);
+ err = request_firmware(&dev->fw.pcm, buf, dev->dev->dev);
+ if (err) {
+ printk(KERN_ERR PFX
+ "Error: PCM \"%s\" not available or load failed.\n",
+ buf);
+ goto error;
+ }
+ }
+
+ if (!dev->fw.initvals0) {
+ if (rev == 2 || rev == 4) {
+ switch (dev->phy.type) {
+ case BCM43xx_PHYTYPE_A:
+ nr = 3;
+ break;
+ case BCM43xx_PHYTYPE_B:
+ case BCM43xx_PHYTYPE_G:
+ nr = 1;
+ break;
+ default:
+ goto err_noinitval;
+ }
+
+ } else if (rev >= 5) {
+ switch (dev->phy.type) {
+ case BCM43xx_PHYTYPE_A:
+ nr = 7;
+ break;
+ case BCM43xx_PHYTYPE_B:
+ case BCM43xx_PHYTYPE_G:
+ nr = 5;
+ break;
+ default:
+ goto err_noinitval;
+ }
+ } else
+ goto err_noinitval;
+ snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
+ nr, modparam_fwpostfix);
+
+ err = request_firmware(&dev->fw.initvals0, buf, dev->dev->dev);
+ if (err) {
+ printk(KERN_ERR PFX
+ "Error: InitVals \"%s\" not available or load failed.\n",
+ buf);
+ goto error;
+ }
+ if (dev->fw.initvals0->size % sizeof(struct bcm43xx_initval)) {
+ printk(KERN_ERR PFX "InitVals fileformat error.\n");
+ goto error;
+ }
+ }
+
+ if (!dev->fw.initvals1) {
+ if (rev >= 5) {
+ u32 sbtmstatehigh;
+
+ switch (dev->phy.type) {
+ case BCM43xx_PHYTYPE_A:
+ sbtmstatehigh = ssb_read32(dev->dev, SSB_TMSHIGH);
+ if (sbtmstatehigh & 0x00010000)
+ nr = 9;
+ else
+ nr = 10;
+ break;
+ case BCM43xx_PHYTYPE_B:
+ case BCM43xx_PHYTYPE_G:
+ nr = 6;
+ break;
+ default:
+ goto err_noinitval;
+ }
+ snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
+ nr, modparam_fwpostfix);
+
+ err = request_firmware(&dev->fw.initvals1, buf, dev->dev->dev);
+ if (err) {
+ printk(KERN_ERR PFX
+ "Error: InitVals \"%s\" not available or load failed.\n",
+ buf);
+ goto error;
+ }
+ if (dev->fw.initvals1->size % sizeof(struct bcm43xx_initval)) {
+ printk(KERN_ERR PFX "InitVals fileformat error.\n");
+ goto error;
+ }
+ }
+ }
+
+out:
+ return err;
+error:
+ bcm43xx_release_firmware(dev);
+ goto out;
+err_noinitval:
+ printk(KERN_ERR PFX "Error: No InitVals available!\n");
+ err = -ENOENT;
+ goto error;
+}
+
+static int bcm43xx_upload_microcode(struct bcm43xx_wldev *dev)
+{
+ const __be32 *data;
+ unsigned int i, len;
+ u16 fwrev, fwpatch, fwdate, fwtime;
+ u32 tmp;
+ int err = 0;
+
+ /* Upload Microcode. */
+ data = (__be32 *)(dev->fw.ucode->data);
+ len = dev->fw.ucode->size / sizeof(__be32);
+ bcm43xx_shm_control_word(dev,
+ BCM43xx_SHM_UCODE | BCM43xx_SHM_AUTOINC_W,
+ 0x0000);
+ for (i = 0; i < len; i++) {
+ bcm43xx_write32(dev, BCM43xx_MMIO_SHM_DATA,
+ be32_to_cpu(data[i]));
+ udelay(10);
+ }
+
+ /* Upload PCM data. */
+ data = (__be32 *)(dev->fw.pcm->data);
+ len = dev->fw.pcm->size / sizeof(__be32);
+ bcm43xx_shm_control_word(dev, BCM43xx_SHM_HW, 0x01EA);
+ bcm43xx_write32(dev, BCM43xx_MMIO_SHM_DATA, 0x00004000);
+ /* No need for autoinc bit in SHM_HW */
+ bcm43xx_shm_control_word(dev, BCM43xx_SHM_HW, 0x01EB);
+ for (i = 0; i < len; i++) {
+ bcm43xx_write32(dev, BCM43xx_MMIO_SHM_DATA,
+ be32_to_cpu(data[i]));
+ udelay(10);
+ }
+
+ bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_ALL);
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
+
+ /* Wait for the microcode to load and respond */
+ i = 0;
+ while (1) {
+ tmp = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON);
+ if (tmp == BCM43xx_IRQ_MAC_SUSPENDED)
+ break;
+ i++;
+ if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
+ printk(KERN_ERR PFX "Microcode not responding\n");
+ err = -ENODEV;
+ goto out;
+ }
+ udelay(10);
+ }
+ bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
+
+ /* Get and check the revisions. */
+ fwrev = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_UCODEREV);
+ fwpatch = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_UCODEPATCH);
+ fwdate = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_UCODEDATE);
+ fwtime = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_UCODETIME);
+
+ if (fwrev <= 0x128) {
+ printk(KERN_ERR PFX "YOUR FIRMWARE IS TOO OLD. Firmware from "
+ "binary drivers older than version 4.x is unsupported. "
+ "You must upgrade your firmware files.\n");
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, 0);
+ err = -EOPNOTSUPP;
+ goto out;
+ }
+ printk(KERN_DEBUG PFX "Loading firmware version %u.%u "
+ "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
+ fwrev, fwpatch,
+ (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
+ (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
+
+ dev->fw.rev = fwrev;
+ dev->fw.patch = fwpatch;
+
+out:
+ return err;
+}
+
+static int bcm43xx_write_initvals(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_initval *data,
+ const unsigned int len)
+{
+ u16 offset, size;
+ u32 value;
+ unsigned int i;
+
+ for (i = 0; i < len; i++) {
+ offset = be16_to_cpu(data[i].offset);
+ size = be16_to_cpu(data[i].size);
+ value = be32_to_cpu(data[i].value);
+
+ if (unlikely(offset >= 0x1000))
+ goto err_format;
+ if (size == 2) {
+ if (unlikely(value & 0xFFFF0000))
+ goto err_format;
+ bcm43xx_write16(dev, offset, (u16)value);
+ } else if (size == 4) {
+ bcm43xx_write32(dev, offset, value);
+ } else
+ goto err_format;
+ }
+
+ return 0;
+
+err_format:
+ printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
+ "Please fix your bcm43xx firmware files.\n");
+ return -EPROTO;
+}
+
+static int bcm43xx_upload_initvals(struct bcm43xx_wldev *dev)
+{
+ int err;
+
+ err = bcm43xx_write_initvals(dev, (struct bcm43xx_initval *)dev->fw.initvals0->data,
+ dev->fw.initvals0->size / sizeof(struct bcm43xx_initval));
+ if (err)
+ goto out;
+ if (dev->fw.initvals1) {
+ err = bcm43xx_write_initvals(dev, (struct bcm43xx_initval *)dev->fw.initvals1->data,
+ dev->fw.initvals1->size / sizeof(struct bcm43xx_initval));
+ if (err)
+ goto out;
+ }
+out:
+ return err;
+}
+
+/* Initialize the GPIOs
+ * http://bcm-specs.sipsolutions.net/GPIO
+ */
+static int bcm43xx_gpio_init(struct bcm43xx_wldev *dev)
+{
+ struct ssb_bus *bus = dev->dev->bus;
+ struct ssb_device *gpiodev, *pcidev = NULL;
+ u32 mask, set;
+
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
+ bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
+ & 0xFFFF3FFF);
+
+ bcm43xx_leds_switch_all(dev, 0);
+ bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_MASK,
+ bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_MASK)
+ | 0x000F);
+
+ mask = 0x0000001F;
+ set = 0x0000000F;
+ if (dev->dev->bus->chip_id == 0x4301) {
+ mask |= 0x0060;
+ set |= 0x0060;
+ }
+ if (0 /* FIXME: conditional unknown */) {
+ bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_MASK,
+ bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_MASK)
+ | 0x0100);
+ mask |= 0x0180;
+ set |= 0x0180;
+ }
+ if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_PACTRL) {
+ bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_MASK,
+ bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_MASK)
+ | 0x0200);
+ mask |= 0x0200;
+ set |= 0x0200;
+ }
+ if (dev->dev->id.revision >= 2)
+ mask |= 0x0010; /* FIXME: This is redundant. */
+
+#ifdef CONFIG_SSB_DRIVER_PCICORE
+ pcidev = bus->pcicore.dev;
+#endif
+ gpiodev = bus->chipco.dev ? : pcidev;
+ if (!gpiodev)
+ return 0;
+ ssb_write32(gpiodev, BCM43xx_GPIO_CONTROL,
+ (ssb_read32(gpiodev, BCM43xx_GPIO_CONTROL)
+ & mask) | set);
+
+ return 0;
+}
+
+/* Turn off all GPIO stuff. Call this on module unload, for example. */
+static void bcm43xx_gpio_cleanup(struct bcm43xx_wldev *dev)
+{
+ struct ssb_bus *bus = dev->dev->bus;
+ struct ssb_device *gpiodev, *pcidev = NULL;
+
+#ifdef CONFIG_SSB_DRIVER_PCICORE
+ pcidev = bus->pcicore.dev;
+#endif
+ gpiodev = bus->chipco.dev ? : pcidev;
+ if (!gpiodev)
+ return;
+ ssb_write32(gpiodev, BCM43xx_GPIO_CONTROL, 0);
+}
+
+/* http://bcm-specs.sipsolutions.net/EnableMac */
+void bcm43xx_mac_enable(struct bcm43xx_wldev *dev)
+{
+ dev->mac_suspended--;
+ assert(dev->mac_suspended >= 0);
+ if (dev->mac_suspended == 0) {
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
+ bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
+ | BCM43xx_SBF_MAC_ENABLED);
+ bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON,
+ BCM43xx_IRQ_MAC_SUSPENDED);
+ bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
+ bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
+ bcm43xx_power_saving_ctl_bits(dev, -1, -1);
+ }
+}
+
+/* http://bcm-specs.sipsolutions.net/SuspendMAC */
+void bcm43xx_mac_suspend(struct bcm43xx_wldev *dev)
+{
+ int i;
+ u32 tmp;
+
+ assert(dev->mac_suspended >= 0);
+ if (dev->mac_suspended == 0) {
+ bcm43xx_power_saving_ctl_bits(dev, -1, 1);
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
+ bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
+ & ~BCM43xx_SBF_MAC_ENABLED);
+ bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
+ for (i = 10000; i; i--) {
+ tmp = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON);
+ if (tmp & BCM43xx_IRQ_MAC_SUSPENDED)
+ goto out;
+ udelay(1);
+ }
+ printkl(KERN_ERR PFX "MAC suspend failed\n");
+ }
+out:
+ dev->mac_suspended++;
+}
+
+static void bcm43xx_adjust_opmode(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_wl *wl = dev->wl;
+ u32 ctl;
+ u16 cfp_pretbtt;
+
+ ctl = bcm43xx_read32(dev, BCM43xx_MMIO_MACCTL);
+ /* Reset status to STA infrastructure mode. */
+ ctl &= ~BCM43xx_MACCTL_AP;
+ ctl &= ~BCM43xx_MACCTL_KEEP_CTL;
+ ctl &= ~BCM43xx_MACCTL_KEEP_BADPLCP;
+ ctl &= ~BCM43xx_MACCTL_KEEP_BAD;
+ ctl &= ~BCM43xx_MACCTL_PROMISC;
+ ctl |= BCM43xx_MACCTL_INFRA;
+
+ if (wl->operating) {
+ switch (wl->if_type) {
+ case IEEE80211_IF_TYPE_AP:
+ ctl |= BCM43xx_MACCTL_AP;
+ break;
+ case IEEE80211_IF_TYPE_IBSS:
+ ctl &= ~BCM43xx_MACCTL_INFRA;
+ break;
+ case IEEE80211_IF_TYPE_STA:
+ case IEEE80211_IF_TYPE_MNTR:
+ case IEEE80211_IF_TYPE_WDS:
+ break;
+ default:
+ assert(0);
+ }
+ }
+ if (wl->monitor) {
+ ctl |= BCM43xx_MACCTL_PROMISC;
+ ctl |= BCM43xx_MACCTL_KEEP_CTL;
+ if (modparam_mon_keep_bad)
+ ctl |= BCM43xx_MACCTL_KEEP_BAD;
+ if (modparam_mon_keep_badplcp)
+ ctl |= BCM43xx_MACCTL_KEEP_BADPLCP;
+ }
+ if (wl->promisc)
+ ctl |= BCM43xx_MACCTL_PROMISC;
+
+ bcm43xx_write32(dev, BCM43xx_MMIO_MACCTL, ctl);
+
+ cfp_pretbtt = 2;
+ if ((ctl & BCM43xx_MACCTL_INFRA) &&
+ !(ctl & BCM43xx_MACCTL_AP)) {
+ if (dev->dev->bus->chip_id == 0x4306 &&
+ dev->dev->bus->chip_rev == 3)
+ cfp_pretbtt = 100;
+ else
+ cfp_pretbtt = 50;
+ }
+ bcm43xx_write16(dev, 0x612, cfp_pretbtt);
+}
+
+static void bcm43xx_rate_memory_write(struct bcm43xx_wldev *dev,
+ u16 rate,
+ int is_ofdm)
+{
+ u16 offset;
+
+ if (is_ofdm) {
+ offset = 0x480;
+ offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
+ } else {
+ offset = 0x4C0;
+ offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
+ }
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, offset + 0x20,
+ bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, offset));
+}
+
+static void bcm43xx_rate_memory_init(struct bcm43xx_wldev *dev)
+{
+ switch (dev->phy.type) {
+ case BCM43xx_PHYTYPE_A:
+ case BCM43xx_PHYTYPE_G:
+ bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_6MB, 1);
+ bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_12MB, 1);
+ bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_18MB, 1);
+ bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_24MB, 1);
+ bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_36MB, 1);
+ bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_48MB, 1);
+ bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_54MB, 1);
+ case BCM43xx_PHYTYPE_B:
+ bcm43xx_rate_memory_write(dev, BCM43xx_CCK_RATE_1MB, 0);
+ bcm43xx_rate_memory_write(dev, BCM43xx_CCK_RATE_2MB, 0);
+ bcm43xx_rate_memory_write(dev, BCM43xx_CCK_RATE_5MB, 0);
+ bcm43xx_rate_memory_write(dev, BCM43xx_CCK_RATE_11MB, 0);
+ break;
+ default:
+ assert(0);
+ }
+}
+
+/* Set the TX-Antenna for management frames sent by firmware. */
+static void bcm43xx_mgmtframe_txantenna(struct bcm43xx_wldev *dev,
+ int antenna)
+{
+ u16 ant = 0;
+ u16 tmp;
+
+ switch (antenna) {
+ case BCM43xx_ANTENNA0:
+ ant |= BCM43xx_TX4_PHY_ANT0;
+ break;
+ case BCM43xx_ANTENNA1:
+ ant |= BCM43xx_TX4_PHY_ANT1;
+ break;
+ case BCM43xx_ANTENNA_AUTO:
+ ant |= BCM43xx_TX4_PHY_ANTLAST;
+ break;
+ default:
+ assert(0);
+ }
+
+ /* FIXME We also need to set the other flags of the PHY control field somewhere. */
+
+ /* For Beacons */
+ tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_BEACPHYCTL);
+ tmp = (tmp & ~BCM43xx_TX4_PHY_ANT) | ant;
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_BEACPHYCTL, tmp);
+ /* For ACK/CTS */
+ tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_ACKCTSPHYCTL);
+ tmp = (tmp & ~BCM43xx_TX4_PHY_ANT) | ant;
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_ACKCTSPHYCTL, tmp);
+ /* For Probe Resposes */
+ tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_PRPHYCTL);
+ tmp = (tmp & ~BCM43xx_TX4_PHY_ANT) | ant;
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_PRPHYCTL, tmp);
+}
+
+/* This is the opposite of bcm43xx_chip_init() */
+static void bcm43xx_chip_exit(struct bcm43xx_wldev *dev)
+{
+ bcm43xx_radio_turn_off(dev);
+ if (!modparam_noleds)
+ bcm43xx_leds_exit(dev);
+ bcm43xx_gpio_cleanup(dev);
+ /* firmware is released later */
+}
+
+/* Initialize the chip
+ * http://bcm-specs.sipsolutions.net/ChipInit
+ */
+static int bcm43xx_chip_init(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ int err, tmp;
+ u32 value32;
+ u16 value16;
+
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
+ BCM43xx_SBF_CORE_READY
+ | BCM43xx_SBF_400);
+
+ err = bcm43xx_request_firmware(dev);
+ if (err)
+ goto out;
+ err = bcm43xx_upload_microcode(dev);
+ if (err)
+ goto out; /* firmware is released later */
+
+ err = bcm43xx_gpio_init(dev);
+ if (err)
+ goto out; /* firmware is released later */
+ err = bcm43xx_upload_initvals(dev);
+ if (err)
+ goto err_gpio_cleanup;
+ bcm43xx_radio_turn_on(dev);
+ dev->radio_hw_enable = bcm43xx_is_hw_radio_enabled(dev);
+ dprintk(KERN_INFO PFX "Radio %s by hardware\n",
+ (dev->radio_hw_enable == 0) ? "disabled" : "enabled");
+
+ bcm43xx_write16(dev, 0x03E6, 0x0000);
+ err = bcm43xx_phy_init(dev);
+ if (err)
+ goto err_radio_off;
+
+ /* Select initial Interference Mitigation. */
+ tmp = phy->interfmode;
+ phy->interfmode = BCM43xx_INTERFMODE_NONE;
+ bcm43xx_radio_set_interference_mitigation(dev, tmp);
+
+ bcm43xx_set_rx_antenna(dev, BCM43xx_ANTENNA_DEFAULT);
+ bcm43xx_mgmtframe_txantenna(dev, BCM43xx_ANTENNA_DEFAULT);
+
+ if (phy->type == BCM43xx_PHYTYPE_B) {
+ value16 = bcm43xx_read16(dev, 0x005E);
+ value16 |= 0x0004;
+ bcm43xx_write16(dev, 0x005E, value16);
+ }
+ bcm43xx_write32(dev, 0x0100, 0x01000000);
+ if (dev->dev->id.revision < 5)
+ bcm43xx_write32(dev, 0x010C, 0x01000000);
+
+ value32 = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
+ value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, value32);
+ value32 = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
+ value32 |= BCM43xx_SBF_MODE_NOTADHOC;
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, value32);
+
+ value32 = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
+ value32 |= 0x100000;
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, value32);
+
+ if (bcm43xx_using_pio(dev)) {
+ bcm43xx_write32(dev, 0x0210, 0x00000100);
+ bcm43xx_write32(dev, 0x0230, 0x00000100);
+ bcm43xx_write32(dev, 0x0250, 0x00000100);
+ bcm43xx_write32(dev, 0x0270, 0x00000100);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
+ }
+
+ /* Probe Response Timeout value */
+ /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
+
+ /* Initially set the wireless operation mode. */
+ bcm43xx_adjust_opmode(dev);
+
+ if (dev->dev->id.revision < 3) {
+ bcm43xx_write16(dev, 0x060E, 0x0000);
+ bcm43xx_write16(dev, 0x0610, 0x8000);
+ bcm43xx_write16(dev, 0x0604, 0x0000);
+ bcm43xx_write16(dev, 0x0606, 0x0200);
+ } else {
+ bcm43xx_write32(dev, 0x0188, 0x80000000);
+ bcm43xx_write32(dev, 0x018C, 0x02000000);
+ }
+ bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
+ bcm43xx_write32(dev, BCM43xx_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
+ bcm43xx_write32(dev, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
+ bcm43xx_write32(dev, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
+ bcm43xx_write32(dev, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
+ bcm43xx_write32(dev, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
+ bcm43xx_write32(dev, BCM43xx_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
+
+ value32 = ssb_read32(dev->dev, SSB_TMSLOW);
+ value32 |= 0x00100000;
+ ssb_write32(dev->dev, SSB_TMSLOW, value32);
+
+ bcm43xx_write16(dev, BCM43xx_MMIO_POWERUP_DELAY,
+ dev->dev->bus->chipco.fast_pwrup_delay);
+
+ assert(err == 0);
+ dprintk(KERN_INFO PFX "Chip initialized\n");
+out:
+ return err;
+
+err_radio_off:
+ bcm43xx_radio_turn_off(dev);
+err_gpio_cleanup:
+ bcm43xx_gpio_cleanup(dev);
+ goto out;
+}
+
+static void bcm43xx_periodic_every120sec(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
+ return;
+
+ bcm43xx_mac_suspend(dev);
+ bcm43xx_lo_g_measure(dev);
+ bcm43xx_mac_enable(dev);
+}
+
+static void bcm43xx_periodic_every60sec(struct bcm43xx_wldev *dev)
+{
+ bcm43xx_lo_g_ctl_mark_all_unused(dev);
+ if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_RSSI) {
+ bcm43xx_mac_suspend(dev);
+ bcm43xx_calc_nrssi_slope(dev);
+ bcm43xx_mac_enable(dev);
+ }
+}
+
+static void bcm43xx_periodic_every30sec(struct bcm43xx_wldev *dev)
+{
+ /* Update device statistics. */
+ bcm43xx_calculate_link_quality(dev);
+}
+
+static void bcm43xx_periodic_every15sec(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ if (phy->type == BCM43xx_PHYTYPE_G) {
+ //TODO: update_aci_moving_average
+ if (phy->aci_enable && phy->aci_wlan_automatic) {
+ bcm43xx_mac_suspend(dev);
+ if (!phy->aci_enable && 1 /*TODO: not scanning? */) {
+ if (0 /*TODO: bunch of conditions*/) {
+ bcm43xx_radio_set_interference_mitigation(dev,
+ BCM43xx_INTERFMODE_MANUALWLAN);
+ }
+ } else if (1/*TODO*/) {
+ /*
+ if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(dev))) {
+ bcm43xx_radio_set_interference_mitigation(dev,
+ BCM43xx_INTERFMODE_NONE);
+ }
+ */
+ }
+ bcm43xx_mac_enable(dev);
+ } else if (phy->interfmode == BCM43xx_INTERFMODE_NONWLAN &&
+ phy->rev == 1) {
+ //TODO: implement rev1 workaround
+ }
+ }
+ bcm43xx_phy_xmitpower(dev); //FIXME: unless scanning?
+ //TODO for APHY (temperature?)
+}
+
+static void bcm43xx_periodic_every1sec(struct bcm43xx_wldev *dev)
+{
+ int radio_hw_enable;
+
+ /* check if radio hardware enabled status changed */
+ radio_hw_enable = bcm43xx_is_hw_radio_enabled(dev);
+ if (unlikely(dev->radio_hw_enable != radio_hw_enable)) {
+ dev->radio_hw_enable = radio_hw_enable;
+ dprintk(KERN_INFO PFX "Radio hardware status changed to %s\n",
+ (radio_hw_enable == 0) ? "disabled" : "enabled");
+ bcm43xx_leds_update(dev, 0);
+ }
+}
+
+static void do_periodic_work(struct bcm43xx_wldev *dev)
+{
+ unsigned int state;
+
+ state = dev->periodic_state;
+ if (state % 120 == 0)
+ bcm43xx_periodic_every120sec(dev);
+ if (state % 60 == 0)
+ bcm43xx_periodic_every60sec(dev);
+ if (state % 30 == 0)
+ bcm43xx_periodic_every30sec(dev);
+ if (state % 15 == 0)
+ bcm43xx_periodic_every15sec(dev);
+ bcm43xx_periodic_every1sec(dev);
+
+ dev->periodic_state = state + 1;
+
+ schedule_delayed_work(&dev->periodic_work, HZ);
+}
+
+/* Estimate a "Badness" value based on the periodic work
+ * state-machine state. "Badness" is worse (bigger), if the
+ * periodic work will take longer.
+ */
+static int estimate_periodic_work_badness(unsigned int state)
+{
+ int badness = 0;
+
+ if (state % 120 == 0) /* every 120 sec */
+ badness += 10;
+ if (state % 60 == 0) /* every 60 sec */
+ badness += 5;
+ if (state % 30 == 0) /* every 30 sec */
+ badness += 1;
+ if (state % 15 == 0) /* every 15 sec */
+ badness += 1;
+
+#define BADNESS_LIMIT 4
+ return badness;
+}
+
+static void bcm43xx_periodic_work_handler(struct work_struct *work)
+{
+ struct bcm43xx_wldev *dev =
+ container_of(work, struct bcm43xx_wldev, periodic_work.work);
+ unsigned long flags;
+ u32 savedirqs = 0;
+ int badness;
+
+ mutex_lock(&dev->wl->mutex);
+ badness = estimate_periodic_work_badness(dev->periodic_state);
+ if (badness > BADNESS_LIMIT) {
+ /* Periodic work will take a long time, so we want it to
+ * be preemtible.
+ */
+ ieee80211_stop_queues(dev->wl->hw);
+ spin_lock_irqsave(&dev->wl->irq_lock, flags);
+ bcm43xx_mac_suspend(dev);
+ if (bcm43xx_using_pio(dev))
+ bcm43xx_pio_freeze_txqueues(dev);
+ savedirqs = bcm43xx_interrupt_disable(dev, BCM43xx_IRQ_ALL);
+ spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+ bcm43xx_synchronize_irq(dev);
+ } else {
+ /* Periodic work should take short time, so we want low
+ * locking overhead.
+ */
+ spin_lock_irqsave(&dev->wl->irq_lock, flags);
+ }
+
+ do_periodic_work(dev);
+
+ if (badness > BADNESS_LIMIT) {
+ spin_lock_irqsave(&dev->wl->irq_lock, flags);
+ bcm43xx_interrupt_enable(dev, savedirqs);
+ if (bcm43xx_using_pio(dev))
+ bcm43xx_pio_thaw_txqueues(dev);
+ bcm43xx_mac_enable(dev);
+ ieee80211_start_queues(dev->wl->hw);
+ }
+ mmiowb();
+ spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+ mutex_unlock(&dev->wl->mutex);
+}
+
+static void bcm43xx_periodic_tasks_delete(struct bcm43xx_wldev *dev)
+{
+ cancel_rearming_delayed_work(&dev->periodic_work);
+}
+
+static void bcm43xx_periodic_tasks_setup(struct bcm43xx_wldev *dev)
+{
+ struct delayed_work *work = &dev->periodic_work;
+
+ assert(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED);
+ dev->periodic_state = 0;
+ INIT_DELAYED_WORK(work, bcm43xx_periodic_work_handler);
+ schedule_delayed_work(work, 0);
+}
+
+/* Validate access to the chip (SHM) */
+static int bcm43xx_validate_chipaccess(struct bcm43xx_wldev *dev)
+{
+ u32 value;
+ u32 shm_backup;
+
+ shm_backup = bcm43xx_shm_read32(dev, BCM43xx_SHM_SHARED, 0);
+ bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED, 0, 0xAA5555AA);
+ if (bcm43xx_shm_read32(dev, BCM43xx_SHM_SHARED, 0) != 0xAA5555AA)
+ goto error;
+ bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED, 0, 0x55AAAA55);
+ if (bcm43xx_shm_read32(dev, BCM43xx_SHM_SHARED, 0) != 0x55AAAA55)
+ goto error;
+ bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED, 0, shm_backup);
+
+ value = bcm43xx_read32(dev, BCM43xx_MMIO_MACCTL);
+ if ((value | BCM43xx_MACCTL_GMODE) !=
+ (BCM43xx_MACCTL_GMODE | BCM43xx_MACCTL_IHR_ENABLED))
+ goto error;
+
+ value = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON);
+ if (value)
+ goto error;
+
+ return 0;
+error:
+ printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
+ return -ENODEV;
+}
+
+static void bcm43xx_security_init(struct bcm43xx_wldev *dev)
+{
+ dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
+ assert(dev->max_nr_keys <= ARRAY_SIZE(dev->key));
+ dev->ktp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_KTP);
+ /* KTP is a word address, but we address SHM bytewise.
+ * So multiply by two.
+ */
+ dev->ktp *= 2;
+ if (dev->dev->id.revision >= 5) {
+ /* Number of RCMTA address slots */
+ bcm43xx_write16(dev, BCM43xx_MMIO_RCMTA_COUNT,
+ dev->max_nr_keys - 8);
+ }
+ bcm43xx_clear_keys(dev);
+}
+
+static int bcm43xx_rng_read(struct hwrng *rng, u32 *data)
+{
+ struct bcm43xx_wl *wl = (struct bcm43xx_wl *)rng->priv;
+ unsigned long flags;
+
+ /* Don't take wl->mutex here, as it could deadlock with
+ * hwrng internal locking. It's not needed to take
+ * wl->mutex here, anyway. */
+
+ spin_lock_irqsave(&wl->irq_lock, flags);
+ *data = bcm43xx_read16(wl->current_dev, BCM43xx_MMIO_RNG);
+ spin_unlock_irqrestore(&wl->irq_lock, flags);
+
+ return (sizeof(u16));
+}
+
+static void bcm43xx_rng_exit(struct bcm43xx_wl *wl)
+{
+ if (wl->rng_initialized)
+ hwrng_unregister(&wl->rng);
+}
+
+static int bcm43xx_rng_init(struct bcm43xx_wl *wl)
+{
+ int err;
+
+ snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
+ "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
+ wl->rng.name = wl->rng_name;
+ wl->rng.data_read = bcm43xx_rng_read;
+ wl->rng.priv = (unsigned long)wl;
+ wl->rng_initialized = 1;
+ err = hwrng_register(&wl->rng);
+ if (err) {
+ wl->rng_initialized = 0;
+ printk(KERN_ERR PFX "Failed to register the random "
+ "number generator (%d)\n", err);
+ }
+
+ return err;
+}
+
+static int bcm43xx_tx(struct ieee80211_hw *hw,
+ struct sk_buff *skb,
+ struct ieee80211_tx_control *ctl)
+{
+ struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+ struct bcm43xx_wldev *dev = wl->current_dev;
+ int err = -ENODEV;
+ unsigned long flags;
+
+ if (unlikely(!dev))
+ goto out;
+ spin_lock_irqsave(&wl->irq_lock, flags);
+ if (likely(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED)) {
+ if (bcm43xx_using_pio(dev))
+ err = bcm43xx_pio_tx(dev, skb, ctl);
+ else
+ err = bcm43xx_dma_tx(dev, skb, ctl);
+ }
+ spin_unlock_irqrestore(&wl->irq_lock, flags);
+out:
+ if (unlikely(err))
+ return NETDEV_TX_BUSY;
+ return NETDEV_TX_OK;
+}
+
+static int bcm43xx_conf_tx(struct ieee80211_hw *hw,
+ int queue,
+ const struct ieee80211_tx_queue_params *params)
+{
+ return 0;
+}
+
+static int bcm43xx_get_tx_stats(struct ieee80211_hw *hw,
+ struct ieee80211_tx_queue_stats *stats)
+{
+ struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+ struct bcm43xx_wldev *dev = wl->current_dev;
+ unsigned long flags;
+ int err = -ENODEV;
+
+ if (!dev)
+ goto out;
+ spin_lock_irqsave(&wl->irq_lock, flags);
+ if (likely(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED)) {
+ if (bcm43xx_using_pio(dev))
+ bcm43xx_pio_get_tx_stats(dev, stats);
+ else
+ bcm43xx_dma_get_tx_stats(dev, stats);
+ err = 0;
+ }
+ spin_unlock_irqrestore(&wl->irq_lock, flags);
+out:
+ return err;
+}
+
+static int bcm43xx_get_stats(struct ieee80211_hw *hw,
+ struct ieee80211_low_level_stats *stats)
+{
+ struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+ unsigned long flags;
+
+ spin_lock_irqsave(&wl->irq_lock, flags);
+ memcpy(stats, &wl->ieee_stats, sizeof(*stats));
+ spin_unlock_irqrestore(&wl->irq_lock, flags);
+
+ return 0;
+}
+
+static int bcm43xx_dev_reset(struct ieee80211_hw *hw)
+{
+ struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+ struct bcm43xx_wldev *dev = wl->current_dev;
+ unsigned long flags;
+
+ if (!dev)
+ return -ENODEV;
+ spin_lock_irqsave(&wl->irq_lock, flags);
+ bcm43xx_controller_restart(dev, "Reset by ieee80211 subsystem");
+ spin_unlock_irqrestore(&wl->irq_lock, flags);
+
+ return 0;
+}
+
+static const char * phymode_to_string(unsigned int phymode)
+{
+ switch (phymode) {
+ case BCM43xx_PHYMODE_A:
+ return "A";
+ case BCM43xx_PHYMODE_B:
+ return "B";
+ case BCM43xx_PHYMODE_G:
+ return "G";
+ default:
+ assert(0);
+ }
+ return "";
+}
+
+static int find_wldev_for_phymode(struct bcm43xx_wl *wl,
+ unsigned int phymode,
+ struct bcm43xx_wldev **dev,
+ int *gmode)
+{
+ struct bcm43xx_wldev *d;
+
+ list_for_each_entry(d, &wl->devlist, list) {
+ if (d->phy.possible_phymodes & phymode) {
+ /* Ok, this device supports the PHY-mode.
+ * Now figure out how the gmode bit has to be
+ * set to support it. */
+ if (phymode == BCM43xx_PHYMODE_A)
+ *gmode = 0;
+ else
+ *gmode = 1;
+ *dev = d;
+
+ return 0;
+ }
+ }
+
+ return -ESRCH;
+}
+
+static void bcm43xx_put_phy_into_reset(struct bcm43xx_wldev *dev)
+{
+ struct ssb_device *sdev = dev->dev;
+ u32 tmslow;
+
+ tmslow = ssb_read32(sdev, SSB_TMSLOW);
+ tmslow &= ~BCM43xx_TMSLOW_GMODE;
+ tmslow |= BCM43xx_TMSLOW_PHYRESET;
+ tmslow |= SSB_TMSLOW_FGC;
+ ssb_write32(sdev, SSB_TMSLOW, tmslow);
+ msleep(1);
+
+ tmslow = ssb_read32(sdev, SSB_TMSLOW);
+ tmslow &= ~SSB_TMSLOW_FGC;
+ tmslow |= BCM43xx_TMSLOW_PHYRESET;
+ ssb_write32(sdev, SSB_TMSLOW, tmslow);
+ msleep(1);
+}
+
+static int bcm43xx_switch_phymode(struct bcm43xx_wl *wl,
+ unsigned int new_mode)
+{
+ struct bcm43xx_wldev *up_dev;
+ struct bcm43xx_wldev *down_dev;
+ int err;
+ int gmode = -1;
+ int old_was_started = 0;
+ int old_was_inited = 0;
+
+ err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
+ if (err) {
+ printk(KERN_INFO PFX "Could not find a device for %s-PHY mode\n",
+ phymode_to_string(new_mode));
+ return err;
+ }
+ assert(gmode == 0 || gmode == 1);
+ if ((up_dev == wl->current_dev) &&
+ (wl->current_dev->phy.gmode == gmode)) {
+ /* This device is already running. */
+ return 0;
+ }
+ dprintk(KERN_INFO PFX "Reconfiguring PHYmode to %s-PHY\n",
+ phymode_to_string(new_mode));
+ down_dev = wl->current_dev;
+
+ /* Shutdown the currently running core. */
+ if (down_dev->started) {
+ old_was_started = 1;
+ bcm43xx_wireless_core_stop(down_dev);
+ }
+ if (bcm43xx_status(down_dev) == BCM43xx_STAT_INITIALIZED) {
+ old_was_inited = 1;
+ bcm43xx_wireless_core_exit(down_dev);
+ }
+
+ if (down_dev != up_dev) {
+ /* We switch to a different core, so we put PHY into
+ * RESET on the old core. */
+ bcm43xx_put_phy_into_reset(down_dev);
+ }
+
+ /* Now start the new core. */
+ up_dev->phy.gmode = gmode;
+ if (old_was_inited) {
+ err = bcm43xx_wireless_core_init(up_dev);
+ if (err) {
+ printk(KERN_INFO PFX "Fatal: Could not initialize device for "
+ "new selected %s-PHY mode\n",
+ phymode_to_string(new_mode));
+ return err;
+ }
+ }
+ if (old_was_started) {
+ assert(old_was_inited);
+ err = bcm43xx_wireless_core_start(up_dev);
+ if (err) {
+ printk(KERN_INFO PFX "Fatal: Coult not start device for "
+ "new selected %s-PHY mode\n",
+ phymode_to_string(new_mode));
+ bcm43xx_wireless_core_exit(up_dev);
+ return err;
+ }
+ }
+
+ wl->current_dev = up_dev;
+
+ return 0;
+}
+
+static int bcm43xx_antenna_from_ieee80211(u8 antenna)
+{
+ switch (antenna) {
+ case 0: /* default/diversity */
+ return BCM43xx_ANTENNA_DEFAULT;
+ case 1: /* Antenna 0 */
+ return BCM43xx_ANTENNA0;
+ case 2: /* Antenna 1 */
+ return BCM43xx_ANTENNA1;
+ default:
+ return BCM43xx_ANTENNA_DEFAULT;
+ }
+}
+
+static int bcm43xx_dev_config(struct ieee80211_hw *hw,
+ struct ieee80211_conf *conf)
+{
+ struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+ struct bcm43xx_wldev *dev;
+ struct bcm43xx_phy *phy;
+ unsigned long flags;
+ unsigned int new_phymode = 0xFFFF;
+ int antenna_tx;
+ int antenna_rx;
+ int err = 0;
+
+ antenna_tx = bcm43xx_antenna_from_ieee80211(conf->antenna_sel_tx);
+ antenna_rx = bcm43xx_antenna_from_ieee80211(conf->antenna_sel_rx);
+
+ mutex_lock(&wl->mutex);
+
+ /* Switch the PHY mode (if necessary). */
+ switch (conf->phymode) {
+ case MODE_IEEE80211A:
+ new_phymode = BCM43xx_PHYMODE_A;
+ break;
+ case MODE_IEEE80211B:
+ new_phymode = BCM43xx_PHYMODE_B;
+ break;
+ case MODE_IEEE80211G:
+ new_phymode = BCM43xx_PHYMODE_G;
+ break;
+ default:
+ assert(0);
+ }
+ err = bcm43xx_switch_phymode(wl, new_phymode);
+ if (err)
+ goto out_unlock_mutex;
+ dev = wl->current_dev;
+ phy = &dev->phy;
+
+ spin_lock_irqsave(&wl->irq_lock, flags);
+ if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED)
+ goto out_unlock;
+
+ /* Switch to the requested channel. */
+ if (conf->channel_val != phy->channel)
+ bcm43xx_radio_selectchannel(dev, conf->channel_val, 0);
+
+ /* Enable/Disable ShortSlot timing. */
+ if (!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) != dev->short_slot) {
+ assert(phy->type == BCM43xx_PHYTYPE_G);
+ if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
+ bcm43xx_short_slot_timing_enable(dev);
+ else
+ bcm43xx_short_slot_timing_disable(dev);
+ }
+
+ /* Adjust the desired TX power level. */
+ if (conf->power_level != 0) {
+ if (conf->power_level != phy->power_level) {
+ phy->power_level = conf->power_level;
+ bcm43xx_phy_xmitpower(dev);
+ }
+ }
+
+ /* Hide/Show the SSID (AP mode only). */
+ if (conf->flags & IEEE80211_CONF_SSID_HIDDEN) {
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
+ bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
+ | BCM43xx_SBF_NO_SSID_BCAST);
+ } else {
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
+ bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
+ & ~BCM43xx_SBF_NO_SSID_BCAST);
+ }
+
+ /* Antennas for RX and management frame TX. */
+ bcm43xx_mgmtframe_txantenna(dev, antenna_tx);
+ bcm43xx_set_rx_antenna(dev, antenna_rx);
+
+ /* Update templates for AP mode. */
+ if (bcm43xx_is_mode(wl, IEEE80211_IF_TYPE_AP))
+ bcm43xx_set_beacon_int(dev, conf->beacon_int);
+
+out_unlock:
+ spin_unlock_irqrestore(&wl->irq_lock, flags);
+out_unlock_mutex:
+ mutex_unlock(&wl->mutex);
+
+ return err;
+}
+
+static int bcm43xx_dev_set_key(struct ieee80211_hw *hw,
+ set_key_cmd cmd,
+ u8 *addr,
+ struct ieee80211_key_conf *key,
+ int aid)
+{
+ struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+ struct bcm43xx_wldev *dev = wl->current_dev;
+ unsigned long flags;
+ u8 algorithm;
+ u8 index;
+ int err = -EINVAL;
+
+ if (!dev)
+ return -ENODEV;
+ switch (key->alg) {
+ case ALG_NONE:
+ case ALG_NULL:
+ algorithm = BCM43xx_SEC_ALGO_NONE;
+ break;
+ case ALG_WEP:
+ if (key->keylen == 5)
+ algorithm = BCM43xx_SEC_ALGO_WEP40;
+ else
+ algorithm = BCM43xx_SEC_ALGO_WEP104;
+ break;
+ case ALG_TKIP:
+ algorithm = BCM43xx_SEC_ALGO_TKIP;
+ break;
+ case ALG_CCMP:
+ algorithm = BCM43xx_SEC_ALGO_AES;
+ break;
+ default:
+ assert(0);
+ goto out;
+ }
+
+ index = (u8)(key->keyidx);
+ if (index > 3)
+ goto out;
+
+ mutex_lock(&wl->mutex);
+ spin_lock_irqsave(&wl->irq_lock, flags);
+
+ if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED) {
+ err = -ENODEV;
+ goto out_unlock;
+ }
+
+ switch (cmd) {
+ case SET_KEY:
+ key->flags &= ~IEEE80211_KEY_FORCE_SW_ENCRYPT;
+
+ if (algorithm == BCM43xx_SEC_ALGO_TKIP) {
+ /* FIXME: No TKIP hardware encryption for now. */
+ key->flags |= IEEE80211_KEY_FORCE_SW_ENCRYPT;
+ }
+
+ if (is_broadcast_ether_addr(addr)) {
+ /* addr is FF:FF:FF:FF:FF:FF for default keys */
+ err = bcm43xx_key_write(dev, index, algorithm,
+ key->key, key->keylen,
+ NULL, key);
+ } else {
+ err = bcm43xx_key_write(dev, -1, algorithm,
+ key->key, key->keylen,
+ addr, key);
+ }
+ if (err) {
+ key->flags |= IEEE80211_KEY_FORCE_SW_ENCRYPT;
+ goto out_unlock;
+ }
+ dev->key[key->hw_key_idx].enabled = 1;
+
+ if (algorithm == BCM43xx_SEC_ALGO_WEP40 ||
+ algorithm == BCM43xx_SEC_ALGO_WEP104) {
+ bcm43xx_hf_write(dev,
+ bcm43xx_hf_read(dev) |
+ BCM43xx_HF_USEDEFKEYS);
+ } else {
+ bcm43xx_hf_write(dev,
+ bcm43xx_hf_read(dev) &
+ ~BCM43xx_HF_USEDEFKEYS);
+ }
+ break;
+ case DISABLE_KEY: {
+ static const u8 zero[BCM43xx_SEC_KEYSIZE] = { 0 };
+
+ algorithm = BCM43xx_SEC_ALGO_NONE;
+ if (is_broadcast_ether_addr(addr)) {
+ err = bcm43xx_key_write(dev, index, algorithm,
+ zero, BCM43xx_SEC_KEYSIZE,
+ NULL, key);
+ } else {
+ err = bcm43xx_key_write(dev, -1, algorithm,
+ zero, BCM43xx_SEC_KEYSIZE,
+ addr, key);
+ }
+ dev->key[key->hw_key_idx].enabled = 0;
+ break;
+ }
+ case REMOVE_ALL_KEYS:
+ bcm43xx_clear_keys(dev);
+ err = 0;
+ break;
+ default:
+ assert(0);
+ }
+out_unlock:
+ spin_unlock_irqrestore(&wl->irq_lock, flags);
+ mutex_unlock(&wl->mutex);
+out:
+ if (!err) {
+ dprintk(KERN_DEBUG PFX "Using %s based encryption for keyidx: %d, "
+ "mac: " MAC_FMT "\n",
+ (key->flags & IEEE80211_KEY_FORCE_SW_ENCRYPT) ?
+ "software" : "hardware",
+ key->keyidx, MAC_ARG(addr));
+ }
+ return err;
+}
+
+static void bcm43xx_set_multicast_list(struct ieee80211_hw *hw,
+ unsigned short netflags,
+ int mc_count)
+{
+ struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+ struct bcm43xx_wldev *dev = wl->current_dev;
+ unsigned long flags;
+
+ if (!dev)
+ return;
+ spin_lock_irqsave(&wl->irq_lock, flags);
+ if (wl->promisc != !!(netflags & IFF_PROMISC)) {
+ wl->promisc = !!(netflags & IFF_PROMISC);
+ if (bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED)
+ bcm43xx_adjust_opmode(dev);
+ }
+ spin_unlock_irqrestore(&wl->irq_lock, flags);
+}
+
+static int bcm43xx_config_interface(struct ieee80211_hw *hw,
+ int if_id,
+ struct ieee80211_if_conf *conf)
+{
+ struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+ struct bcm43xx_wldev *dev = wl->current_dev;
+ unsigned long flags;
+
+ if (!dev)
+ return -ENODEV;
+ mutex_lock(&wl->mutex);
+ spin_lock_irqsave(&wl->irq_lock, flags);
+ if (conf->type != IEEE80211_IF_TYPE_MNTR) {
+ assert(wl->if_id == if_id);
+ wl->bssid = conf->bssid;
+ if (bcm43xx_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
+ assert(conf->type == IEEE80211_IF_TYPE_AP);
+ bcm43xx_set_ssid(dev, conf->ssid, conf->ssid_len);
+ if (conf->beacon)
+ bcm43xx_refresh_templates(dev, conf->beacon);
+ }
+ }
+ spin_unlock_irqrestore(&wl->irq_lock, flags);
+ mutex_unlock(&wl->mutex);
+
+ return 0;
+}
+
+/* Locking: wl->mutex */
+static void bcm43xx_wireless_core_stop(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_wl *wl = dev->wl;
+ unsigned long flags;
+
+ if (!dev->started)
+ return;
+
+ mutex_unlock(&wl->mutex);
+ bcm43xx_periodic_tasks_delete(dev);
+ flush_scheduled_work();
+ mutex_lock(&wl->mutex);
+
+ ieee80211_stop_queues(wl->hw);
+
+ /* Disable and sync interrupts. */
+ spin_lock_irqsave(&wl->irq_lock, flags);
+ dev->irq_savedstate = bcm43xx_interrupt_disable(dev, BCM43xx_IRQ_ALL);
+ bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_MASK); /* flush */
+ spin_unlock_irqrestore(&wl->irq_lock, flags);
+ bcm43xx_synchronize_irq(dev);
+
+ bcm43xx_mac_suspend(dev);
+ free_irq(dev->dev->irq, dev);
+ dev->started = 0;
+ dprintk(KERN_INFO PFX "Wireless interface stopped\n");
+}
+
+/* Locking: wl->mutex */
+static int bcm43xx_wireless_core_start(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_wl *wl = dev->wl;
+ int err;
+
+ assert(!dev->started);
+
+ drain_txstatus_queue(dev);
+ err = request_irq(dev->dev->irq, bcm43xx_interrupt_handler,
+ IRQF_SHARED, KBUILD_MODNAME, dev);
+ if (err) {
+ printk(KERN_ERR PFX "Cannot request IRQ-%d\n",
+ dev->dev->irq);
+ goto out;
+ }
+ dev->started = 1;
+ bcm43xx_interrupt_enable(dev, dev->irq_savedstate);
+ bcm43xx_mac_enable(dev);
+
+ ieee80211_start_queues(wl->hw);
+ bcm43xx_periodic_tasks_setup(dev);
+ dprintk(KERN_INFO PFX "Wireless interface started\n");
+out:
+ return err;
+}
+
+/* Get PHY and RADIO versioning numbers */
+static int bcm43xx_phy_versioning(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u32 tmp;
+ u8 analog_type;
+ u8 phy_type;
+ u8 phy_rev;
+ u16 radio_manuf;
+ u16 radio_ver;
+ u16 radio_rev;
+ int unsupported = 0;
+
+ /* Get PHY versioning */
+ tmp = bcm43xx_read16(dev, BCM43xx_MMIO_PHY_VER);
+ analog_type = (tmp & BCM43xx_PHYVER_ANALOG) >> BCM43xx_PHYVER_ANALOG_SHIFT;
+ phy_type = (tmp & BCM43xx_PHYVER_TYPE) >> BCM43xx_PHYVER_TYPE_SHIFT;
+ phy_rev = (tmp & BCM43xx_PHYVER_VERSION);
+ switch (phy_type) {
+ case BCM43xx_PHYTYPE_A:
+ if (phy_rev >= 4)
+ unsupported = 1;
+ break;
+ case BCM43xx_PHYTYPE_B:
+ if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
+ unsupported = 1;
+ break;
+ case BCM43xx_PHYTYPE_G:
+ if (phy_rev > 8)
+ unsupported = 1;
+ break;
+ default:
+ unsupported = 1;
+ };
+ if (unsupported) {
+ printk(KERN_ERR PFX "FOUND UNSUPPORTED PHY "
+ "(Analog %u, Type %u, Revision %u)\n",
+ analog_type, phy_type, phy_rev);
+ return -EOPNOTSUPP;
+ }
+ dprintk(KERN_INFO PFX "Found PHY: Analog %u, Type %u, Revision %u\n",
+ analog_type, phy_type, phy_rev);
+
+
+ /* Get RADIO versioning */
+ if (dev->dev->bus->chip_id == 0x4317) {
+ if (dev->dev->bus->chip_rev == 0)
+ tmp = 0x3205017F;
+ else if (dev->dev->bus->chip_rev == 1)
+ tmp = 0x4205017F;
+ else
+ tmp = 0x5205017F;
+ } else {
+ bcm43xx_write16(dev, BCM43xx_MMIO_RADIO_CONTROL,
+ BCM43xx_RADIOCTL_ID);
+ tmp = bcm43xx_read16(dev, BCM43xx_MMIO_RADIO_DATA_HIGH);
+ tmp <<= 16;
+ bcm43xx_write16(dev, BCM43xx_MMIO_RADIO_CONTROL,
+ BCM43xx_RADIOCTL_ID);
+ tmp |= bcm43xx_read16(dev, BCM43xx_MMIO_RADIO_DATA_LOW);
+ }
+ radio_manuf = (tmp & 0x00000FFF);
+ radio_ver = (tmp & 0x0FFFF000) >> 12;
+ radio_rev = (tmp & 0xF0000000) >> 28;
+ switch (phy_type) {
+ case BCM43xx_PHYTYPE_A:
+ if (radio_ver != 0x2060)
+ unsupported = 1;
+ if (radio_rev != 1)
+ unsupported = 1;
+ if (radio_manuf != 0x17F)
+ unsupported = 1;
+ break;
+ case BCM43xx_PHYTYPE_B:
+ if ((radio_ver & 0xFFF0) != 0x2050)
+ unsupported = 1;
+ break;
+ case BCM43xx_PHYTYPE_G:
+ if (radio_ver != 0x2050)
+ unsupported = 1;
+ break;
+ default:
+ assert(0);
+ }
+ if (unsupported) {
+ printk(KERN_ERR PFX "FOUND UNSUPPORTED RADIO "
+ "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
+ radio_manuf, radio_ver, radio_rev);
+ return -EOPNOTSUPP;
+ }
+ dprintk(KERN_INFO PFX "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
+ radio_manuf, radio_ver, radio_rev);
+
+
+ phy->radio_manuf = radio_manuf;
+ phy->radio_ver = radio_ver;
+ phy->radio_rev = radio_rev;
+
+ phy->analog = analog_type;
+ phy->type = phy_type;
+ phy->rev = phy_rev;
+
+ return 0;
+}
+
+static void setup_struct_phy_for_init(struct bcm43xx_wldev *dev,
+ struct bcm43xx_phy *phy)
+{
+ struct bcm43xx_txpower_lo_control *lo;
+ int i;
+
+ memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
+ memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
+
+ /* Flags */
+ phy->locked = 0;
+
+ phy->aci_enable = 0;
+ phy->aci_wlan_automatic = 0;
+ phy->aci_hw_rssi = 0;
+
+ lo = phy->lo_control;
+ if (lo) {
+ memset(lo, 0, sizeof(*(phy->lo_control)));
+ lo->rebuild = 1;
+ lo->tx_bias = 0xFF;
+ }
+ phy->max_lb_gain = 0;
+ phy->trsw_rx_gain = 0;
+
+ /* Set default attenuation values. */
+ phy->bbatt = bcm43xx_default_baseband_attenuation(dev);
+ phy->rfatt = bcm43xx_default_radio_attenuation(dev);
+ phy->txctl1 = bcm43xx_default_txctl1(dev);
+ phy->txpwr_offset = 0;
+
+ /* NRSSI */
+ phy->nrssislope = 0;
+ for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
+ phy->nrssi[i] = -1000;
+ for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
+ phy->nrssi_lt[i] = i;
+
+ phy->lofcal = 0xFFFF;
+ phy->initval = 0xFFFF;
+
+ spin_lock_init(&phy->lock);
+ phy->interfmode = BCM43xx_INTERFMODE_NONE;
+ phy->channel = 0xFF;
+}
+
+static void setup_struct_wldev_for_init(struct bcm43xx_wldev *dev)
+{
+ /* Flags */
+ dev->reg124_set_0x4 = 0;
+
+ /* Stats */
+ memset(&dev->stats, 0, sizeof(dev->stats));
+
+ setup_struct_phy_for_init(dev, &dev->phy);
+
+ /* IRQ related flags */
+ dev->irq_reason = 0;
+ memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
+ dev->irq_savedstate = BCM43xx_IRQ_MASKTEMPLATE;
+
+ dev->mac_suspended = 1;
+
+ /* Noise calculation context */
+ memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
+}
+
+static void bcm43xx_bluetooth_coext_enable(struct bcm43xx_wldev *dev)
+{
+ struct ssb_sprom *sprom = &dev->dev->bus->sprom;
+ u32 hf;
+
+ if (!(sprom->r1.boardflags_lo & BCM43xx_BFL_BTCOEXIST))
+ return;
+ if (dev->phy.type != BCM43xx_PHYTYPE_B && !dev->phy.gmode)
+ return;
+
+ hf = bcm43xx_hf_read(dev);
+ if (sprom->r1.boardflags_lo & BCM43xx_BFL_BTCMOD)
+ hf |= BCM43xx_HF_BTCOEXALT;
+ else
+ hf |= BCM43xx_HF_BTCOEX;
+ bcm43xx_hf_write(dev, hf);
+ //TODO
+}
+
+static void bcm43xx_bluetooth_coext_disable(struct bcm43xx_wldev *dev)
+{//TODO
+}
+
+static void bcm43xx_imcfglo_timeouts_workaround(struct bcm43xx_wldev *dev)
+{
+#ifdef CONFIG_SSB_DRIVER_PCICORE
+ struct ssb_bus *bus = dev->dev->bus;
+ u32 tmp;
+
+ if (bus->pcicore.dev &&
+ bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
+ bus->pcicore.dev->id.revision <= 5) {
+ /* IMCFGLO timeouts workaround. */
+ tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
+ tmp &= ~SSB_IMCFGLO_REQTO;
+ tmp &= ~SSB_IMCFGLO_SERTO;
+ switch (bus->bustype) {
+ case SSB_BUSTYPE_PCI:
+ case SSB_BUSTYPE_PCMCIA:
+ tmp |= 0x32;
+ break;
+ case SSB_BUSTYPE_SSB:
+ tmp |= 0x53;
+ break;
+ }
+ ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
+ }
+#endif /* CONFIG_SSB_DRIVER_PCICORE */
+}
+
+/* Shutdown a wireless core */
+static void bcm43xx_wireless_core_exit(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED)
+ return;
+
+ bcm43xx_rng_exit(dev->wl);
+ bcm43xx_pio_free(dev);
+ bcm43xx_dma_free(dev);
+ bcm43xx_chip_exit(dev);
+ bcm43xx_radio_turn_off(dev);
+ bcm43xx_switch_analog(dev, 0);
+ if (phy->dyn_tssi_tbl)
+ kfree(phy->tssi2dbm);
+ kfree(phy->lo_control);
+ phy->lo_control = NULL;
+ ssb_device_disable(dev->dev, 0);
+ ssb_bus_may_powerdown(dev->dev->bus);
+ bcm43xx_set_status(dev, BCM43xx_STAT_UNINIT);
+}
+
+/* Initialize a wireless core */
+static int bcm43xx_wireless_core_init(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_wl *wl = dev->wl;
+ struct ssb_bus *bus = dev->dev->bus;
+ struct ssb_sprom *sprom = &bus->sprom;
+ struct bcm43xx_phy *phy = &dev->phy;
+ int err;
+ u32 hf, tmp;
+
+ assert(bcm43xx_status(dev) == BCM43xx_STAT_UNINIT);
+ bcm43xx_set_status(dev, BCM43xx_STAT_INITIALIZING);
+
+ err = ssb_bus_powerup(bus, 0);
+ if (err)
+ goto out;
+ if (!ssb_device_is_enabled(dev->dev)) {
+ tmp = phy->gmode ? BCM43xx_TMSLOW_GMODE : 0;
+ bcm43xx_wireless_core_reset(dev, tmp);
+ }
+
+ if ((phy->type == BCM43xx_PHYTYPE_B) || (phy->type == BCM43xx_PHYTYPE_G)) {
+ phy->lo_control = kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
+ if (!phy->lo_control) {
+ err = -ENOMEM;
+ goto err_busdown;
+ }
+ }
+ setup_struct_wldev_for_init(dev);
+
+ err = bcm43xx_phy_init_tssi2dbm_table(dev);
+ if (err)
+ goto err_kfree_lo_control;
+
+ /* Enable IRQ routing to this device. */
+ ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
+
+ bcm43xx_imcfglo_timeouts_workaround(dev);
+ bcm43xx_bluetooth_coext_disable(dev);
+ bcm43xx_phy_early_init(dev);
+ err = bcm43xx_chip_init(dev);
+ if (err)
+ goto err_kfree_tssitbl;
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_WLCOREREV,
+ dev->dev->id.revision);
+ hf = bcm43xx_hf_read(dev);
+ if (phy->type == BCM43xx_PHYTYPE_G) {
+ hf |= BCM43xx_HF_SYMW;
+ if (phy->rev == 1)
+ hf |= BCM43xx_HF_GDCW;
+ if (sprom->r1.boardflags_lo & BCM43xx_BFL_PACTRL)
+ hf |= BCM43xx_HF_OFDMPABOOST;
+ } else if (phy->type == BCM43xx_PHYTYPE_B) {
+ hf |= BCM43xx_HF_SYMW;
+ if (phy->rev >= 2 && phy->radio_ver == 0x2050)
+ hf &= ~BCM43xx_HF_GDCW;
+ }
+ bcm43xx_hf_write(dev, hf);
+
+ /* Short/Long Retry Limit.
+ * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
+ * the chip-internal counter.
+ */
+ tmp = limit_value(modparam_short_retry, 0, 0xF);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SCRATCH,
+ BCM43xx_SHM_SC_SRLIMIT, tmp);
+ tmp = limit_value(modparam_long_retry, 0, 0xF);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SCRATCH,
+ BCM43xx_SHM_SC_LRLIMIT, tmp);
+
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_SFFBLIM, 3);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_LFFBLIM, 2);
+
+ bcm43xx_rate_memory_init(dev);
+
+ /* Minimum Contention Window */
+ if (phy->type == BCM43xx_PHYTYPE_B) {
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SCRATCH,
+ BCM43xx_SHM_SC_MINCONT, 0x1F);
+ } else {
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SCRATCH,
+ BCM43xx_SHM_SC_MINCONT, 0xF);
+ }
+ /* Maximum Contention Window */
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SCRATCH,
+ BCM43xx_SHM_SC_MAXCONT, 0x3FF);
+
+ bcm43xx_write_mac_bssid_templates(dev);
+
+ do {
+ if (bcm43xx_using_pio(dev))
+ err = bcm43xx_pio_init(dev);
+ else
+ err = bcm43xx_dma_init(dev);
+ } while (err == -EAGAIN);
+ if (err)
+ goto err_chip_exit;
+
+//FIXME
+#if 1
+ bcm43xx_write16(dev, 0x0612, 0x0050);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
+#endif
+
+ bcm43xx_bluetooth_coext_enable(dev);
+
+ ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
+ bcm43xx_macfilter_clear(dev, BCM43xx_MACFILTER_ASSOC);
+ bcm43xx_macfilter_set(dev, BCM43xx_MACFILTER_SELF,
+ (u8 *)(wl->hw->wiphy->perm_addr));
+ bcm43xx_security_init(dev);
+ bcm43xx_measure_channel_change_time(dev);
+ bcm43xx_rng_init(wl);
+
+ bcm43xx_set_status(dev, BCM43xx_STAT_INITIALIZED);
+
+out:
+ return err;
+
+err_chip_exit:
+ bcm43xx_chip_exit(dev);
+err_kfree_tssitbl:
+ if (phy->dyn_tssi_tbl)
+ kfree(phy->tssi2dbm);
+err_kfree_lo_control:
+ kfree(phy->lo_control);
+ phy->lo_control = NULL;
+err_busdown:
+ ssb_bus_may_powerdown(bus);
+ bcm43xx_set_status(dev, BCM43xx_STAT_UNINIT);
+ return err;
+}
+
+static int bcm43xx_add_interface(struct ieee80211_hw *hw,
+ struct ieee80211_if_init_conf *conf)
+{
+ struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+ struct bcm43xx_wldev *dev;
+ unsigned long flags;
+ int err = -EOPNOTSUPP;
+ int did_init = 0;
+
+ mutex_lock(&wl->mutex);
+ if ((conf->type != IEEE80211_IF_TYPE_MNTR) &&
+ wl->operating)
+ goto out_mutex_unlock;
+
+ dprintk(KERN_INFO PFX "Adding Interface type %d\n", conf->type);
+
+ dev = wl->current_dev;
+ if (bcm43xx_status(dev) == BCM43xx_STAT_UNINIT) {
+ err = bcm43xx_wireless_core_init(dev);
+ if (err)
+ goto out_mutex_unlock;
+ did_init = 1;
+ }
+ if (!dev->started) {
+ err = bcm43xx_wireless_core_start(dev);
+ if (err) {
+ if (did_init)
+ bcm43xx_wireless_core_exit(dev);
+ goto out_mutex_unlock;
+ }
+ }
+
+ spin_lock_irqsave(&wl->irq_lock, flags);
+ switch (conf->type) {
+ case IEEE80211_IF_TYPE_MNTR:
+ wl->monitor++;
+ break;
+ default:
+ wl->operating = 1;
+ wl->if_id = conf->if_id;
+ wl->mac_addr = conf->mac_addr;
+ wl->if_type = conf->type;
+ }
+ bcm43xx_adjust_opmode(dev);
+ spin_unlock_irqrestore(&wl->irq_lock, flags);
+
+ err = 0;
+out_mutex_unlock:
+ mutex_unlock(&wl->mutex);
+
+ return err;
+}
+
+static void bcm43xx_remove_interface(struct ieee80211_hw *hw,
+ struct ieee80211_if_init_conf *conf)
+{
+ struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+ struct bcm43xx_wldev *dev;
+ unsigned long flags;
+
+ dprintk(KERN_INFO PFX "Removing Interface type %d\n", conf->type);
+
+ mutex_lock(&wl->mutex);
+ if (conf->type == IEEE80211_IF_TYPE_MNTR) {
+ wl->monitor--;
+ assert(wl->monitor >= 0);
+ } else {
+ assert(wl->operating);
+ wl->operating = 0;
+ }
+
+ dev = wl->current_dev;
+ if (!wl->operating && wl->monitor == 0) {
+ if (dev->started)
+ bcm43xx_wireless_core_stop(dev);
+ bcm43xx_wireless_core_exit(dev);
+ } else {
+ spin_lock_irqsave(&wl->irq_lock, flags);
+ bcm43xx_adjust_opmode(dev);
+ spin_unlock_irqrestore(&wl->irq_lock, flags);
+ }
+ mutex_unlock(&wl->mutex);
+}
+
+
+static const struct ieee80211_ops bcm43xx_hw_ops = {
+ .tx = bcm43xx_tx,
+ .conf_tx = bcm43xx_conf_tx,
+ .add_interface = bcm43xx_add_interface,
+ .remove_interface = bcm43xx_remove_interface,
+ .reset = bcm43xx_dev_reset,
+ .config = bcm43xx_dev_config,
+ .config_interface = bcm43xx_config_interface,
+ .set_multicast_list = bcm43xx_set_multicast_list,
+ .set_key = bcm43xx_dev_set_key,
+ .get_stats = bcm43xx_get_stats,
+ .get_tx_stats = bcm43xx_get_tx_stats,
+};
+
+/* Hard-reset the chip. Do not call this directly.
+ * Use bcm43xx_controller_restart()
+ */
+static void bcm43xx_chip_reset(struct work_struct *work)
+{
+ struct bcm43xx_wldev *dev =
+ container_of(work, struct bcm43xx_wldev, restart_work);
+ struct bcm43xx_wl *wl = dev->wl;
+ int err;
+ int was_started = 0;
+ int was_inited = 0;
+
+ mutex_lock(&wl->mutex);
+
+ /* Bring the device down... */
+ if (dev->started) {
+ was_started = 1;
+ bcm43xx_wireless_core_stop(dev);
+ }
+ if (bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED) {
+ was_inited = 1;
+ bcm43xx_wireless_core_exit(dev);
+ }
+
+ /* ...and up again. */
+ if (was_inited) {
+ err = bcm43xx_wireless_core_init(dev);
+ if (err)
+ goto out;
+ }
+ if (was_started) {
+ assert(was_inited);
+ err = bcm43xx_wireless_core_start(dev);
+ if (err) {
+ bcm43xx_wireless_core_exit(dev);
+ goto out;
+ }
+ }
+out:
+ mutex_unlock(&wl->mutex);
+ if (err)
+ printk(KERN_ERR PFX "Controller restart FAILED\n");
+ else
+ printk(KERN_INFO PFX "Controller restarted\n");
+}
+
+static int bcm43xx_setup_modes(struct bcm43xx_wldev *dev,
+ int have_aphy,
+ int have_bphy,
+ int have_gphy)
+{
+ struct ieee80211_hw *hw = dev->wl->hw;
+ struct ieee80211_hw_mode *mode;
+ struct bcm43xx_phy *phy = &dev->phy;
+ int cnt = 0;
+ int err;
+
+/*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
+have_aphy = 0;
+
+ phy->possible_phymodes = 0;
+ for ( ; 1; cnt++) {
+ if (have_aphy) {
+ assert(cnt < BCM43xx_MAX_PHYHWMODES);
+ mode = &phy->hwmodes[cnt];
+
+ mode->mode = MODE_IEEE80211A;
+ mode->num_channels = bcm43xx_a_chantable_size;
+ mode->channels = bcm43xx_a_chantable;
+ mode->num_rates = bcm43xx_a_ratetable_size;
+ mode->rates = bcm43xx_a_ratetable;
+ err = ieee80211_register_hwmode(hw, mode);
+ if (err)
+ return err;
+
+ phy->possible_phymodes |= BCM43xx_PHYMODE_A;
+ have_aphy = 0;
+ continue;
+ }
+ if (have_bphy) {
+ assert(cnt < BCM43xx_MAX_PHYHWMODES);
+ mode = &phy->hwmodes[cnt];
+
+ mode->mode = MODE_IEEE80211B;
+ mode->num_channels = bcm43xx_bg_chantable_size;
+ mode->channels = bcm43xx_bg_chantable;
+ mode->num_rates = bcm43xx_b_ratetable_size;
+ mode->rates = bcm43xx_b_ratetable;
+ err = ieee80211_register_hwmode(hw, mode);
+ if (err)
+ return err;
+
+ phy->possible_phymodes |= BCM43xx_PHYMODE_B;
+ have_bphy = 0;
+ continue;
+ }
+ if (have_gphy) {
+ assert(cnt < BCM43xx_MAX_PHYHWMODES);
+ mode = &phy->hwmodes[cnt];
+
+ mode->mode = MODE_IEEE80211G;
+ mode->num_channels = bcm43xx_bg_chantable_size;
+ mode->channels = bcm43xx_bg_chantable;
+ mode->num_rates = bcm43xx_g_ratetable_size;
+ mode->rates = bcm43xx_g_ratetable;
+ err = ieee80211_register_hwmode(hw, mode);
+ if (err)
+ return err;
+
+ phy->possible_phymodes |= BCM43xx_PHYMODE_G;
+ have_gphy = 0;
+ continue;
+ }
+ break;
+ }
+
+ return 0;
+}
+
+static void bcm43xx_wireless_core_detach(struct bcm43xx_wldev *dev)
+{
+ /* We release firmware that late to not be required to re-request
+ * is all the time when we reinit the core. */
+ bcm43xx_release_firmware(dev);
+}
+
+static int bcm43xx_wireless_core_attach(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_wl *wl = dev->wl;
+ struct ssb_bus *bus = dev->dev->bus;
+ struct pci_dev *pdev = bus->host_pci;
+ int err;
+ int have_aphy = 0, have_bphy = 0, have_gphy = 0;
+ u32 tmp;
+
+ /* Do NOT do any device initialization here.
+ * Do it in wireless_core_init() instead.
+ * This function is for gathering basic information about the HW, only.
+ * Also some structs may be set up here. But most likely you want to have
+ * that in core_init(), too.
+ */
+
+ /* Get the PHY type. */
+ if (dev->dev->id.revision >= 5) {
+ u32 tmshigh;
+
+ tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
+ have_aphy = !!(tmshigh & BCM43xx_TMSHIGH_APHY);
+ have_gphy = !!(tmshigh & BCM43xx_TMSHIGH_GPHY);
+ if (!have_aphy && !have_gphy)
+ have_bphy = 1;
+ } else if (dev->dev->id.revision == 4) {
+ have_gphy = 1;
+ have_aphy = 1;
+ } else
+ have_bphy = 1;
+
+ /* Initialize LEDs structs. */
+ err = bcm43xx_leds_init(dev);
+ if (err)
+ goto out;
+
+ dev->phy.gmode = (have_gphy || have_bphy);
+ tmp = dev->phy.gmode ? BCM43xx_TMSLOW_GMODE : 0;
+ bcm43xx_wireless_core_reset(dev, tmp);
+
+ err = bcm43xx_phy_versioning(dev);
+ if (err)
+ goto err_leds_exit;
+ /* Check if this device supports multiband. */
+ if (!pdev ||
+ (pdev->device != 0x4312 &&
+ pdev->device != 0x4319 &&
+ pdev->device != 0x4324)) {
+ /* No multiband support. */
+ have_aphy = 0;
+ have_bphy = 0;
+ have_gphy = 0;
+ switch (dev->phy.type) {
+ case BCM43xx_PHYTYPE_A:
+ have_aphy = 1;
+ break;
+ case BCM43xx_PHYTYPE_B:
+ have_bphy = 1;
+ break;
+ case BCM43xx_PHYTYPE_G:
+ have_gphy = 1;
+ break;
+ default:
+ assert(0);
+ }
+ }
+ dev->phy.gmode = (have_gphy || have_bphy);
+ tmp = dev->phy.gmode ? BCM43xx_TMSLOW_GMODE : 0;
+ bcm43xx_wireless_core_reset(dev, tmp);
+
+ err = bcm43xx_validate_chipaccess(dev);
+ if (err)
+ goto err_leds_exit;
+ err = bcm43xx_setup_modes(dev, have_aphy,
+ have_bphy, have_gphy);
+ if (err)
+ goto err_leds_exit;
+
+ /* Now set some default "current_dev" */
+ if (!wl->current_dev)
+ wl->current_dev = dev;
+ INIT_WORK(&dev->restart_work, bcm43xx_chip_reset);
+
+ bcm43xx_radio_turn_off(dev);
+ bcm43xx_switch_analog(dev, 0);
+ ssb_device_disable(dev->dev, 0);
+ ssb_bus_may_powerdown(bus);
+
+out:
+ return err;
+
+err_leds_exit:
+ bcm43xx_leds_exit(dev);
+ return err;
+}
+
+static void bcm43xx_one_core_detach(struct ssb_device *dev)
+{
+ struct bcm43xx_wldev *wldev;
+ struct bcm43xx_wl *wl;
+
+ wldev = ssb_get_drvdata(dev);
+ wl = wldev->wl;
+ bcm43xx_debugfs_remove_device(wldev);
+ bcm43xx_wireless_core_detach(wldev);
+ list_del(&wldev->list);
+ wl->nr_devs--;
+ ssb_set_drvdata(dev, NULL);
+ kfree(wldev);
+}
+
+static int bcm43xx_one_core_attach(struct ssb_device *dev,
+ struct bcm43xx_wl *wl)
+{
+ struct bcm43xx_wldev *wldev;
+ struct pci_dev *pdev;
+ int err = -ENOMEM;
+
+ if (!list_empty(&wl->devlist)) {
+ /* We are not the first core on this chip. */
+ pdev = dev->bus->host_pci;
+ /* Only special chips support more than one wireless
+ * core, although some of the other chips have more than
+ * one wireless core as well. Check for this and
+ * bail out early.
+ */
+ if (!pdev ||
+ ((pdev->device != 0x4321) &&
+ (pdev->device != 0x4313) &&
+ (pdev->device != 0x431A))) {
+ dprintk(KERN_INFO PFX "Ignoring unconnected 802.11 core\n");
+ return -ENODEV;
+ }
+ }
+
+ wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
+ if (!wldev)
+ goto out;
+
+ wldev->dev = dev;
+ wldev->wl = wl;
+ bcm43xx_set_status(wldev, BCM43xx_STAT_UNINIT);
+ wldev->bad_frames_preempt = modparam_bad_frames_preempt;
+ tasklet_init(&wldev->isr_tasklet,
+ (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
+ (unsigned long)wldev);
+ if (modparam_pio)
+ wldev->__using_pio = 1;
+ INIT_LIST_HEAD(&wldev->list);
+
+ err = bcm43xx_wireless_core_attach(wldev);
+ if (err)
+ goto err_kfree_wldev;
+
+ list_add(&wldev->list, &wl->devlist);
+ wl->nr_devs++;
+ ssb_set_drvdata(dev, wldev);
+ bcm43xx_debugfs_add_device(wldev);
+
+out:
+ return err;
+
+err_kfree_wldev:
+ kfree(wldev);
+ return err;
+}
+
+static void bcm43xx_sprom_fixup(struct ssb_bus *bus)
+{
+ /* boardflags workarounds */
+ if (bus->board_vendor == SSB_BOARDVENDOR_DELL &&
+ bus->chip_id == 0x4301 &&
+ bus->board_rev == 0x74)
+ bus->sprom.r1.boardflags_lo |= BCM43xx_BFL_BTCOEXIST;
+ if (bus->board_vendor == PCI_VENDOR_ID_APPLE &&
+ bus->board_type == 0x4E &&
+ bus->board_rev > 0x40)
+ bus->sprom.r1.boardflags_lo |= BCM43xx_BFL_PACTRL;
+
+ /* Convert Antennagain values to Q5.2 */
+ bus->sprom.r1.antenna_gain_a <<= 2;
+ bus->sprom.r1.antenna_gain_bg <<= 2;
+}
+
+static void bcm43xx_wireless_exit(struct ssb_device *dev,
+ struct bcm43xx_wl *wl)
+{
+ struct ieee80211_hw *hw = wl->hw;
+
+ ssb_set_devtypedata(dev, NULL);
+ ieee80211_free_hw(hw);
+}
+
+static int bcm43xx_wireless_init(struct ssb_device *dev)
+{
+ struct ssb_sprom *sprom = &dev->bus->sprom;
+ struct ieee80211_hw *hw;
+ struct bcm43xx_wl *wl;
+ int err = -ENOMEM;
+
+ bcm43xx_sprom_fixup(dev->bus);
+
+ hw = ieee80211_alloc_hw(sizeof(*wl), &bcm43xx_hw_ops);
+ if (!hw) {
+ printk(KERN_ERR PFX "Could not allocate ieee80211 device\n");
+ goto out;
+ }
+
+ /* fill hw info */
+ hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
+ IEEE80211_HW_MONITOR_DURING_OPER |
+ IEEE80211_HW_DEVICE_HIDES_WEP |
+ IEEE80211_HW_WEP_INCLUDE_IV;
+ hw->max_signal = 100;
+ hw->max_rssi = -110;
+ hw->max_noise = -110;
+ hw->queues = 1;
+ SET_IEEE80211_DEV(hw, dev->dev);
+ if (is_valid_ether_addr(sprom->r1.et1mac))
+ SET_IEEE80211_PERM_ADDR(hw, sprom->r1.et1mac);
+ else
+ SET_IEEE80211_PERM_ADDR(hw, sprom->r1.il0mac);
+
+ /* Get and initialize struct bcm43xx_wl */
+ wl = hw_to_bcm43xx_wl(hw);
+ memset(wl, 0, sizeof(*wl));
+ wl->hw = hw;
+ spin_lock_init(&wl->irq_lock);
+ spin_lock_init(&wl->leds_lock);
+ mutex_init(&wl->mutex);
+ INIT_LIST_HEAD(&wl->devlist);
+
+ ssb_set_devtypedata(dev, wl);
+ printk(KERN_INFO PFX "Broadcom %04X WLAN found\n", dev->bus->chip_id);
+ err = 0;
+out:
+ return err;
+}
+
+static int bcm43xx_probe(struct ssb_device *dev,
+ const struct ssb_device_id *id)
+{
+ struct bcm43xx_wl *wl;
+ int err;
+ int first = 0;
+
+ wl = ssb_get_devtypedata(dev);
+ if (!wl) {
+ /* Probing the first core. Must setup common struct bcm43xx_wl */
+ first = 1;
+ err = bcm43xx_wireless_init(dev);
+ if (err)
+ goto out;
+ wl = ssb_get_devtypedata(dev);
+ assert(wl);
+ }
+ err = bcm43xx_one_core_attach(dev, wl);
+ if (err)
+ goto err_wireless_exit;
+
+ if (first) {
+ err = ieee80211_register_hw(wl->hw);
+ if (err)
+ goto err_one_core_detach;
+ }
+
+out:
+ return err;
+
+err_one_core_detach:
+ bcm43xx_one_core_detach(dev);
+err_wireless_exit:
+ if (first)
+ bcm43xx_wireless_exit(dev, wl);
+ return err;
+}
+
+static void bcm43xx_remove(struct ssb_device *dev)
+{
+ struct bcm43xx_wl *wl = ssb_get_devtypedata(dev);
+ struct bcm43xx_wldev *wldev = ssb_get_drvdata(dev);
+
+ assert(wl);
+ if (wl->current_dev == wldev)
+ ieee80211_unregister_hw(wl->hw);
+
+ bcm43xx_one_core_detach(dev);
+
+ if (list_empty(&wl->devlist)) {
+ /* Last core on the chip unregistered.
+ * We can destroy common struct bcm43xx_wl.
+ */
+ bcm43xx_wireless_exit(dev, wl);
+ }
+}
+
+/* Hard-reset the chip.
+ * This can be called from interrupt or process context.
+ * dev->irq_lock must be locked.
+ */
+void bcm43xx_controller_restart(struct bcm43xx_wldev *dev, const char *reason)
+{
+ if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED)
+ return;
+ printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
+ schedule_work(&dev->restart_work);
+}
+
+#ifdef CONFIG_PM
+
+static int bcm43xx_suspend(struct ssb_device *dev, pm_message_t state)
+{
+ struct bcm43xx_wldev *wldev = ssb_get_drvdata(dev);
+ struct bcm43xx_wl *wl = wldev->wl;
+
+ dprintk(KERN_INFO PFX "Suspending...\n");
+
+ mutex_lock(&wl->mutex);
+ wldev->was_started = !!wldev->started;
+ wldev->was_initialized = (bcm43xx_status(wldev) == BCM43xx_STAT_INITIALIZED);
+ if (wldev->started)
+ bcm43xx_wireless_core_stop(wldev);
+ if (bcm43xx_status(wldev) == BCM43xx_STAT_INITIALIZED)
+ bcm43xx_wireless_core_exit(wldev);
+
+ mutex_unlock(&wl->mutex);
+
+ dprintk(KERN_INFO PFX "Device suspended.\n");
+
+ return 0;
+}
+
+static int bcm43xx_resume(struct ssb_device *dev)
+{
+ struct bcm43xx_wldev *wldev = ssb_get_drvdata(dev);
+ int err = 0;
+
+ dprintk(KERN_INFO PFX "Resuming...\n");
+
+ if (wldev->was_initialized) {
+ err = bcm43xx_wireless_core_init(wldev);
+ if (err) {
+ printk(KERN_ERR PFX "Resume failed at core init\n");
+ goto out;
+ }
+ }
+ if (wldev->was_started) {
+ assert(wldev->was_initialized);
+ err = bcm43xx_wireless_core_start(wldev);
+ if (err) {
+ printk(KERN_ERR PFX "Resume failed at core start\n");
+ goto out;
+ }
+ }
+
+ dprintk(KERN_INFO PFX "Device resumed.\n");
+out:
+ return err;
+}
+
+#else /* CONFIG_PM */
+# define bcm43xx_suspend NULL
+# define bcm43xx_resume NULL
+#endif /* CONFIG_PM */
+
+static struct ssb_driver bcm43xx_ssb_driver = {
+ .name = KBUILD_MODNAME,
+ .id_table = bcm43xx_ssb_tbl,
+ .probe = bcm43xx_probe,
+ .remove = bcm43xx_remove,
+ .suspend = bcm43xx_suspend,
+ .resume = bcm43xx_resume,
+};
+
+#ifdef CONFIG_BCM43XX_MAC80211_PCI
+/* The PCI frontend stub */
+static const struct pci_device_id bcm43xx_pci_tbl[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4307) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4311) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
+ { 0 },
+};
+MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
+
+static struct pci_driver bcm43xx_pci_driver = {
+ .name = "bcm43xx-pci",
+ .id_table = bcm43xx_pci_tbl,
+};
+#endif /* CONFIG_BCM43XX_MAC80211_PCI */
+
+static int __init bcm43xx_init(void)
+{
+ int err;
+
+ bcm43xx_debugfs_init();
+#ifdef CONFIG_BCM43XX_MAC80211_PCI
+ err = ssb_pcihost_register(&bcm43xx_pci_driver);
+ if (err)
+ goto err_dfs_exit;
+#endif
+ err = bcm43xx_pcmcia_init();
+ if (err)
+ goto err_pci_exit;
+ err = ssb_driver_register(&bcm43xx_ssb_driver);
+ if (err)
+ goto err_pcmcia_exit;
+
+ return err;
+
+err_pcmcia_exit:
+ bcm43xx_pcmcia_exit();
+err_pci_exit:
+#ifdef CONFIG_BCM43XX_MAC80211_PCI
+ ssb_pcihost_unregister(&bcm43xx_pci_driver);
+#endif
+err_dfs_exit:
+ bcm43xx_debugfs_exit();
+ return err;
+}
+
+static void __exit bcm43xx_exit(void)
+{
+ ssb_driver_unregister(&bcm43xx_ssb_driver);
+ bcm43xx_pcmcia_exit();
+#ifdef CONFIG_BCM43XX_MAC80211_PCI
+ ssb_pcihost_unregister(&bcm43xx_pci_driver);
+#endif
+ bcm43xx_debugfs_exit();
+}
+
+module_init(bcm43xx_init)
+module_exit(bcm43xx_exit)
--- /dev/null
+/*
+
+ Broadcom BCM43xx wireless driver
+
+ Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
+ Stefano Brivio <st3@riseup.net>
+ Michael Buesch <mb@bu3sch.de>
+ Danny van Dyk <kugelfang@gentoo.org>
+ Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+ Some parts of the code in this file are derived from the ipw2200
+ driver Copyright(c) 2003 - 2004 Intel Corporation.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING. If not, write to
+ the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+ Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef BCM43xx_MAIN_H_
+#define BCM43xx_MAIN_H_
+
+#include "bcm43xx.h"
+
+
+#define P4D_BYT3S(magic, nr_bytes) u8 __p4dding##magic[nr_bytes]
+#define P4D_BYTES(line, nr_bytes) P4D_BYT3S(line, nr_bytes)
+/* Magic helper macro to pad structures. Ignore those above. It's magic. */
+#define PAD_BYTES(nr_bytes) P4D_BYTES( __LINE__ , (nr_bytes))
+
+
+/* Lightweight function to convert a frequency (in Mhz) to a channel number. */
+static inline
+u8 bcm43xx_freq_to_channel_a(int freq)
+{
+ return ((freq - 5000) / 5);
+}
+static inline
+u8 bcm43xx_freq_to_channel_bg(int freq)
+{
+ u8 channel;
+
+ if (freq == 2484)
+ channel = 14;
+ else
+ channel = (freq - 2407) / 5;
+
+ return channel;
+}
+static inline
+u8 bcm43xx_freq_to_channel(struct bcm43xx_wldev *dev,
+ int freq)
+{
+ if (dev->phy.type == BCM43xx_PHYTYPE_A)
+ return bcm43xx_freq_to_channel_a(freq);
+ return bcm43xx_freq_to_channel_bg(freq);
+}
+
+/* Lightweight function to convert a channel number to a frequency (in Mhz). */
+static inline
+int bcm43xx_channel_to_freq_a(u8 channel)
+{
+ return (5000 + (5 * channel));
+}
+static inline
+int bcm43xx_channel_to_freq_bg(u8 channel)
+{
+ int freq;
+
+ if (channel == 14)
+ freq = 2484;
+ else
+ freq = 2407 + (5 * channel);
+
+ return freq;
+}
+static inline
+int bcm43xx_channel_to_freq(struct bcm43xx_wldev *dev,
+ u8 channel)
+{
+ if (dev->phy.type == BCM43xx_PHYTYPE_A)
+ return bcm43xx_channel_to_freq_a(channel);
+ return bcm43xx_channel_to_freq_bg(channel);
+}
+
+static inline
+int bcm43xx_is_cck_rate(int rate)
+{
+ return (rate == BCM43xx_CCK_RATE_1MB ||
+ rate == BCM43xx_CCK_RATE_2MB ||
+ rate == BCM43xx_CCK_RATE_5MB ||
+ rate == BCM43xx_CCK_RATE_11MB);
+}
+
+static inline
+int bcm43xx_is_ofdm_rate(int rate)
+{
+ return !bcm43xx_is_cck_rate(rate);
+}
+
+static inline
+int bcm43xx_is_hw_radio_enabled(struct bcm43xx_wldev *dev)
+{
+ /* function to return state of hardware enable of radio
+ * returns 0 if radio disabled, 1 if radio enabled
+ */
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ if (phy->rev >= 3)
+ return ((bcm43xx_read32(dev, BCM43xx_MMIO_RADIO_HWENABLED_HI)
+ & BCM43xx_MMIO_RADIO_HWENABLED_HI_MASK)
+ == 0) ? 1 : 0;
+ else
+ return ((bcm43xx_read16(dev, BCM43xx_MMIO_RADIO_HWENABLED_LO)
+ & BCM43xx_MMIO_RADIO_HWENABLED_LO_MASK)
+ == 0) ? 0 : 1;
+}
+
+void bcm43xx_tsf_read(struct bcm43xx_wldev *dev, u64 *tsf);
+void bcm43xx_tsf_write(struct bcm43xx_wldev *dev, u64 tsf);
+
+u32 bcm43xx_shm_read32(struct bcm43xx_wldev *dev,
+ u16 routing, u16 offset);
+u16 bcm43xx_shm_read16(struct bcm43xx_wldev *dev,
+ u16 routing, u16 offset);
+void bcm43xx_shm_write32(struct bcm43xx_wldev *dev,
+ u16 routing, u16 offset,
+ u32 value);
+void bcm43xx_shm_write16(struct bcm43xx_wldev *dev,
+ u16 routing, u16 offset,
+ u16 value);
+
+u32 bcm43xx_hf_read(struct bcm43xx_wldev *dev);
+void bcm43xx_hf_write(struct bcm43xx_wldev *dev, u32 value);
+
+void bcm43xx_dummy_transmission(struct bcm43xx_wldev *dev);
+
+void bcm43xx_wireless_core_reset(struct bcm43xx_wldev *dev, u32 flags);
+
+void bcm43xx_mac_suspend(struct bcm43xx_wldev *dev);
+void bcm43xx_mac_enable(struct bcm43xx_wldev *dev);
+
+void bcm43xx_controller_restart(struct bcm43xx_wldev *dev, const char *reason);
+
+#endif /* BCM43xx_MAIN_H_ */
--- /dev/null
+/*
+
+ Broadcom BCM43xx wireless driver
+
+ Copyright (c) 2007 Michael Buesch <mb@bu3sch.de>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING. If not, write to
+ the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+ Boston, MA 02110-1301, USA.
+
+*/
+
+#include <linux/ssb/ssb.h>
+
+#include <pcmcia/cs_types.h>
+#include <pcmcia/cs.h>
+#include <pcmcia/cistpl.h>
+#include <pcmcia/ciscode.h>
+#include <pcmcia/ds.h>
+#include <pcmcia/cisreg.h>
+
+
+static /*const*/ struct pcmcia_device_id bcm43xx_pcmcia_tbl[] = {
+ PCMCIA_DEVICE_MANF_CARD(0x2D0, 0x448),
+ PCMCIA_DEVICE_NULL,
+};
+MODULE_DEVICE_TABLE(pcmcia, bcm43xx_pcmcia_tbl);
+
+
+#ifdef CONFIG_PM
+static int bcm43xx_pcmcia_suspend(struct pcmcia_device *dev)
+{
+ //TODO
+ return 0;
+}
+
+static int bcm43xx_pcmcia_resume(struct pcmcia_device *dev)
+{
+ //TODO
+ return 0;
+}
+#else /* CONFIG_PM */
+# define bcm43xx_pcmcia_suspend NULL
+# define bcm43xx_pcmcia_resume NULL
+#endif /* CONFIG_PM */
+
+static void bcm43xx_pcmcia_fill_sprom(struct ssb_sprom *sprom)
+{//TODO
+}
+
+static int __devinit bcm43xx_pcmcia_probe(struct pcmcia_device *dev)
+{
+ struct ssb_bus *ssb;
+ win_req_t win;
+ memreq_t mem;
+ tuple_t tuple;
+ cisparse_t parse;
+ int err = -ENOMEM;
+ int res;
+ unsigned char buf[64];
+
+ ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
+ if (!ssb)
+ goto out;
+
+ err = -ENODEV;
+ tuple.DesiredTuple = CISTPL_CONFIG;
+ tuple.Attributes = 0;
+ tuple.TupleData = buf;
+ tuple.TupleDataMax = sizeof(buf);
+ tuple.TupleOffset = 0;
+
+ res = pcmcia_get_first_tuple(dev, &tuple);
+ if (res != CS_SUCCESS)
+ goto err_kfree_ssb;
+ res = pcmcia_get_tuple_data(dev, &tuple);
+ if (res != CS_SUCCESS)
+ goto err_kfree_ssb;
+ res = pcmcia_parse_tuple(dev, &tuple, &parse);
+ if (res != CS_SUCCESS)
+ goto err_kfree_ssb;
+
+ dev->conf.ConfigBase = parse.config.base;
+ dev->conf.Present = parse.config.rmask[0];
+
+ dev->io.BasePort2 = 0;
+ dev->io.NumPorts2 = 0;
+ dev->io.Attributes2 = 0;
+
+ win.Attributes = WIN_MEMORY_TYPE_CM | WIN_ENABLE | WIN_USE_WAIT;
+ win.Base = 0;
+ win.Size = SSB_CORE_SIZE;
+ win.AccessSpeed = 1000;
+ res = pcmcia_request_window(&dev, &win, &dev->win);
+ if (res != CS_SUCCESS)
+ goto err_kfree_ssb;
+
+ mem.CardOffset = 0;
+ mem.Page = 0;
+ res = pcmcia_map_mem_page(dev->win, &mem);
+ if (res != CS_SUCCESS)
+ goto err_kfree_ssb;
+
+ res = pcmcia_request_configuration(dev, &dev->conf);
+ if (res != CS_SUCCESS)
+ goto err_disable;
+
+ err = ssb_bus_pcmciabus_register(ssb, dev, win.Base,
+ bcm43xx_pcmcia_fill_sprom);
+ dev->priv = ssb;
+
+out:
+ return err;
+err_disable:
+ pcmcia_disable_device(dev);
+err_kfree_ssb:
+ kfree(ssb);
+ return err;
+}
+
+static void __devexit bcm43xx_pcmcia_remove(struct pcmcia_device *dev)
+{
+ struct ssb_bus *ssb = dev->priv;
+
+ ssb_bus_unregister(ssb);
+ pcmcia_release_window(dev->win);
+ pcmcia_disable_device(dev);
+ kfree(ssb);
+ dev->priv = NULL;
+}
+
+static struct pcmcia_driver bcm43xx_pcmcia_driver = {
+ .owner = THIS_MODULE,
+ .drv = {
+ .name = "bcm43xx-pcmcia",
+ },
+ .id_table = bcm43xx_pcmcia_tbl,
+ .probe = bcm43xx_pcmcia_probe,
+ .remove = bcm43xx_pcmcia_remove,
+ .suspend = bcm43xx_pcmcia_suspend,
+ .resume = bcm43xx_pcmcia_resume,
+};
+
+int bcm43xx_pcmcia_init(void)
+{
+ return pcmcia_register_driver(&bcm43xx_pcmcia_driver);
+}
+
+void bcm43xx_pcmcia_exit(void)
+{
+ pcmcia_unregister_driver(&bcm43xx_pcmcia_driver);
+}
--- /dev/null
+#ifndef BCM43xx_PCMCIA_H_
+#define BCM43xx_PCMCIA_H_
+
+#ifdef CONFIG_BCM43XX_MAC80211_PCMCIA
+
+int bcm43xx_pcmcia_init(void);
+void bcm43xx_pcmcia_exit(void);
+
+#else /* CONFIG_BCM43XX_MAC80211_PCMCIA */
+
+static inline
+int bcm43xx_pcmcia_init(void)
+{
+ return 0;
+}
+static inline
+void bcm43xx_pcmcia_exit(void)
+{
+}
+
+#endif /* CONFIG_BCM43XX_MAC80211_PCMCIA */
+#endif /* BCM43xx_PCMCIA_H_ */
--- /dev/null
+/*
+
+ Broadcom BCM43xx wireless driver
+
+ Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
+ Copyright (c) 2005, 2006 Stefano Brivio <st3@riseup.net>
+ Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
+ Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
+ Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING. If not, write to
+ the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+ Boston, MA 02110-1301, USA.
+
+*/
+
+#include <linux/delay.h>
+#include <linux/types.h>
+
+#include "bcm43xx.h"
+#include "bcm43xx_phy.h"
+#include "bcm43xx_main.h"
+#include "bcm43xx_tables.h"
+#include "bcm43xx_power.h"
+#include "bcm43xx_lo.h"
+
+
+static const s8 bcm43xx_tssi2dbm_b_table[] = {
+ 0x4D, 0x4C, 0x4B, 0x4A,
+ 0x4A, 0x49, 0x48, 0x47,
+ 0x47, 0x46, 0x45, 0x45,
+ 0x44, 0x43, 0x42, 0x42,
+ 0x41, 0x40, 0x3F, 0x3E,
+ 0x3D, 0x3C, 0x3B, 0x3A,
+ 0x39, 0x38, 0x37, 0x36,
+ 0x35, 0x34, 0x32, 0x31,
+ 0x30, 0x2F, 0x2D, 0x2C,
+ 0x2B, 0x29, 0x28, 0x26,
+ 0x25, 0x23, 0x21, 0x1F,
+ 0x1D, 0x1A, 0x17, 0x14,
+ 0x10, 0x0C, 0x06, 0x00,
+ -7, -7, -7, -7,
+ -7, -7, -7, -7,
+ -7, -7, -7, -7,
+};
+
+static const s8 bcm43xx_tssi2dbm_g_table[] = {
+ 77, 77, 77, 76,
+ 76, 76, 75, 75,
+ 74, 74, 73, 73,
+ 73, 72, 72, 71,
+ 71, 70, 70, 69,
+ 68, 68, 67, 67,
+ 66, 65, 65, 64,
+ 63, 63, 62, 61,
+ 60, 59, 58, 57,
+ 56, 55, 54, 53,
+ 52, 50, 49, 47,
+ 45, 43, 40, 37,
+ 33, 28, 22, 14,
+ 5, -7, -20, -20,
+ -20, -20, -20, -20,
+ -20, -20, -20, -20,
+};
+
+const u8 bcm43xx_radio_channel_codes_bg[] = {
+ 12, 17, 22, 27,
+ 32, 37, 42, 47,
+ 52, 57, 62, 67,
+ 72, 84,
+};
+
+
+static void bcm43xx_phy_initg(struct bcm43xx_wldev *dev);
+
+/* Reverse the bits of a 4bit value.
+ * Example: 1101 is flipped 1011
+ */
+static u16 flip_4bit(u16 value)
+{
+ u16 flipped = 0x0000;
+
+ assert((value & ~0x000F) == 0x0000);
+
+ flipped |= (value & 0x0001) << 3;
+ flipped |= (value & 0x0002) << 1;
+ flipped |= (value & 0x0004) >> 1;
+ flipped |= (value & 0x0008) >> 3;
+
+ return flipped;
+}
+
+static void generate_rfatt_list(struct bcm43xx_wldev *dev,
+ struct bcm43xx_rfatt_list *list)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ /* APHY.rev < 5 || GPHY.rev < 6 */
+ static const struct bcm43xx_rfatt rfatt_0[] = {
+ { .att = 3, .with_padmix = 0, },
+ { .att = 1, .with_padmix = 0, },
+ { .att = 5, .with_padmix = 0, },
+ { .att = 7, .with_padmix = 0, },
+ { .att = 9, .with_padmix = 0, },
+ { .att = 2, .with_padmix = 0, },
+ { .att = 0, .with_padmix = 0, },
+ { .att = 4, .with_padmix = 0, },
+ { .att = 6, .with_padmix = 0, },
+ { .att = 8, .with_padmix = 0, },
+ { .att = 1, .with_padmix = 1, },
+ { .att = 2, .with_padmix = 1, },
+ { .att = 3, .with_padmix = 1, },
+ { .att = 4, .with_padmix = 1, },
+ };
+ /* Radio.rev == 8 && Radio.version == 0x2050 */
+ static const struct bcm43xx_rfatt rfatt_1[] = {
+ { .att = 2, .with_padmix = 1, },
+ { .att = 4, .with_padmix = 1, },
+ { .att = 6, .with_padmix = 1, },
+ { .att = 8, .with_padmix = 1, },
+ { .att = 10, .with_padmix = 1, },
+ { .att = 12, .with_padmix = 1, },
+ { .att = 14, .with_padmix = 1, },
+ };
+ /* Otherwise */
+ static const struct bcm43xx_rfatt rfatt_2[] = {
+ { .att = 0, .with_padmix = 1, },
+ { .att = 2, .with_padmix = 1, },
+ { .att = 4, .with_padmix = 1, },
+ { .att = 6, .with_padmix = 1, },
+ { .att = 8, .with_padmix = 1, },
+ { .att = 9, .with_padmix = 1, },
+ { .att = 9, .with_padmix = 1, },
+ };
+
+ if ((phy->type == BCM43xx_PHYTYPE_A && phy->rev < 5) ||
+ (phy->type == BCM43xx_PHYTYPE_G && phy->rev < 6)) {
+ /* Software pctl */
+ list->list = rfatt_0;
+ list->len = ARRAY_SIZE(rfatt_0);
+ list->min_val = 0;
+ list->max_val = 9;
+ return;
+ }
+ if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
+ /* Hardware pctl */
+ list->list = rfatt_1;
+ list->len = ARRAY_SIZE(rfatt_1);
+ list->min_val = 2;
+ list->max_val = 14;
+ return;
+ }
+ /* Hardware pctl */
+ list->list = rfatt_2;
+ list->len = ARRAY_SIZE(rfatt_2);
+ list->min_val = 0;
+ list->max_val = 9;
+}
+
+static void generate_bbatt_list(struct bcm43xx_wldev *dev,
+ struct bcm43xx_bbatt_list *list)
+{
+ static const struct bcm43xx_bbatt bbatt_0[] = {
+ { .att = 0, },
+ { .att = 1, },
+ { .att = 2, },
+ { .att = 3, },
+ { .att = 4, },
+ { .att = 5, },
+ { .att = 6, },
+ { .att = 7, },
+ { .att = 8, },
+ };
+
+ list->list = bbatt_0;
+ list->len = ARRAY_SIZE(bbatt_0);
+ list->min_val = 0;
+ list->max_val = 8;
+}
+
+static void bcm43xx_shm_clear_tssi(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ switch (phy->type) {
+ case BCM43xx_PHYTYPE_A:
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0068, 0x7F7F);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x006a, 0x7F7F);
+ break;
+ case BCM43xx_PHYTYPE_B:
+ case BCM43xx_PHYTYPE_G:
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0058, 0x7F7F);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x005a, 0x7F7F);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0070, 0x7F7F);
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0072, 0x7F7F);
+ break;
+ }
+}
+
+void bcm43xx_raw_phy_lock(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ assert(irqs_disabled());
+ if (bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD) == 0) {
+ phy->locked = 0;
+ return;
+ }
+ if (dev->dev->id.revision < 3) {
+ bcm43xx_mac_suspend(dev);
+ spin_lock(&phy->lock);
+ } else {
+ if (!bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
+ bcm43xx_power_saving_ctl_bits(dev, -1, 1);
+ }
+ phy->locked = 1;
+}
+
+void bcm43xx_raw_phy_unlock(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ assert(irqs_disabled());
+ if (dev->dev->id.revision < 3) {
+ if (phy->locked) {
+ spin_unlock(&phy->lock);
+ bcm43xx_mac_enable(dev);
+ }
+ } else {
+ if (!bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
+ bcm43xx_power_saving_ctl_bits(dev, -1, -1);
+ }
+ phy->locked = 0;
+}
+
+/* Different PHYs require different register routing flags.
+ * This adjusts (and does sanity checks on) the routing flags.
+ */
+static inline u16 adjust_phyreg_for_phytype(struct bcm43xx_phy *phy,
+ u16 offset)
+{
+ if (phy->type == BCM43xx_PHYTYPE_A) {
+ /* OFDM registers are base-registers for the A-PHY. */
+ offset &= ~BCM43xx_PHYROUTE_OFDM_GPHY;
+ }
+ if (offset & BCM43xx_PHYROUTE_EXT_GPHY) {
+ /* Ext-G registers are only available on G-PHYs */
+ if (phy->type != BCM43xx_PHYTYPE_G) {
+ dprintk(KERN_ERR PFX "EXT-G PHY access at "
+ "0x%04X on %u type PHY\n",
+ offset, phy->type);
+ }
+ }
+
+ return offset;
+}
+
+u16 bcm43xx_phy_read(struct bcm43xx_wldev *dev, u16 offset)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ offset = adjust_phyreg_for_phytype(phy, offset);
+ bcm43xx_write16(dev, BCM43xx_MMIO_PHY_CONTROL, offset);
+ return bcm43xx_read16(dev, BCM43xx_MMIO_PHY_DATA);
+}
+
+void bcm43xx_phy_write(struct bcm43xx_wldev *dev, u16 offset, u16 val)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ offset = adjust_phyreg_for_phytype(phy, offset);
+ bcm43xx_write16(dev, BCM43xx_MMIO_PHY_CONTROL, offset);
+ mmiowb();
+ bcm43xx_write16(dev, BCM43xx_MMIO_PHY_DATA, val);
+}
+
+/* This func is called "PHY calibrate" in the specs... */
+void bcm43xx_phy_early_init(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+
+ bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD); /* Dummy read. */
+ if (phy->type == BCM43xx_PHYTYPE_B ||
+ phy->type == BCM43xx_PHYTYPE_G) {
+ generate_rfatt_list(dev, &lo->rfatt_list);
+ generate_bbatt_list(dev, &lo->bbatt_list);
+ }
+ if (phy->type == BCM43xx_PHYTYPE_G && phy->rev == 1) {
+ /* Workaround: Temporarly disable gmode through the early init
+ * phase, as the gmode stuff is not needed for phy rev 1 */
+ phy->gmode = 0;
+ bcm43xx_wireless_core_reset(dev, 0);
+ bcm43xx_phy_initg(dev);
+ phy->gmode = 1;
+ bcm43xx_wireless_core_reset(dev, BCM43xx_TMSLOW_GMODE);
+ }
+}
+
+/* GPHY_TSSI_Power_Lookup_Table_Init */
+static void bcm43xx_gphy_tssi_power_lt_init(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ int i;
+ u16 value;
+
+ for (i = 0; i < 32; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x3C20, i, phy->tssi2dbm[i]);
+ for (i = 32; i < 64; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x3C00, i - 32, phy->tssi2dbm[i]);
+ for (i = 0; i < 64; i += 2) {
+ value = (u16)phy->tssi2dbm[i];
+ value |= ((u16)phy->tssi2dbm[i + 1]) << 8;
+ bcm43xx_phy_write(dev, 0x380 + (i / 2), value);
+ }
+}
+
+/* GPHY_Gain_Lookup_Table_Init */
+static void bcm43xx_gphy_gain_lt_init(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+ u16 nr_written = 0;
+ u16 tmp;
+ u8 rf, bb;
+
+ if (!lo->lo_measured) {
+ bcm43xx_phy_write(dev, 0x3FF, 0);
+ return;
+ }
+
+ for (rf = 0; rf < lo->rfatt_list.len; rf++) {
+ for (bb = 0; bb < lo->bbatt_list.len; bb++) {
+ if (nr_written >= 0x40)
+ return;
+ tmp = lo->bbatt_list.list[bb].att;
+ tmp <<= 8;
+ if (phy->radio_rev == 8)
+ tmp |= 0x50;
+ else
+ tmp |= 0x40;
+ tmp |= lo->rfatt_list.list[rf].att;
+ bcm43xx_phy_write(dev, 0x3C0 + nr_written,
+ tmp);
+ nr_written++;
+ }
+ }
+}
+
+/* GPHY_DC_Lookup_Table */
+void bcm43xx_gphy_dc_lt_init(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+ struct bcm43xx_loctl *loctl0;
+ struct bcm43xx_loctl *loctl1;
+ int i;
+ int rf_offset, bb_offset;
+ u16 tmp;
+
+ for (i = 0;
+ i < lo->rfatt_list.len + lo->bbatt_list.len;
+ i += 2) {
+ rf_offset = i / lo->rfatt_list.len;
+ bb_offset = i % lo->rfatt_list.len;
+
+ loctl0 = bcm43xx_get_lo_g_ctl(dev, &lo->rfatt_list.list[rf_offset],
+ &lo->bbatt_list.list[bb_offset]);
+ if (i + 1 < lo->rfatt_list.len * lo->bbatt_list.len) {
+ rf_offset = (i + 1) / lo->rfatt_list.len;
+ bb_offset = (i + 1) % lo->rfatt_list.len;
+
+ loctl1 = bcm43xx_get_lo_g_ctl(dev, &lo->rfatt_list.list[rf_offset],
+ &lo->bbatt_list.list[bb_offset]);
+ } else
+ loctl1 = loctl0;
+
+ tmp = ((u16)loctl0->q & 0xF);
+ tmp |= ((u16)loctl0->i & 0xF) << 4;
+ tmp |= ((u16)loctl1->q & 0xF) << 8;
+ tmp |= ((u16)loctl1->i & 0xF) << 12;//FIXME?
+ bcm43xx_phy_write(dev, 0x3A0 + (i / 2),
+ tmp);
+ }
+}
+
+static void hardware_pctl_init_aphy(struct bcm43xx_wldev *dev)
+{
+ //TODO
+}
+
+static void hardware_pctl_init_gphy(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ bcm43xx_phy_write(dev, 0x0036,
+ (bcm43xx_phy_read(dev, 0x0036) & 0xFFC0)
+ | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
+ bcm43xx_phy_write(dev, 0x0478,
+ (bcm43xx_phy_read(dev, 0x0478) & 0xFF00)
+ | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
+ bcm43xx_gphy_tssi_power_lt_init(dev);
+ bcm43xx_gphy_gain_lt_init(dev);
+ bcm43xx_phy_write(dev, 0x0060,
+ bcm43xx_phy_read(dev, 0x0060) & 0xFFBF);
+ bcm43xx_phy_write(dev, 0x0014, 0x0000);
+
+ assert(phy->rev >= 6);
+ bcm43xx_phy_write(dev, 0x0478,
+ bcm43xx_phy_read(dev, 0x0478)
+ | 0x0800);
+ bcm43xx_phy_write(dev, 0x0478,
+ bcm43xx_phy_read(dev, 0x0478)
+ & 0xFEFF);
+ bcm43xx_phy_write(dev, 0x0801,
+ bcm43xx_phy_read(dev, 0x0801)
+ & 0xFFBF);
+
+ bcm43xx_gphy_dc_lt_init(dev);
+}
+
+/* HardwarePowerControl for A and G PHY.
+ * This does nothing, if the card does not have HW PCTL
+ */
+static void bcm43xx_hardware_pctl_init(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ if (!has_hardware_pctl(phy))
+ return;
+ if (phy->type == BCM43xx_PHYTYPE_A) {
+ hardware_pctl_init_aphy(dev);
+ return;
+ }
+ if (phy->type == BCM43xx_PHYTYPE_G) {
+ hardware_pctl_init_gphy(dev);
+ return;
+ }
+ assert(0);
+}
+
+static void bcm43xx_hardware_pctl_early_init(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ if (!has_hardware_pctl(phy)) {
+ bcm43xx_phy_write(dev, 0x047A, 0xC111);
+ return;
+ }
+
+ bcm43xx_phy_write(dev, 0x0036,
+ bcm43xx_phy_read(dev, 0x0036) & 0xFEFF);
+ bcm43xx_phy_write(dev, 0x002F, 0x0202);
+ bcm43xx_phy_write(dev, 0x047C,
+ bcm43xx_phy_read(dev, 0x047C) | 0x0002);
+ bcm43xx_phy_write(dev, 0x047A,
+ bcm43xx_phy_read(dev, 0x047A) | 0xF000);
+ if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
+ bcm43xx_phy_write(dev, 0x047A,
+ (bcm43xx_phy_read(dev, 0x047A)
+ & 0xFF0F) | 0x0010);
+ bcm43xx_phy_write(dev, 0x005D,
+ bcm43xx_phy_read(dev, 0x005D)
+ | 0x8000);
+ bcm43xx_phy_write(dev, 0x004E,
+ (bcm43xx_phy_read(dev, 0x004E)
+ & 0xFFC0) | 0x0010);
+ bcm43xx_phy_write(dev, 0x002E, 0xC07F);
+ bcm43xx_phy_write(dev, 0x0036,
+ bcm43xx_phy_read(dev, 0x0036)
+ | 0x0400);
+ } else {
+ bcm43xx_phy_write(dev, 0x0036,
+ bcm43xx_phy_read(dev, 0x0036)
+ | 0x0200);
+ bcm43xx_phy_write(dev, 0x0036,
+ bcm43xx_phy_read(dev, 0x0036)
+ | 0x0400);
+ bcm43xx_phy_write(dev, 0x005D,
+ bcm43xx_phy_read(dev, 0x005D)
+ & 0x7FFF);
+ bcm43xx_phy_write(dev, 0x004F,
+ bcm43xx_phy_read(dev, 0x004F)
+ & 0xFFFE);
+ bcm43xx_phy_write(dev, 0x004E,
+ (bcm43xx_phy_read(dev, 0x004E)
+ & 0xFFC0) | 0x0010);
+ bcm43xx_phy_write(dev, 0x002E, 0xC07F);
+ bcm43xx_phy_write(dev, 0x047A,
+ (bcm43xx_phy_read(dev, 0x047A)
+ & 0xFF0F) | 0x0010);
+ }
+}
+
+/* Intialize B/G PHY power control
+ * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
+ */
+static void bcm43xx_phy_init_pctl(struct bcm43xx_wldev *dev)
+{
+ struct ssb_bus *bus = dev->dev->bus;
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ if ((bus->board_vendor == SSB_BOARDVENDOR_BCM) &&
+ (bus->board_type == SSB_BOARD_BU4306))
+ return;
+
+ bcm43xx_phy_write(dev, 0x0028, 0x8018);
+
+ /* This does something with the Analog... */
+ bcm43xx_write16(dev, BCM43xx_MMIO_PHY0,
+ bcm43xx_read16(dev, BCM43xx_MMIO_PHY0)
+ & 0xFFDF);
+
+ if (phy->type == BCM43xx_PHYTYPE_G && !phy->gmode)
+ return;
+ bcm43xx_hardware_pctl_early_init(dev);
+ if (phy->cur_idle_tssi == 0) {
+ if (phy->radio_ver == 0x2050 && phy->analog == 0) {
+ bcm43xx_radio_write16(dev, 0x0076,
+ (bcm43xx_radio_read16(dev, 0x0076)
+ & 0x00F7) | 0x0084);
+ } else {
+ if (phy->radio_rev == 8)
+ bcm43xx_radio_set_txpower_bg(dev, 0xB, 0x1F, 0);
+ else
+ bcm43xx_radio_set_txpower_bg(dev, 0xB, 9, 0);
+ }
+ bcm43xx_dummy_transmission(dev);
+ phy->cur_idle_tssi = bcm43xx_phy_read(dev, BCM43xx_PHY_ITSSI);
+ if (BCM43xx_DEBUG) {
+ /* Current-Idle-TSSI sanity check. */
+ if (abs(phy->cur_idle_tssi - phy->tgt_idle_tssi) >= 20) {
+ dprintk(KERN_ERR PFX "!WARNING! Idle-TSSI phy->cur_idle_tssi "
+ "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
+ "adjustment.\n", phy->cur_idle_tssi, phy->tgt_idle_tssi);
+ phy->cur_idle_tssi = 0;
+ }
+ }
+
+ if (phy->radio_ver == 0x2050 && phy->analog == 0) {
+ bcm43xx_radio_write16(dev, 0x0076,
+ bcm43xx_radio_read16(dev, 0x0076)
+ & 0xFF7B);
+ } else
+ bcm43xx_radio_set_txpower_bg(dev, -1, -1, -1);
+ }
+ bcm43xx_hardware_pctl_init(dev);
+ bcm43xx_shm_clear_tssi(dev);
+}
+
+static void bcm43xx_phy_agcsetup(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 offset = 0x0000;
+
+ if (phy->rev == 1)
+ offset = 0x4C00;
+
+ bcm43xx_ofdmtab_write16(dev, offset, 0, 0x00FE);
+ bcm43xx_ofdmtab_write16(dev, offset, 1, 0x000D);
+ bcm43xx_ofdmtab_write16(dev, offset, 2, 0x0013);
+ bcm43xx_ofdmtab_write16(dev, offset, 3, 0x0019);
+
+ if (phy->rev == 1) {
+ bcm43xx_ofdmtab_write16(dev, 0x1800, 0, 0x2710);
+ bcm43xx_ofdmtab_write16(dev, 0x1801, 0, 0x9B83);
+ bcm43xx_ofdmtab_write16(dev, 0x1802, 0, 0x9B83);
+ bcm43xx_ofdmtab_write16(dev, 0x1803, 0, 0x0F8D);
+ bcm43xx_phy_write(dev, 0x0455, 0x0004);
+ }
+
+ bcm43xx_phy_write(dev, 0x04A5,
+ (bcm43xx_phy_read(dev, 0x04A5)
+ & 0x00FF) | 0x5700);
+ bcm43xx_phy_write(dev, 0x041A,
+ (bcm43xx_phy_read(dev, 0x041A)
+ & 0xFF80) | 0x000F);
+ bcm43xx_phy_write(dev, 0x041A,
+ (bcm43xx_phy_read(dev, 0x041A)
+ & 0xC07F) | 0x2B80);
+ bcm43xx_phy_write(dev, 0x048C,
+ (bcm43xx_phy_read(dev, 0x048C)
+ & 0xF0FF) | 0x0300);
+
+ bcm43xx_radio_write16(dev, 0x007A,
+ bcm43xx_radio_read16(dev, 0x007A)
+ | 0x0008);
+
+ bcm43xx_phy_write(dev, 0x04A0,
+ (bcm43xx_phy_read(dev, 0x04A0)
+ & 0xFFF0) | 0x0008);
+ bcm43xx_phy_write(dev, 0x04A1,
+ (bcm43xx_phy_read(dev, 0x04A1)
+ & 0xF0FF) | 0x0600);
+ bcm43xx_phy_write(dev, 0x04A2,
+ (bcm43xx_phy_read(dev, 0x04A2)
+ & 0xF0FF) | 0x0700);
+ bcm43xx_phy_write(dev, 0x04A0,
+ (bcm43xx_phy_read(dev, 0x04A0)
+ & 0xF0FF) | 0x0100);
+
+ if (phy->rev == 1) {
+ bcm43xx_phy_write(dev, 0x04A2,
+ (bcm43xx_phy_read(dev, 0x04A2)
+ & 0xFFF0) | 0x0007);
+ }
+
+ bcm43xx_phy_write(dev, 0x0488,
+ (bcm43xx_phy_read(dev, 0x0488)
+ & 0xFF00) | 0x001C);
+ bcm43xx_phy_write(dev, 0x0488,
+ (bcm43xx_phy_read(dev, 0x0488)
+ & 0xC0FF) | 0x0200);
+ bcm43xx_phy_write(dev, 0x0496,
+ (bcm43xx_phy_read(dev, 0x0496)
+ & 0xFF00) | 0x001C);
+ bcm43xx_phy_write(dev, 0x0489,
+ (bcm43xx_phy_read(dev, 0x0489)
+ & 0xFF00) | 0x0020);
+ bcm43xx_phy_write(dev, 0x0489,
+ (bcm43xx_phy_read(dev, 0x0489)
+ & 0xC0FF) | 0x0200);
+ bcm43xx_phy_write(dev, 0x0482,
+ (bcm43xx_phy_read(dev, 0x0482)
+ & 0xFF00) | 0x002E);
+ bcm43xx_phy_write(dev, 0x0496,
+ (bcm43xx_phy_read(dev, 0x0496)
+ & 0x00FF) | 0x1A00);
+ bcm43xx_phy_write(dev, 0x0481,
+ (bcm43xx_phy_read(dev, 0x0481)
+ & 0xFF00) | 0x0028);
+ bcm43xx_phy_write(dev, 0x0481,
+ (bcm43xx_phy_read(dev, 0x0481)
+ & 0x00FF) | 0x2C00);
+
+ if (phy->rev == 1) {
+ bcm43xx_phy_write(dev, 0x0430, 0x092B);
+ bcm43xx_phy_write(dev, 0x041B,
+ (bcm43xx_phy_read(dev, 0x041B)
+ & 0xFFE1) | 0x0002);
+ } else {
+ bcm43xx_phy_write(dev, 0x041B,
+ bcm43xx_phy_read(dev, 0x041B)
+ & 0xFFE1);
+ bcm43xx_phy_write(dev, 0x041F, 0x287A);
+ bcm43xx_phy_write(dev, 0x0420,
+ (bcm43xx_phy_read(dev, 0x0420)
+ & 0xFFF0) | 0x0004);
+ }
+
+ if (phy->rev >= 6) {
+ bcm43xx_phy_write(dev, 0x0422, 0x287A);
+ bcm43xx_phy_write(dev, 0x0420,
+ (bcm43xx_phy_read(dev, 0x0420)
+ & 0x0FFF) | 0x3000);
+ }
+
+ bcm43xx_phy_write(dev, 0x04A8,
+ (bcm43xx_phy_read(dev, 0x04A8)
+ & 0x8080) | 0x7874);
+ bcm43xx_phy_write(dev, 0x048E, 0x1C00);
+
+ offset = 0x0800;
+ if (phy->rev == 1) {
+ offset = 0x5400;
+ bcm43xx_phy_write(dev, 0x04AB,
+ (bcm43xx_phy_read(dev, 0x04AB)
+ & 0xF0FF) | 0x0600);
+ bcm43xx_phy_write(dev, 0x048B, 0x005E);
+ bcm43xx_phy_write(dev, 0x048C,
+ (bcm43xx_phy_read(dev, 0x048C)
+ & 0xFF00) | 0x001E);
+ bcm43xx_phy_write(dev, 0x048D, 0x0002);
+ }
+ bcm43xx_ofdmtab_write16(dev, offset, 0, 0x00);
+ bcm43xx_ofdmtab_write16(dev, offset, 1, 0x07);
+ bcm43xx_ofdmtab_write16(dev, offset, 2, 0x10);
+ bcm43xx_ofdmtab_write16(dev, offset, 3, 0x1C);
+
+ if (phy->rev >= 6) {
+ bcm43xx_phy_write(dev, 0x0426,
+ bcm43xx_phy_read(dev, 0x0426)
+ & 0xFFFC);
+ bcm43xx_phy_write(dev, 0x0426,
+ bcm43xx_phy_read(dev, 0x0426)
+ & 0xEFFF);
+ }
+}
+
+static void bcm43xx_phy_setupg(struct bcm43xx_wldev *dev)
+{
+ struct ssb_bus *bus = dev->dev->bus;
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 i;
+
+ assert(phy->type == BCM43xx_PHYTYPE_G);
+ if (phy->rev == 1) {
+ bcm43xx_phy_write(dev, 0x0406, 0x4F19);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
+ (bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS) & 0xFC3F) | 0x0340);
+ bcm43xx_phy_write(dev, 0x042C, 0x005A);
+ bcm43xx_phy_write(dev, 0x0427, 0x001A);
+
+ for (i = 0; i < BCM43xx_TAB_FINEFREQG_SIZE; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x5800, i, bcm43xx_tab_finefreqg[i]);
+ for (i = 0; i < BCM43xx_TAB_NOISEG1_SIZE; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x1800, i, bcm43xx_tab_noiseg1[i]);
+ for (i = 0; i < BCM43xx_TAB_ROTOR_SIZE; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x2000, i, bcm43xx_tab_rotor[i]);
+ } else {
+ /* nrssi values are signed 6-bit values. Not sure why we write 0x7654 here... */
+ bcm43xx_nrssi_hw_write(dev, 0xBA98, (s16)0x7654);
+
+ if (phy->rev == 2) {
+ bcm43xx_phy_write(dev, 0x04C0, 0x1861);
+ bcm43xx_phy_write(dev, 0x04C1, 0x0271);
+ } else if (phy->rev > 2) {
+ bcm43xx_phy_write(dev, 0x04C0, 0x0098);
+ bcm43xx_phy_write(dev, 0x04C1, 0x0070);
+ bcm43xx_phy_write(dev, 0x04C9, 0x0080);
+ }
+ bcm43xx_phy_write(dev, 0x042B, bcm43xx_phy_read(dev, 0x042B) | 0x800);
+
+ for (i = 0; i < 64; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x4000, i, i);
+ for (i = 0; i < BCM43xx_TAB_NOISEG2_SIZE; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x1800, i, bcm43xx_tab_noiseg2[i]);
+ }
+
+ if (phy->rev <= 2)
+ for (i = 0; i < BCM43xx_TAB_NOISESCALEG_SIZE; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x1400, i, bcm43xx_tab_noisescaleg1[i]);
+ else if ((phy->rev >= 7) && (bcm43xx_phy_read(dev, 0x0449) & 0x0200))
+ for (i = 0; i < BCM43xx_TAB_NOISESCALEG_SIZE; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x1400, i, bcm43xx_tab_noisescaleg3[i]);
+ else
+ for (i = 0; i < BCM43xx_TAB_NOISESCALEG_SIZE; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x1400, i, bcm43xx_tab_noisescaleg2[i]);
+
+ if (phy->rev == 2)
+ for (i = 0; i < BCM43xx_TAB_SIGMASQR_SIZE; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x5000, i, bcm43xx_tab_sigmasqr1[i]);
+ else if ((phy->rev > 2) && (phy->rev <= 8))
+ for (i = 0; i < BCM43xx_TAB_SIGMASQR_SIZE; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x5000, i, bcm43xx_tab_sigmasqr2[i]);
+
+ if (phy->rev == 1) {
+ for (i = 0; i < BCM43xx_TAB_RETARD_SIZE; i++)
+ bcm43xx_ofdmtab_write32(dev, 0x2400, i, bcm43xx_tab_retard[i]);
+ for (i = 0; i < 4; i++) {
+ bcm43xx_ofdmtab_write16(dev, 0x5404, i, 0x0020);
+ bcm43xx_ofdmtab_write16(dev, 0x5408, i, 0x0020);
+ bcm43xx_ofdmtab_write16(dev, 0x540C, i, 0x0020);
+ bcm43xx_ofdmtab_write16(dev, 0x5410, i, 0x0020);
+ }
+ bcm43xx_phy_agcsetup(dev);
+
+ if ((bus->board_vendor == SSB_BOARDVENDOR_BCM) &&
+ (bus->board_type == SSB_BOARD_BU4306) &&
+ (bus->board_rev == 0x17))
+ return;
+
+ bcm43xx_ofdmtab_write16(dev, 0x5001, 0, 0x0002);
+ bcm43xx_ofdmtab_write16(dev, 0x5002, 0, 0x0001);
+ } else {
+ for (i = 0; i <= 0x2F; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x1000, i, 0x0820);
+ bcm43xx_phy_agcsetup(dev);
+ bcm43xx_phy_read(dev, 0x0400); /* dummy read */
+ bcm43xx_phy_write(dev, 0x0403, 0x1000);
+ bcm43xx_ofdmtab_write16(dev, 0x3C02, 0, 0x000F);
+ bcm43xx_ofdmtab_write16(dev, 0x3C03, 0, 0x0014);
+
+ if ((bus->board_vendor == SSB_BOARDVENDOR_BCM) &&
+ (bus->board_type == SSB_BOARD_BU4306) &&
+ (bus->board_rev == 0x17))
+ return;
+
+ bcm43xx_ofdmtab_write16(dev, 0x0401, 0, 0x0002);
+ bcm43xx_ofdmtab_write16(dev, 0x0402, 0, 0x0001);
+ }
+}
+
+/* Initialize the noisescaletable for APHY */
+static void bcm43xx_phy_init_noisescaletbl(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ int i;
+
+ for (i = 0; i < 12; i++) {
+ if (phy->rev == 2)
+ bcm43xx_ofdmtab_write16(dev, 0x1400, i, 0x6767);
+ else
+ bcm43xx_ofdmtab_write16(dev, 0x1400, i, 0x2323);
+ }
+ if (phy->rev == 2)
+ bcm43xx_ofdmtab_write16(dev, 0x1400, i, 0x6700);
+ else
+ bcm43xx_ofdmtab_write16(dev, 0x1400, i, 0x2300);
+ for (i = 0; i < 11; i++) {
+ if (phy->rev == 2)
+ bcm43xx_ofdmtab_write16(dev, 0x1400, i, 0x6767);
+ else
+ bcm43xx_ofdmtab_write16(dev, 0x1400, i, 0x2323);
+ }
+ if (phy->rev == 2)
+ bcm43xx_ofdmtab_write16(dev, 0x1400, i, 0x0067);
+ else
+ bcm43xx_ofdmtab_write16(dev, 0x1400, i, 0x0023);
+}
+
+static void bcm43xx_phy_setupa(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 i;
+
+ assert(phy->type == BCM43xx_PHYTYPE_A);
+ switch (phy->rev) {
+ case 2:
+ bcm43xx_phy_write(dev, 0x008E, 0x3800);
+ bcm43xx_phy_write(dev, 0x0035, 0x03FF);
+ bcm43xx_phy_write(dev, 0x0036, 0x0400);
+
+ bcm43xx_ofdmtab_write16(dev, 0x3807, 0, 0x0051);
+
+ bcm43xx_phy_write(dev, 0x001C, 0x0FF9);
+ bcm43xx_phy_write(dev, 0x0020, bcm43xx_phy_read(dev, 0x0020) & 0xFF0F);
+ bcm43xx_ofdmtab_write16(dev, 0x3C0C, 0, 0x07BF);
+ bcm43xx_radio_write16(dev, 0x0002, 0x07BF);
+
+ bcm43xx_phy_write(dev, 0x0024, 0x4680);
+ bcm43xx_phy_write(dev, 0x0020, 0x0003);
+ bcm43xx_phy_write(dev, 0x001D, 0x0F40);
+ bcm43xx_phy_write(dev, 0x001F, 0x1C00);
+
+ bcm43xx_phy_write(dev, 0x002A,
+ (bcm43xx_phy_read(dev, 0x002A)
+ & 0x00FF) | 0x0400);
+ bcm43xx_phy_write(dev, 0x002B,
+ bcm43xx_phy_read(dev, 0x002B)
+ & 0xFBFF);
+ bcm43xx_phy_write(dev, 0x008E, 0x58C1);
+
+ bcm43xx_ofdmtab_write16(dev, 0x0803, 0, 0x000F);
+ bcm43xx_ofdmtab_write16(dev, 0x0804, 0, 0x001F);
+ bcm43xx_ofdmtab_write16(dev, 0x0805, 0, 0x002A);
+ bcm43xx_ofdmtab_write16(dev, 0x0805, 0, 0x0030);
+ bcm43xx_ofdmtab_write16(dev, 0x0807, 0, 0x003A);
+
+ bcm43xx_ofdmtab_write16(dev, 0x0000, 0, 0x0013);
+ bcm43xx_ofdmtab_write16(dev, 0x0000, 1, 0x0013);
+ bcm43xx_ofdmtab_write16(dev, 0x0000, 2, 0x0013);
+ bcm43xx_ofdmtab_write16(dev, 0x0000, 3, 0x0013);
+ bcm43xx_ofdmtab_write16(dev, 0x0000, 4, 0x0015);
+ bcm43xx_ofdmtab_write16(dev, 0x0000, 5, 0x0015);
+ bcm43xx_ofdmtab_write16(dev, 0x0000, 6, 0x0019);
+
+ bcm43xx_ofdmtab_write16(dev, 0x0404, 0, 0x0003);
+ bcm43xx_ofdmtab_write16(dev, 0x0405, 0, 0x0003);
+ bcm43xx_ofdmtab_write16(dev, 0x0406, 0, 0x0007);
+
+ for (i = 0; i < 16; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x4000, i, (0x8 + i) & 0x000F);
+
+ bcm43xx_ofdmtab_write16(dev, 0x3003, 0, 0x1044);
+ bcm43xx_ofdmtab_write16(dev, 0x3004, 0, 0x7201);
+ bcm43xx_ofdmtab_write16(dev, 0x3006, 0, 0x0040);
+ bcm43xx_ofdmtab_write16(dev, 0x3001, 0, (bcm43xx_ofdmtab_read16(dev, 0x3001, 0) & 0x0010) | 0x0008);
+
+ for (i = 0; i < BCM43xx_TAB_FINEFREQA_SIZE; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x5800, i, bcm43xx_tab_finefreqa[i]);
+ for (i = 0; i < BCM43xx_TAB_NOISEA2_SIZE; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x1800, i, bcm43xx_tab_noisea2[i]);
+ for (i = 0; i < BCM43xx_TAB_ROTOR_SIZE; i++)
+ bcm43xx_ofdmtab_write32(dev, 0x2000, i, bcm43xx_tab_rotor[i]);
+ bcm43xx_phy_init_noisescaletbl(dev);
+ for (i = 0; i < BCM43xx_TAB_RETARD_SIZE; i++)
+ bcm43xx_ofdmtab_write32(dev, 0x2400, i, bcm43xx_tab_retard[i]);
+ break;
+ case 3:
+ for (i = 0; i < 64; i++)
+ bcm43xx_ofdmtab_write16(dev, 0x4000, i, i);
+
+ bcm43xx_ofdmtab_write16(dev, 0x3807, 0, 0x0051);
+
+ bcm43xx_phy_write(dev, 0x001C, 0x0FF9);
+ bcm43xx_phy_write(dev, 0x0020,
+ bcm43xx_phy_read(dev, 0x0020) & 0xFF0F);
+ bcm43xx_radio_write16(dev, 0x0002, 0x07BF);
+
+ bcm43xx_phy_write(dev, 0x0024, 0x4680);
+ bcm43xx_phy_write(dev, 0x0020, 0x0003);
+ bcm43xx_phy_write(dev, 0x001D, 0x0F40);
+ bcm43xx_phy_write(dev, 0x001F, 0x1C00);
+ bcm43xx_phy_write(dev, 0x002A,
+ (bcm43xx_phy_read(dev, 0x002A)
+ & 0x00FF) | 0x0400);
+
+ bcm43xx_ofdmtab_write16(dev, 0x3000, 1,
+ (bcm43xx_ofdmtab_read16(dev, 0x3000, 1)
+ & 0x0010) | 0x0008);
+ for (i = 0; i < BCM43xx_TAB_NOISEA3_SIZE; i++) {
+ bcm43xx_ofdmtab_write16(dev, 0x1800, i,
+ bcm43xx_tab_noisea3[i]);
+ }
+ bcm43xx_phy_init_noisescaletbl(dev);
+ for (i = 0; i < BCM43xx_TAB_SIGMASQR_SIZE; i++) {
+ bcm43xx_ofdmtab_write16(dev, 0x5000, i,
+ bcm43xx_tab_sigmasqr1[i]);
+ }
+
+ bcm43xx_phy_write(dev, 0x0003, 0x1808);
+
+ bcm43xx_ofdmtab_write16(dev, 0x0803, 0, 0x000F);
+ bcm43xx_ofdmtab_write16(dev, 0x0804, 0, 0x001F);
+ bcm43xx_ofdmtab_write16(dev, 0x0805, 0, 0x002A);
+ bcm43xx_ofdmtab_write16(dev, 0x0805, 0, 0x0030);
+ bcm43xx_ofdmtab_write16(dev, 0x0807, 0, 0x003A);
+
+ bcm43xx_ofdmtab_write16(dev, 0x0000, 0, 0x0013);
+ bcm43xx_ofdmtab_write16(dev, 0x0001, 0, 0x0013);
+ bcm43xx_ofdmtab_write16(dev, 0x0002, 0, 0x0013);
+ bcm43xx_ofdmtab_write16(dev, 0x0003, 0, 0x0013);
+ bcm43xx_ofdmtab_write16(dev, 0x0004, 0, 0x0015);
+ bcm43xx_ofdmtab_write16(dev, 0x0005, 0, 0x0015);
+ bcm43xx_ofdmtab_write16(dev, 0x0006, 0, 0x0019);
+
+ bcm43xx_ofdmtab_write16(dev, 0x0404, 0, 0x0003);
+ bcm43xx_ofdmtab_write16(dev, 0x0405, 0, 0x0003);
+ bcm43xx_ofdmtab_write16(dev, 0x0406, 0, 0x0007);
+
+ bcm43xx_ofdmtab_write16(dev, 0x3C02, 0, 0x000F);
+ bcm43xx_ofdmtab_write16(dev, 0x3C03, 0, 0x0014);
+ break;
+ default:
+ assert(0);
+ }
+}
+
+/* Initialize APHY. This is also called for the GPHY in some cases. */
+static void bcm43xx_phy_inita(struct bcm43xx_wldev *dev)
+{
+ struct ssb_bus *bus = dev->dev->bus;
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 tval;
+
+ if (phy->type == BCM43xx_PHYTYPE_A) {
+ bcm43xx_phy_setupa(dev);
+ } else {
+ bcm43xx_phy_setupg(dev);
+ if (phy->gmode &&
+ (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_PACTRL))
+ bcm43xx_phy_write(dev, 0x046E, 0x03CF);
+ return;
+ }
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_A_CRS,
+ (bcm43xx_phy_read(dev, BCM43xx_PHY_A_CRS) & 0xF83C) | 0x0340);
+ bcm43xx_phy_write(dev, 0x0034, 0x0001);
+
+ TODO();//TODO: RSSI AGC
+ bcm43xx_phy_write(dev, BCM43xx_PHY_A_CRS,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_A_CRS) | (1 << 14));
+ bcm43xx_radio_init2060(dev);
+
+ if ((bus->board_vendor == SSB_BOARDVENDOR_BCM) &&
+ ((bus->board_type == SSB_BOARD_BU4306) ||
+ (bus->board_type == SSB_BOARD_BU4309))) {
+ if (phy->lofcal == 0xFFFF) {
+ TODO();//TODO: LOF Cal
+ bcm43xx_radio_set_tx_iq(dev);
+ } else
+ bcm43xx_radio_write16(dev, 0x001E, phy->lofcal);
+ }
+
+ bcm43xx_phy_write(dev, 0x007A, 0xF111);
+
+ if (phy->cur_idle_tssi == 0) {
+ bcm43xx_radio_write16(dev, 0x0019, 0x0000);
+ bcm43xx_radio_write16(dev, 0x0017, 0x0020);
+
+ tval = bcm43xx_ofdmtab_read16(dev, 0x3001, 0);
+ if (phy->rev == 1) {
+ bcm43xx_ofdmtab_write16(dev, 0x3001, 0,
+ (bcm43xx_ofdmtab_read16(dev, 0x3001, 0) & 0xFF87)
+ | 0x0058);
+ } else {
+ bcm43xx_ofdmtab_write16(dev, 0x3001, 0,
+ (bcm43xx_ofdmtab_read16(dev, 0x3001, 0) & 0xFFC3)
+ | 0x002C);
+ }
+ bcm43xx_dummy_transmission(dev);
+ phy->cur_idle_tssi = bcm43xx_phy_read(dev, BCM43xx_PHY_A_PCTL);
+ bcm43xx_ofdmtab_write16(dev, 0x3001, 0, tval);
+
+ bcm43xx_radio_set_txpower_a(dev, 0x0018);
+ }
+ bcm43xx_shm_clear_tssi(dev);
+}
+
+static void bcm43xx_phy_initb2(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 offset, val;
+
+ bcm43xx_write16(dev, 0x03EC, 0x3F22);
+ bcm43xx_phy_write(dev, 0x0020, 0x301C);
+ bcm43xx_phy_write(dev, 0x0026, 0x0000);
+ bcm43xx_phy_write(dev, 0x0030, 0x00C6);
+ bcm43xx_phy_write(dev, 0x0088, 0x3E00);
+ val = 0x3C3D;
+ for (offset = 0x0089; offset < 0x00A7; offset++) {
+ bcm43xx_phy_write(dev, offset, val);
+ val -= 0x0202;
+ }
+ bcm43xx_phy_write(dev, 0x03E4, 0x3000);
+ if (phy->channel == 0xFF)
+ bcm43xx_radio_selectchannel(dev, BCM43xx_DEFAULT_CHANNEL_BG, 0);
+ else
+ bcm43xx_radio_selectchannel(dev, phy->channel, 0);
+ if (phy->radio_ver != 0x2050) {
+ bcm43xx_radio_write16(dev, 0x0075, 0x0080);
+ bcm43xx_radio_write16(dev, 0x0079, 0x0081);
+ }
+ bcm43xx_radio_write16(dev, 0x0050, 0x0020);
+ bcm43xx_radio_write16(dev, 0x0050, 0x0023);
+ if (phy->radio_ver == 0x2050) {
+ bcm43xx_radio_write16(dev, 0x0050, 0x0020);
+ bcm43xx_radio_write16(dev, 0x005A, 0x0070);
+ bcm43xx_radio_write16(dev, 0x005B, 0x007B);
+ bcm43xx_radio_write16(dev, 0x005C, 0x00B0);
+ bcm43xx_radio_write16(dev, 0x007A, 0x000F);
+ bcm43xx_phy_write(dev, 0x0038, 0x0677);
+ bcm43xx_radio_init2050(dev);
+ }
+ bcm43xx_phy_write(dev, 0x0014, 0x0080);
+ bcm43xx_phy_write(dev, 0x0032, 0x00CA);
+ bcm43xx_phy_write(dev, 0x0032, 0x00CC);
+ bcm43xx_phy_write(dev, 0x0035, 0x07C2);
+ bcm43xx_lo_b_measure(dev);
+ bcm43xx_phy_write(dev, 0x0026, 0xCC00);
+ if (phy->radio_ver != 0x2050)
+ bcm43xx_phy_write(dev, 0x0026, 0xCE00);
+ bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL_EXT, 0x1000);
+ bcm43xx_phy_write(dev, 0x002A, 0x88A3);
+ if (phy->radio_ver != 0x2050)
+ bcm43xx_phy_write(dev, 0x002A, 0x88C2);
+ bcm43xx_radio_set_txpower_bg(dev, -1, -1, -1);
+ bcm43xx_phy_init_pctl(dev);
+}
+
+static void bcm43xx_phy_initb4(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 offset, val;
+
+ bcm43xx_write16(dev, 0x03EC, 0x3F22);
+ bcm43xx_phy_write(dev, 0x0020, 0x301C);
+ bcm43xx_phy_write(dev, 0x0026, 0x0000);
+ bcm43xx_phy_write(dev, 0x0030, 0x00C6);
+ bcm43xx_phy_write(dev, 0x0088, 0x3E00);
+ val = 0x3C3D;
+ for (offset = 0x0089; offset < 0x00A7; offset++) {
+ bcm43xx_phy_write(dev, offset, val);
+ val -= 0x0202;
+ }
+ bcm43xx_phy_write(dev, 0x03E4, 0x3000);
+ if (phy->channel == 0xFF)
+ bcm43xx_radio_selectchannel(dev, BCM43xx_DEFAULT_CHANNEL_BG, 0);
+ else
+ bcm43xx_radio_selectchannel(dev, phy->channel, 0);
+ if (phy->radio_ver != 0x2050) {
+ bcm43xx_radio_write16(dev, 0x0075, 0x0080);
+ bcm43xx_radio_write16(dev, 0x0079, 0x0081);
+ }
+ bcm43xx_radio_write16(dev, 0x0050, 0x0020);
+ bcm43xx_radio_write16(dev, 0x0050, 0x0023);
+ if (phy->radio_ver == 0x2050) {
+ bcm43xx_radio_write16(dev, 0x0050, 0x0020);
+ bcm43xx_radio_write16(dev, 0x005A, 0x0070);
+ bcm43xx_radio_write16(dev, 0x005B, 0x007B);
+ bcm43xx_radio_write16(dev, 0x005C, 0x00B0);
+ bcm43xx_radio_write16(dev, 0x007A, 0x000F);
+ bcm43xx_phy_write(dev, 0x0038, 0x0677);
+ bcm43xx_radio_init2050(dev);
+ }
+ bcm43xx_phy_write(dev, 0x0014, 0x0080);
+ bcm43xx_phy_write(dev, 0x0032, 0x00CA);
+ if (phy->radio_ver == 0x2050)
+ bcm43xx_phy_write(dev, 0x0032, 0x00E0);
+ bcm43xx_phy_write(dev, 0x0035, 0x07C2);
+
+ bcm43xx_lo_b_measure(dev);
+
+ bcm43xx_phy_write(dev, 0x0026, 0xCC00);
+ if (phy->radio_ver == 0x2050)
+ bcm43xx_phy_write(dev, 0x0026, 0xCE00);
+ bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL_EXT, 0x1100);
+ bcm43xx_phy_write(dev, 0x002A, 0x88A3);
+ if (phy->radio_ver == 0x2050)
+ bcm43xx_phy_write(dev, 0x002A, 0x88C2);
+ bcm43xx_radio_set_txpower_bg(dev, 0xFFFF, 0xFFFF, 0xFFFF);
+ if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_RSSI) {
+ bcm43xx_calc_nrssi_slope(dev);
+ bcm43xx_calc_nrssi_threshold(dev);
+ }
+ bcm43xx_phy_init_pctl(dev);
+}
+
+static void bcm43xx_phy_initb5(struct bcm43xx_wldev *dev)
+{
+ struct ssb_bus *bus = dev->dev->bus;
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 offset, value;
+ u8 old_channel;
+
+ if (phy->analog == 1) {
+ bcm43xx_radio_write16(dev, 0x007A,
+ bcm43xx_radio_read16(dev, 0x007A)
+ | 0x0050);
+ }
+ if ((bus->board_vendor != SSB_BOARDVENDOR_BCM) &&
+ (bus->board_type != SSB_BOARD_BU4306)) {
+ value = 0x2120;
+ for (offset = 0x00A8 ; offset < 0x00C7; offset++) {
+ bcm43xx_phy_write(dev, offset, value);
+ value += 0x202;
+ }
+ }
+ bcm43xx_phy_write(dev, 0x0035,
+ (bcm43xx_phy_read(dev, 0x0035) & 0xF0FF)
+ | 0x0700);
+ if (phy->radio_ver == 0x2050)
+ bcm43xx_phy_write(dev, 0x0038, 0x0667);
+
+ if (phy->gmode || phy->rev >= 2) {
+ if (phy->radio_ver == 0x2050) {
+ bcm43xx_radio_write16(dev, 0x007A,
+ bcm43xx_radio_read16(dev, 0x007A)
+ | 0x0020);
+ bcm43xx_radio_write16(dev, 0x0051,
+ bcm43xx_radio_read16(dev, 0x0051)
+ | 0x0004);
+ }
+ bcm43xx_write16(dev, BCM43xx_MMIO_PHY_RADIO, 0x0000);
+
+ bcm43xx_phy_write(dev, 0x0802, bcm43xx_phy_read(dev, 0x0802) | 0x0100);
+ bcm43xx_phy_write(dev, 0x042B, bcm43xx_phy_read(dev, 0x042B) | 0x2000);
+
+ bcm43xx_phy_write(dev, 0x001C, 0x186A);
+
+ bcm43xx_phy_write(dev, 0x0013, (bcm43xx_phy_read(dev, 0x0013) & 0x00FF) | 0x1900);
+ bcm43xx_phy_write(dev, 0x0035, (bcm43xx_phy_read(dev, 0x0035) & 0xFFC0) | 0x0064);
+ bcm43xx_phy_write(dev, 0x005D, (bcm43xx_phy_read(dev, 0x005D) & 0xFF80) | 0x000A);
+ }
+
+ if (dev->bad_frames_preempt) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RADIO_BITFIELD,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_RADIO_BITFIELD) | (1 << 11));
+ }
+
+ if (phy->analog == 1) {
+ bcm43xx_phy_write(dev, 0x0026, 0xCE00);
+ bcm43xx_phy_write(dev, 0x0021, 0x3763);
+ bcm43xx_phy_write(dev, 0x0022, 0x1BC3);
+ bcm43xx_phy_write(dev, 0x0023, 0x06F9);
+ bcm43xx_phy_write(dev, 0x0024, 0x037E);
+ } else
+ bcm43xx_phy_write(dev, 0x0026, 0xCC00);
+ bcm43xx_phy_write(dev, 0x0030, 0x00C6);
+ bcm43xx_write16(dev, 0x03EC, 0x3F22);
+
+ if (phy->analog == 1)
+ bcm43xx_phy_write(dev, 0x0020, 0x3E1C);
+ else
+ bcm43xx_phy_write(dev, 0x0020, 0x301C);
+
+ if (phy->analog == 0)
+ bcm43xx_write16(dev, 0x03E4, 0x3000);
+
+ old_channel = phy->channel;
+ /* Force to channel 7, even if not supported. */
+ bcm43xx_radio_selectchannel(dev, 7, 0);
+
+ if (phy->radio_ver != 0x2050) {
+ bcm43xx_radio_write16(dev, 0x0075, 0x0080);
+ bcm43xx_radio_write16(dev, 0x0079, 0x0081);
+ }
+
+ bcm43xx_radio_write16(dev, 0x0050, 0x0020);
+ bcm43xx_radio_write16(dev, 0x0050, 0x0023);
+
+ if (phy->radio_ver == 0x2050) {
+ bcm43xx_radio_write16(dev, 0x0050, 0x0020);
+ bcm43xx_radio_write16(dev, 0x005A, 0x0070);
+ }
+
+ bcm43xx_radio_write16(dev, 0x005B, 0x007B);
+ bcm43xx_radio_write16(dev, 0x005C, 0x00B0);
+
+ bcm43xx_radio_write16(dev, 0x007A, bcm43xx_radio_read16(dev, 0x007A) | 0x0007);
+
+ bcm43xx_radio_selectchannel(dev, old_channel, 0);
+
+ bcm43xx_phy_write(dev, 0x0014, 0x0080);
+ bcm43xx_phy_write(dev, 0x0032, 0x00CA);
+ bcm43xx_phy_write(dev, 0x002A, 0x88A3);
+
+ bcm43xx_radio_set_txpower_bg(dev, -1, -1, -1);
+
+ if (phy->radio_ver == 0x2050)
+ bcm43xx_radio_write16(dev, 0x005D, 0x000D);
+
+ bcm43xx_write16(dev, 0x03E4, (bcm43xx_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
+}
+
+static void bcm43xx_phy_initb6(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 offset, val;
+ u8 old_channel;
+
+ bcm43xx_phy_write(dev, 0x003E, 0x817A);
+ bcm43xx_radio_write16(dev, 0x007A,
+ (bcm43xx_radio_read16(dev, 0x007A) | 0x0058));
+ if (phy->radio_rev == 4 || phy->radio_rev == 5) {
+ bcm43xx_radio_write16(dev, 0x51, 0x37);
+ bcm43xx_radio_write16(dev, 0x52, 0x70);
+ bcm43xx_radio_write16(dev, 0x53, 0xB3);
+ bcm43xx_radio_write16(dev, 0x54, 0x9B);
+ bcm43xx_radio_write16(dev, 0x5A, 0x88);
+ bcm43xx_radio_write16(dev, 0x5B, 0x88);
+ bcm43xx_radio_write16(dev, 0x5D, 0x88);
+ bcm43xx_radio_write16(dev, 0x5E, 0x88);
+ bcm43xx_radio_write16(dev, 0x7D, 0x88);
+ bcm43xx_hf_write(dev, bcm43xx_hf_read(dev)
+ | BCM43xx_HF_TSSIRPSMW);
+ }
+ assert(phy->radio_rev != 6 && phy->radio_rev != 7); /* We had code for these revs here...*/
+ if (phy->radio_rev == 8) {
+ bcm43xx_radio_write16(dev, 0x51, 0);
+ bcm43xx_radio_write16(dev, 0x52, 0x40);
+ bcm43xx_radio_write16(dev, 0x53, 0xB7);
+ bcm43xx_radio_write16(dev, 0x54, 0x98);
+ bcm43xx_radio_write16(dev, 0x5A, 0x88);
+ bcm43xx_radio_write16(dev, 0x5B, 0x6B);
+ bcm43xx_radio_write16(dev, 0x5C, 0x0F);
+ if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_ALTIQ) {
+ bcm43xx_radio_write16(dev, 0x5D, 0xFA);
+ bcm43xx_radio_write16(dev, 0x5E, 0xD8);
+ } else {
+ bcm43xx_radio_write16(dev, 0x5D, 0xF5);
+ bcm43xx_radio_write16(dev, 0x5E, 0xB8);
+ }
+ bcm43xx_radio_write16(dev, 0x0073, 0x0003);
+ bcm43xx_radio_write16(dev, 0x007D, 0x00A8);
+ bcm43xx_radio_write16(dev, 0x007C, 0x0001);
+ bcm43xx_radio_write16(dev, 0x007E, 0x0008);
+ }
+ val = 0x1E1F;
+ for (offset = 0x0088; offset < 0x0098; offset++) {
+ bcm43xx_phy_write(dev, offset, val);
+ val -= 0x0202;
+ }
+ val = 0x3E3F;
+ for (offset = 0x0098; offset < 0x00A8; offset++) {
+ bcm43xx_phy_write(dev, offset, val);
+ val -= 0x0202;
+ }
+ val = 0x2120;
+ for (offset = 0x00A8; offset < 0x00C8; offset++) {
+ bcm43xx_phy_write(dev, offset, (val & 0x3F3F));
+ val += 0x0202;
+ }
+ if (phy->type == BCM43xx_PHYTYPE_G) {
+ bcm43xx_radio_write16(dev, 0x007A,
+ bcm43xx_radio_read16(dev, 0x007A) | 0x0020);
+ bcm43xx_radio_write16(dev, 0x0051,
+ bcm43xx_radio_read16(dev, 0x0051) | 0x0004);
+ bcm43xx_phy_write(dev, 0x0802,
+ bcm43xx_phy_read(dev, 0x0802) | 0x0100);
+ bcm43xx_phy_write(dev, 0x042B,
+ bcm43xx_phy_read(dev, 0x042B) | 0x2000);
+ bcm43xx_phy_write(dev, 0x5B, 0);
+ bcm43xx_phy_write(dev, 0x5C, 0);
+ }
+
+ old_channel = phy->channel;
+ if (old_channel >= 8)
+ bcm43xx_radio_selectchannel(dev, 1, 0);
+ else
+ bcm43xx_radio_selectchannel(dev, 13, 0);
+
+ bcm43xx_radio_write16(dev, 0x0050, 0x0020);
+ bcm43xx_radio_write16(dev, 0x0050, 0x0023);
+ udelay(40);
+ if (phy->radio_rev < 6 || phy->radio_rev == 8) {
+ bcm43xx_radio_write16(dev, 0x7C,
+ (bcm43xx_radio_read16(dev, 0x7C)
+ | 0x0002));
+ bcm43xx_radio_write16(dev, 0x50, 0x20);
+ }
+ if (phy->radio_rev <= 2) {
+ bcm43xx_radio_write16(dev, 0x7C, 0x20);
+ bcm43xx_radio_write16(dev, 0x5A, 0x70);
+ bcm43xx_radio_write16(dev, 0x5B, 0x7B);
+ bcm43xx_radio_write16(dev, 0x5C, 0xB0);
+ }
+ bcm43xx_radio_write16(dev, 0x007A,
+ (bcm43xx_radio_read16(dev, 0x007A) & 0x00F8) | 0x0007);
+
+ bcm43xx_radio_selectchannel(dev, old_channel, 0);
+
+ bcm43xx_phy_write(dev, 0x0014, 0x0200);
+ if (phy->radio_rev >= 6)
+ bcm43xx_phy_write(dev, 0x2A, 0x88C2);
+ else
+ bcm43xx_phy_write(dev, 0x2A, 0x8AC0);
+ bcm43xx_phy_write(dev, 0x0038, 0x0668);
+ bcm43xx_radio_set_txpower_bg(dev, -1, -1, -1);
+ if (phy->radio_rev <= 5) {
+ bcm43xx_phy_write(dev, 0x5D,
+ (bcm43xx_phy_read(dev, 0x5D)
+ & 0xFF80) | 0x0003);
+ }
+ if (phy->radio_rev <= 2)
+ bcm43xx_radio_write16(dev, 0x005D, 0x000D);
+
+ if (phy->analog == 4) {
+ bcm43xx_write16(dev, 0x3E4, 9);
+ bcm43xx_phy_write(dev, 0x61,
+ bcm43xx_phy_read(dev, 0x61)
+ & 0x0FFF);
+ } else {
+ bcm43xx_phy_write(dev, 0x0002,
+ (bcm43xx_phy_read(dev, 0x0002) & 0xFFC0)
+ | 0x0004);
+ }
+ if (phy->type == BCM43xx_PHYTYPE_B) {
+ bcm43xx_write16(dev, 0x03E6, 0x8140);
+ bcm43xx_phy_write(dev, 0x0016, 0x0410);
+ bcm43xx_phy_write(dev, 0x0017, 0x0820);
+ bcm43xx_phy_write(dev, 0x0062, 0x0007);
+ bcm43xx_radio_init2050(dev);
+ bcm43xx_lo_g_measure(dev);
+ if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_RSSI) {
+ bcm43xx_calc_nrssi_slope(dev);
+ bcm43xx_calc_nrssi_threshold(dev);
+ }
+ bcm43xx_phy_init_pctl(dev);
+ } else if (phy->type == BCM43xx_PHYTYPE_G)
+ bcm43xx_write16(dev, 0x03E6, 0x0);
+}
+
+static void bcm43xx_calc_loopback_gain(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 backup_phy[16] = {0};
+ u16 backup_radio[3];
+ u16 backup_bband;
+ u16 i, j, loop_i_max;
+ u16 trsw_rx;
+ u16 loop1_outer_done, loop1_inner_done;
+
+ backup_phy[0] = bcm43xx_phy_read(dev, BCM43xx_PHY_CRS0);
+ backup_phy[1] = bcm43xx_phy_read(dev, BCM43xx_PHY_CCKBBANDCFG);
+ backup_phy[2] = bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER);
+ backup_phy[3] = bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL);
+ if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
+ backup_phy[4] = bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVER);
+ backup_phy[5] = bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVERVAL);
+ }
+ backup_phy[6] = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x5A));
+ backup_phy[7] = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x59));
+ backup_phy[8] = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x58));
+ backup_phy[9] = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x0A));
+ backup_phy[10] = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x03));
+ backup_phy[11] = bcm43xx_phy_read(dev, BCM43xx_PHY_LO_MASK);
+ backup_phy[12] = bcm43xx_phy_read(dev, BCM43xx_PHY_LO_CTL);
+ backup_phy[13] = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x2B));
+ backup_phy[14] = bcm43xx_phy_read(dev, BCM43xx_PHY_PGACTL);
+ backup_phy[15] = bcm43xx_phy_read(dev, BCM43xx_PHY_LO_LEAKAGE);
+ backup_bband = phy->bbatt;
+ backup_radio[0] = bcm43xx_radio_read16(dev, 0x52);
+ backup_radio[1] = bcm43xx_radio_read16(dev, 0x43);
+ backup_radio[2] = bcm43xx_radio_read16(dev, 0x7A);
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_CRS0,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_CRS0) & 0x3FFF);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_CCKBBANDCFG,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_CCKBBANDCFG) | 0x8000);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER) | 0x0002);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL) & 0xFFFD);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER) | 0x0001);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL) & 0xFFFE);
+ if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVER) | 0x0001);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVERVAL) & 0xFFFE);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVER) | 0x0002);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVERVAL) & 0xFFFD);
+ }
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER) | 0x000C);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL) | 0x000C);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER) | 0x0030);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ (bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL)
+ & 0xFFCF) | 0x10);
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x5A), 0x0780);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x59), 0xC810);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), 0x000D);
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x0A),
+ bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x0A)) | 0x2000);
+ if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVER) | 0x0004);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVERVAL) & 0xFFFB);
+ }
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x03),
+ (bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x03))
+ & 0xFF9F) | 0x40);
+
+ if (phy->radio_rev == 8) {
+ bcm43xx_radio_write16(dev, 0x43, 0x000F);
+ } else {
+ bcm43xx_radio_write16(dev, 0x52, 0);
+ bcm43xx_radio_write16(dev, 0x43,
+ (bcm43xx_radio_read16(dev, 0x43)
+ & 0xFFF0) | 0x9);
+ }
+ bcm43xx_phy_set_baseband_attenuation(dev, 11);
+
+ if (phy->rev >= 3)
+ bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, 0xC020);
+ else
+ bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, 0x8020);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_LO_CTL, 0);
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2B),
+ (bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x2B))
+ & 0xFFC0) | 0x01);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2B),
+ (bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x2B))
+ & 0xC0FF) | 0x800);
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER) | 0x0100);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL) & 0xCFFF);
+
+ if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_EXTLNA) {
+ if (phy->rev >= 7) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER)
+ | 0x0800);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL)
+ | 0x8000);
+ }
+ }
+ bcm43xx_radio_write16(dev, 0x7A,
+ bcm43xx_radio_read16(dev, 0x7A)
+ & 0x00F7);
+
+ j = 0;
+ loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
+ for (i = 0; i < loop_i_max; i++) {
+ for (j = 0; j < 16; j++) {
+ bcm43xx_radio_write16(dev, 0x43, i);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ (bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL)
+ & 0xF0FF) | (j << 8));
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL,
+ (bcm43xx_phy_read(dev, BCM43xx_PHY_PGACTL)
+ & 0x0FFF) | 0xA000);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_PGACTL)
+ | 0xF000);
+ udelay(20);
+ if (bcm43xx_phy_read(dev, BCM43xx_PHY_LO_LEAKAGE) >= 0xDFC)
+ goto exit_loop1;
+ }
+ }
+exit_loop1:
+ loop1_outer_done = i;
+ loop1_inner_done = j;
+ if (j >= 8) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL)
+ | 0x30);
+ trsw_rx = 0x1B;
+ for (j = j - 8; j < 16; j++) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ (bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL)
+ & 0xF0FF) | (j << 8));
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL,
+ (bcm43xx_phy_read(dev, BCM43xx_PHY_PGACTL)
+ & 0x0FFF) | 0xA000);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_PGACTL)
+ | 0xF000);
+ udelay(20);
+ trsw_rx -= 3;
+ if (bcm43xx_phy_read(dev, BCM43xx_PHY_LO_LEAKAGE) >= 0xDFC)
+ goto exit_loop2;
+ }
+ } else
+ trsw_rx = 0x18;
+exit_loop2:
+
+ if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER, backup_phy[4]);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL, backup_phy[5]);
+ }
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x5A), backup_phy[6]);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x59), backup_phy[7]);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), backup_phy[8]);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x0A), backup_phy[9]);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x03), backup_phy[10]);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, backup_phy[11]);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_LO_CTL, backup_phy[12]);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2B), backup_phy[13]);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, backup_phy[14]);
+
+ bcm43xx_phy_set_baseband_attenuation(dev, backup_bband);
+
+ bcm43xx_radio_write16(dev, 0x52, backup_radio[0]);
+ bcm43xx_radio_write16(dev, 0x43, backup_radio[1]);
+ bcm43xx_radio_write16(dev, 0x7A, backup_radio[2]);
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, backup_phy[2] | 0x0003);
+ udelay(10);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, backup_phy[2]);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, backup_phy[3]);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_CRS0, backup_phy[0]);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_CCKBBANDCFG, backup_phy[1]);
+
+ phy->max_lb_gain = ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
+ phy->trsw_rx_gain = trsw_rx * 2;
+}
+
+static void bcm43xx_phy_initg(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 tmp;
+
+ if (phy->rev == 1)
+ bcm43xx_phy_initb5(dev);
+ else
+ bcm43xx_phy_initb6(dev);
+
+ if (phy->rev >= 2 || phy->gmode)
+ bcm43xx_phy_inita(dev);
+
+ if (phy->rev >= 2) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER, 0);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL, 0);
+ }
+ if (phy->rev == 2) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, 0);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xC0);
+ }
+ if (phy->rev > 5) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, 0x400);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xC0);
+ }
+ if (phy->gmode || phy->rev >= 2) {
+ tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_VERSION_OFDM);
+ tmp &= BCM43xx_PHYVER_VERSION;
+ if (tmp == 3 || tmp == 5) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM(0xC2), 0x1816);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM(0xC3), 0x8006);
+ }
+ if (tmp == 5) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM(0xCC),
+ (bcm43xx_phy_read(dev, BCM43xx_PHY_OFDM(0xCC))
+ & 0x00FF) | 0x1F00);
+ }
+ }
+ if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
+ bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM(0x7E), 0x78);
+ if (phy->radio_rev == 8) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_EXTG(0x01),
+ bcm43xx_phy_read(dev, BCM43xx_PHY_EXTG(0x01))
+ | 0x80);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM(0x3E),
+ bcm43xx_phy_read(dev, BCM43xx_PHY_OFDM(0x3E))
+ | 0x4);
+ }
+ if (has_loopback_gain(phy))
+ bcm43xx_calc_loopback_gain(dev);
+
+ if (phy->radio_rev != 8) {
+ if (phy->initval == 0xFFFF)
+ phy->initval = bcm43xx_radio_init2050(dev);
+ else
+ bcm43xx_radio_write16(dev, 0x0078, phy->initval);
+ }
+ if (phy->lo_control->tx_bias == 0xFF) {
+ bcm43xx_lo_g_measure(dev);
+ } else {
+ if (has_tx_magnification(phy)) {
+ bcm43xx_radio_write16(dev, 0x52,
+ (bcm43xx_radio_read16(dev, 0x52) & 0xFF00) |
+ phy->lo_control->tx_bias |
+ phy->lo_control->tx_magn);
+ } else {
+ bcm43xx_radio_write16(dev, 0x52,
+ (bcm43xx_radio_read16(dev, 0x52) & 0xFFF0) |
+ phy->lo_control->tx_bias);
+ }
+ if (phy->rev >= 6) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x36),
+ (bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x36))
+ & 0x0FFF) | (phy->lo_control->tx_bias << 12));
+ }
+ if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_PACTRL)
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2E), 0x8075);
+ else
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2E), 0x807F);
+ if (phy->rev < 2)
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2F), 0x101);
+ else
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2F), 0x202);
+ }
+ if (phy->gmode || phy->rev >= 2) {
+ bcm43xx_lo_g_adjust(dev);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, 0x8078);
+ }
+
+ if (!(dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_RSSI)) {
+ /* The specs state to update the NRSSI LT with
+ * the value 0x7FFFFFFF here. I think that is some weird
+ * compiler optimization in the original driver.
+ * Essentially, what we do here is resetting all NRSSI LT
+ * entries to -32 (see the limit_value() in nrssi_hw_update())
+ */
+ bcm43xx_nrssi_hw_update(dev, 0xFFFF);//FIXME?
+ bcm43xx_calc_nrssi_threshold(dev);
+ } else if (phy->gmode || phy->rev >= 2) {
+ if (phy->nrssi[0] == -1000) {
+ assert(phy->nrssi[1] == -1000);
+ bcm43xx_calc_nrssi_slope(dev);
+ } else
+ bcm43xx_calc_nrssi_threshold(dev);
+ }
+ if (phy->radio_rev == 8)
+ bcm43xx_phy_write(dev, BCM43xx_PHY_EXTG(0x05), 0x3230);
+ bcm43xx_phy_init_pctl(dev);
+ /* FIXME: The spec says in the following if, the 0 should be replaced
+ 'if OFDM may not be used in the current locale'
+ but OFDM is legal everywhere */
+ if ((dev->dev->bus->chip_id == 0x4306 && dev->dev->bus->chip_package == 2) || 0) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_CRS0,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_CRS0)
+ & 0xBFFF);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM(0xC3),
+ bcm43xx_phy_read(dev, BCM43xx_PHY_OFDM(0xC3))
+ & 0x7FFF);
+ }
+}
+
+/* Set the baseband attenuation value on chip. */
+void bcm43xx_phy_set_baseband_attenuation(struct bcm43xx_wldev *dev,
+ u16 baseband_attenuation)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 value;
+
+ if (phy->analog == 0) {
+ value = (bcm43xx_read16(dev, 0x03E6) & 0xFFF0);
+ value |= (baseband_attenuation & 0x000F);
+ bcm43xx_write16(dev, 0x03E6, value);
+ return;
+ }
+
+ if (phy->analog > 1) {
+ value = bcm43xx_phy_read(dev, 0x0060) & ~0x003C;
+ value |= (baseband_attenuation << 2) & 0x003C;
+ } else {
+ value = bcm43xx_phy_read(dev, 0x0060) & ~0x0078;
+ value |= (baseband_attenuation << 3) & 0x0078;
+ }
+ bcm43xx_phy_write(dev, 0x0060, value);
+}
+
+/* http://bcm-specs.sipsolutions.net/EstimatePowerOut
+ * This function converts a TSSI value to dBm in Q5.2
+ */
+static s8 bcm43xx_phy_estimate_power_out(struct bcm43xx_wldev *dev, s8 tssi)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ s8 dbm = 0;
+ s32 tmp;
+
+ tmp = (phy->tgt_idle_tssi - phy->cur_idle_tssi + tssi);
+
+ switch (phy->type) {
+ case BCM43xx_PHYTYPE_A:
+ tmp += 0x80;
+ tmp = limit_value(tmp, 0x00, 0xFF);
+ dbm = phy->tssi2dbm[tmp];
+ TODO(); //TODO: There's a FIXME on the specs
+ break;
+ case BCM43xx_PHYTYPE_B:
+ case BCM43xx_PHYTYPE_G:
+ tmp = limit_value(tmp, 0x00, 0x3F);
+ dbm = phy->tssi2dbm[tmp];
+ break;
+ default:
+ assert(0);
+ }
+
+ return dbm;
+}
+
+static void put_attenuation_into_ranges(struct bcm43xx_wldev *dev,
+ int *_rfatt, int *_bbatt)
+{
+ int rfatt = *_rfatt;
+ int bbatt = *_bbatt;
+
+ /* Get baseband and radio attenuation values into their permitted ranges.
+ * Radio attenuation affects power level 4 times as much as baseband. */
+
+ /* Range constants */
+ const int rf_min = 0;
+ const int rf_max = 9;
+ const int bb_min = 0;
+ const int bb_max = 11;
+
+ while (1) {
+ if (rfatt > rf_max &&
+ bbatt > bb_max - 4)
+ break; /* Can not get it into ranges */
+ if (rfatt < rf_min &&
+ bbatt < bb_min + 4)
+ break; /* Can not get it into ranges */
+ if (bbatt > bb_max &&
+ rfatt > rf_max - 1)
+ break; /* Can not get it into ranges */
+ if (bbatt < bb_min &&
+ rfatt < rf_min + 1)
+ break; /* Can not get it into ranges */
+
+ if (bbatt > bb_max) {
+ bbatt -= 4;
+ rfatt += 1;
+ continue;
+ }
+ if (bbatt < bb_min) {
+ bbatt += 4;
+ rfatt -= 1;
+ continue;
+ }
+ if (rfatt > rf_max) {
+ rfatt -= 1;
+ bbatt += 4;
+ continue;
+ }
+ if (rfatt < rf_min) {
+ rfatt += 1;
+ bbatt -= 4;
+ continue;
+ }
+ break;
+ }
+
+ *_rfatt = limit_value(rfatt, rf_min, rf_max);
+ *_bbatt = limit_value(bbatt, bb_min, bb_max);
+}
+
+/* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */
+void bcm43xx_phy_xmitpower(struct bcm43xx_wldev *dev)
+{
+ struct ssb_bus *bus = dev->dev->bus;
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ if (phy->cur_idle_tssi == 0)
+ return;
+ if ((bus->board_vendor == SSB_BOARDVENDOR_BCM) &&
+ (bus->board_type == SSB_BOARD_BU4306))
+ return;
+
+ switch (phy->type) {
+ case BCM43xx_PHYTYPE_A: {
+
+ TODO(); //TODO: Nothing for A PHYs yet :-/
+
+ break;
+ }
+ case BCM43xx_PHYTYPE_B:
+ case BCM43xx_PHYTYPE_G: {
+ u16 tmp;
+ u16 txpower;
+ s8 v0, v1, v2, v3;
+ s8 average;
+ u8 max_pwr;
+ s16 desired_pwr, estimated_pwr, pwr_adjust;
+ int radio_att_delta, baseband_att_delta;
+ int radio_attenuation, baseband_attenuation;
+ unsigned long phylock_flags;
+
+ tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x0058);
+ v0 = (s8)(tmp & 0x00FF);
+ v1 = (s8)((tmp & 0xFF00) >> 8);
+ tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x005A);
+ v2 = (s8)(tmp & 0x00FF);
+ v3 = (s8)((tmp & 0xFF00) >> 8);
+ tmp = 0;
+
+ if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F) {
+ tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x0070);
+ v0 = (s8)(tmp & 0x00FF);
+ v1 = (s8)((tmp & 0xFF00) >> 8);
+ tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x0072);
+ v2 = (s8)(tmp & 0x00FF);
+ v3 = (s8)((tmp & 0xFF00) >> 8);
+ if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F)
+ return;
+ v0 = (v0 + 0x20) & 0x3F;
+ v1 = (v1 + 0x20) & 0x3F;
+ v2 = (v2 + 0x20) & 0x3F;
+ v3 = (v3 + 0x20) & 0x3F;
+ tmp = 1;
+ }
+ bcm43xx_shm_clear_tssi(dev);
+
+ average = (v0 + v1 + v2 + v3 + 2) / 4;
+
+ if (tmp && (bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x005E) & 0x8))
+ average -= 13;
+
+ estimated_pwr = bcm43xx_phy_estimate_power_out(dev, average);
+
+ max_pwr = dev->dev->bus->sprom.r1.maxpwr_bg;
+
+ if ((dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_PACTRL) &&
+ (phy->type == BCM43xx_PHYTYPE_G))
+ max_pwr -= 0x3;
+
+ /*TODO:
+ max_pwr = min(REG - dev->dev->bus->sprom.antennagain_bgphy - 0x6, max_pwr)
+ where REG is the max power as per the regulatory domain
+ */
+
+ desired_pwr = phy->power_level;
+ /* Convert the desired_pwr to Q5.2 and limit it. */
+ desired_pwr = limit_value((desired_pwr << 2), 0, max_pwr);
+
+ pwr_adjust = desired_pwr - estimated_pwr;
+ radio_att_delta = -((pwr_adjust + 7) >> 3);
+ baseband_att_delta = (-(pwr_adjust >> 1)) - (4 * radio_att_delta);
+ if ((radio_att_delta == 0) && (baseband_att_delta == 0)) {
+ bcm43xx_lo_g_ctl_mark_cur_used(dev);
+ return;
+ }
+
+ /* Calculate the new attenuation values. */
+ baseband_attenuation = phy->bbatt;
+ baseband_attenuation += baseband_att_delta;
+ radio_attenuation = phy->rfatt;
+ radio_attenuation += radio_att_delta;
+ put_attenuation_into_ranges(dev, &radio_attenuation,
+ &baseband_attenuation);
+
+ txpower = phy->txctl1;
+ if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
+ if (radio_attenuation <= 1) {
+ if (txpower == 0) {
+ txpower = 3;
+ radio_attenuation += 2;
+ baseband_attenuation += 2;
+ } else if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_PACTRL) {
+ baseband_attenuation += 4 * (radio_attenuation - 2);
+ radio_attenuation = 2;
+ }
+ } else if (radio_attenuation > 4 && txpower != 0) {
+ txpower = 0;
+ if (baseband_attenuation < 3) {
+ radio_attenuation -= 3;
+ baseband_attenuation += 2;
+ } else {
+ radio_attenuation -= 2;
+ baseband_attenuation -= 2;
+ }
+ }
+ }
+ phy->txctl1 = txpower;
+ baseband_attenuation = limit_value(baseband_attenuation, 0, 11);
+ radio_attenuation = limit_value(radio_attenuation, 0, 9);
+
+ bcm43xx_phy_lock(dev, phylock_flags);
+ bcm43xx_radio_lock(dev);
+ bcm43xx_radio_set_txpower_bg(dev, baseband_attenuation,
+ radio_attenuation, txpower);
+ bcm43xx_lo_g_ctl_mark_cur_used(dev);
+ bcm43xx_radio_unlock(dev);
+ bcm43xx_phy_unlock(dev, phylock_flags);
+ break;
+ }
+ default:
+ assert(0);
+ }
+}
+
+static inline
+s32 bcm43xx_tssi2dbm_ad(s32 num, s32 den)
+{
+ if (num < 0)
+ return num/den;
+ else
+ return (num+den/2)/den;
+}
+
+static inline
+s8 bcm43xx_tssi2dbm_entry(s8 entry [], u8 index, s16 pab0, s16 pab1, s16 pab2)
+{
+ s32 m1, m2, f = 256, q, delta;
+ s8 i = 0;
+
+ m1 = bcm43xx_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
+ m2 = max(bcm43xx_tssi2dbm_ad(32768 + index * pab2, 256), 1);
+ do {
+ if (i > 15)
+ return -EINVAL;
+ q = bcm43xx_tssi2dbm_ad(f * 4096 -
+ bcm43xx_tssi2dbm_ad(m2 * f, 16) * f, 2048);
+ delta = abs(q - f);
+ f = q;
+ i++;
+ } while (delta >= 2);
+ entry[index] = limit_value(bcm43xx_tssi2dbm_ad(m1 * f, 8192), -127, 128);
+ return 0;
+}
+
+/* http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table */
+int bcm43xx_phy_init_tssi2dbm_table(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ s16 pab0, pab1, pab2;
+ u8 idx;
+ s8 *dyn_tssi2dbm;
+
+ if (phy->type == BCM43xx_PHYTYPE_A) {
+ pab0 = (s16)(dev->dev->bus->sprom.r1.pa1b0);
+ pab1 = (s16)(dev->dev->bus->sprom.r1.pa1b1);
+ pab2 = (s16)(dev->dev->bus->sprom.r1.pa1b2);
+ } else {
+ pab0 = (s16)(dev->dev->bus->sprom.r1.pa0b0);
+ pab1 = (s16)(dev->dev->bus->sprom.r1.pa0b1);
+ pab2 = (s16)(dev->dev->bus->sprom.r1.pa0b2);
+ }
+
+ if ((dev->dev->bus->chip_id == 0x4301) && (phy->radio_ver != 0x2050)) {
+ phy->tgt_idle_tssi = 0x34;
+ phy->tssi2dbm = bcm43xx_tssi2dbm_b_table;
+ return 0;
+ }
+
+ if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
+ pab0 != -1 && pab1 != -1 && pab2 != -1) {
+ /* The pabX values are set in SPROM. Use them. */
+ if (phy->type == BCM43xx_PHYTYPE_A) {
+ if ((s8)dev->dev->bus->sprom.r1.itssi_a != 0 &&
+ (s8)dev->dev->bus->sprom.r1.itssi_a != -1)
+ phy->tgt_idle_tssi = (s8)(dev->dev->bus->sprom.r1.itssi_a);
+ else
+ phy->tgt_idle_tssi = 62;
+ } else {
+ if ((s8)dev->dev->bus->sprom.r1.itssi_bg != 0 &&
+ (s8)dev->dev->bus->sprom.r1.itssi_bg != -1)
+ phy->tgt_idle_tssi = (s8)(dev->dev->bus->sprom.r1.itssi_bg);
+ else
+ phy->tgt_idle_tssi = 62;
+ }
+ dyn_tssi2dbm = kmalloc(64, GFP_KERNEL);
+ if (dyn_tssi2dbm == NULL) {
+ printk(KERN_ERR PFX "Could not allocate memory"
+ "for tssi2dbm table\n");
+ return -ENOMEM;
+ }
+ for (idx = 0; idx < 64; idx++)
+ if (bcm43xx_tssi2dbm_entry(dyn_tssi2dbm, idx, pab0, pab1, pab2)) {
+ phy->tssi2dbm = NULL;
+ printk(KERN_ERR PFX "Could not generate "
+ "tssi2dBm table\n");
+ kfree(dyn_tssi2dbm);
+ return -ENODEV;
+ }
+ phy->tssi2dbm = dyn_tssi2dbm;
+ phy->dyn_tssi_tbl = 1;
+ } else {
+ /* pabX values not set in SPROM. */
+ switch (phy->type) {
+ case BCM43xx_PHYTYPE_A:
+ /* APHY needs a generated table. */
+ phy->tssi2dbm = NULL;
+ printk(KERN_ERR PFX "Could not generate tssi2dBm "
+ "table (wrong SPROM info)!\n");
+ return -ENODEV;
+ case BCM43xx_PHYTYPE_B:
+ phy->tgt_idle_tssi = 0x34;
+ phy->tssi2dbm = bcm43xx_tssi2dbm_b_table;
+ break;
+ case BCM43xx_PHYTYPE_G:
+ phy->tgt_idle_tssi = 0x34;
+ phy->tssi2dbm = bcm43xx_tssi2dbm_g_table;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+int bcm43xx_phy_init(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ int err = -ENODEV;
+
+ switch (phy->type) {
+ case BCM43xx_PHYTYPE_A:
+ if (phy->rev == 2 || phy->rev == 3) {
+ bcm43xx_phy_inita(dev);
+ err = 0;
+ }
+ break;
+ case BCM43xx_PHYTYPE_B:
+ switch (phy->rev) {
+ case 2:
+ bcm43xx_phy_initb2(dev);
+ err = 0;
+ break;
+ case 4:
+ bcm43xx_phy_initb4(dev);
+ err = 0;
+ break;
+ case 5:
+ bcm43xx_phy_initb5(dev);
+ err = 0;
+ break;
+ case 6:
+ bcm43xx_phy_initb6(dev);
+ err = 0;
+ break;
+ }
+ break;
+ case BCM43xx_PHYTYPE_G:
+ bcm43xx_phy_initg(dev);
+ err = 0;
+ break;
+ }
+ if (err)
+ printk(KERN_WARNING PFX "Unknown PHYTYPE found!\n");
+
+ return err;
+}
+
+void bcm43xx_set_rx_antenna(struct bcm43xx_wldev *dev, int antenna)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u32 hf;
+ u16 tmp;
+ int autodiv = 0;
+
+ if (antenna == BCM43xx_ANTENNA_AUTO0 ||
+ antenna == BCM43xx_ANTENNA_AUTO1)
+ autodiv = 1;
+
+ hf = bcm43xx_hf_read(dev);
+ hf &= ~BCM43xx_HF_ANTDIVHELP;
+ bcm43xx_hf_write(dev, hf);
+
+ switch (phy->type) {
+ case BCM43xx_PHYTYPE_A:
+ case BCM43xx_PHYTYPE_G:
+ tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_BBANDCFG);
+ tmp &= ~BCM43xx_PHY_BBANDCFG_RXANT;
+ tmp |= (autodiv ? BCM43xx_ANTENNA_AUTO0 : antenna)
+ << BCM43xx_PHY_BBANDCFG_RXANT_SHIFT;
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BBANDCFG, tmp);
+
+ if (autodiv) {
+ tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_ANTDWELL);
+ if (antenna == BCM43xx_ANTENNA_AUTO0)
+ tmp &= ~BCM43xx_PHY_ANTDWELL_AUTODIV1;
+ else
+ tmp |= BCM43xx_PHY_ANTDWELL_AUTODIV1;
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANTDWELL, tmp);
+ }
+ if (phy->type == BCM43xx_PHYTYPE_G) {
+ tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_ANTWRSETT);
+ if (autodiv)
+ tmp |= BCM43xx_PHY_ANTWRSETT_ARXDIV;
+ else
+ tmp &= ~BCM43xx_PHY_ANTWRSETT_ARXDIV;
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANTWRSETT, tmp);
+ if (phy->rev >= 2) {
+ tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_OFDM61);
+ tmp |= BCM43xx_PHY_OFDM61_10;
+ bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM61, tmp);
+
+ tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_DIVSRCHGAINBACK);
+ tmp = (tmp & 0xFF00) | 0x15;
+ bcm43xx_phy_write(dev, BCM43xx_PHY_DIVSRCHGAINBACK, tmp);
+
+ if (phy->rev == 2) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ADIVRELATED, 8);
+ } else {
+ tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_ADIVRELATED);
+ tmp = (tmp & 0xFF00) | 8;
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ADIVRELATED, tmp);
+ }
+ }
+ if (phy->rev >= 6)
+ bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM9B, 0xDC);
+ } else {
+ if (phy->rev < 3) {
+ tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_ANTDWELL);
+ tmp = (tmp & 0xFF00) | 0x24;
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANTDWELL, tmp);
+ } else {
+ tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_OFDM61);
+ tmp |= 0x10;
+ bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM61, tmp);
+ if (phy->analog == 3) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_CLIPPWRDOWNT, 0x1D);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ADIVRELATED, 8);
+ } else {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_CLIPPWRDOWNT, 0x3A);
+ tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_ADIVRELATED);
+ tmp = (tmp & 0xFF00) | 8;
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ADIVRELATED, tmp);
+ }
+ }
+ }
+ break;
+ case BCM43xx_PHYTYPE_B:
+ tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_CCKBBANDCFG);
+ tmp &= ~BCM43xx_PHY_BBANDCFG_RXANT;
+ tmp |= (autodiv ? BCM43xx_ANTENNA_AUTO0 : antenna)
+ << BCM43xx_PHY_BBANDCFG_RXANT_SHIFT;
+ bcm43xx_phy_write(dev, BCM43xx_PHY_CCKBBANDCFG, tmp);
+ break;
+ default:
+ assert(0);
+ }
+
+ hf |= BCM43xx_HF_ANTDIVHELP;
+ bcm43xx_hf_write(dev, hf);
+}
+
+/* Get the freq, as it has to be written to the device. */
+static inline
+u16 channel2freq_bg(u8 channel)
+{
+ assert(channel >= 1 && channel <= 14);
+
+ return bcm43xx_radio_channel_codes_bg[channel - 1];
+}
+
+/* Get the freq, as it has to be written to the device. */
+static inline
+u16 channel2freq_a(u8 channel)
+{
+ assert(channel <= 200);
+
+ return (5000 + 5 * channel);
+}
+
+void bcm43xx_radio_lock(struct bcm43xx_wldev *dev)
+{
+ u32 status;
+
+ status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
+ status |= BCM43xx_SBF_RADIOREG_LOCK;
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, status);
+ mmiowb();
+ udelay(10);
+}
+
+void bcm43xx_radio_unlock(struct bcm43xx_wldev *dev)
+{
+ u32 status;
+
+ bcm43xx_read16(dev, BCM43xx_MMIO_PHY_VER); /* dummy read */
+ status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
+ status &= ~BCM43xx_SBF_RADIOREG_LOCK;
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, status);
+ mmiowb();
+}
+
+u16 bcm43xx_radio_read16(struct bcm43xx_wldev *dev, u16 offset)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ switch (phy->type) {
+ case BCM43xx_PHYTYPE_A:
+ offset |= 0x0040;
+ break;
+ case BCM43xx_PHYTYPE_B:
+ if (phy->radio_ver == 0x2053) {
+ if (offset < 0x70)
+ offset += 0x80;
+ else if (offset < 0x80)
+ offset += 0x70;
+ } else if (phy->radio_ver == 0x2050) {
+ offset |= 0x80;
+ } else
+ assert(0);
+ break;
+ case BCM43xx_PHYTYPE_G:
+ offset |= 0x80;
+ break;
+ }
+
+ bcm43xx_write16(dev, BCM43xx_MMIO_RADIO_CONTROL, offset);
+ return bcm43xx_read16(dev, BCM43xx_MMIO_RADIO_DATA_LOW);
+}
+
+void bcm43xx_radio_write16(struct bcm43xx_wldev *dev, u16 offset, u16 val)
+{
+ bcm43xx_write16(dev, BCM43xx_MMIO_RADIO_CONTROL, offset);
+ mmiowb();
+ bcm43xx_write16(dev, BCM43xx_MMIO_RADIO_DATA_LOW, val);
+}
+
+static void bcm43xx_set_all_gains(struct bcm43xx_wldev *dev,
+ s16 first, s16 second, s16 third)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 i;
+ u16 start = 0x08, end = 0x18;
+ u16 tmp;
+ u16 table;
+
+ if (phy->rev <= 1) {
+ start = 0x10;
+ end = 0x20;
+ }
+
+ table = BCM43xx_OFDMTAB_GAINX;
+ if (phy->rev <= 1)
+ table = BCM43xx_OFDMTAB_GAINX_R1;
+ for (i = 0; i < 4; i++)
+ bcm43xx_ofdmtab_write16(dev, table, i, first);
+
+ for (i = start; i < end; i++)
+ bcm43xx_ofdmtab_write16(dev, table, i, second);
+
+ if (third != -1) {
+ tmp = ((u16)third << 14) | ((u16)third << 6);
+ bcm43xx_phy_write(dev, 0x04A0,
+ (bcm43xx_phy_read(dev, 0x04A0) & 0xBFBF) | tmp);
+ bcm43xx_phy_write(dev, 0x04A1,
+ (bcm43xx_phy_read(dev, 0x04A1) & 0xBFBF) | tmp);
+ bcm43xx_phy_write(dev, 0x04A2,
+ (bcm43xx_phy_read(dev, 0x04A2) & 0xBFBF) | tmp);
+ }
+ bcm43xx_dummy_transmission(dev);
+}
+
+static void bcm43xx_set_original_gains(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 i, tmp;
+ u16 table;
+ u16 start = 0x0008, end = 0x0018;
+
+ if (phy->rev <= 1) {
+ start = 0x0010;
+ end = 0x0020;
+ }
+
+ table = BCM43xx_OFDMTAB_GAINX;
+ if (phy->rev <= 1)
+ table = BCM43xx_OFDMTAB_GAINX_R1;
+ for (i = 0; i < 4; i++) {
+ tmp = (i & 0xFFFC);
+ tmp |= (i & 0x0001) << 1;
+ tmp |= (i & 0x0002) >> 1;
+
+ bcm43xx_ofdmtab_write16(dev, table, i, tmp);
+ }
+
+ for (i = start; i < end; i++)
+ bcm43xx_ofdmtab_write16(dev, table, i, i - start);
+
+ bcm43xx_phy_write(dev, 0x04A0,
+ (bcm43xx_phy_read(dev, 0x04A0) & 0xBFBF) | 0x4040);
+ bcm43xx_phy_write(dev, 0x04A1,
+ (bcm43xx_phy_read(dev, 0x04A1) & 0xBFBF) | 0x4040);
+ bcm43xx_phy_write(dev, 0x04A2,
+ (bcm43xx_phy_read(dev, 0x04A2) & 0xBFBF) | 0x4000);
+ bcm43xx_dummy_transmission(dev);
+}
+
+/* Synthetic PU workaround */
+static void bcm43xx_synth_pu_workaround(struct bcm43xx_wldev *dev, u8 channel)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
+ /* We do not need the workaround. */
+ return;
+ }
+
+ if (channel <= 10) {
+ bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL,
+ channel2freq_bg(channel + 4));
+ } else {
+ bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL,
+ channel2freq_bg(1));
+ }
+ udelay(100);
+ bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL,
+ channel2freq_bg(channel));
+}
+
+u8 bcm43xx_radio_aci_detect(struct bcm43xx_wldev *dev, u8 channel)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u8 ret = 0;
+ u16 saved, rssi, temp;
+ int i, j = 0;
+
+ saved = bcm43xx_phy_read(dev, 0x0403);
+ bcm43xx_radio_selectchannel(dev, channel, 0);
+ bcm43xx_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
+ if (phy->aci_hw_rssi)
+ rssi = bcm43xx_phy_read(dev, 0x048A) & 0x3F;
+ else
+ rssi = saved & 0x3F;
+ /* clamp temp to signed 5bit */
+ if (rssi > 32)
+ rssi -= 64;
+ for (i = 0;i < 100; i++) {
+ temp = (bcm43xx_phy_read(dev, 0x047F) >> 8) & 0x3F;
+ if (temp > 32)
+ temp -= 64;
+ if (temp < rssi)
+ j++;
+ if (j >= 20)
+ ret = 1;
+ }
+ bcm43xx_phy_write(dev, 0x0403, saved);
+
+ return ret;
+}
+
+u8 bcm43xx_radio_aci_scan(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u8 ret[13];
+ unsigned int channel = phy->channel;
+ unsigned int i, j, start, end;
+ unsigned long phylock_flags;
+
+ if (!((phy->type == BCM43xx_PHYTYPE_G) && (phy->rev > 0)))
+ return 0;
+
+ bcm43xx_phy_lock(dev, phylock_flags);
+ bcm43xx_radio_lock(dev);
+ bcm43xx_phy_write(dev, 0x0802,
+ bcm43xx_phy_read(dev, 0x0802) & 0xFFFC);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS) & 0x7FFF);
+ bcm43xx_set_all_gains(dev, 3, 8, 1);
+
+ start = (channel - 5 > 0) ? channel - 5 : 1;
+ end = (channel + 5 < 14) ? channel + 5 : 13;
+
+ for (i = start; i <= end; i++) {
+ if (abs(channel - i) > 2)
+ ret[i-1] = bcm43xx_radio_aci_detect(dev, i);
+ }
+ bcm43xx_radio_selectchannel(dev, channel, 0);
+ bcm43xx_phy_write(dev, 0x0802,
+ (bcm43xx_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003);
+ bcm43xx_phy_write(dev, 0x0403,
+ bcm43xx_phy_read(dev, 0x0403) & 0xFFF8);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS) | 0x8000);
+ bcm43xx_set_original_gains(dev);
+ for (i = 0; i < 13; i++) {
+ if (!ret[i])
+ continue;
+ end = (i + 5 < 13) ? i + 5 : 13;
+ for (j = i; j < end; j++)
+ ret[j] = 1;
+ }
+ bcm43xx_radio_unlock(dev);
+ bcm43xx_phy_unlock(dev, phylock_flags);
+
+ return ret[channel - 1];
+}
+
+/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
+void bcm43xx_nrssi_hw_write(struct bcm43xx_wldev *dev, u16 offset, s16 val)
+{
+ bcm43xx_phy_write(dev, BCM43xx_PHY_NRSSILT_CTRL, offset);
+ mmiowb();
+ bcm43xx_phy_write(dev, BCM43xx_PHY_NRSSILT_DATA, (u16)val);
+}
+
+/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
+s16 bcm43xx_nrssi_hw_read(struct bcm43xx_wldev *dev, u16 offset)
+{
+ u16 val;
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_NRSSILT_CTRL, offset);
+ val = bcm43xx_phy_read(dev, BCM43xx_PHY_NRSSILT_DATA);
+
+ return (s16)val;
+}
+
+/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
+void bcm43xx_nrssi_hw_update(struct bcm43xx_wldev *dev, u16 val)
+{
+ u16 i;
+ s16 tmp;
+
+ for (i = 0; i < 64; i++) {
+ tmp = bcm43xx_nrssi_hw_read(dev, i);
+ tmp -= val;
+ tmp = limit_value(tmp, -32, 31);
+ bcm43xx_nrssi_hw_write(dev, i, tmp);
+ }
+}
+
+/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
+void bcm43xx_nrssi_mem_update(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ s16 i, delta;
+ s32 tmp;
+
+ delta = 0x1F - phy->nrssi[0];
+ for (i = 0; i < 64; i++) {
+ tmp = (i - delta) * phy->nrssislope;
+ tmp /= 0x10000;
+ tmp += 0x3A;
+ tmp = limit_value(tmp, 0, 0x3F);
+ phy->nrssi_lt[i] = tmp;
+ }
+}
+
+static void bcm43xx_calc_nrssi_offset(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 backup[20] = { 0 };
+ s16 v47F;
+ u16 i;
+ u16 saved = 0xFFFF;
+
+ backup[0] = bcm43xx_phy_read(dev, 0x0001);
+ backup[1] = bcm43xx_phy_read(dev, 0x0811);
+ backup[2] = bcm43xx_phy_read(dev, 0x0812);
+ if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
+ backup[3] = bcm43xx_phy_read(dev, 0x0814);
+ backup[4] = bcm43xx_phy_read(dev, 0x0815);
+ }
+ backup[5] = bcm43xx_phy_read(dev, 0x005A);
+ backup[6] = bcm43xx_phy_read(dev, 0x0059);
+ backup[7] = bcm43xx_phy_read(dev, 0x0058);
+ backup[8] = bcm43xx_phy_read(dev, 0x000A);
+ backup[9] = bcm43xx_phy_read(dev, 0x0003);
+ backup[10] = bcm43xx_radio_read16(dev, 0x007A);
+ backup[11] = bcm43xx_radio_read16(dev, 0x0043);
+
+ bcm43xx_phy_write(dev, 0x0429,
+ bcm43xx_phy_read(dev, 0x0429) & 0x7FFF);
+ bcm43xx_phy_write(dev, 0x0001,
+ (bcm43xx_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000);
+ bcm43xx_phy_write(dev, 0x0811,
+ bcm43xx_phy_read(dev, 0x0811) | 0x000C);
+ bcm43xx_phy_write(dev, 0x0812,
+ (bcm43xx_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004);
+ bcm43xx_phy_write(dev, 0x0802,
+ bcm43xx_phy_read(dev, 0x0802) & ~(0x1 | 0x2));
+ if (phy->rev >= 6) {
+ backup[12] = bcm43xx_phy_read(dev, 0x002E);
+ backup[13] = bcm43xx_phy_read(dev, 0x002F);
+ backup[14] = bcm43xx_phy_read(dev, 0x080F);
+ backup[15] = bcm43xx_phy_read(dev, 0x0810);
+ backup[16] = bcm43xx_phy_read(dev, 0x0801);
+ backup[17] = bcm43xx_phy_read(dev, 0x0060);
+ backup[18] = bcm43xx_phy_read(dev, 0x0014);
+ backup[19] = bcm43xx_phy_read(dev, 0x0478);
+
+ bcm43xx_phy_write(dev, 0x002E, 0);
+ bcm43xx_phy_write(dev, 0x002F, 0);
+ bcm43xx_phy_write(dev, 0x080F, 0);
+ bcm43xx_phy_write(dev, 0x0810, 0);
+ bcm43xx_phy_write(dev, 0x0478,
+ bcm43xx_phy_read(dev, 0x0478) | 0x0100);
+ bcm43xx_phy_write(dev, 0x0801,
+ bcm43xx_phy_read(dev, 0x0801) | 0x0040);
+ bcm43xx_phy_write(dev, 0x0060,
+ bcm43xx_phy_read(dev, 0x0060) | 0x0040);
+ bcm43xx_phy_write(dev, 0x0014,
+ bcm43xx_phy_read(dev, 0x0014) | 0x0200);
+ }
+ bcm43xx_radio_write16(dev, 0x007A,
+ bcm43xx_radio_read16(dev, 0x007A) | 0x0070);
+ bcm43xx_radio_write16(dev, 0x007A,
+ bcm43xx_radio_read16(dev, 0x007A) | 0x0080);
+ udelay(30);
+
+ v47F = (s16)((bcm43xx_phy_read(dev, 0x047F) >> 8) & 0x003F);
+ if (v47F >= 0x20)
+ v47F -= 0x40;
+ if (v47F == 31) {
+ for (i = 7; i >= 4; i--) {
+ bcm43xx_radio_write16(dev, 0x007B, i);
+ udelay(20);
+ v47F = (s16)((bcm43xx_phy_read(dev, 0x047F) >> 8) & 0x003F);
+ if (v47F >= 0x20)
+ v47F -= 0x40;
+ if (v47F < 31 && saved == 0xFFFF)
+ saved = i;
+ }
+ if (saved == 0xFFFF)
+ saved = 4;
+ } else {
+ bcm43xx_radio_write16(dev, 0x007A,
+ bcm43xx_radio_read16(dev, 0x007A) & 0x007F);
+ if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
+ bcm43xx_phy_write(dev, 0x0814,
+ bcm43xx_phy_read(dev, 0x0814) | 0x0001);
+ bcm43xx_phy_write(dev, 0x0815,
+ bcm43xx_phy_read(dev, 0x0815) & 0xFFFE);
+ }
+ bcm43xx_phy_write(dev, 0x0811,
+ bcm43xx_phy_read(dev, 0x0811) | 0x000C);
+ bcm43xx_phy_write(dev, 0x0812,
+ bcm43xx_phy_read(dev, 0x0812) | 0x000C);
+ bcm43xx_phy_write(dev, 0x0811,
+ bcm43xx_phy_read(dev, 0x0811) | 0x0030);
+ bcm43xx_phy_write(dev, 0x0812,
+ bcm43xx_phy_read(dev, 0x0812) | 0x0030);
+ bcm43xx_phy_write(dev, 0x005A, 0x0480);
+ bcm43xx_phy_write(dev, 0x0059, 0x0810);
+ bcm43xx_phy_write(dev, 0x0058, 0x000D);
+ if (phy->rev == 0) {
+ bcm43xx_phy_write(dev, 0x0003, 0x0122);
+ } else {
+ bcm43xx_phy_write(dev, 0x000A,
+ bcm43xx_phy_read(dev, 0x000A)
+ | 0x2000);
+ }
+ if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
+ bcm43xx_phy_write(dev, 0x0814,
+ bcm43xx_phy_read(dev, 0x0814) | 0x0004);
+ bcm43xx_phy_write(dev, 0x0815,
+ bcm43xx_phy_read(dev, 0x0815) & 0xFFFB);
+ }
+ bcm43xx_phy_write(dev, 0x0003,
+ (bcm43xx_phy_read(dev, 0x0003) & 0xFF9F)
+ | 0x0040);
+ bcm43xx_radio_write16(dev, 0x007A,
+ bcm43xx_radio_read16(dev, 0x007A) | 0x000F);
+ bcm43xx_set_all_gains(dev, 3, 0, 1);
+ bcm43xx_radio_write16(dev, 0x0043,
+ (bcm43xx_radio_read16(dev, 0x0043)
+ & 0x00F0) | 0x000F);
+ udelay(30);
+ v47F = (s16)((bcm43xx_phy_read(dev, 0x047F) >> 8) & 0x003F);
+ if (v47F >= 0x20)
+ v47F -= 0x40;
+ if (v47F == -32) {
+ for (i = 0; i < 4; i++) {
+ bcm43xx_radio_write16(dev, 0x007B, i);
+ udelay(20);
+ v47F = (s16)((bcm43xx_phy_read(dev, 0x047F) >> 8) & 0x003F);
+ if (v47F >= 0x20)
+ v47F -= 0x40;
+ if (v47F > -31 && saved == 0xFFFF)
+ saved = i;
+ }
+ if (saved == 0xFFFF)
+ saved = 3;
+ } else
+ saved = 0;
+ }
+ bcm43xx_radio_write16(dev, 0x007B, saved);
+
+ if (phy->rev >= 6) {
+ bcm43xx_phy_write(dev, 0x002E, backup[12]);
+ bcm43xx_phy_write(dev, 0x002F, backup[13]);
+ bcm43xx_phy_write(dev, 0x080F, backup[14]);
+ bcm43xx_phy_write(dev, 0x0810, backup[15]);
+ }
+ if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
+ bcm43xx_phy_write(dev, 0x0814, backup[3]);
+ bcm43xx_phy_write(dev, 0x0815, backup[4]);
+ }
+ bcm43xx_phy_write(dev, 0x005A, backup[5]);
+ bcm43xx_phy_write(dev, 0x0059, backup[6]);
+ bcm43xx_phy_write(dev, 0x0058, backup[7]);
+ bcm43xx_phy_write(dev, 0x000A, backup[8]);
+ bcm43xx_phy_write(dev, 0x0003, backup[9]);
+ bcm43xx_radio_write16(dev, 0x0043, backup[11]);
+ bcm43xx_radio_write16(dev, 0x007A, backup[10]);
+ bcm43xx_phy_write(dev, 0x0802,
+ bcm43xx_phy_read(dev, 0x0802) | 0x1 | 0x2);
+ bcm43xx_phy_write(dev, 0x0429,
+ bcm43xx_phy_read(dev, 0x0429) | 0x8000);
+ bcm43xx_set_original_gains(dev);
+ if (phy->rev >= 6) {
+ bcm43xx_phy_write(dev, 0x0801, backup[16]);
+ bcm43xx_phy_write(dev, 0x0060, backup[17]);
+ bcm43xx_phy_write(dev, 0x0014, backup[18]);
+ bcm43xx_phy_write(dev, 0x0478, backup[19]);
+ }
+ bcm43xx_phy_write(dev, 0x0001, backup[0]);
+ bcm43xx_phy_write(dev, 0x0812, backup[2]);
+ bcm43xx_phy_write(dev, 0x0811, backup[1]);
+}
+
+void bcm43xx_calc_nrssi_slope(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 backup[18] = { 0 };
+ u16 tmp;
+ s16 nrssi0, nrssi1;
+
+ switch (phy->type) {
+ case BCM43xx_PHYTYPE_B:
+ backup[0] = bcm43xx_radio_read16(dev, 0x007A);
+ backup[1] = bcm43xx_radio_read16(dev, 0x0052);
+ backup[2] = bcm43xx_radio_read16(dev, 0x0043);
+ backup[3] = bcm43xx_phy_read(dev, 0x0030);
+ backup[4] = bcm43xx_phy_read(dev, 0x0026);
+ backup[5] = bcm43xx_phy_read(dev, 0x0015);
+ backup[6] = bcm43xx_phy_read(dev, 0x002A);
+ backup[7] = bcm43xx_phy_read(dev, 0x0020);
+ backup[8] = bcm43xx_phy_read(dev, 0x005A);
+ backup[9] = bcm43xx_phy_read(dev, 0x0059);
+ backup[10] = bcm43xx_phy_read(dev, 0x0058);
+ backup[11] = bcm43xx_read16(dev, 0x03E2);
+ backup[12] = bcm43xx_read16(dev, 0x03E6);
+ backup[13] = bcm43xx_read16(dev, BCM43xx_MMIO_CHANNEL_EXT);
+
+ tmp = bcm43xx_radio_read16(dev, 0x007A);
+ tmp &= (phy->rev >= 5) ? 0x007F : 0x000F;
+ bcm43xx_radio_write16(dev, 0x007A, tmp);
+ bcm43xx_phy_write(dev, 0x0030, 0x00FF);
+ bcm43xx_write16(dev, 0x03EC, 0x7F7F);
+ bcm43xx_phy_write(dev, 0x0026, 0x0000);
+ bcm43xx_phy_write(dev, 0x0015,
+ bcm43xx_phy_read(dev, 0x0015) | 0x0020);
+ bcm43xx_phy_write(dev, 0x002A, 0x08A3);
+ bcm43xx_radio_write16(dev, 0x007A,
+ bcm43xx_radio_read16(dev, 0x007A) | 0x0080);
+
+ nrssi0 = (s16)bcm43xx_phy_read(dev, 0x0027);
+ bcm43xx_radio_write16(dev, 0x007A,
+ bcm43xx_radio_read16(dev, 0x007A) & 0x007F);
+ if (phy->rev >= 2) {
+ bcm43xx_write16(dev, 0x03E6, 0x0040);
+ } else if (phy->rev == 0) {
+ bcm43xx_write16(dev, 0x03E6, 0x0122);
+ } else {
+ bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL_EXT,
+ bcm43xx_read16(dev, BCM43xx_MMIO_CHANNEL_EXT) & 0x2000);
+ }
+ bcm43xx_phy_write(dev, 0x0020, 0x3F3F);
+ bcm43xx_phy_write(dev, 0x0015, 0xF330);
+ bcm43xx_radio_write16(dev, 0x005A, 0x0060);
+ bcm43xx_radio_write16(dev, 0x0043,
+ bcm43xx_radio_read16(dev, 0x0043) & 0x00F0);
+ bcm43xx_phy_write(dev, 0x005A, 0x0480);
+ bcm43xx_phy_write(dev, 0x0059, 0x0810);
+ bcm43xx_phy_write(dev, 0x0058, 0x000D);
+ udelay(20);
+
+ nrssi1 = (s16)bcm43xx_phy_read(dev, 0x0027);
+ bcm43xx_phy_write(dev, 0x0030, backup[3]);
+ bcm43xx_radio_write16(dev, 0x007A, backup[0]);
+ bcm43xx_write16(dev, 0x03E2, backup[11]);
+ bcm43xx_phy_write(dev, 0x0026, backup[4]);
+ bcm43xx_phy_write(dev, 0x0015, backup[5]);
+ bcm43xx_phy_write(dev, 0x002A, backup[6]);
+ bcm43xx_synth_pu_workaround(dev, phy->channel);
+ if (phy->rev != 0)
+ bcm43xx_write16(dev, 0x03F4, backup[13]);
+
+ bcm43xx_phy_write(dev, 0x0020, backup[7]);
+ bcm43xx_phy_write(dev, 0x005A, backup[8]);
+ bcm43xx_phy_write(dev, 0x0059, backup[9]);
+ bcm43xx_phy_write(dev, 0x0058, backup[10]);
+ bcm43xx_radio_write16(dev, 0x0052, backup[1]);
+ bcm43xx_radio_write16(dev, 0x0043, backup[2]);
+
+ if (nrssi0 == nrssi1)
+ phy->nrssislope = 0x00010000;
+ else
+ phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
+
+ if (nrssi0 <= -4) {
+ phy->nrssi[0] = nrssi0;
+ phy->nrssi[1] = nrssi1;
+ }
+ break;
+ case BCM43xx_PHYTYPE_G:
+ if (phy->radio_rev >= 9)
+ return;
+ if (phy->radio_rev == 8)
+ bcm43xx_calc_nrssi_offset(dev);
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS) & 0x7FFF);
+ bcm43xx_phy_write(dev, 0x0802,
+ bcm43xx_phy_read(dev, 0x0802) & 0xFFFC);
+ backup[7] = bcm43xx_read16(dev, 0x03E2);
+ bcm43xx_write16(dev, 0x03E2,
+ bcm43xx_read16(dev, 0x03E2) | 0x8000);
+ backup[0] = bcm43xx_radio_read16(dev, 0x007A);
+ backup[1] = bcm43xx_radio_read16(dev, 0x0052);
+ backup[2] = bcm43xx_radio_read16(dev, 0x0043);
+ backup[3] = bcm43xx_phy_read(dev, 0x0015);
+ backup[4] = bcm43xx_phy_read(dev, 0x005A);
+ backup[5] = bcm43xx_phy_read(dev, 0x0059);
+ backup[6] = bcm43xx_phy_read(dev, 0x0058);
+ backup[8] = bcm43xx_read16(dev, 0x03E6);
+ backup[9] = bcm43xx_read16(dev, BCM43xx_MMIO_CHANNEL_EXT);
+ if (phy->rev >= 3) {
+ backup[10] = bcm43xx_phy_read(dev, 0x002E);
+ backup[11] = bcm43xx_phy_read(dev, 0x002F);
+ backup[12] = bcm43xx_phy_read(dev, 0x080F);
+ backup[13] = bcm43xx_phy_read(dev, BCM43xx_PHY_G_LO_CONTROL);
+ backup[14] = bcm43xx_phy_read(dev, 0x0801);
+ backup[15] = bcm43xx_phy_read(dev, 0x0060);
+ backup[16] = bcm43xx_phy_read(dev, 0x0014);
+ backup[17] = bcm43xx_phy_read(dev, 0x0478);
+ bcm43xx_phy_write(dev, 0x002E, 0);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_G_LO_CONTROL, 0);
+ switch (phy->rev) {
+ case 4: case 6: case 7:
+ bcm43xx_phy_write(dev, 0x0478,
+ bcm43xx_phy_read(dev, 0x0478)
+ | 0x0100);
+ bcm43xx_phy_write(dev, 0x0801,
+ bcm43xx_phy_read(dev, 0x0801)
+ | 0x0040);
+ break;
+ case 3: case 5:
+ bcm43xx_phy_write(dev, 0x0801,
+ bcm43xx_phy_read(dev, 0x0801)
+ & 0xFFBF);
+ break;
+ }
+ bcm43xx_phy_write(dev, 0x0060,
+ bcm43xx_phy_read(dev, 0x0060)
+ | 0x0040);
+ bcm43xx_phy_write(dev, 0x0014,
+ bcm43xx_phy_read(dev, 0x0014)
+ | 0x0200);
+ }
+ bcm43xx_radio_write16(dev, 0x007A,
+ bcm43xx_radio_read16(dev, 0x007A) | 0x0070);
+ bcm43xx_set_all_gains(dev, 0, 8, 0);
+ bcm43xx_radio_write16(dev, 0x007A,
+ bcm43xx_radio_read16(dev, 0x007A) & 0x00F7);
+ if (phy->rev >= 2) {
+ bcm43xx_phy_write(dev, 0x0811,
+ (bcm43xx_phy_read(dev, 0x0811) & 0xFFCF) | 0x0030);
+ bcm43xx_phy_write(dev, 0x0812,
+ (bcm43xx_phy_read(dev, 0x0812) & 0xFFCF) | 0x0010);
+ }
+ bcm43xx_radio_write16(dev, 0x007A,
+ bcm43xx_radio_read16(dev, 0x007A) | 0x0080);
+ udelay(20);
+
+ nrssi0 = (s16)((bcm43xx_phy_read(dev, 0x047F) >> 8) & 0x003F);
+ if (nrssi0 >= 0x0020)
+ nrssi0 -= 0x0040;
+
+ bcm43xx_radio_write16(dev, 0x007A,
+ bcm43xx_radio_read16(dev, 0x007A) & 0x007F);
+ if (phy->rev >= 2) {
+ bcm43xx_phy_write(dev, 0x0003,
+ (bcm43xx_phy_read(dev, 0x0003)
+ & 0xFF9F) | 0x0040);
+ }
+
+ bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL_EXT,
+ bcm43xx_read16(dev, BCM43xx_MMIO_CHANNEL_EXT)
+ | 0x2000);
+ bcm43xx_radio_write16(dev, 0x007A,
+ bcm43xx_radio_read16(dev, 0x007A) | 0x000F);
+ bcm43xx_phy_write(dev, 0x0015, 0xF330);
+ if (phy->rev >= 2) {
+ bcm43xx_phy_write(dev, 0x0812,
+ (bcm43xx_phy_read(dev, 0x0812) & 0xFFCF) | 0x0020);
+ bcm43xx_phy_write(dev, 0x0811,
+ (bcm43xx_phy_read(dev, 0x0811) & 0xFFCF) | 0x0020);
+ }
+
+ bcm43xx_set_all_gains(dev, 3, 0, 1);
+ if (phy->radio_rev == 8) {
+ bcm43xx_radio_write16(dev, 0x0043, 0x001F);
+ } else {
+ tmp = bcm43xx_radio_read16(dev, 0x0052) & 0xFF0F;
+ bcm43xx_radio_write16(dev, 0x0052, tmp | 0x0060);
+ tmp = bcm43xx_radio_read16(dev, 0x0043) & 0xFFF0;
+ bcm43xx_radio_write16(dev, 0x0043, tmp | 0x0009);
+ }
+ bcm43xx_phy_write(dev, 0x005A, 0x0480);
+ bcm43xx_phy_write(dev, 0x0059, 0x0810);
+ bcm43xx_phy_write(dev, 0x0058, 0x000D);
+ udelay(20);
+ nrssi1 = (s16)((bcm43xx_phy_read(dev, 0x047F) >> 8) & 0x003F);
+ if (nrssi1 >= 0x0020)
+ nrssi1 -= 0x0040;
+ if (nrssi0 == nrssi1)
+ phy->nrssislope = 0x00010000;
+ else
+ phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
+ if (nrssi0 >= -4) {
+ phy->nrssi[0] = nrssi1;
+ phy->nrssi[1] = nrssi0;
+ }
+ if (phy->rev >= 3) {
+ bcm43xx_phy_write(dev, 0x002E, backup[10]);
+ bcm43xx_phy_write(dev, 0x002F, backup[11]);
+ bcm43xx_phy_write(dev, 0x080F, backup[12]);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_G_LO_CONTROL, backup[13]);
+ }
+ if (phy->rev >= 2) {
+ bcm43xx_phy_write(dev, 0x0812,
+ bcm43xx_phy_read(dev, 0x0812) & 0xFFCF);
+ bcm43xx_phy_write(dev, 0x0811,
+ bcm43xx_phy_read(dev, 0x0811) & 0xFFCF);
+ }
+
+ bcm43xx_radio_write16(dev, 0x007A, backup[0]);
+ bcm43xx_radio_write16(dev, 0x0052, backup[1]);
+ bcm43xx_radio_write16(dev, 0x0043, backup[2]);
+ bcm43xx_write16(dev, 0x03E2, backup[7]);
+ bcm43xx_write16(dev, 0x03E6, backup[8]);
+ bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL_EXT, backup[9]);
+ bcm43xx_phy_write(dev, 0x0015, backup[3]);
+ bcm43xx_phy_write(dev, 0x005A, backup[4]);
+ bcm43xx_phy_write(dev, 0x0059, backup[5]);
+ bcm43xx_phy_write(dev, 0x0058, backup[6]);
+ bcm43xx_synth_pu_workaround(dev, phy->channel);
+ bcm43xx_phy_write(dev, 0x0802,
+ bcm43xx_phy_read(dev, 0x0802) | (0x0001 | 0x0002));
+ bcm43xx_set_original_gains(dev);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS) | 0x8000);
+ if (phy->rev >= 3) {
+ bcm43xx_phy_write(dev, 0x0801, backup[14]);
+ bcm43xx_phy_write(dev, 0x0060, backup[15]);
+ bcm43xx_phy_write(dev, 0x0014, backup[16]);
+ bcm43xx_phy_write(dev, 0x0478, backup[17]);
+ }
+ bcm43xx_nrssi_mem_update(dev);
+ bcm43xx_calc_nrssi_threshold(dev);
+ break;
+ default:
+ assert(0);
+ }
+}
+
+void bcm43xx_calc_nrssi_threshold(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ s32 threshold;
+ s32 a, b;
+ s16 tmp16;
+ u16 tmp_u16;
+
+ switch (phy->type) {
+ case BCM43xx_PHYTYPE_B: {
+ if (phy->radio_ver != 0x2050)
+ return;
+ if (!(dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_RSSI))
+ return;
+
+ if (phy->radio_rev >= 6) {
+ threshold = (phy->nrssi[1] - phy->nrssi[0]) * 32;
+ threshold += 20 * (phy->nrssi[0] + 1);
+ threshold /= 40;
+ } else
+ threshold = phy->nrssi[1] - 5;
+
+ threshold = limit_value(threshold, 0, 0x3E);
+ bcm43xx_phy_read(dev, 0x0020); /* dummy read */
+ bcm43xx_phy_write(dev, 0x0020, (((u16)threshold) << 8) | 0x001C);
+
+ if (phy->radio_rev >= 6) {
+ bcm43xx_phy_write(dev, 0x0087, 0x0E0D);
+ bcm43xx_phy_write(dev, 0x0086, 0x0C0B);
+ bcm43xx_phy_write(dev, 0x0085, 0x0A09);
+ bcm43xx_phy_write(dev, 0x0084, 0x0808);
+ bcm43xx_phy_write(dev, 0x0083, 0x0808);
+ bcm43xx_phy_write(dev, 0x0082, 0x0604);
+ bcm43xx_phy_write(dev, 0x0081, 0x0302);
+ bcm43xx_phy_write(dev, 0x0080, 0x0100);
+ }
+ break;
+ }
+ case BCM43xx_PHYTYPE_G:
+ if (!phy->gmode ||
+ !(dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_RSSI)) {
+ tmp16 = bcm43xx_nrssi_hw_read(dev, 0x20);
+ if (tmp16 >= 0x20)
+ tmp16 -= 0x40;
+ if (tmp16 < 3) {
+ bcm43xx_phy_write(dev, 0x048A,
+ (bcm43xx_phy_read(dev, 0x048A)
+ & 0xF000) | 0x09EB);
+ } else {
+ bcm43xx_phy_write(dev, 0x048A,
+ (bcm43xx_phy_read(dev, 0x048A)
+ & 0xF000) | 0x0AED);
+ }
+ } else {
+ if (phy->interfmode == BCM43xx_INTERFMODE_NONWLAN) {
+ a = 0xE;
+ b = 0xA;
+ } else if (!phy->aci_wlan_automatic && phy->aci_enable) {
+ a = 0x13;
+ b = 0x12;
+ } else {
+ a = 0xE;
+ b = 0x11;
+ }
+
+ a = a * (phy->nrssi[1] - phy->nrssi[0]);
+ a += (phy->nrssi[0] << 6);
+ if (a < 32)
+ a += 31;
+ else
+ a += 32;
+ a = a >> 6;
+ a = limit_value(a, -31, 31);
+
+ b = b * (phy->nrssi[1] - phy->nrssi[0]);
+ b += (phy->nrssi[0] << 6);
+ if (b < 32)
+ b += 31;
+ else
+ b += 32;
+ b = b >> 6;
+ b = limit_value(b, -31, 31);
+
+ tmp_u16 = bcm43xx_phy_read(dev, 0x048A) & 0xF000;
+ tmp_u16 |= ((u32)b & 0x0000003F);
+ tmp_u16 |= (((u32)a & 0x0000003F) << 6);
+ bcm43xx_phy_write(dev, 0x048A, tmp_u16);
+ }
+ break;
+ default:
+ assert(0);
+ }
+}
+
+/* Stack implementation to save/restore values from the
+ * interference mitigation code.
+ * It is save to restore values in random order.
+ */
+static void _stack_save(u32 *_stackptr, size_t *stackidx,
+ u8 id, u16 offset, u16 value)
+{
+ u32 *stackptr = &(_stackptr[*stackidx]);
+
+ assert((offset & 0xF000) == 0x0000);
+ assert((id & 0xF0) == 0x00);
+ *stackptr = offset;
+ *stackptr |= ((u32)id) << 12;
+ *stackptr |= ((u32)value) << 16;
+ (*stackidx)++;
+ assert(*stackidx < BCM43xx_INTERFSTACK_SIZE);
+}
+
+static u16 _stack_restore(u32 *stackptr,
+ u8 id, u16 offset)
+{
+ size_t i;
+
+ assert((offset & 0xF000) == 0x0000);
+ assert((id & 0xF0) == 0x00);
+ for (i = 0; i < BCM43xx_INTERFSTACK_SIZE; i++, stackptr++) {
+ if ((*stackptr & 0x00000FFF) != offset)
+ continue;
+ if (((*stackptr & 0x0000F000) >> 12) != id)
+ continue;
+ return ((*stackptr & 0xFFFF0000) >> 16);
+ }
+ assert(0);
+
+ return 0;
+}
+
+#define phy_stacksave(offset) \
+ do { \
+ _stack_save(stack, &stackidx, 0x1, (offset), \
+ bcm43xx_phy_read(dev, (offset))); \
+ } while (0)
+#define phy_stackrestore(offset) \
+ do { \
+ bcm43xx_phy_write(dev, (offset), \
+ _stack_restore(stack, 0x1, \
+ (offset))); \
+ } while (0)
+#define radio_stacksave(offset) \
+ do { \
+ _stack_save(stack, &stackidx, 0x2, (offset), \
+ bcm43xx_radio_read16(dev, (offset))); \
+ } while (0)
+#define radio_stackrestore(offset) \
+ do { \
+ bcm43xx_radio_write16(dev, (offset), \
+ _stack_restore(stack, 0x2, \
+ (offset))); \
+ } while (0)
+#define ofdmtab_stacksave(table, offset) \
+ do { \
+ _stack_save(stack, &stackidx, 0x3, (offset)|(table), \
+ bcm43xx_ofdmtab_read16(dev, (table), (offset))); \
+ } while (0)
+#define ofdmtab_stackrestore(table, offset) \
+ do { \
+ bcm43xx_ofdmtab_write16(dev, (table), (offset), \
+ _stack_restore(stack, 0x3, \
+ (offset)|(table))); \
+ } while (0)
+
+static void
+bcm43xx_radio_interference_mitigation_enable(struct bcm43xx_wldev *dev,
+ int mode)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 tmp, flipped;
+ size_t stackidx = 0;
+ u32 *stack = phy->interfstack;
+
+ switch (mode) {
+ case BCM43xx_INTERFMODE_NONWLAN:
+ if (phy->rev != 1) {
+ bcm43xx_phy_write(dev, 0x042B,
+ bcm43xx_phy_read(dev, 0x042B) | 0x0800);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS) & ~0x4000);
+ break;
+ }
+ radio_stacksave(0x0078);
+ tmp = (bcm43xx_radio_read16(dev, 0x0078) & 0x001E);
+ flipped = flip_4bit(tmp);
+ if (flipped < 10 && flipped >= 8)
+ flipped = 7;
+ else if (flipped >= 10)
+ flipped -= 3;
+ flipped = flip_4bit(flipped);
+ flipped = (flipped << 1) | 0x0020;
+ bcm43xx_radio_write16(dev, 0x0078, flipped);
+
+ bcm43xx_calc_nrssi_threshold(dev);
+
+ phy_stacksave(0x0406);
+ bcm43xx_phy_write(dev, 0x0406, 0x7E28);
+
+ bcm43xx_phy_write(dev, 0x042B,
+ bcm43xx_phy_read(dev, 0x042B) | 0x0800);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RADIO_BITFIELD,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_RADIO_BITFIELD) | 0x1000);
+
+ phy_stacksave(0x04A0);
+ bcm43xx_phy_write(dev, 0x04A0,
+ (bcm43xx_phy_read(dev, 0x04A0) & 0xC0C0) | 0x0008);
+ phy_stacksave(0x04A1);
+ bcm43xx_phy_write(dev, 0x04A1,
+ (bcm43xx_phy_read(dev, 0x04A1) & 0xC0C0) | 0x0605);
+ phy_stacksave(0x04A2);
+ bcm43xx_phy_write(dev, 0x04A2,
+ (bcm43xx_phy_read(dev, 0x04A2) & 0xC0C0) | 0x0204);
+ phy_stacksave(0x04A8);
+ bcm43xx_phy_write(dev, 0x04A8,
+ (bcm43xx_phy_read(dev, 0x04A8) & 0xC0C0) | 0x0803);
+ phy_stacksave(0x04AB);
+ bcm43xx_phy_write(dev, 0x04AB,
+ (bcm43xx_phy_read(dev, 0x04AB) & 0xC0C0) | 0x0605);
+
+ phy_stacksave(0x04A7);
+ bcm43xx_phy_write(dev, 0x04A7, 0x0002);
+ phy_stacksave(0x04A3);
+ bcm43xx_phy_write(dev, 0x04A3, 0x287A);
+ phy_stacksave(0x04A9);
+ bcm43xx_phy_write(dev, 0x04A9, 0x2027);
+ phy_stacksave(0x0493);
+ bcm43xx_phy_write(dev, 0x0493, 0x32F5);
+ phy_stacksave(0x04AA);
+ bcm43xx_phy_write(dev, 0x04AA, 0x2027);
+ phy_stacksave(0x04AC);
+ bcm43xx_phy_write(dev, 0x04AC, 0x32F5);
+ break;
+ case BCM43xx_INTERFMODE_MANUALWLAN:
+ if (bcm43xx_phy_read(dev, 0x0033) & 0x0800)
+ break;
+
+ phy->aci_enable = 1;
+
+ phy_stacksave(BCM43xx_PHY_RADIO_BITFIELD);
+ phy_stacksave(BCM43xx_PHY_G_CRS);
+ if (phy->rev < 2) {
+ phy_stacksave(0x0406);
+ } else {
+ phy_stacksave(0x04C0);
+ phy_stacksave(0x04C1);
+ }
+ phy_stacksave(0x0033);
+ phy_stacksave(0x04A7);
+ phy_stacksave(0x04A3);
+ phy_stacksave(0x04A9);
+ phy_stacksave(0x04AA);
+ phy_stacksave(0x04AC);
+ phy_stacksave(0x0493);
+ phy_stacksave(0x04A1);
+ phy_stacksave(0x04A0);
+ phy_stacksave(0x04A2);
+ phy_stacksave(0x048A);
+ phy_stacksave(0x04A8);
+ phy_stacksave(0x04AB);
+ if (phy->rev == 2) {
+ phy_stacksave(0x04AD);
+ phy_stacksave(0x04AE);
+ } else if (phy->rev >= 3) {
+ phy_stacksave(0x04AD);
+ phy_stacksave(0x0415);
+ phy_stacksave(0x0416);
+ phy_stacksave(0x0417);
+ ofdmtab_stacksave(0x1A00, 0x2);
+ ofdmtab_stacksave(0x1A00, 0x3);
+ }
+ phy_stacksave(0x042B);
+ phy_stacksave(0x048C);
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RADIO_BITFIELD,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_RADIO_BITFIELD)
+ & ~0x1000);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
+ (bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS)
+ & 0xFFFC) | 0x0002);
+
+ bcm43xx_phy_write(dev, 0x0033, 0x0800);
+ bcm43xx_phy_write(dev, 0x04A3, 0x2027);
+ bcm43xx_phy_write(dev, 0x04A9, 0x1CA8);
+ bcm43xx_phy_write(dev, 0x0493, 0x287A);
+ bcm43xx_phy_write(dev, 0x04AA, 0x1CA8);
+ bcm43xx_phy_write(dev, 0x04AC, 0x287A);
+
+ bcm43xx_phy_write(dev, 0x04A0,
+ (bcm43xx_phy_read(dev, 0x04A0)
+ & 0xFFC0) | 0x001A);
+ bcm43xx_phy_write(dev, 0x04A7, 0x000D);
+
+ if (phy->rev < 2) {
+ bcm43xx_phy_write(dev, 0x0406, 0xFF0D);
+ } else if (phy->rev == 2) {
+ bcm43xx_phy_write(dev, 0x04C0, 0xFFFF);
+ bcm43xx_phy_write(dev, 0x04C1, 0x00A9);
+ } else {
+ bcm43xx_phy_write(dev, 0x04C0, 0x00C1);
+ bcm43xx_phy_write(dev, 0x04C1, 0x0059);
+ }
+
+ bcm43xx_phy_write(dev, 0x04A1,
+ (bcm43xx_phy_read(dev, 0x04A1)
+ & 0xC0FF) | 0x1800);
+ bcm43xx_phy_write(dev, 0x04A1,
+ (bcm43xx_phy_read(dev, 0x04A1)
+ & 0xFFC0) | 0x0015);
+ bcm43xx_phy_write(dev, 0x04A8,
+ (bcm43xx_phy_read(dev, 0x04A8)
+ & 0xCFFF) | 0x1000);
+ bcm43xx_phy_write(dev, 0x04A8,
+ (bcm43xx_phy_read(dev, 0x04A8)
+ & 0xF0FF) | 0x0A00);
+ bcm43xx_phy_write(dev, 0x04AB,
+ (bcm43xx_phy_read(dev, 0x04AB)
+ & 0xCFFF) | 0x1000);
+ bcm43xx_phy_write(dev, 0x04AB,
+ (bcm43xx_phy_read(dev, 0x04AB)
+ & 0xF0FF) | 0x0800);
+ bcm43xx_phy_write(dev, 0x04AB,
+ (bcm43xx_phy_read(dev, 0x04AB)
+ & 0xFFCF) | 0x0010);
+ bcm43xx_phy_write(dev, 0x04AB,
+ (bcm43xx_phy_read(dev, 0x04AB)
+ & 0xFFF0) | 0x0005);
+ bcm43xx_phy_write(dev, 0x04A8,
+ (bcm43xx_phy_read(dev, 0x04A8)
+ & 0xFFCF) | 0x0010);
+ bcm43xx_phy_write(dev, 0x04A8,
+ (bcm43xx_phy_read(dev, 0x04A8)
+ & 0xFFF0) | 0x0006);
+ bcm43xx_phy_write(dev, 0x04A2,
+ (bcm43xx_phy_read(dev, 0x04A2)
+ & 0xF0FF) | 0x0800);
+ bcm43xx_phy_write(dev, 0x04A0,
+ (bcm43xx_phy_read(dev, 0x04A0)
+ & 0xF0FF) | 0x0500);
+ bcm43xx_phy_write(dev, 0x04A2,
+ (bcm43xx_phy_read(dev, 0x04A2)
+ & 0xFFF0) | 0x000B);
+
+ if (phy->rev >= 3) {
+ bcm43xx_phy_write(dev, 0x048A,
+ bcm43xx_phy_read(dev, 0x048A)
+ & ~0x8000);
+ bcm43xx_phy_write(dev, 0x0415,
+ (bcm43xx_phy_read(dev, 0x0415)
+ & 0x8000) | 0x36D8);
+ bcm43xx_phy_write(dev, 0x0416,
+ (bcm43xx_phy_read(dev, 0x0416)
+ & 0x8000) | 0x36D8);
+ bcm43xx_phy_write(dev, 0x0417,
+ (bcm43xx_phy_read(dev, 0x0417)
+ & 0xFE00) | 0x016D);
+ } else {
+ bcm43xx_phy_write(dev, 0x048A,
+ bcm43xx_phy_read(dev, 0x048A)
+ | 0x1000);
+ bcm43xx_phy_write(dev, 0x048A,
+ (bcm43xx_phy_read(dev, 0x048A)
+ & 0x9FFF) | 0x2000);
+ bcm43xx_hf_write(dev, bcm43xx_hf_read(dev) | BCM43xx_HF_ACIW);
+ }
+ if (phy->rev >= 2) {
+ bcm43xx_phy_write(dev, 0x042B,
+ bcm43xx_phy_read(dev, 0x042B)
+ | 0x0800);
+ }
+ bcm43xx_phy_write(dev, 0x048C,
+ (bcm43xx_phy_read(dev, 0x048C)
+ & 0xF0FF) | 0x0200);
+ if (phy->rev == 2) {
+ bcm43xx_phy_write(dev, 0x04AE,
+ (bcm43xx_phy_read(dev, 0x04AE)
+ & 0xFF00) | 0x007F);
+ bcm43xx_phy_write(dev, 0x04AD,
+ (bcm43xx_phy_read(dev, 0x04AD)
+ & 0x00FF) | 0x1300);
+ } else if (phy->rev >= 6) {
+ bcm43xx_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
+ bcm43xx_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
+ bcm43xx_phy_write(dev, 0x04AD,
+ bcm43xx_phy_read(dev, 0x04AD)
+ & 0x00FF);
+ }
+ bcm43xx_calc_nrssi_slope(dev);
+ break;
+ default:
+ assert(0);
+ }
+}
+
+static void
+bcm43xx_radio_interference_mitigation_disable(struct bcm43xx_wldev *dev,
+ int mode)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u32 *stack = phy->interfstack;
+
+ switch (mode) {
+ case BCM43xx_INTERFMODE_NONWLAN:
+ if (phy->rev != 1) {
+ bcm43xx_phy_write(dev, 0x042B,
+ bcm43xx_phy_read(dev, 0x042B) & ~0x0800);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS) | 0x4000);
+ break;
+ }
+ radio_stackrestore(0x0078);
+ bcm43xx_calc_nrssi_threshold(dev);
+ phy_stackrestore(0x0406);
+ bcm43xx_phy_write(dev, 0x042B,
+ bcm43xx_phy_read(dev, 0x042B) & ~0x0800);
+ if (!dev->bad_frames_preempt) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RADIO_BITFIELD,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_RADIO_BITFIELD)
+ & ~(1 << 11));
+ }
+ bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS) | 0x4000);
+ phy_stackrestore(0x04A0);
+ phy_stackrestore(0x04A1);
+ phy_stackrestore(0x04A2);
+ phy_stackrestore(0x04A8);
+ phy_stackrestore(0x04AB);
+ phy_stackrestore(0x04A7);
+ phy_stackrestore(0x04A3);
+ phy_stackrestore(0x04A9);
+ phy_stackrestore(0x0493);
+ phy_stackrestore(0x04AA);
+ phy_stackrestore(0x04AC);
+ break;
+ case BCM43xx_INTERFMODE_MANUALWLAN:
+ if (!(bcm43xx_phy_read(dev, 0x0033) & 0x0800))
+ break;
+
+ phy->aci_enable = 0;
+
+ phy_stackrestore(BCM43xx_PHY_RADIO_BITFIELD);
+ phy_stackrestore(BCM43xx_PHY_G_CRS);
+ phy_stackrestore(0x0033);
+ phy_stackrestore(0x04A3);
+ phy_stackrestore(0x04A9);
+ phy_stackrestore(0x0493);
+ phy_stackrestore(0x04AA);
+ phy_stackrestore(0x04AC);
+ phy_stackrestore(0x04A0);
+ phy_stackrestore(0x04A7);
+ if (phy->rev >= 2) {
+ phy_stackrestore(0x04C0);
+ phy_stackrestore(0x04C1);
+ } else
+ phy_stackrestore(0x0406);
+ phy_stackrestore(0x04A1);
+ phy_stackrestore(0x04AB);
+ phy_stackrestore(0x04A8);
+ if (phy->rev == 2) {
+ phy_stackrestore(0x04AD);
+ phy_stackrestore(0x04AE);
+ } else if (phy->rev >= 3) {
+ phy_stackrestore(0x04AD);
+ phy_stackrestore(0x0415);
+ phy_stackrestore(0x0416);
+ phy_stackrestore(0x0417);
+ ofdmtab_stackrestore(0x1A00, 0x2);
+ ofdmtab_stackrestore(0x1A00, 0x3);
+ }
+ phy_stackrestore(0x04A2);
+ phy_stackrestore(0x048A);
+ phy_stackrestore(0x042B);
+ phy_stackrestore(0x048C);
+ bcm43xx_hf_write(dev, bcm43xx_hf_read(dev) & ~BCM43xx_HF_ACIW);
+ bcm43xx_calc_nrssi_slope(dev);
+ break;
+ default:
+ assert(0);
+ }
+}
+
+#undef phy_stacksave
+#undef phy_stackrestore
+#undef radio_stacksave
+#undef radio_stackrestore
+#undef ofdmtab_stacksave
+#undef ofdmtab_stackrestore
+
+int bcm43xx_radio_set_interference_mitigation(struct bcm43xx_wldev *dev,
+ int mode)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ int currentmode;
+
+ if ((phy->type != BCM43xx_PHYTYPE_G) ||
+ (phy->rev == 0) ||
+ (!phy->gmode))
+ return -ENODEV;
+
+ phy->aci_wlan_automatic = 0;
+ switch (mode) {
+ case BCM43xx_INTERFMODE_AUTOWLAN:
+ phy->aci_wlan_automatic = 1;
+ if (phy->aci_enable)
+ mode = BCM43xx_INTERFMODE_MANUALWLAN;
+ else
+ mode = BCM43xx_INTERFMODE_NONE;
+ break;
+ case BCM43xx_INTERFMODE_NONE:
+ case BCM43xx_INTERFMODE_NONWLAN:
+ case BCM43xx_INTERFMODE_MANUALWLAN:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ currentmode = phy->interfmode;
+ if (currentmode == mode)
+ return 0;
+ if (currentmode != BCM43xx_INTERFMODE_NONE)
+ bcm43xx_radio_interference_mitigation_disable(dev, currentmode);
+
+ if (mode == BCM43xx_INTERFMODE_NONE) {
+ phy->aci_enable = 0;
+ phy->aci_hw_rssi = 0;
+ } else
+ bcm43xx_radio_interference_mitigation_enable(dev, mode);
+ phy->interfmode = mode;
+
+ return 0;
+}
+
+static u16 bcm43xx_radio_core_calibration_value(struct bcm43xx_wldev *dev)
+{
+ u16 reg, index, ret;
+
+ static const u8 rcc_table[] = {
+ 0x02, 0x03, 0x01, 0x0F,
+ 0x06, 0x07, 0x05, 0x0F,
+ 0x0A, 0x0B, 0x09, 0x0F,
+ 0x0E, 0x0F, 0x0D, 0x0F,
+ };
+
+ reg = bcm43xx_radio_read16(dev, 0x60);
+ index = (reg & 0x001E) >> 1;
+ ret = rcc_table[index] << 1;
+ ret |= (reg & 0x0001);
+ ret |= 0x0020;
+
+ return ret;
+}
+
+#define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0))
+static u16 radio2050_rfover_val(struct bcm43xx_wldev *dev,
+ u16 phy_register,
+ unsigned int lpd)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
+
+ if (!phy->gmode)
+ return 0;
+
+ if (has_loopback_gain(phy)) {
+ int max_lb_gain = phy->max_lb_gain;
+ u16 extlna;
+ u16 i;
+
+ if (phy->radio_rev == 8)
+ max_lb_gain += 0x3E;
+ else
+ max_lb_gain += 0x26;
+ if (max_lb_gain >= 0x46) {
+ extlna = 0x3000;
+ max_lb_gain -= 0x46;
+ } else if (max_lb_gain >= 0x3A) {
+ extlna = 0x1000;
+ max_lb_gain -= 0x3A;
+ } else if (max_lb_gain >= 0x2E) {
+ extlna = 0x2000;
+ max_lb_gain -= 0x2E;
+ } else {
+ extlna = 0;
+ max_lb_gain -= 0x10;
+ }
+
+ for (i = 0; i < 16; i++) {
+ max_lb_gain -= (i * 6);
+ if (max_lb_gain < 6)
+ break;
+ }
+
+ if ((phy->rev < 7) ||
+ !(sprom->r1.boardflags_lo & BCM43xx_BFL_EXTLNA)) {
+ if (phy_register == BCM43xx_PHY_RFOVER) {
+ return 0x1B3;
+ } else if (phy_register == BCM43xx_PHY_RFOVERVAL) {
+ extlna |= (i << 8);
+ switch (lpd) {
+ case LPD(0, 1, 1):
+ return 0x0F92;
+ case LPD(0, 0, 1):
+ case LPD(1, 0, 1):
+ return (0x0092 | extlna);
+ case LPD(1, 0, 0):
+ return (0x0093 | extlna);
+ }
+ assert(0);
+ }
+ assert(0);
+ } else {
+ if (phy_register == BCM43xx_PHY_RFOVER) {
+ return 0x9B3;
+ } else if (phy_register == BCM43xx_PHY_RFOVERVAL) {
+ if (extlna)
+ extlna |= 0x8000;
+ extlna |= (i << 8);
+ switch (lpd) {
+ case LPD(0, 1, 1):
+ return 0x8F92;
+ case LPD(0, 0, 1):
+ return (0x8092 | extlna);
+ case LPD(1, 0, 1):
+ return (0x2092 | extlna);
+ case LPD(1, 0, 0):
+ return (0x2093 | extlna);
+ }
+ assert(0);
+ }
+ assert(0);
+ }
+ } else {
+ if ((phy->rev < 7) ||
+ !(sprom->r1.boardflags_lo & BCM43xx_BFL_EXTLNA)) {
+ if (phy_register == BCM43xx_PHY_RFOVER) {
+ return 0x1B3;
+ } else if (phy_register == BCM43xx_PHY_RFOVERVAL) {
+ switch (lpd) {
+ case LPD(0, 1, 1):
+ return 0x0FB2;
+ case LPD(0, 0, 1):
+ return 0x00B2;
+ case LPD(1, 0, 1):
+ return 0x30B2;
+ case LPD(1, 0, 0):
+ return 0x30B3;
+ }
+ assert(0);
+ }
+ assert(0);
+ } else {
+ if (phy_register == BCM43xx_PHY_RFOVER) {
+ return 0x9B3;
+ } else if (phy_register == BCM43xx_PHY_RFOVERVAL) {
+ switch (lpd) {
+ case LPD(0, 1, 1):
+ return 0x8FB2;
+ case LPD(0, 0, 1):
+ return 0x80B2;
+ case LPD(1, 0, 1):
+ return 0x20B2;
+ case LPD(1, 0, 0):
+ return 0x20B3;
+ }
+ assert(0);
+ }
+ assert(0);
+ }
+ }
+ return 0;
+}
+
+struct init2050_saved_values {
+ /* Core registers */
+ u16 reg_3EC;
+ u16 reg_3E6;
+ u16 reg_3F4;
+ /* Radio registers */
+ u16 radio_43;
+ u16 radio_51;
+ u16 radio_52;
+ /* PHY registers */
+ u16 phy_pgactl;
+ u16 phy_base_5A;
+ u16 phy_base_59;
+ u16 phy_base_58;
+ u16 phy_base_30;
+ u16 phy_rfover;
+ u16 phy_rfoverval;
+ u16 phy_analogover;
+ u16 phy_analogoverval;
+ u16 phy_crs0;
+ u16 phy_classctl;
+ u16 phy_lo_mask;
+ u16 phy_lo_ctl;
+ u16 phy_syncctl;
+};
+
+u16 bcm43xx_radio_init2050(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ struct init2050_saved_values sav;
+ u16 rcc;
+ u16 radio78;
+ u16 ret;
+ u16 i, j;
+ u32 tmp1 = 0, tmp2 = 0;
+
+ memset(&sav, 0, sizeof(sav)); /* get rid of "may be used uninitialized..." */
+
+ sav.radio_43 = bcm43xx_radio_read16(dev, 0x43);
+ sav.radio_51 = bcm43xx_radio_read16(dev, 0x51);
+ sav.radio_52 = bcm43xx_radio_read16(dev, 0x52);
+ sav.phy_pgactl = bcm43xx_phy_read(dev, BCM43xx_PHY_PGACTL);
+ sav.phy_base_5A = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x5A));
+ sav.phy_base_59 = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x59));
+ sav.phy_base_58 = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x58));
+
+ if (phy->type == BCM43xx_PHYTYPE_B) {
+ sav.phy_base_30 = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x30));
+ sav.reg_3EC = bcm43xx_read16(dev, 0x3EC);
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x30), 0xFF);
+ bcm43xx_write16(dev, 0x3EC, 0x3F3F);
+ } else if (phy->gmode || phy->rev >= 2) {
+ sav.phy_rfover = bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER);
+ sav.phy_rfoverval = bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL);
+ sav.phy_analogover = bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVER);
+ sav.phy_analogoverval = bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVERVAL);
+ sav.phy_crs0 = bcm43xx_phy_read(dev, BCM43xx_PHY_CRS0);
+ sav.phy_classctl = bcm43xx_phy_read(dev, BCM43xx_PHY_CLASSCTL);
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVER)
+ | 0x0003);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVERVAL)
+ & 0xFFFC);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_CRS0,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_CRS0)
+ & 0x7FFF);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_CLASSCTL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_CLASSCTL)
+ & 0xFFFC);
+ if (has_loopback_gain(phy)) {
+ sav.phy_lo_mask = bcm43xx_phy_read(dev, BCM43xx_PHY_LO_MASK);
+ sav.phy_lo_ctl = bcm43xx_phy_read(dev, BCM43xx_PHY_LO_CTL);
+
+ if (phy->rev >= 3)
+ bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, 0xC020);
+ else
+ bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, 0x8020);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_LO_CTL, 0);
+ }
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
+ LPD(0, 1, 1)));
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER,
+ radio2050_rfover_val(dev, BCM43xx_PHY_RFOVER, 0));
+ }
+ bcm43xx_write16(dev, 0x3E2, bcm43xx_read16(dev, 0x3E2) | 0x8000);
+
+ sav.phy_syncctl = bcm43xx_phy_read(dev, BCM43xx_PHY_SYNCCTL);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_SYNCCTL,
+ bcm43xx_phy_read(dev, BCM43xx_PHY_SYNCCTL)
+ & 0xFF7F);
+ sav.reg_3E6 = bcm43xx_read16(dev, 0x3E6);
+ sav.reg_3F4 = bcm43xx_read16(dev, 0x3F4);
+
+ if (phy->analog == 0) {
+ bcm43xx_write16(dev, 0x03E6, 0x0122);
+ } else {
+ if (phy->analog >= 2) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x03),
+ (bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x03))
+ & 0xFFBF) | 0x40);
+ }
+ bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL_EXT,
+ (bcm43xx_read16(dev, BCM43xx_MMIO_CHANNEL_EXT) | 0x2000));
+ }
+
+ rcc = bcm43xx_radio_core_calibration_value(dev);
+
+ if (phy->type == BCM43xx_PHYTYPE_B)
+ bcm43xx_radio_write16(dev, 0x78, 0x26);
+ if (phy->gmode || phy->rev >= 2) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
+ LPD(0, 1, 1)));
+ }
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xBFAF);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2B), 0x1403);
+ if (phy->gmode || phy->rev >= 2) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
+ LPD(0, 0, 1)));
+ }
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xBFA0);
+ bcm43xx_radio_write16(dev, 0x51,
+ bcm43xx_radio_read16(dev, 0x51)
+ | 0x0004);
+ if (phy->radio_rev == 8) {
+ bcm43xx_radio_write16(dev, 0x43, 0x1F);
+ } else {
+ bcm43xx_radio_write16(dev, 0x52, 0);
+ bcm43xx_radio_write16(dev, 0x43,
+ (bcm43xx_radio_read16(dev, 0x43)
+ & 0xFFF0) | 0x0009);
+ }
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), 0);
+
+ for (i = 0; i < 16; i++) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x5A), 0x0480);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x59), 0xC810);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), 0x000D);
+ if (phy->gmode || phy->rev >= 2) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
+ LPD(1, 0, 1)));
+ }
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xAFB0);
+ udelay(10);
+ if (phy->gmode || phy->rev >= 2) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
+ LPD(1, 0, 1)));
+ }
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xEFB0);
+ udelay(10);
+ if (phy->gmode || phy->rev >= 2) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
+ LPD(1, 0, 0)));
+ }
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xFFF0);
+ udelay(20);
+ tmp1 += bcm43xx_phy_read(dev, BCM43xx_PHY_LO_LEAKAGE);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), 0);
+ if (phy->gmode || phy->rev >= 2) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
+ LPD(1, 0, 1)));
+ }
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xAFB0);
+ }
+ udelay(10);
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), 0);
+ tmp1++;
+ tmp1 >>= 9;
+
+ for (i = 0; i < 16; i++) {
+ radio78 = ((flip_4bit(i) << 1) | 0x20);
+ bcm43xx_radio_write16(dev, 0x78, radio78);
+ udelay(10);
+ for (j = 0; j < 16; j++) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x5A), 0x0D80);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x59), 0xC810);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), 0x000D);
+ if (phy->gmode || phy->rev >= 2) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
+ LPD(1, 0, 1)));
+ }
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xAFB0);
+ udelay(10);
+ if (phy->gmode || phy->rev >= 2) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
+ LPD(1, 0, 1)));
+ }
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xEFB0);
+ udelay(10);
+ if (phy->gmode || phy->rev >= 2) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
+ LPD(1, 0, 0)));
+ }
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xFFF0);
+ udelay(10);
+ tmp2 += bcm43xx_phy_read(dev, BCM43xx_PHY_LO_LEAKAGE);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), 0);
+ if (phy->gmode || phy->rev >= 2) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
+ radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
+ LPD(1, 0, 1)));
+ }
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xAFB0);
+ }
+ tmp2++;
+ tmp2 >>= 8;
+ if (tmp1 < tmp2)
+ break;
+ }
+
+ /* Restore the registers */
+ bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, sav.phy_pgactl);
+ bcm43xx_radio_write16(dev, 0x51, sav.radio_51);
+ bcm43xx_radio_write16(dev, 0x52, sav.radio_52);
+ bcm43xx_radio_write16(dev, 0x43, sav.radio_43);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x5A), sav.phy_base_5A);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x59), sav.phy_base_59);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), sav.phy_base_58);
+ bcm43xx_write16(dev, 0x3E6, sav.reg_3E6);
+ if (phy->analog != 0)
+ bcm43xx_write16(dev, 0x3F4, sav.reg_3F4);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_SYNCCTL, sav.phy_syncctl);
+ bcm43xx_synth_pu_workaround(dev, phy->channel);
+ if (phy->type == BCM43xx_PHYTYPE_B) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x30), sav.phy_base_30);
+ bcm43xx_write16(dev, 0x3EC, sav.reg_3EC);
+ } else if (phy->gmode) {
+ bcm43xx_write16(dev, BCM43xx_MMIO_PHY_RADIO,
+ bcm43xx_read16(dev, BCM43xx_MMIO_PHY_RADIO)
+ & 0x7FFF);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, sav.phy_rfover);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, sav.phy_rfoverval);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER, sav.phy_analogover);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL, sav.phy_analogoverval);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_CRS0, sav.phy_crs0);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_CLASSCTL, sav.phy_classctl);
+ if (has_loopback_gain(phy)) {
+ bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, sav.phy_lo_mask);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_LO_CTL, sav.phy_lo_ctl);
+ }
+ }
+ if (i > 15)
+ ret = radio78;
+ else
+ ret = rcc;
+
+ return ret;
+}
+
+void bcm43xx_radio_init2060(struct bcm43xx_wldev *dev)
+{
+ int err;
+
+ bcm43xx_radio_write16(dev, 0x0004, 0x00C0);
+ bcm43xx_radio_write16(dev, 0x0005, 0x0008);
+ bcm43xx_radio_write16(dev, 0x0009, 0x0040);
+ bcm43xx_radio_write16(dev, 0x0005, 0x00AA);
+ bcm43xx_radio_write16(dev, 0x0032, 0x008F);
+ bcm43xx_radio_write16(dev, 0x0006, 0x008F);
+ bcm43xx_radio_write16(dev, 0x0034, 0x008F);
+ bcm43xx_radio_write16(dev, 0x002C, 0x0007);
+ bcm43xx_radio_write16(dev, 0x0082, 0x0080);
+ bcm43xx_radio_write16(dev, 0x0080, 0x0000);
+ bcm43xx_radio_write16(dev, 0x003F, 0x00DA);
+ bcm43xx_radio_write16(dev, 0x0005, bcm43xx_radio_read16(dev, 0x0005) & ~0x0008);
+ bcm43xx_radio_write16(dev, 0x0081, bcm43xx_radio_read16(dev, 0x0081) & ~0x0010);
+ bcm43xx_radio_write16(dev, 0x0081, bcm43xx_radio_read16(dev, 0x0081) & ~0x0020);
+ bcm43xx_radio_write16(dev, 0x0081, bcm43xx_radio_read16(dev, 0x0081) & ~0x0020);
+ udelay(400);
+
+ bcm43xx_radio_write16(dev, 0x0081, (bcm43xx_radio_read16(dev, 0x0081) & ~0x0020) | 0x0010);
+ udelay(400);
+
+ bcm43xx_radio_write16(dev, 0x0005, (bcm43xx_radio_read16(dev, 0x0005) & ~0x0008) | 0x0008);
+ bcm43xx_radio_write16(dev, 0x0085, bcm43xx_radio_read16(dev, 0x0085) & ~0x0010);
+ bcm43xx_radio_write16(dev, 0x0005, bcm43xx_radio_read16(dev, 0x0005) & ~0x0008);
+ bcm43xx_radio_write16(dev, 0x0081, bcm43xx_radio_read16(dev, 0x0081) & ~0x0040);
+ bcm43xx_radio_write16(dev, 0x0081, (bcm43xx_radio_read16(dev, 0x0081) & ~0x0040) | 0x0040);
+ bcm43xx_radio_write16(dev, 0x0005, (bcm43xx_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
+ bcm43xx_phy_write(dev, 0x0063, 0xDDC6);
+ bcm43xx_phy_write(dev, 0x0069, 0x07BE);
+ bcm43xx_phy_write(dev, 0x006A, 0x0000);
+
+ err = bcm43xx_radio_selectchannel(dev, BCM43xx_DEFAULT_CHANNEL_A, 0);
+ assert(err == 0);
+ udelay(1000);
+}
+
+static inline
+u16 freq_r3A_value(u16 frequency)
+{
+ u16 value;
+
+ if (frequency < 5091)
+ value = 0x0040;
+ else if (frequency < 5321)
+ value = 0x0000;
+ else if (frequency < 5806)
+ value = 0x0080;
+ else
+ value = 0x0040;
+
+ return value;
+}
+
+void bcm43xx_radio_set_tx_iq(struct bcm43xx_wldev *dev)
+{
+ static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
+ static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
+ u16 tmp = bcm43xx_radio_read16(dev, 0x001E);
+ int i, j;
+
+ for (i = 0; i < 5; i++) {
+ for (j = 0; j < 5; j++) {
+ if (tmp == (data_high[i] << 4 | data_low[j])) {
+ bcm43xx_phy_write(dev, 0x0069, (i - j) << 8 | 0x00C0);
+ return;
+ }
+ }
+ }
+}
+
+int bcm43xx_radio_selectchannel(struct bcm43xx_wldev *dev,
+ u8 channel,
+ int synthetic_pu_workaround)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 r8, tmp;
+ u16 freq;
+ u16 channelcookie;
+
+ /* First we set the channel radio code to prevent the
+ * firmware from sending ghost packets.
+ */
+ channelcookie = channel;
+ if (phy->type == BCM43xx_PHYTYPE_A)
+ channelcookie |= 0x100;
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+ BCM43xx_SHM_SH_CHAN, channelcookie);
+
+ if (phy->type == BCM43xx_PHYTYPE_A) {
+ if (channel > 200)
+ return -EINVAL;
+ freq = channel2freq_a(channel);
+
+ r8 = bcm43xx_radio_read16(dev, 0x0008);
+ bcm43xx_write16(dev, 0x03F0, freq);
+ bcm43xx_radio_write16(dev, 0x0008, r8);
+
+ TODO();//TODO: write max channel TX power? to Radio 0x2D
+ tmp = bcm43xx_radio_read16(dev, 0x002E);
+ tmp &= 0x0080;
+ TODO();//TODO: OR tmp with the Power out estimation for this channel?
+ bcm43xx_radio_write16(dev, 0x002E, tmp);
+
+ if (freq >= 4920 && freq <= 5500) {
+ /*
+ * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
+ * = (freq * 0.025862069
+ */
+ r8 = 3 * freq / 116; /* is equal to r8 = freq * 0.025862 */
+ }
+ bcm43xx_radio_write16(dev, 0x0007, (r8 << 4) | r8);
+ bcm43xx_radio_write16(dev, 0x0020, (r8 << 4) | r8);
+ bcm43xx_radio_write16(dev, 0x0021, (r8 << 4) | r8);
+ bcm43xx_radio_write16(dev, 0x0022,
+ (bcm43xx_radio_read16(dev, 0x0022)
+ & 0x000F) | (r8 << 4));
+ bcm43xx_radio_write16(dev, 0x002A, (r8 << 4));
+ bcm43xx_radio_write16(dev, 0x002B, (r8 << 4));
+ bcm43xx_radio_write16(dev, 0x0008,
+ (bcm43xx_radio_read16(dev, 0x0008)
+ & 0x00F0) | (r8 << 4));
+ bcm43xx_radio_write16(dev, 0x0029,
+ (bcm43xx_radio_read16(dev, 0x0029)
+ & 0xFF0F) | 0x00B0);
+ bcm43xx_radio_write16(dev, 0x0035, 0x00AA);
+ bcm43xx_radio_write16(dev, 0x0036, 0x0085);
+ bcm43xx_radio_write16(dev, 0x003A,
+ (bcm43xx_radio_read16(dev, 0x003A)
+ & 0xFF20) | freq_r3A_value(freq));
+ bcm43xx_radio_write16(dev, 0x003D,
+ bcm43xx_radio_read16(dev, 0x003D) & 0x00FF);
+ bcm43xx_radio_write16(dev, 0x0081,
+ (bcm43xx_radio_read16(dev, 0x0081)
+ & 0xFF7F) | 0x0080);
+ bcm43xx_radio_write16(dev, 0x0035,
+ bcm43xx_radio_read16(dev, 0x0035) & 0xFFEF);
+ bcm43xx_radio_write16(dev, 0x0035,
+ (bcm43xx_radio_read16(dev, 0x0035)
+ & 0xFFEF) | 0x0010);
+ bcm43xx_radio_set_tx_iq(dev);
+ TODO(); //TODO: TSSI2dbm workaround
+ bcm43xx_phy_xmitpower(dev);//FIXME correct?
+ } else {
+ if ((channel < 1) || (channel > 14))
+ return -EINVAL;
+
+ if (synthetic_pu_workaround)
+ bcm43xx_synth_pu_workaround(dev, channel);
+
+ bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL,
+ channel2freq_bg(channel));
+
+ if (channel == 14) {
+ if (dev->dev->bus->sprom.r1.country_code == SSB_SPROM1CCODE_JAPAN)
+ bcm43xx_hf_write(dev, bcm43xx_hf_read(dev) & ~BCM43xx_HF_ACPR);
+ else
+ bcm43xx_hf_write(dev, bcm43xx_hf_read(dev) | BCM43xx_HF_ACPR);
+ bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL_EXT,
+ bcm43xx_read16(dev, BCM43xx_MMIO_CHANNEL_EXT)
+ | (1 << 11));
+ } else {
+ bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL_EXT,
+ bcm43xx_read16(dev, BCM43xx_MMIO_CHANNEL_EXT)
+ & 0xF7BF);
+ }
+ }
+
+ phy->channel = channel;
+ //XXX: Using the longer of 2 timeouts (8000 vs 2000 usecs). Specs states
+ // that 2000 usecs might suffice.
+ udelay(8000);
+
+ return 0;
+}
+
+/* http://bcm-specs.sipsolutions.net/TX_Gain_Base_Band */
+static u16 bcm43xx_get_txgain_base_band(u16 txpower)
+{
+ u16 ret;
+
+ assert(txpower <= 63);
+
+ if (txpower >= 54)
+ ret = 2;
+ else if (txpower >= 49)
+ ret = 4;
+ else if (txpower >= 44)
+ ret = 5;
+ else
+ ret = 6;
+
+ return ret;
+}
+
+/* http://bcm-specs.sipsolutions.net/TX_Gain_Radio_Frequency_Power_Amplifier */
+static u16 bcm43xx_get_txgain_freq_power_amp(u16 txpower)
+{
+ u16 ret;
+
+ assert(txpower <= 63);
+
+ if (txpower >= 32)
+ ret = 0;
+ else if (txpower >= 25)
+ ret = 1;
+ else if (txpower >= 20)
+ ret = 2;
+ else if (txpower >= 12)
+ ret = 3;
+ else
+ ret = 4;
+
+ return ret;
+}
+
+/* http://bcm-specs.sipsolutions.net/TX_Gain_Digital_Analog_Converter */
+static u16 bcm43xx_get_txgain_dac(u16 txpower)
+{
+ u16 ret;
+
+ assert(txpower <= 63);
+
+ if (txpower >= 54)
+ ret = txpower - 53;
+ else if (txpower >= 49)
+ ret = txpower - 42;
+ else if (txpower >= 44)
+ ret = txpower - 37;
+ else if (txpower >= 32)
+ ret = txpower - 32;
+ else if (txpower >= 25)
+ ret = txpower - 20;
+ else if (txpower >= 20)
+ ret = txpower - 13;
+ else if (txpower >= 12)
+ ret = txpower - 8;
+ else
+ ret = txpower;
+
+ return ret;
+}
+
+void bcm43xx_radio_set_txpower_a(struct bcm43xx_wldev *dev, u16 txpower)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 pamp, base, dac, t;
+
+ txpower = limit_value(txpower, 0, 63);
+
+ pamp = bcm43xx_get_txgain_freq_power_amp(txpower);
+ pamp <<= 5;
+ pamp &= 0x00E0;
+ bcm43xx_phy_write(dev, 0x0019, pamp);
+
+ base = bcm43xx_get_txgain_base_band(txpower);
+ base &= 0x000F;
+ bcm43xx_phy_write(dev, 0x0017, base | 0x0020);
+
+ t = bcm43xx_ofdmtab_read16(dev, 0x3000, 1);
+ t &= 0x0007;
+
+ dac = bcm43xx_get_txgain_dac(txpower);
+ dac <<= 3;
+ dac |= t;
+
+ bcm43xx_ofdmtab_write16(dev, 0x3000, 1, dac);
+
+ phy->txpwr_offset = txpower;
+
+ TODO();
+ //TODO: FuncPlaceholder (Adjust BB loft cancel)
+}
+
+void bcm43xx_radio_set_txpower_bg(struct bcm43xx_wldev *dev,
+ s16 baseband_attenuation,
+ s16 radio_attenuation,
+ s16 _tx_magn)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ u8 tx_bias = phy->lo_control->tx_bias;
+ u8 tx_magn;
+
+ if (baseband_attenuation < 0)
+ baseband_attenuation = phy->bbatt;
+ if (radio_attenuation < 0)
+ radio_attenuation = phy->rfatt;
+ if (_tx_magn < 0)
+ _tx_magn = phy->lo_control->tx_magn;
+ tx_magn = _tx_magn;
+ phy->bbatt = baseband_attenuation;
+ phy->rfatt = radio_attenuation;
+
+ /* Set Baseband Attenuation on device. */
+ bcm43xx_phy_set_baseband_attenuation(dev, baseband_attenuation);
+
+ /* Set Radio Attenuation on device. */
+ bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+ 0x0064, radio_attenuation);
+ if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
+ bcm43xx_phy_write(dev, 0x0043, radio_attenuation);
+ } else {
+ bcm43xx_radio_write16(dev, 0x0043,
+ (bcm43xx_radio_read16(dev, 0x0043)
+ & 0xFFF0) | radio_attenuation);
+ }
+
+ if (phy->radio_ver == 0x2050) {//FIXME: It seems like tx_magn and tx_bias are swapped in this func.
+ if (phy->radio_rev < 6) {
+ bcm43xx_radio_write16(dev, 0x0043,
+ (bcm43xx_radio_read16(dev, 0x0043)
+ & 0xFF8F) | tx_magn);
+ } else if (phy->radio_rev != 8) {
+ bcm43xx_radio_write16(dev, 0x0052,
+ (bcm43xx_radio_read16(dev, 0x0052)
+ & 0xFF8F) | tx_magn);
+ } else {
+ bcm43xx_radio_write16(dev, 0x52,
+ (bcm43xx_radio_read16(dev, 0x52) & 0xFF00) |
+ tx_magn | tx_bias);
+ }
+ }
+ if (phy->radio_rev != 8) {
+ bcm43xx_radio_write16(dev, 0x0052,
+ (bcm43xx_radio_read16(dev, 0x0052)
+ & 0xFFF0) | tx_bias);
+ }
+ if (phy->type == BCM43xx_PHYTYPE_G)
+ bcm43xx_lo_g_adjust(dev);
+}
+
+u16 bcm43xx_default_baseband_attenuation(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
+ return 0;
+ return 2;
+}
+
+u16 bcm43xx_default_radio_attenuation(struct bcm43xx_wldev *dev)
+{
+ struct ssb_bus *bus = dev->dev->bus;
+ struct bcm43xx_phy *phy = &dev->phy;
+ u16 att = 0xFFFF;
+
+ if (phy->type == BCM43xx_PHYTYPE_A)
+ return 0x60;
+
+ switch (phy->radio_ver) {
+ case 0x2053:
+ switch (phy->radio_rev) {
+ case 1:
+ att = 6;
+ break;
+ }
+ break;
+ case 0x2050:
+ switch (phy->radio_rev) {
+ case 0:
+ att = 5;
+ break;
+ case 1:
+ if (phy->type == BCM43xx_PHYTYPE_G) {
+ if (bus->board_vendor == SSB_BOARDVENDOR_BCM &&
+ bus->board_type == SSB_BOARD_BCM4309G &&
+ bus->board_rev >= 30)
+ att = 3;
+ else if (bus->board_vendor == SSB_BOARDVENDOR_BCM &&
+ bus->board_type == SSB_BOARD_BU4306)
+ att = 3;
+ else
+ att = 1;
+ } else {
+ if (bus->board_vendor == SSB_BOARDVENDOR_BCM &&
+ bus->board_type == SSB_BOARD_BCM4309G &&
+ bus->board_rev >= 30)
+ att = 7;
+ else
+ att = 6;
+ }
+ break;
+ case 2:
+ if (phy->type == BCM43xx_PHYTYPE_G) {
+ if (bus->board_vendor == SSB_BOARDVENDOR_BCM &&
+ bus->board_type == SSB_BOARD_BCM4309G &&
+ bus->board_rev >= 30)
+ att = 3;
+ else if (bus->board_vendor == SSB_BOARDVENDOR_BCM &&
+ bus->board_type == SSB_BOARD_BU4306)
+ att = 5;
+ else if (bus->chip_id == 0x4320)
+ att = 4;
+ else
+ att = 3;
+ } else
+ att = 6;
+ break;
+ case 3:
+ att = 5;
+ break;
+ case 4:
+ case 5:
+ att = 1;
+ break;
+ case 6:
+ case 7:
+ att = 5;
+ break;
+ case 8:
+ att = 0x1A;
+ break;
+ case 9:
+ default:
+ att = 5;
+ }
+ }
+ if (bus->board_vendor == SSB_BOARDVENDOR_BCM &&
+ bus->board_type == SSB_BOARD_BCM4309G) {
+ if (bus->board_rev < 0x43)
+ att = 2;
+ else if (bus->board_rev < 0x51)
+ att = 3;
+ }
+ if (att == 0xFFFF)
+ att = 5;
+
+ return att;
+}
+
+u16 bcm43xx_default_txctl1(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ if (phy->radio_ver != 0x2050)
+ return 0;
+ if (phy->radio_rev == 1)
+ return 3;
+ if (phy->radio_rev < 6)
+ return 2;
+ if (phy->radio_rev == 8)
+ return 1;
+ return 0;
+}
+
+void bcm43xx_radio_turn_on(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ int err;
+
+ if (phy->radio_on)
+ return;
+
+ switch (phy->type) {
+ case BCM43xx_PHYTYPE_A:
+ bcm43xx_radio_write16(dev, 0x0004, 0x00C0);
+ bcm43xx_radio_write16(dev, 0x0005, 0x0008);
+ bcm43xx_phy_write(dev, 0x0010, bcm43xx_phy_read(dev, 0x0010) & 0xFFF7);
+ bcm43xx_phy_write(dev, 0x0011, bcm43xx_phy_read(dev, 0x0011) & 0xFFF7);
+ bcm43xx_radio_init2060(dev);
+ break;
+ case BCM43xx_PHYTYPE_B:
+ case BCM43xx_PHYTYPE_G:
+ bcm43xx_phy_write(dev, 0x0015, 0x8000);
+ bcm43xx_phy_write(dev, 0x0015, 0xCC00);
+ bcm43xx_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
+ err = bcm43xx_radio_selectchannel(dev, BCM43xx_DEFAULT_CHANNEL_BG, 1);
+ assert(err == 0);
+ break;
+ default:
+ assert(0);
+ }
+ phy->radio_on = 1;
+ dprintk(KERN_INFO PFX "Radio turned on\n");
+}
+
+void bcm43xx_radio_turn_off(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+
+ if (phy->type == BCM43xx_PHYTYPE_A) {
+ bcm43xx_radio_write16(dev, 0x0004, 0x00FF);
+ bcm43xx_radio_write16(dev, 0x0005, 0x00FB);
+ bcm43xx_phy_write(dev, 0x0010, bcm43xx_phy_read(dev, 0x0010) | 0x0008);
+ bcm43xx_phy_write(dev, 0x0011, bcm43xx_phy_read(dev, 0x0011) | 0x0008);
+ }
+ if (phy->type == BCM43xx_PHYTYPE_G && dev->dev->id.revision >= 5) {
+ bcm43xx_phy_write(dev, 0x0811, bcm43xx_phy_read(dev, 0x0811) | 0x008C);
+ bcm43xx_phy_write(dev, 0x0812, bcm43xx_phy_read(dev, 0x0812) & 0xFF73);
+ } else
+ bcm43xx_phy_write(dev, 0x0015, 0xAA00);
+ phy->radio_on = 0;
+ dprintk(KERN_INFO PFX "Radio turned off\n");
+}
--- /dev/null
+#ifndef BCM43xx_PHY_H_
+#define BCM43xx_PHY_H_
+
+#include <linux/types.h>
+
+struct bcm43xx_wldev;
+
+
+/*** PHY Registers ***/
+
+/* Routing */
+#define BCM43xx_PHYROUTE_OFDM_GPHY 0x400
+#define BCM43xx_PHYROUTE_EXT_GPHY 0x800
+
+/* Base registers. */
+#define BCM43xx_PHY_BASE(reg) (reg)
+/* OFDM (A) registers of a G-PHY */
+#define BCM43xx_PHY_OFDM(reg) ((reg) | BCM43xx_PHYROUTE_OFDM_GPHY)
+/* Extended G-PHY registers */
+#define BCM43xx_PHY_EXTG(reg) ((reg) | BCM43xx_PHYROUTE_EXT_GPHY)
+
+
+/* OFDM (A) PHY Registers */
+#define BCM43xx_PHY_VERSION_OFDM BCM43xx_PHY_OFDM(0x00) /* Versioning register for A-PHY */
+#define BCM43xx_PHY_BBANDCFG BCM43xx_PHY_OFDM(0x01) /* Baseband config */
+#define BCM43xx_PHY_BBANDCFG_RXANT 0x180 /* RX Antenna selection */
+#define BCM43xx_PHY_BBANDCFG_RXANT_SHIFT 7
+#define BCM43xx_PHY_PWRDOWN BCM43xx_PHY_OFDM(0x03) /* Powerdown */
+#define BCM43xx_PHY_CRSTHRES1 BCM43xx_PHY_OFDM(0x06) /* CRS Threshold 1 */
+#define BCM43xx_PHY_LNAHPFCTL BCM43xx_PHY_OFDM(0x1C) /* LNA/HPF control */
+#define BCM43xx_PHY_ADIVRELATED BCM43xx_PHY_OFDM(0x27) /* FIXME rename */
+#define BCM43xx_PHY_CRS0 BCM43xx_PHY_OFDM(0x29)
+#define BCM43xx_PHY_ANTDWELL BCM43xx_PHY_OFDM(0x2B) /* Antenna dwell */
+#define BCM43xx_PHY_ANTDWELL_AUTODIV1 0x0100 /* Automatic RX diversity start antenna */
+#define BCM43xx_PHY_ENCORE BCM43xx_PHY_OFDM(0x49) /* "Encore" (RangeMax / BroadRange) */
+#define BCM43xx_PHY_ENCORE_EN 0x0200 /* Encore enable */
+#define BCM43xx_PHY_LMS BCM43xx_PHY_OFDM(0x55)
+#define BCM43xx_PHY_OFDM61 BCM43xx_PHY_OFDM(0x61) /* FIXME rename */
+#define BCM43xx_PHY_OFDM61_10 0x0010 /* FIXME rename */
+#define BCM43xx_PHY_IQBAL BCM43xx_PHY_OFDM(0x69) /* I/Q balance */
+#define BCM43xx_PHY_OTABLECTL BCM43xx_PHY_OFDM(0x72) /* OFDM table control (see below) */
+#define BCM43xx_PHY_OTABLEOFF 0x03FF /* OFDM table offset (see below) */
+#define BCM43xx_PHY_OTABLENR 0xFC00 /* OFDM table number (see below) */
+#define BCM43xx_PHY_OTABLENR_SHIFT 10
+#define BCM43xx_PHY_OTABLEI BCM43xx_PHY_OFDM(0x73) /* OFDM table data I */
+#define BCM43xx_PHY_OTABLEQ BCM43xx_PHY_OFDM(0x74) /* OFDM table data Q */
+#define BCM43xx_PHY_HPWR_TSSICTL BCM43xx_PHY_OFDM(0x78) /* Hardware power TSSI control */
+#define BCM43xx_PHY_NRSSITHRES BCM43xx_PHY_OFDM(0x8A) /* NRSSI threshold */
+#define BCM43xx_PHY_ANTWRSETT BCM43xx_PHY_OFDM(0x8C) /* Antenna WR settle */
+#define BCM43xx_PHY_ANTWRSETT_ARXDIV 0x2000 /* Automatic RX diversity enabled */
+#define BCM43xx_PHY_CLIPPWRDOWNT BCM43xx_PHY_OFDM(0x93) /* Clip powerdown threshold */
+#define BCM43xx_PHY_OFDM9B BCM43xx_PHY_OFDM(0x9B) /* FIXME rename */
+#define BCM43xx_PHY_N1P1GAIN BCM43xx_PHY_OFDM(0xA0)
+#define BCM43xx_PHY_P1P2GAIN BCM43xx_PHY_OFDM(0xA1)
+#define BCM43xx_PHY_N1N2GAIN BCM43xx_PHY_OFDM(0xA2)
+#define BCM43xx_PHY_CLIPTHRES BCM43xx_PHY_OFDM(0xA3)
+#define BCM43xx_PHY_CLIPN1P2THRES BCM43xx_PHY_OFDM(0xA4)
+#define BCM43xx_PHY_DIVSRCHIDX BCM43xx_PHY_OFDM(0xA8) /* Divider search gain/index */
+#define BCM43xx_PHY_CLIPP2THRES BCM43xx_PHY_OFDM(0xA9)
+#define BCM43xx_PHY_CLIPP3THRES BCM43xx_PHY_OFDM(0xAA)
+#define BCM43xx_PHY_DIVP1P2GAIN BCM43xx_PHY_OFDM(0xAB)
+#define BCM43xx_PHY_DIVSRCHGAINBACK BCM43xx_PHY_OFDM(0xAD) /* Divider search gain back */
+#define BCM43xx_PHY_DIVSRCHGAINCHNG BCM43xx_PHY_OFDM(0xAE) /* Divider search gain change */
+#define BCM43xx_PHY_CRSTHRES1_R1 BCM43xx_PHY_OFDM(0xC0) /* CRS Threshold 1 (rev 1 only) */
+#define BCM43xx_PHY_CRSTHRES2_R1 BCM43xx_PHY_OFDM(0xC1) /* CRS Threshold 2 (rev 1 only) */
+#define BCM43xx_PHY_TSSIP_LTBASE BCM43xx_PHY_OFDM(0x380) /* TSSI power lookup table base */
+#define BCM43xx_PHY_DC_LTBASE BCM43xx_PHY_OFDM(0x3A0) /* DC lookup table base */
+#define BCM43xx_PHY_GAIN_LTBASE BCM43xx_PHY_OFDM(0x3C0) /* Gain lookup table base */
+
+/* CCK (B) PHY Registers */
+#define BCM43xx_PHY_VERSION_CCK BCM43xx_PHY_BASE(0x00) /* Versioning register for B-PHY */
+#define BCM43xx_PHY_CCKBBANDCFG BCM43xx_PHY_BASE(0x01) /* Contains antenna 0/1 control bit */
+#define BCM43xx_PHY_PGACTL BCM43xx_PHY_BASE(0x15) /* PGA control */
+#define BCM43xx_PHY_PGACTL_LPF 0x1000 /* Low pass filter (?) */
+#define BCM43xx_PHY_PGACTL_LOWBANDW 0x0040 /* Low bandwidth flag */
+#define BCM43xx_PHY_PGACTL_UNKNOWN 0xEFA0
+#define BCM43xx_PHY_FBCTL1 BCM43xx_PHY_BASE(0x18) /* Frequency bandwidth control 1 */
+#define BCM43xx_PHY_ITSSI BCM43xx_PHY_BASE(0x29) /* Idle TSSI */
+#define BCM43xx_PHY_LO_LEAKAGE BCM43xx_PHY_BASE(0x2D) /* Measured LO leakage */
+#define BCM43xx_PHY_ENERGY BCM43xx_PHY_BASE(0x33) /* Energy */
+#define BCM43xx_PHY_SYNCCTL BCM43xx_PHY_BASE(0x35)
+#define BCM43xx_PHY_FBCTL2 BCM43xx_PHY_BASE(0x38) /* Frequency bandwidth control 2 */
+#define BCM43xx_PHY_DACCTL BCM43xx_PHY_BASE(0x60) /* DAC control */
+#define BCM43xx_PHY_RCCALOVER BCM43xx_PHY_BASE(0x78) /* RC calibration override */
+
+/* Extended G-PHY Registers */
+#define BCM43xx_PHY_CLASSCTL BCM43xx_PHY_EXTG(0x02) /* Classify control */
+#define BCM43xx_PHY_GTABCTL BCM43xx_PHY_EXTG(0x03) /* G-PHY table control (see below) */
+#define BCM43xx_PHY_GTABOFF 0x03FF /* G-PHY table offset (see below) */
+#define BCM43xx_PHY_GTABNR 0xFC00 /* G-PHY table number (see below) */
+#define BCM43xx_PHY_GTABNR_SHIFT 10
+#define BCM43xx_PHY_GTABDATA BCM43xx_PHY_EXTG(0x04) /* G-PHY table data */
+#define BCM43xx_PHY_LO_MASK BCM43xx_PHY_EXTG(0x0F) /* Local Oscillator control mask */
+#define BCM43xx_PHY_LO_CTL BCM43xx_PHY_EXTG(0x10) /* Local Oscillator control */
+#define BCM43xx_PHY_RFOVER BCM43xx_PHY_EXTG(0x11) /* RF override */
+#define BCM43xx_PHY_RFOVERVAL BCM43xx_PHY_EXTG(0x12) /* RF override value */
+#define BCM43xx_PHY_RFOVERVAL_EXTLNA 0x8000
+#define BCM43xx_PHY_RFOVERVAL_LNA 0x7000
+#define BCM43xx_PHY_RFOVERVAL_LNA_SHIFT 12
+#define BCM43xx_PHY_RFOVERVAL_PGA 0x0F00
+#define BCM43xx_PHY_RFOVERVAL_PGA_SHIFT 8
+#define BCM43xx_PHY_RFOVERVAL_UNK 0x0010 /* Unknown, always set. */
+#define BCM43xx_PHY_RFOVERVAL_TRSWRX 0x00E0
+#define BCM43xx_PHY_RFOVERVAL_BW 0x0003 /* Bandwidth flags */
+#define BCM43xx_PHY_RFOVERVAL_BW_LPF 0x0001 /* Low Pass Filter */
+#define BCM43xx_PHY_RFOVERVAL_BW_LBW 0x0002 /* Low Bandwidth (when set), high when unset */
+#define BCM43xx_PHY_ANALOGOVER BCM43xx_PHY_EXTG(0x14) /* Analog override */
+#define BCM43xx_PHY_ANALOGOVERVAL BCM43xx_PHY_EXTG(0x15) /* Analog override value */
+
+
+
+/*** OFDM table numbers ***/
+#define BCM43xx_OFDMTAB(number, offset) (((number) << BCM43xx_PHY_OTABLENR_SHIFT) | (offset))
+#define BCM43xx_OFDMTAB_AGC1 BCM43xx_OFDMTAB(0x00, 0)
+#define BCM43xx_OFDMTAB_GAIN0 BCM43xx_OFDMTAB(0x00, 0)
+#define BCM43xx_OFDMTAB_GAINX BCM43xx_OFDMTAB(0x01, 0) //TODO rename
+#define BCM43xx_OFDMTAB_GAIN1 BCM43xx_OFDMTAB(0x01, 4)
+#define BCM43xx_OFDMTAB_AGC3 BCM43xx_OFDMTAB(0x02, 0)
+#define BCM43xx_OFDMTAB_GAIN2 BCM43xx_OFDMTAB(0x02, 3)
+#define BCM43xx_OFDMTAB_LNAHPFGAIN1 BCM43xx_OFDMTAB(0x03, 0)
+#define BCM43xx_OFDMTAB_WRSSI BCM43xx_OFDMTAB(0x04, 0)
+#define BCM43xx_OFDMTAB_LNAHPFGAIN2 BCM43xx_OFDMTAB(0x04, 0)
+#define BCM43xx_OFDMTAB_NOISESCALE BCM43xx_OFDMTAB(0x05, 0)
+#define BCM43xx_OFDMTAB_AGC2 BCM43xx_OFDMTAB(0x06, 0)
+#define BCM43xx_OFDMTAB_ROTOR BCM43xx_OFDMTAB(0x08, 0)
+#define BCM43xx_OFDMTAB_ADVRETARD BCM43xx_OFDMTAB(0x09, 0)
+#define BCM43xx_OFDMTAB_DAC BCM43xx_OFDMTAB(0x0C, 0)
+#define BCM43xx_OFDMTAB_DC BCM43xx_OFDMTAB(0x0E, 7)
+#define BCM43xx_OFDMTAB_PWRDYN2 BCM43xx_OFDMTAB(0x0E, 12)
+#define BCM43xx_OFDMTAB_LNAGAIN BCM43xx_OFDMTAB(0x0E, 13)
+//TODO
+#define BCM43xx_OFDMTAB_LPFGAIN BCM43xx_OFDMTAB(0x0F, 12)
+#define BCM43xx_OFDMTAB_RSSI BCM43xx_OFDMTAB(0x10, 0)
+//TODO
+#define BCM43xx_OFDMTAB_AGC1_R1 BCM43xx_OFDMTAB(0x13, 0)
+#define BCM43xx_OFDMTAB_GAINX_R1 BCM43xx_OFDMTAB(0x14, 0) //TODO rename
+#define BCM43xx_OFDMTAB_MINSIGSQ BCM43xx_OFDMTAB(0x14, 1)
+#define BCM43xx_OFDMTAB_AGC3_R1 BCM43xx_OFDMTAB(0x15, 0)
+#define BCM43xx_OFDMTAB_WRSSI_R1 BCM43xx_OFDMTAB(0x15, 4)
+#define BCM43xx_OFDMTAB_TSSI BCM43xx_OFDMTAB(0x15, 0)
+#define BCM43xx_OFDMTAB_DACRFPABB BCM43xx_OFDMTAB(0x16, 0)
+#define BCM43xx_OFDMTAB_DACOFF BCM43xx_OFDMTAB(0x17, 0)
+#define BCM43xx_OFDMTAB_DCBIAS BCM43xx_OFDMTAB(0x18, 0)
+
+u16 bcm43xx_ofdmtab_read16(struct bcm43xx_wldev *dev, u16 table, u16 offset);
+void bcm43xx_ofdmtab_write16(struct bcm43xx_wldev *dev, u16 table,
+ u16 offset, u16 value);
+u32 bcm43xx_ofdmtab_read32(struct bcm43xx_wldev *dev, u16 table, u16 offset);
+void bcm43xx_ofdmtab_write32(struct bcm43xx_wldev *dev, u16 table,
+ u16 offset, u32 value);
+
+
+/*** G-PHY table numbers */
+#define BCM43xx_GTAB(number, offset) (((number) << BCM43xx_PHY_GTABNR_SHIFT) | (offset))
+#define BCM43xx_GTAB_NRSSI BCM43xx_GTAB(0x00, 0)
+#define BCM43xx_GTAB_TRFEMW BCM43xx_GTAB(0x0C, 0x120)
+#define BCM43xx_GTAB_ORIGTR BCM43xx_GTAB(0x2E, 0x298)
+
+u16 bcm43xx_gtab_read(struct bcm43xx_wldev *dev, u16 table, u16 offset); //TODO implement
+void bcm43xx_gtab_write(struct bcm43xx_wldev *dev, u16 table,
+ u16 offset, u16 value); //TODO implement
+
+
+
+#define BCM43xx_DEFAULT_CHANNEL_A 36
+#define BCM43xx_DEFAULT_CHANNEL_BG 6
+
+enum {
+ BCM43xx_ANTENNA0, /* Antenna 0 */
+ BCM43xx_ANTENNA1, /* Antenna 0 */
+ BCM43xx_ANTENNA_AUTO1, /* Automatic, starting with antenna 1 */
+ BCM43xx_ANTENNA_AUTO0, /* Automatic, starting with antenna 0 */
+
+ BCM43xx_ANTENNA_AUTO = BCM43xx_ANTENNA_AUTO0,
+ BCM43xx_ANTENNA_DEFAULT = BCM43xx_ANTENNA_AUTO,
+};
+
+enum {
+ BCM43xx_INTERFMODE_NONE,
+ BCM43xx_INTERFMODE_NONWLAN,
+ BCM43xx_INTERFMODE_MANUALWLAN,
+ BCM43xx_INTERFMODE_AUTOWLAN,
+};
+
+
+/* Masks for the different PHY versioning registers. */
+#define BCM43xx_PHYVER_ANALOG 0xF000
+#define BCM43xx_PHYVER_ANALOG_SHIFT 12
+#define BCM43xx_PHYVER_TYPE 0x0F00
+#define BCM43xx_PHYVER_TYPE_SHIFT 8
+#define BCM43xx_PHYVER_VERSION 0x00FF
+
+
+void bcm43xx_raw_phy_lock(struct bcm43xx_wldev *dev);
+#define bcm43xx_phy_lock(dev, flags) \
+ do { \
+ local_irq_save(flags); \
+ bcm43xx_raw_phy_lock(dev); \
+ } while (0)
+void bcm43xx_raw_phy_unlock(struct bcm43xx_wldev *dev);
+#define bcm43xx_phy_unlock(dev, flags) \
+ do { \
+ bcm43xx_raw_phy_unlock(dev); \
+ local_irq_restore(flags); \
+ } while (0)
+
+u16 bcm43xx_phy_read(struct bcm43xx_wldev *dev, u16 offset);
+void bcm43xx_phy_write(struct bcm43xx_wldev *dev, u16 offset, u16 val);
+
+int bcm43xx_phy_init_tssi2dbm_table(struct bcm43xx_wldev *dev);
+
+void bcm43xx_phy_early_init(struct bcm43xx_wldev *dev);
+int bcm43xx_phy_init(struct bcm43xx_wldev *dev);
+
+void bcm43xx_set_rx_antenna(struct bcm43xx_wldev *dev, int antenna);
+
+void bcm43xx_phy_xmitpower(struct bcm43xx_wldev *dev);
+void bcm43xx_gphy_dc_lt_init(struct bcm43xx_wldev *dev);
+
+/* Returns the boolean whether the board has HardwarePowerControl */
+#define has_hardware_pctl(phy) \
+ (((phy)->type == BCM43xx_PHYTYPE_A && (phy)->rev >= 5) || \
+ ((phy)->type == BCM43xx_PHYTYPE_G && (phy)->rev >= 6))
+/* Returns the boolean whether "TX Magnification" is enabled. */
+#define has_tx_magnification(phy) \
+ (((phy)->rev >= 2) && \
+ ((phy)->radio_ver == 0x2050) && \
+ ((phy)->radio_rev == 8))
+/* Card uses the loopback gain stuff */
+#define has_loopback_gain(phy) \
+ (((phy)->rev > 1) || ((phy)->gmode))
+
+/* Radio Attenuation (RF Attenuation) */
+struct bcm43xx_rfatt {
+ u8 att; /* Attenuation value */
+ u8 with_padmix; /* Flag, PAD Mixer enabled. */
+};
+struct bcm43xx_rfatt_list {
+ /* Attenuation values list */
+ const struct bcm43xx_rfatt *list;
+ u8 len;
+ /* Minimum/Maximum attenuation values */
+ u8 min_val;
+ u8 max_val;
+};
+
+/* Baseband Attenuation */
+struct bcm43xx_bbatt {
+ u8 att; /* Attenuation value */
+};
+struct bcm43xx_bbatt_list {
+ /* Attenuation values list */
+ const struct bcm43xx_bbatt *list;
+ u8 len;
+ /* Minimum/Maximum attenuation values */
+ u8 min_val;
+ u8 max_val;
+};
+
+/* Write BasebandAttenuation value to the device. */
+void bcm43xx_phy_set_baseband_attenuation(struct bcm43xx_wldev *dev,
+ u16 baseband_attenuation);
+
+
+extern const u8 bcm43xx_radio_channel_codes_bg[];
+
+void bcm43xx_radio_lock(struct bcm43xx_wldev *dev);
+void bcm43xx_radio_unlock(struct bcm43xx_wldev *dev);
+
+u16 bcm43xx_radio_read16(struct bcm43xx_wldev *dev, u16 offset);
+void bcm43xx_radio_write16(struct bcm43xx_wldev *dev, u16 offset, u16 val);
+
+u16 bcm43xx_radio_init2050(struct bcm43xx_wldev *dev);
+void bcm43xx_radio_init2060(struct bcm43xx_wldev *dev);
+
+void bcm43xx_radio_turn_on(struct bcm43xx_wldev *dev);
+void bcm43xx_radio_turn_off(struct bcm43xx_wldev *dev);
+
+int bcm43xx_radio_selectchannel(struct bcm43xx_wldev *dev, u8 channel,
+ int synthetic_pu_workaround);
+
+void bcm43xx_radio_set_txpower_a(struct bcm43xx_wldev *dev, u16 txpower);
+/* Set the txpower on device. If the values are < 0, use the saved ones. */
+void bcm43xx_radio_set_txpower_bg(struct bcm43xx_wldev *dev,
+ s16 baseband_attenuation,
+ s16 radio_attenuation,
+ s16 txctl1);
+
+u16 bcm43xx_default_baseband_attenuation(struct bcm43xx_wldev *dev);
+u16 bcm43xx_default_radio_attenuation(struct bcm43xx_wldev *dev);
+u16 bcm43xx_default_txctl1(struct bcm43xx_wldev *dev);
+
+u8 bcm43xx_radio_aci_detect(struct bcm43xx_wldev *dev, u8 channel);
+u8 bcm43xx_radio_aci_scan(struct bcm43xx_wldev *dev);
+
+int bcm43xx_radio_set_interference_mitigation(struct bcm43xx_wldev *dev, int mode);
+
+void bcm43xx_calc_nrssi_slope(struct bcm43xx_wldev *dev);
+void bcm43xx_calc_nrssi_threshold(struct bcm43xx_wldev *dev);
+s16 bcm43xx_nrssi_hw_read(struct bcm43xx_wldev *dev, u16 offset);
+void bcm43xx_nrssi_hw_write(struct bcm43xx_wldev *dev, u16 offset, s16 val);
+void bcm43xx_nrssi_hw_update(struct bcm43xx_wldev *dev, u16 val);
+void bcm43xx_nrssi_mem_update(struct bcm43xx_wldev *dev);
+
+void bcm43xx_radio_set_tx_iq(struct bcm43xx_wldev *dev);
+u16 bcm43xx_radio_calibrationvalue(struct bcm43xx_wldev *dev);
+
+
+#endif /* BCM43xx_PHY_H_ */
--- /dev/null
+/*
+
+ Broadcom BCM43xx wireless driver
+
+ PIO Transmission
+
+ Copyright (c) 2005 Michael Buesch <mb@bu3sch.de>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING. If not, write to
+ the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+ Boston, MA 02110-1301, USA.
+
+*/
+
+#include "bcm43xx.h"
+#include "bcm43xx_pio.h"
+#include "bcm43xx_main.h"
+#include "bcm43xx_xmit.h"
+#include "bcm43xx_power.h"
+
+#include <linux/delay.h>
+
+
+static void tx_start(struct bcm43xx_pioqueue *queue)
+{
+ bcm43xx_pio_write(queue, BCM43xx_PIO_TXCTL,
+ BCM43xx_PIO_TXCTL_INIT);
+}
+
+static void tx_octet(struct bcm43xx_pioqueue *queue,
+ u8 octet)
+{
+ if (queue->need_workarounds) {
+ bcm43xx_pio_write(queue, BCM43xx_PIO_TXDATA,
+ octet);
+ bcm43xx_pio_write(queue, BCM43xx_PIO_TXCTL,
+ BCM43xx_PIO_TXCTL_WRITELO);
+ } else {
+ bcm43xx_pio_write(queue, BCM43xx_PIO_TXCTL,
+ BCM43xx_PIO_TXCTL_WRITELO);
+ bcm43xx_pio_write(queue, BCM43xx_PIO_TXDATA,
+ octet);
+ }
+}
+
+static u16 tx_get_next_word(const u8 *txhdr,
+ const u8 *packet,
+ size_t txhdr_size,
+ unsigned int *pos)
+{
+ const u8 *source;
+ unsigned int i = *pos;
+ u16 ret;
+
+ if (i < txhdr_size) {
+ source = txhdr;
+ } else {
+ source = packet;
+ i -= txhdr_size;
+ }
+ ret = le16_to_cpu( *((u16 *)(source + i)) );
+ *pos += 2;
+
+ return ret;
+}
+
+static void tx_data(struct bcm43xx_pioqueue *queue,
+ u8 *txhdr,
+ const u8 *packet,
+ unsigned int octets)
+{
+ u16 data;
+ unsigned int i = 0;
+
+ if (queue->need_workarounds) {
+ data = tx_get_next_word(txhdr, packet,
+ sizeof(struct bcm43xx_txhdr_fw4), &i);
+ bcm43xx_pio_write(queue, BCM43xx_PIO_TXDATA, data);
+ }
+ bcm43xx_pio_write(queue, BCM43xx_PIO_TXCTL,
+ BCM43xx_PIO_TXCTL_WRITELO |
+ BCM43xx_PIO_TXCTL_WRITEHI);
+ while (i < octets - 1) {
+ data = tx_get_next_word(txhdr, packet,
+ sizeof(struct bcm43xx_txhdr_fw4), &i);
+ bcm43xx_pio_write(queue, BCM43xx_PIO_TXDATA, data);
+ }
+ if (octets % 2)
+ tx_octet(queue, packet[octets - sizeof(struct bcm43xx_txhdr_fw4) - 1]);
+}
+
+static void tx_complete(struct bcm43xx_pioqueue *queue,
+ struct sk_buff *skb)
+{
+ if (queue->need_workarounds) {
+ bcm43xx_pio_write(queue, BCM43xx_PIO_TXDATA,
+ skb->data[skb->len - 1]);
+ bcm43xx_pio_write(queue, BCM43xx_PIO_TXCTL,
+ BCM43xx_PIO_TXCTL_WRITELO |
+ BCM43xx_PIO_TXCTL_COMPLETE);
+ } else {
+ bcm43xx_pio_write(queue, BCM43xx_PIO_TXCTL,
+ BCM43xx_PIO_TXCTL_COMPLETE);
+ }
+}
+
+static u16 generate_cookie(struct bcm43xx_pioqueue *queue,
+ struct bcm43xx_pio_txpacket *packet)
+{
+ u16 cookie = 0x0000;
+ int packetindex;
+
+ /* We use the upper 4 bits for the PIO
+ * controller ID and the lower 12 bits
+ * for the packet index (in the cache).
+ */
+ switch (queue->mmio_base) {
+ case BCM43xx_MMIO_PIO1_BASE:
+ break;
+ case BCM43xx_MMIO_PIO2_BASE:
+ cookie = 0x1000;
+ break;
+ case BCM43xx_MMIO_PIO3_BASE:
+ cookie = 0x2000;
+ break;
+ case BCM43xx_MMIO_PIO4_BASE:
+ cookie = 0x3000;
+ break;
+ default:
+ assert(0);
+ }
+ packetindex = pio_txpacket_getindex(packet);
+ assert(((u16)packetindex & 0xF000) == 0x0000);
+ cookie |= (u16)packetindex;
+
+ return cookie;
+}
+
+static
+struct bcm43xx_pioqueue * parse_cookie(struct bcm43xx_wldev *dev,
+ u16 cookie,
+ struct bcm43xx_pio_txpacket **packet)
+{
+ struct bcm43xx_pio *pio = &dev->pio;
+ struct bcm43xx_pioqueue *queue = NULL;
+ int packetindex;
+
+ switch (cookie & 0xF000) {
+ case 0x0000:
+ queue = pio->queue0;
+ break;
+ case 0x1000:
+ queue = pio->queue1;
+ break;
+ case 0x2000:
+ queue = pio->queue2;
+ break;
+ case 0x3000:
+ queue = pio->queue3;
+ break;
+ default:
+ assert(0);
+ }
+ packetindex = (cookie & 0x0FFF);
+ assert(packetindex >= 0 && packetindex < BCM43xx_PIO_MAXTXPACKETS);
+ *packet = &(queue->tx_packets_cache[packetindex]);
+
+ return queue;
+}
+
+union txhdr_union {
+ struct bcm43xx_txhdr_fw4 txhdr_fw4;
+};
+
+static void pio_tx_write_fragment(struct bcm43xx_pioqueue *queue,
+ struct sk_buff *skb,
+ struct bcm43xx_pio_txpacket *packet,
+ size_t txhdr_size)
+{
+ union txhdr_union txhdr_data;
+ u8 *txhdr = NULL;
+ unsigned int octets;
+
+ txhdr = (u8 *)(&txhdr_data.txhdr_fw4);
+
+ assert(skb_shinfo(skb)->nr_frags == 0);
+ bcm43xx_generate_txhdr(queue->dev,
+ txhdr, skb->data, skb->len,
+ &packet->txstat.control,
+ generate_cookie(queue, packet));
+
+ tx_start(queue);
+ octets = skb->len + txhdr_size;
+ if (queue->need_workarounds)
+ octets--;
+ tx_data(queue, txhdr, (u8 *)skb->data, octets);
+ tx_complete(queue, skb);
+}
+
+static void free_txpacket(struct bcm43xx_pio_txpacket *packet,
+ int irq_context)
+{
+ struct bcm43xx_pioqueue *queue = packet->queue;
+
+ if (packet->skb) {
+ if (irq_context)
+ dev_kfree_skb_irq(packet->skb);
+ else
+ dev_kfree_skb(packet->skb);
+ }
+ list_move(&packet->list, &queue->txfree);
+ queue->nr_txfree++;
+}
+
+static int pio_tx_packet(struct bcm43xx_pio_txpacket *packet)
+{
+ struct bcm43xx_pioqueue *queue = packet->queue;
+ struct sk_buff *skb = packet->skb;
+ u16 octets;
+
+ octets = (u16)skb->len + sizeof(struct bcm43xx_txhdr_fw4);
+ if (queue->tx_devq_size < octets) {
+ printkl(KERN_WARNING PFX "PIO queue too small. "
+ "Dropping packet.\n");
+ /* Drop it silently (return success) */
+ free_txpacket(packet, 1);
+ return 0;
+ }
+ assert(queue->tx_devq_packets <= BCM43xx_PIO_MAXTXDEVQPACKETS);
+ assert(queue->tx_devq_used <= queue->tx_devq_size);
+ /* Check if there is sufficient free space on the device
+ * TX queue. If not, return and let the TX tasklet
+ * retry later.
+ */
+ if (queue->tx_devq_packets == BCM43xx_PIO_MAXTXDEVQPACKETS)
+ return -EBUSY;
+ if (queue->tx_devq_used + octets > queue->tx_devq_size)
+ return -EBUSY;
+ /* Now poke the device. */
+ pio_tx_write_fragment(queue, skb, packet, sizeof(struct bcm43xx_txhdr_fw4));
+
+ /* Account for the packet size.
+ * (We must not overflow the device TX queue)
+ */
+ queue->tx_devq_packets++;
+ queue->tx_devq_used += octets;
+
+ /* Transmission started, everything ok, move the
+ * packet to the txrunning list.
+ */
+ list_move_tail(&packet->list, &queue->txrunning);
+
+ return 0;
+}
+
+static void tx_tasklet(unsigned long d)
+{
+ struct bcm43xx_pioqueue *queue = (struct bcm43xx_pioqueue *)d;
+ struct bcm43xx_wldev *dev = queue->dev;
+ unsigned long flags;
+ struct bcm43xx_pio_txpacket *packet, *tmp_packet;
+ int err;
+ u16 txctl;
+
+ spin_lock_irqsave(&dev->wl->irq_lock, flags);
+ if (queue->tx_frozen)
+ goto out_unlock;
+ txctl = bcm43xx_pio_read(queue, BCM43xx_PIO_TXCTL);
+ if (txctl & BCM43xx_PIO_TXCTL_SUSPEND)
+ goto out_unlock;
+
+ list_for_each_entry_safe(packet, tmp_packet, &queue->txqueue, list) {
+ /* Try to transmit the packet. This can fail, if
+ * the device queue is full. In case of failure, the
+ * packet is left in the txqueue.
+ * If transmission succeed, the packet is moved to txrunning.
+ * If it is impossible to transmit the packet, it
+ * is dropped.
+ */
+ err = pio_tx_packet(packet);
+ if (err)
+ break;
+ }
+out_unlock:
+ spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+}
+
+static void setup_txqueues(struct bcm43xx_pioqueue *queue)
+{
+ struct bcm43xx_pio_txpacket *packet;
+ int i;
+
+ queue->nr_txfree = BCM43xx_PIO_MAXTXPACKETS;
+ for (i = 0; i < BCM43xx_PIO_MAXTXPACKETS; i++) {
+ packet = &(queue->tx_packets_cache[i]);
+
+ packet->queue = queue;
+ INIT_LIST_HEAD(&packet->list);
+
+ list_add(&packet->list, &queue->txfree);
+ }
+}
+
+static
+struct bcm43xx_pioqueue * bcm43xx_setup_pioqueue(struct bcm43xx_wldev *dev,
+ u16 pio_mmio_base)
+{
+ struct bcm43xx_pioqueue *queue;
+ u32 value;
+ u16 qsize;
+
+ queue = kzalloc(sizeof(*queue), GFP_KERNEL);
+ if (!queue)
+ goto out;
+
+ queue->dev = dev;
+ queue->mmio_base = pio_mmio_base;
+ queue->need_workarounds = (dev->dev->id.revision < 3);
+
+ INIT_LIST_HEAD(&queue->txfree);
+ INIT_LIST_HEAD(&queue->txqueue);
+ INIT_LIST_HEAD(&queue->txrunning);
+ tasklet_init(&queue->txtask, tx_tasklet,
+ (unsigned long)queue);
+
+ value = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
+ value &= ~BCM43xx_SBF_XFER_REG_BYTESWAP;
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, value);
+
+ qsize = bcm43xx_read16(dev, queue->mmio_base + BCM43xx_PIO_TXQBUFSIZE);
+ if (qsize == 0) {
+ printk(KERN_ERR PFX "ERROR: This card does not support PIO "
+ "operation mode. Please use DMA mode "
+ "(module parameter pio=0).\n");
+ goto err_freequeue;
+ }
+ if (qsize <= BCM43xx_PIO_TXQADJUST) {
+ printk(KERN_ERR PFX "PIO tx device-queue too small (%u)\n",
+ qsize);
+ goto err_freequeue;
+ }
+ qsize -= BCM43xx_PIO_TXQADJUST;
+ queue->tx_devq_size = qsize;
+
+ setup_txqueues(queue);
+
+out:
+ return queue;
+
+err_freequeue:
+ kfree(queue);
+ queue = NULL;
+ goto out;
+}
+
+static void cancel_transfers(struct bcm43xx_pioqueue *queue)
+{
+ struct bcm43xx_pio_txpacket *packet, *tmp_packet;
+
+ tasklet_disable(&queue->txtask);
+
+ list_for_each_entry_safe(packet, tmp_packet, &queue->txrunning, list)
+ free_txpacket(packet, 0);
+ list_for_each_entry_safe(packet, tmp_packet, &queue->txqueue, list)
+ free_txpacket(packet, 0);
+}
+
+static void bcm43xx_destroy_pioqueue(struct bcm43xx_pioqueue *queue)
+{
+ if (!queue)
+ return;
+
+ cancel_transfers(queue);
+ kfree(queue);
+}
+
+void bcm43xx_pio_free(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_pio *pio;
+
+ if (!bcm43xx_using_pio(dev))
+ return;
+ pio = &dev->pio;
+
+ bcm43xx_destroy_pioqueue(pio->queue3);
+ pio->queue3 = NULL;
+ bcm43xx_destroy_pioqueue(pio->queue2);
+ pio->queue2 = NULL;
+ bcm43xx_destroy_pioqueue(pio->queue1);
+ pio->queue1 = NULL;
+ bcm43xx_destroy_pioqueue(pio->queue0);
+ pio->queue0 = NULL;
+}
+
+int bcm43xx_pio_init(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_pio *pio = &dev->pio;
+ struct bcm43xx_pioqueue *queue;
+ int err = -ENOMEM;
+
+ queue = bcm43xx_setup_pioqueue(dev, BCM43xx_MMIO_PIO1_BASE);
+ if (!queue)
+ goto out;
+ pio->queue0 = queue;
+
+ queue = bcm43xx_setup_pioqueue(dev, BCM43xx_MMIO_PIO2_BASE);
+ if (!queue)
+ goto err_destroy0;
+ pio->queue1 = queue;
+
+ queue = bcm43xx_setup_pioqueue(dev, BCM43xx_MMIO_PIO3_BASE);
+ if (!queue)
+ goto err_destroy1;
+ pio->queue2 = queue;
+
+ queue = bcm43xx_setup_pioqueue(dev, BCM43xx_MMIO_PIO4_BASE);
+ if (!queue)
+ goto err_destroy2;
+ pio->queue3 = queue;
+
+ if (dev->dev->id.revision < 3)
+ dev->irq_savedstate |= BCM43xx_IRQ_PIO_WORKAROUND;
+
+ dprintk(KERN_INFO PFX "PIO initialized\n");
+ err = 0;
+out:
+ return err;
+
+err_destroy2:
+ bcm43xx_destroy_pioqueue(pio->queue2);
+ pio->queue2 = NULL;
+err_destroy1:
+ bcm43xx_destroy_pioqueue(pio->queue1);
+ pio->queue1 = NULL;
+err_destroy0:
+ bcm43xx_destroy_pioqueue(pio->queue0);
+ pio->queue0 = NULL;
+ goto out;
+}
+
+int bcm43xx_pio_tx(struct bcm43xx_wldev *dev,
+ struct sk_buff *skb,
+ struct ieee80211_tx_control *ctl)
+{
+ struct bcm43xx_pioqueue *queue = dev->pio.queue1;
+ struct bcm43xx_pio_txpacket *packet;
+
+ assert(!queue->tx_suspended);
+ assert(!list_empty(&queue->txfree));
+
+ packet = list_entry(queue->txfree.next, struct bcm43xx_pio_txpacket, list);
+ packet->skb = skb;
+
+ memset(&packet->txstat, 0, sizeof(packet->txstat));
+ memcpy(&packet->txstat.control, ctl, sizeof(*ctl));
+
+ list_move_tail(&packet->list, &queue->txqueue);
+ queue->nr_txfree--;
+ queue->nr_tx_packets++;
+ assert(queue->nr_txfree < BCM43xx_PIO_MAXTXPACKETS);
+
+ tasklet_schedule(&queue->txtask);
+
+ return 0;
+}
+
+void bcm43xx_pio_handle_txstatus(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_txstatus *status)
+{
+ struct bcm43xx_pioqueue *queue;
+ struct bcm43xx_pio_txpacket *packet;
+
+ queue = parse_cookie(dev, status->cookie, &packet);
+ assert(queue);
+
+ queue->tx_devq_packets--;
+ queue->tx_devq_used -= (packet->skb->len + sizeof(struct bcm43xx_txhdr_fw4));
+
+ if (status->acked)
+ packet->txstat.flags |= IEEE80211_TX_STATUS_ACK;
+ packet->txstat.retry_count = status->frame_count - 1;
+ ieee80211_tx_status_irqsafe(dev->wl->hw, packet->skb,
+ &(packet->txstat));
+ packet->skb = NULL;
+
+ free_txpacket(packet, 1);
+ /* If there are packets on the txqueue, poke the tasklet
+ * to transmit them.
+ */
+ if (!list_empty(&queue->txqueue))
+ tasklet_schedule(&queue->txtask);
+}
+
+void bcm43xx_pio_get_tx_stats(struct bcm43xx_wldev *dev,
+ struct ieee80211_tx_queue_stats *stats)
+{
+ struct bcm43xx_pio *pio = &dev->pio;
+ struct bcm43xx_pioqueue *queue;
+ struct ieee80211_tx_queue_stats_data *data;
+
+ queue = pio->queue1;
+ data = &(stats->data[0]);
+ data->len = BCM43xx_PIO_MAXTXPACKETS - queue->nr_txfree;
+ data->limit = BCM43xx_PIO_MAXTXPACKETS;
+ data->count = queue->nr_tx_packets;
+}
+
+static void pio_rx_error(struct bcm43xx_pioqueue *queue,
+ int clear_buffers,
+ const char *error)
+{
+ int i;
+
+ printkl("PIO RX error: %s\n", error);
+ bcm43xx_pio_write(queue, BCM43xx_PIO_RXCTL,
+ BCM43xx_PIO_RXCTL_READY);
+ if (clear_buffers) {
+ assert(queue->mmio_base == BCM43xx_MMIO_PIO1_BASE);
+ for (i = 0; i < 15; i++) {
+ /* Dummy read. */
+ bcm43xx_pio_read(queue, BCM43xx_PIO_RXDATA);
+ }
+ }
+}
+
+void bcm43xx_pio_rx(struct bcm43xx_pioqueue *queue)
+{
+ u16 preamble[21] = { 0 };
+ struct bcm43xx_rxhdr_fw4 *rxhdr;
+ u16 tmp, len, macstat;
+ int i, preamble_readwords;
+ struct sk_buff *skb;
+
+ tmp = bcm43xx_pio_read(queue, BCM43xx_PIO_RXCTL);
+ if (!(tmp & BCM43xx_PIO_RXCTL_DATAAVAILABLE))
+ return;
+ bcm43xx_pio_write(queue, BCM43xx_PIO_RXCTL,
+ BCM43xx_PIO_RXCTL_DATAAVAILABLE);
+
+ for (i = 0; i < 10; i++) {
+ tmp = bcm43xx_pio_read(queue, BCM43xx_PIO_RXCTL);
+ if (tmp & BCM43xx_PIO_RXCTL_READY)
+ goto data_ready;
+ udelay(10);
+ }
+ dprintkl(KERN_ERR PFX "PIO RX timed out\n");
+ return;
+data_ready:
+
+ len = bcm43xx_pio_read(queue, BCM43xx_PIO_RXDATA);
+ if (unlikely(len > 0x700)) {
+ pio_rx_error(queue, 0, "len > 0x700");
+ return;
+ }
+ if (unlikely(len == 0 && queue->mmio_base != BCM43xx_MMIO_PIO4_BASE)) {
+ pio_rx_error(queue, 0, "len == 0");
+ return;
+ }
+ preamble[0] = cpu_to_le16(len);
+ if (queue->mmio_base == BCM43xx_MMIO_PIO4_BASE)
+ preamble_readwords = 14 / sizeof(u16);
+ else
+ preamble_readwords = 18 / sizeof(u16);
+ for (i = 0; i < preamble_readwords; i++) {
+ tmp = bcm43xx_pio_read(queue, BCM43xx_PIO_RXDATA);
+ preamble[i + 1] = cpu_to_le16(tmp);
+ }
+ rxhdr = (struct bcm43xx_rxhdr_fw4 *)preamble;
+ macstat = le16_to_cpu(rxhdr->mac_status);
+ if (macstat & BCM43xx_RX_MAC_FCSERR) {
+ pio_rx_error(queue,
+ (queue->mmio_base == BCM43xx_MMIO_PIO1_BASE),
+ "Frame FCS error");
+ return;
+ }
+ if (queue->mmio_base == BCM43xx_MMIO_PIO4_BASE) {
+ /* We received an xmit status. */
+ struct bcm43xx_hwtxstatus *hw;
+
+ hw = (struct bcm43xx_hwtxstatus *)(preamble + 1);
+ bcm43xx_handle_hwtxstatus(queue->dev, hw);
+
+ return;
+ }
+
+ skb = dev_alloc_skb(len);
+ if (unlikely(!skb)) {
+ pio_rx_error(queue, 1, "OOM");
+ return;
+ }
+ skb_put(skb, len);
+ for (i = 0; i < len - 1; i += 2) {
+ tmp = bcm43xx_pio_read(queue, BCM43xx_PIO_RXDATA);
+ *((u16 *)(skb->data + i)) = cpu_to_le16(tmp);
+ }
+ if (len % 2) {
+ tmp = bcm43xx_pio_read(queue, BCM43xx_PIO_RXDATA);
+ skb->data[len - 1] = (tmp & 0x00FF);
+/* The specs say the following is required, but
+ * it is wrong and corrupts the PLCP. If we don't do
+ * this, the PLCP seems to be correct. So ifdef it out for now.
+ */
+#if 0
+ if (rxflags2 & BCM43xx_RXHDR_FLAGS2_TYPE2FRAME)
+ skb->data[2] = (tmp & 0xFF00) >> 8;
+ else
+ skb->data[0] = (tmp & 0xFF00) >> 8;
+#endif
+ }
+ bcm43xx_rx(queue->dev, skb, rxhdr);
+}
+
+void bcm43xx_pio_tx_suspend(struct bcm43xx_pioqueue *queue)
+{
+ bcm43xx_power_saving_ctl_bits(queue->dev, -1, 1);
+ bcm43xx_pio_write(queue, BCM43xx_PIO_TXCTL,
+ bcm43xx_pio_read(queue, BCM43xx_PIO_TXCTL)
+ | BCM43xx_PIO_TXCTL_SUSPEND);
+}
+
+void bcm43xx_pio_tx_resume(struct bcm43xx_pioqueue *queue)
+{
+ bcm43xx_pio_write(queue, BCM43xx_PIO_TXCTL,
+ bcm43xx_pio_read(queue, BCM43xx_PIO_TXCTL)
+ & ~BCM43xx_PIO_TXCTL_SUSPEND);
+ bcm43xx_power_saving_ctl_bits(queue->dev, -1, -1);
+ tasklet_schedule(&queue->txtask);
+}
+
+void bcm43xx_pio_freeze_txqueues(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_pio *pio;
+
+ assert(bcm43xx_using_pio(dev));
+ pio = &dev->pio;
+ pio->queue0->tx_frozen = 1;
+ pio->queue1->tx_frozen = 1;
+ pio->queue2->tx_frozen = 1;
+ pio->queue3->tx_frozen = 1;
+}
+
+void bcm43xx_pio_thaw_txqueues(struct bcm43xx_wldev *dev)
+{
+ struct bcm43xx_pio *pio;
+
+ assert(bcm43xx_using_pio(dev));
+ pio = &dev->pio;
+ pio->queue0->tx_frozen = 0;
+ pio->queue1->tx_frozen = 0;
+ pio->queue2->tx_frozen = 0;
+ pio->queue3->tx_frozen = 0;
+ if (!list_empty(&pio->queue0->txqueue))
+ tasklet_schedule(&pio->queue0->txtask);
+ if (!list_empty(&pio->queue1->txqueue))
+ tasklet_schedule(&pio->queue1->txtask);
+ if (!list_empty(&pio->queue2->txqueue))
+ tasklet_schedule(&pio->queue2->txtask);
+ if (!list_empty(&pio->queue3->txqueue))
+ tasklet_schedule(&pio->queue3->txtask);
+}
--- /dev/null
+#ifndef BCM43xx_PIO_H_
+#define BCM43xx_PIO_H_
+
+#include "bcm43xx.h"
+
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/skbuff.h>
+
+
+#define BCM43xx_PIO_TXCTL 0x00
+#define BCM43xx_PIO_TXDATA 0x02
+#define BCM43xx_PIO_TXQBUFSIZE 0x04
+#define BCM43xx_PIO_RXCTL 0x08
+#define BCM43xx_PIO_RXDATA 0x0A
+
+#define BCM43xx_PIO_TXCTL_WRITELO (1 << 0)
+#define BCM43xx_PIO_TXCTL_WRITEHI (1 << 1)
+#define BCM43xx_PIO_TXCTL_COMPLETE (1 << 2)
+#define BCM43xx_PIO_TXCTL_INIT (1 << 3)
+#define BCM43xx_PIO_TXCTL_SUSPEND (1 << 7)
+
+#define BCM43xx_PIO_RXCTL_DATAAVAILABLE (1 << 0)
+#define BCM43xx_PIO_RXCTL_READY (1 << 1)
+
+/* PIO constants */
+#define BCM43xx_PIO_MAXTXDEVQPACKETS 31
+#define BCM43xx_PIO_TXQADJUST 80
+
+/* PIO tuning knobs */
+#define BCM43xx_PIO_MAXTXPACKETS 256
+
+
+
+#ifdef CONFIG_BCM43XX_MAC80211_PIO
+
+
+struct bcm43xx_pioqueue;
+struct bcm43xx_xmitstatus;
+
+struct bcm43xx_pio_txpacket {
+ struct bcm43xx_pioqueue *queue;
+ struct sk_buff *skb;
+ struct ieee80211_tx_status txstat;
+ struct list_head list;
+};
+
+#define pio_txpacket_getindex(packet) ((int)((packet) - (packet)->queue->tx_packets_cache))
+
+struct bcm43xx_pioqueue {
+ struct bcm43xx_wldev *dev;
+ u16 mmio_base;
+
+ u8 tx_suspended:1,
+ tx_frozen:1,
+ need_workarounds:1; /* Workarounds needed for core.rev < 3 */
+
+ /* Adjusted size of the device internal TX buffer. */
+ u16 tx_devq_size;
+ /* Used octets of the device internal TX buffer. */
+ u16 tx_devq_used;
+ /* Used packet slots in the device internal TX buffer. */
+ u8 tx_devq_packets;
+ /* Packets from the txfree list can
+ * be taken on incoming TX requests.
+ */
+ struct list_head txfree;
+ unsigned int nr_txfree;
+ /* Packets on the txqueue are queued,
+ * but not completely written to the chip, yet.
+ */
+ struct list_head txqueue;
+ /* Packets on the txrunning queue are completely
+ * posted to the device. We are waiting for the txstatus.
+ */
+ struct list_head txrunning;
+ /* Total number or packets sent.
+ * (This counter can obviously wrap).
+ */
+ unsigned int nr_tx_packets;
+ struct tasklet_struct txtask;
+ struct bcm43xx_pio_txpacket tx_packets_cache[BCM43xx_PIO_MAXTXPACKETS];
+};
+
+static inline
+u16 bcm43xx_pio_read(struct bcm43xx_pioqueue *queue,
+ u16 offset)
+{
+ return bcm43xx_read16(queue->dev, queue->mmio_base + offset);
+}
+
+static inline
+void bcm43xx_pio_write(struct bcm43xx_pioqueue *queue,
+ u16 offset, u16 value)
+{
+ bcm43xx_write16(queue->dev, queue->mmio_base + offset, value);
+ mmiowb();
+}
+
+
+int bcm43xx_pio_init(struct bcm43xx_wldev *dev);
+void bcm43xx_pio_free(struct bcm43xx_wldev *dev);
+
+int bcm43xx_pio_tx(struct bcm43xx_wldev *dev,
+ struct sk_buff *skb,
+ struct ieee80211_tx_control *ctl);
+void bcm43xx_pio_handle_txstatus(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_txstatus *status);
+void bcm43xx_pio_get_tx_stats(struct bcm43xx_wldev *dev,
+ struct ieee80211_tx_queue_stats *stats);
+void bcm43xx_pio_rx(struct bcm43xx_pioqueue *queue);
+
+/* Suspend TX queue in hardware. */
+void bcm43xx_pio_tx_suspend(struct bcm43xx_pioqueue *queue);
+void bcm43xx_pio_tx_resume(struct bcm43xx_pioqueue *queue);
+/* Suspend (freeze) the TX tasklet (software level). */
+void bcm43xx_pio_freeze_txqueues(struct bcm43xx_wldev *dev);
+void bcm43xx_pio_thaw_txqueues(struct bcm43xx_wldev *dev);
+
+#else /* CONFIG_BCM43XX_MAC80211_PIO */
+
+static inline
+int bcm43xx_pio_init(struct bcm43xx_wldev *dev)
+{
+ return 0;
+}
+static inline
+void bcm43xx_pio_free(struct bcm43xx_wldev *dev)
+{
+}
+static inline
+int bcm43xx_pio_tx(struct bcm43xx_wldev *dev,
+ struct sk_buff *skb,
+ struct ieee80211_tx_control *ctl)
+{
+ return 0;
+}
+static inline
+void bcm43xx_pio_handle_txstatus(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_txstatus *status)
+{
+}
+static inline
+void bcm43xx_pio_get_tx_stats(struct bcm43xx_wldev *dev,
+ struct ieee80211_tx_queue_stats *stats)
+{
+}
+static inline
+void bcm43xx_pio_rx(struct bcm43xx_pioqueue *queue)
+{
+}
+static inline
+void bcm43xx_pio_tx_suspend(struct bcm43xx_pioqueue *queue)
+{
+}
+static inline
+void bcm43xx_pio_tx_resume(struct bcm43xx_pioqueue *queue)
+{
+}
+static inline
+void bcm43xx_pio_freeze_txqueues(struct bcm43xx_wldev *dev)
+{
+}
+static inline
+void bcm43xx_pio_thaw_txqueues(struct bcm43xx_wldev *dev)
+{
+}
+
+#endif /* CONFIG_BCM43XX_MAC80211_PIO */
+#endif /* BCM43xx_PIO_H_ */
--- /dev/null
+/*
+
+ Broadcom BCM43xx wireless driver
+
+ Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
+ Stefano Brivio <st3@riseup.net>
+ Michael Buesch <mb@bu3sch.de>
+ Danny van Dyk <kugelfang@gentoo.org>
+ Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+ Some parts of the code in this file are derived from the ipw2200
+ driver Copyright(c) 2003 - 2004 Intel Corporation.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING. If not, write to
+ the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+ Boston, MA 02110-1301, USA.
+
+*/
+
+#include <linux/delay.h>
+
+#include "bcm43xx.h"
+#include "bcm43xx_power.h"
+#include "bcm43xx_main.h"
+
+
+//TODO Kill this file.
+
+/* Set the PowerSavingControlBits.
+ * Bitvalues:
+ * 0 => unset the bit
+ * 1 => set the bit
+ * -1 => calculate the bit
+ */
+void bcm43xx_power_saving_ctl_bits(struct bcm43xx_wldev *dev,
+ int bit25, int bit26)
+{
+ int i;
+ u32 status;
+
+//FIXME: Force 25 to off and 26 to on for now:
+bit25 = 0;
+bit26 = 1;
+
+ if (bit25 == -1) {
+ //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
+ // and thus is not an AP and we are associated, set bit 25
+ }
+ if (bit26 == -1) {
+ //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
+ // or we are associated, or FIXME, or the latest PS-Poll packet sent was
+ // successful, set bit26
+ }
+ status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
+ if (bit25)
+ status |= BCM43xx_SBF_PS1;
+ else
+ status &= ~BCM43xx_SBF_PS1;
+ if (bit26)
+ status |= BCM43xx_SBF_PS2;
+ else
+ status &= ~BCM43xx_SBF_PS2;
+ bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, status);
+ if (bit26 && dev->dev->id.revision >= 5) {
+ for (i = 0; i < 100; i++) {
+ if (bcm43xx_shm_read32(dev, BCM43xx_SHM_SHARED, 0x0040) != 4)
+ break;
+ udelay(10);
+ }
+ }
+}
--- /dev/null
+/*
+
+ Broadcom BCM43xx wireless driver
+
+ Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
+ Stefano Brivio <st3@riseup.net>
+ Michael Buesch <mb@bu3sch.de>
+ Danny van Dyk <kugelfang@gentoo.org>
+ Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+ Some parts of the code in this file are derived from the ipw2200
+ driver Copyright(c) 2003 - 2004 Intel Corporation.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING. If not, write to
+ the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+ Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef BCM43xx_POWER_H_
+#define BCM43xx_POWER_H_
+
+//TODO kill this file
+
+struct bcm43xx_wldev;
+
+void bcm43xx_power_saving_ctl_bits(struct bcm43xx_wldev *dev,
+ int bit25, int bit26);
+
+#endif /* BCM43xx_POWER_H_ */
--- /dev/null
+/*
+
+ Broadcom BCM43xx wireless driver
+
+ SYSFS support routines
+
+ Copyright (c) 2006 Michael Buesch <mb@bu3sch.de>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING. If not, write to
+ the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+ Boston, MA 02110-1301, USA.
+
+*/
+
+#include "bcm43xx_sysfs.h"
+#include "bcm43xx.h"
+#include "bcm43xx_main.h"
+#include "bcm43xx_phy.h"
+
+#include <linux/capability.h>
+
+
+#define GENERIC_FILESIZE 64
+
+
+static int get_integer(const char *buf, size_t count)
+{
+ char tmp[10 + 1] = { 0 };
+ int ret = -EINVAL;
+
+ if (count == 0)
+ goto out;
+ count = min(count, (size_t)10);
+ memcpy(tmp, buf, count);
+ ret = simple_strtol(tmp, NULL, 10);
+out:
+ return ret;
+}
+
+static int get_boolean(const char *buf, size_t count)
+{
+ if (count != 0) {
+ if (buf[0] == '1')
+ return 1;
+ if (buf[0] == '0')
+ return 0;
+ if (count >= 4 && memcmp(buf, "true", 4) == 0)
+ return 1;
+ if (count >= 5 && memcmp(buf, "false", 5) == 0)
+ return 0;
+ if (count >= 3 && memcmp(buf, "yes", 3) == 0)
+ return 1;
+ if (count >= 2 && memcmp(buf, "no", 2) == 0)
+ return 0;
+ if (count >= 2 && memcmp(buf, "on", 2) == 0)
+ return 1;
+ if (count >= 3 && memcmp(buf, "off", 3) == 0)
+ return 0;
+ }
+ return -EINVAL;
+}
+
+static ssize_t bcm43xx_attr_interfmode_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct bcm43xx_wldev *wldev = dev_to_bcm43xx_wldev(dev);
+ ssize_t count = 0;
+
+ if (!capable(CAP_NET_ADMIN))
+ return -EPERM;
+
+ mutex_lock(&wldev->wl->mutex);
+
+ switch (wldev->phy.interfmode) {
+ case BCM43xx_INTERFMODE_NONE:
+ count = snprintf(buf, PAGE_SIZE, "0 (No Interference Mitigation)\n");
+ break;
+ case BCM43xx_INTERFMODE_NONWLAN:
+ count = snprintf(buf, PAGE_SIZE, "1 (Non-WLAN Interference Mitigation)\n");
+ break;
+ case BCM43xx_INTERFMODE_MANUALWLAN:
+ count = snprintf(buf, PAGE_SIZE, "2 (WLAN Interference Mitigation)\n");
+ break;
+ default:
+ assert(0);
+ }
+
+ mutex_unlock(&wldev->wl->mutex);
+
+ return count;
+}
+
+static ssize_t bcm43xx_attr_interfmode_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct bcm43xx_wldev *wldev = dev_to_bcm43xx_wldev(dev);
+ unsigned long flags;
+ int err;
+ int mode;
+
+ if (!capable(CAP_NET_ADMIN))
+ return -EPERM;
+
+ mode = get_integer(buf, count);
+ switch (mode) {
+ case 0:
+ mode = BCM43xx_INTERFMODE_NONE;
+ break;
+ case 1:
+ mode = BCM43xx_INTERFMODE_NONWLAN;
+ break;
+ case 2:
+ mode = BCM43xx_INTERFMODE_MANUALWLAN;
+ break;
+ case 3:
+ mode = BCM43xx_INTERFMODE_AUTOWLAN;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ mutex_lock(&wldev->wl->mutex);
+ spin_lock_irqsave(&wldev->wl->irq_lock, flags);
+
+ err = bcm43xx_radio_set_interference_mitigation(wldev, mode);
+ if (err) {
+ printk(KERN_ERR PFX "Interference Mitigation not "
+ "supported by device\n");
+ }
+ mmiowb();
+ spin_unlock_irqrestore(&wldev->wl->irq_lock, flags);
+ mutex_unlock(&wldev->wl->mutex);
+
+ return err ? err : count;
+}
+
+static DEVICE_ATTR(interference, 0644,
+ bcm43xx_attr_interfmode_show,
+ bcm43xx_attr_interfmode_store);
+
+static ssize_t bcm43xx_attr_preamble_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct bcm43xx_wldev *wldev = dev_to_bcm43xx_wldev(dev);
+ ssize_t count;
+
+ if (!capable(CAP_NET_ADMIN))
+ return -EPERM;
+
+ mutex_lock(&wldev->wl->mutex);
+
+ if (wldev->short_preamble)
+ count = snprintf(buf, PAGE_SIZE, "1 (Short Preamble enabled)\n");
+ else
+ count = snprintf(buf, PAGE_SIZE, "0 (Short Preamble disabled)\n");
+
+ mutex_unlock(&wldev->wl->mutex);
+
+ return count;
+}
+
+static ssize_t bcm43xx_attr_preamble_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct bcm43xx_wldev *wldev = dev_to_bcm43xx_wldev(dev);
+ unsigned long flags;
+ int value;
+
+ if (!capable(CAP_NET_ADMIN))
+ return -EPERM;
+
+ value = get_boolean(buf, count);
+ if (value < 0)
+ return value;
+ mutex_lock(&wldev->wl->mutex);
+ spin_lock_irqsave(&wldev->wl->irq_lock, flags);
+
+ wldev->short_preamble = !!value;
+
+ spin_unlock_irqrestore(&wldev->wl->irq_lock, flags);
+ mutex_unlock(&wldev->wl->mutex);
+
+ return count;
+}
+
+static DEVICE_ATTR(shortpreamble, 0644,
+ bcm43xx_attr_preamble_show,
+ bcm43xx_attr_preamble_store);
+
+int bcm43xx_sysfs_register(struct bcm43xx_wldev *wldev)
+{
+ struct device *dev = wldev->dev->dev;
+ int err;
+
+ assert(bcm43xx_status(wldev) == BCM43xx_STAT_INITIALIZED);
+
+ err = device_create_file(dev, &dev_attr_interference);
+ if (err)
+ goto out;
+ err = device_create_file(dev, &dev_attr_shortpreamble);
+ if (err)
+ goto err_remove_interfmode;
+
+out:
+ return err;
+err_remove_interfmode:
+ device_remove_file(dev, &dev_attr_interference);
+ goto out;
+}
+
+void bcm43xx_sysfs_unregister(struct bcm43xx_wldev *wldev)
+{
+ struct device *dev = wldev->dev->dev;
+
+ device_remove_file(dev, &dev_attr_shortpreamble);
+ device_remove_file(dev, &dev_attr_interference);
+}
--- /dev/null
+#ifndef BCM43xx_SYSFS_H_
+#define BCM43xx_SYSFS_H_
+
+struct bcm43xx_wldev;
+
+int bcm43xx_sysfs_register(struct bcm43xx_wldev *dev);
+void bcm43xx_sysfs_unregister(struct bcm43xx_wldev *dev);
+
+#endif /* BCM43xx_SYSFS_H_ */
--- /dev/null
+/*
+
+ Broadcom BCM43xx wireless driver
+
+ Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
+ Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
+ Copyright (c) 2006, 2006 Michael Buesch <mb@bu3sch.de>
+ Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
+ Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING. If not, write to
+ the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+ Boston, MA 02110-1301, USA.
+
+*/
+
+#include "bcm43xx.h"
+#include "bcm43xx_tables.h"
+#include "bcm43xx_phy.h"
+
+
+const u32 bcm43xx_tab_rotor[] = {
+ 0xFEB93FFD, 0xFEC63FFD, /* 0 */
+ 0xFED23FFD, 0xFEDF3FFD,
+ 0xFEEC3FFE, 0xFEF83FFE,
+ 0xFF053FFE, 0xFF113FFE,
+ 0xFF1E3FFE, 0xFF2A3FFF, /* 8 */
+ 0xFF373FFF, 0xFF443FFF,
+ 0xFF503FFF, 0xFF5D3FFF,
+ 0xFF693FFF, 0xFF763FFF,
+ 0xFF824000, 0xFF8F4000, /* 16 */
+ 0xFF9B4000, 0xFFA84000,
+ 0xFFB54000, 0xFFC14000,
+ 0xFFCE4000, 0xFFDA4000,
+ 0xFFE74000, 0xFFF34000, /* 24 */
+ 0x00004000, 0x000D4000,
+ 0x00194000, 0x00264000,
+ 0x00324000, 0x003F4000,
+ 0x004B4000, 0x00584000, /* 32 */
+ 0x00654000, 0x00714000,
+ 0x007E4000, 0x008A3FFF,
+ 0x00973FFF, 0x00A33FFF,
+ 0x00B03FFF, 0x00BC3FFF, /* 40 */
+ 0x00C93FFF, 0x00D63FFF,
+ 0x00E23FFE, 0x00EF3FFE,
+ 0x00FB3FFE, 0x01083FFE,
+ 0x01143FFE, 0x01213FFD, /* 48 */
+ 0x012E3FFD, 0x013A3FFD,
+ 0x01473FFD,
+};
+
+const u32 bcm43xx_tab_retard[] = {
+ 0xDB93CB87, 0xD666CF64, /* 0 */
+ 0xD1FDD358, 0xCDA6D826,
+ 0xCA38DD9F, 0xC729E2B4,
+ 0xC469E88E, 0xC26AEE2B,
+ 0xC0DEF46C, 0xC073FA62, /* 8 */
+ 0xC01D00D5, 0xC0760743,
+ 0xC1560D1E, 0xC2E51369,
+ 0xC4ED18FF, 0xC7AC1ED7,
+ 0xCB2823B2, 0xCEFA28D9, /* 16 */
+ 0xD2F62D3F, 0xD7BB3197,
+ 0xDCE53568, 0xE1FE3875,
+ 0xE7D13B35, 0xED663D35,
+ 0xF39B3EC4, 0xF98E3FA7, /* 24 */
+ 0x00004000, 0x06723FA7,
+ 0x0C653EC4, 0x129A3D35,
+ 0x182F3B35, 0x1E023875,
+ 0x231B3568, 0x28453197, /* 32 */
+ 0x2D0A2D3F, 0x310628D9,
+ 0x34D823B2, 0x38541ED7,
+ 0x3B1318FF, 0x3D1B1369,
+ 0x3EAA0D1E, 0x3F8A0743, /* 40 */
+ 0x3FE300D5, 0x3F8DFA62,
+ 0x3F22F46C, 0x3D96EE2B,
+ 0x3B97E88E, 0x38D7E2B4,
+ 0x35C8DD9F, 0x325AD826, /* 48 */
+ 0x2E03D358, 0x299ACF64,
+ 0x246DCB87,
+};
+
+const u16 bcm43xx_tab_finefreqa[] = {
+ 0x0082, 0x0082, 0x0102, 0x0182, /* 0 */
+ 0x0202, 0x0282, 0x0302, 0x0382,
+ 0x0402, 0x0482, 0x0502, 0x0582,
+ 0x05E2, 0x0662, 0x06E2, 0x0762,
+ 0x07E2, 0x0842, 0x08C2, 0x0942, /* 16 */
+ 0x09C2, 0x0A22, 0x0AA2, 0x0B02,
+ 0x0B82, 0x0BE2, 0x0C62, 0x0CC2,
+ 0x0D42, 0x0DA2, 0x0E02, 0x0E62,
+ 0x0EE2, 0x0F42, 0x0FA2, 0x1002, /* 32 */
+ 0x1062, 0x10C2, 0x1122, 0x1182,
+ 0x11E2, 0x1242, 0x12A2, 0x12E2,
+ 0x1342, 0x13A2, 0x1402, 0x1442,
+ 0x14A2, 0x14E2, 0x1542, 0x1582, /* 48 */
+ 0x15E2, 0x1622, 0x1662, 0x16C1,
+ 0x1701, 0x1741, 0x1781, 0x17E1,
+ 0x1821, 0x1861, 0x18A1, 0x18E1,
+ 0x1921, 0x1961, 0x19A1, 0x19E1, /* 64 */
+ 0x1A21, 0x1A61, 0x1AA1, 0x1AC1,
+ 0x1B01, 0x1B41, 0x1B81, 0x1BA1,
+ 0x1BE1, 0x1C21, 0x1C41, 0x1C81,
+ 0x1CA1, 0x1CE1, 0x1D01, 0x1D41, /* 80 */
+ 0x1D61, 0x1DA1, 0x1DC1, 0x1E01,
+ 0x1E21, 0x1E61, 0x1E81, 0x1EA1,
+ 0x1EE1, 0x1F01, 0x1F21, 0x1F41,
+ 0x1F81, 0x1FA1, 0x1FC1, 0x1FE1, /* 96 */
+ 0x2001, 0x2041, 0x2061, 0x2081,
+ 0x20A1, 0x20C1, 0x20E1, 0x2101,
+ 0x2121, 0x2141, 0x2161, 0x2181,
+ 0x21A1, 0x21C1, 0x21E1, 0x2201, /* 112 */
+ 0x2221, 0x2241, 0x2261, 0x2281,
+ 0x22A1, 0x22C1, 0x22C1, 0x22E1,
+ 0x2301, 0x2321, 0x2341, 0x2361,
+ 0x2361, 0x2381, 0x23A1, 0x23C1, /* 128 */
+ 0x23E1, 0x23E1, 0x2401, 0x2421,
+ 0x2441, 0x2441, 0x2461, 0x2481,
+ 0x2481, 0x24A1, 0x24C1, 0x24C1,
+ 0x24E1, 0x2501, 0x2501, 0x2521, /* 144 */
+ 0x2541, 0x2541, 0x2561, 0x2561,
+ 0x2581, 0x25A1, 0x25A1, 0x25C1,
+ 0x25C1, 0x25E1, 0x2601, 0x2601,
+ 0x2621, 0x2621, 0x2641, 0x2641, /* 160 */
+ 0x2661, 0x2661, 0x2681, 0x2681,
+ 0x26A1, 0x26A1, 0x26C1, 0x26C1,
+ 0x26E1, 0x26E1, 0x2701, 0x2701,
+ 0x2721, 0x2721, 0x2740, 0x2740, /* 176 */
+ 0x2760, 0x2760, 0x2780, 0x2780,
+ 0x2780, 0x27A0, 0x27A0, 0x27C0,
+ 0x27C0, 0x27E0, 0x27E0, 0x27E0,
+ 0x2800, 0x2800, 0x2820, 0x2820, /* 192 */
+ 0x2820, 0x2840, 0x2840, 0x2840,
+ 0x2860, 0x2860, 0x2880, 0x2880,
+ 0x2880, 0x28A0, 0x28A0, 0x28A0,
+ 0x28C0, 0x28C0, 0x28C0, 0x28E0, /* 208 */
+ 0x28E0, 0x28E0, 0x2900, 0x2900,
+ 0x2900, 0x2920, 0x2920, 0x2920,
+ 0x2940, 0x2940, 0x2940, 0x2960,
+ 0x2960, 0x2960, 0x2960, 0x2980, /* 224 */
+ 0x2980, 0x2980, 0x29A0, 0x29A0,
+ 0x29A0, 0x29A0, 0x29C0, 0x29C0,
+ 0x29C0, 0x29E0, 0x29E0, 0x29E0,
+ 0x29E0, 0x2A00, 0x2A00, 0x2A00, /* 240 */
+ 0x2A00, 0x2A20, 0x2A20, 0x2A20,
+ 0x2A20, 0x2A40, 0x2A40, 0x2A40,
+ 0x2A40, 0x2A60, 0x2A60, 0x2A60,
+};
+
+const u16 bcm43xx_tab_finefreqg[] = {
+ 0x0089, 0x02E9, 0x0409, 0x04E9, /* 0 */
+ 0x05A9, 0x0669, 0x0709, 0x0789,
+ 0x0829, 0x08A9, 0x0929, 0x0989,
+ 0x0A09, 0x0A69, 0x0AC9, 0x0B29,
+ 0x0BA9, 0x0BE9, 0x0C49, 0x0CA9, /* 16 */
+ 0x0D09, 0x0D69, 0x0DA9, 0x0E09,
+ 0x0E69, 0x0EA9, 0x0F09, 0x0F49,
+ 0x0FA9, 0x0FE9, 0x1029, 0x1089,
+ 0x10C9, 0x1109, 0x1169, 0x11A9, /* 32 */
+ 0x11E9, 0x1229, 0x1289, 0x12C9,
+ 0x1309, 0x1349, 0x1389, 0x13C9,
+ 0x1409, 0x1449, 0x14A9, 0x14E9,
+ 0x1529, 0x1569, 0x15A9, 0x15E9, /* 48 */
+ 0x1629, 0x1669, 0x16A9, 0x16E8,
+ 0x1728, 0x1768, 0x17A8, 0x17E8,
+ 0x1828, 0x1868, 0x18A8, 0x18E8,
+ 0x1928, 0x1968, 0x19A8, 0x19E8, /* 64 */
+ 0x1A28, 0x1A68, 0x1AA8, 0x1AE8,
+ 0x1B28, 0x1B68, 0x1BA8, 0x1BE8,
+ 0x1C28, 0x1C68, 0x1CA8, 0x1CE8,
+ 0x1D28, 0x1D68, 0x1DC8, 0x1E08, /* 80 */
+ 0x1E48, 0x1E88, 0x1EC8, 0x1F08,
+ 0x1F48, 0x1F88, 0x1FE8, 0x2028,
+ 0x2068, 0x20A8, 0x2108, 0x2148,
+ 0x2188, 0x21C8, 0x2228, 0x2268, /* 96 */
+ 0x22C8, 0x2308, 0x2348, 0x23A8,
+ 0x23E8, 0x2448, 0x24A8, 0x24E8,
+ 0x2548, 0x25A8, 0x2608, 0x2668,
+ 0x26C8, 0x2728, 0x2787, 0x27E7, /* 112 */
+ 0x2847, 0x28C7, 0x2947, 0x29A7,
+ 0x2A27, 0x2AC7, 0x2B47, 0x2BE7,
+ 0x2CA7, 0x2D67, 0x2E47, 0x2F67,
+ 0x3247, 0x3526, 0x3646, 0x3726, /* 128 */
+ 0x3806, 0x38A6, 0x3946, 0x39E6,
+ 0x3A66, 0x3AE6, 0x3B66, 0x3BC6,
+ 0x3C45, 0x3CA5, 0x3D05, 0x3D85,
+ 0x3DE5, 0x3E45, 0x3EA5, 0x3EE5, /* 144 */
+ 0x3F45, 0x3FA5, 0x4005, 0x4045,
+ 0x40A5, 0x40E5, 0x4145, 0x4185,
+ 0x41E5, 0x4225, 0x4265, 0x42C5,
+ 0x4305, 0x4345, 0x43A5, 0x43E5, /* 160 */
+ 0x4424, 0x4464, 0x44C4, 0x4504,
+ 0x4544, 0x4584, 0x45C4, 0x4604,
+ 0x4644, 0x46A4, 0x46E4, 0x4724,
+ 0x4764, 0x47A4, 0x47E4, 0x4824, /* 176 */
+ 0x4864, 0x48A4, 0x48E4, 0x4924,
+ 0x4964, 0x49A4, 0x49E4, 0x4A24,
+ 0x4A64, 0x4AA4, 0x4AE4, 0x4B23,
+ 0x4B63, 0x4BA3, 0x4BE3, 0x4C23, /* 192 */
+ 0x4C63, 0x4CA3, 0x4CE3, 0x4D23,
+ 0x4D63, 0x4DA3, 0x4DE3, 0x4E23,
+ 0x4E63, 0x4EA3, 0x4EE3, 0x4F23,
+ 0x4F63, 0x4FC3, 0x5003, 0x5043, /* 208 */
+ 0x5083, 0x50C3, 0x5103, 0x5143,
+ 0x5183, 0x51E2, 0x5222, 0x5262,
+ 0x52A2, 0x52E2, 0x5342, 0x5382,
+ 0x53C2, 0x5402, 0x5462, 0x54A2, /* 224 */
+ 0x5502, 0x5542, 0x55A2, 0x55E2,
+ 0x5642, 0x5682, 0x56E2, 0x5722,
+ 0x5782, 0x57E1, 0x5841, 0x58A1,
+ 0x5901, 0x5961, 0x59C1, 0x5A21, /* 240 */
+ 0x5AA1, 0x5B01, 0x5B81, 0x5BE1,
+ 0x5C61, 0x5D01, 0x5D80, 0x5E20,
+ 0x5EE0, 0x5FA0, 0x6080, 0x61C0,
+};
+
+const u16 bcm43xx_tab_noisea2[] = {
+ 0x0001, 0x0001, 0x0001, 0xFFFE,
+ 0xFFFE, 0x3FFF, 0x1000, 0x0393,
+};
+
+const u16 bcm43xx_tab_noisea3[] = {
+ 0x4C4C, 0x4C4C, 0x4C4C, 0x2D36,
+ 0x4C4C, 0x4C4C, 0x4C4C, 0x2D36,
+};
+
+const u16 bcm43xx_tab_noiseg1[] = {
+ 0x013C, 0x01F5, 0x031A, 0x0631,
+ 0x0001, 0x0001, 0x0001, 0x0001,
+};
+
+const u16 bcm43xx_tab_noiseg2[] = {
+ 0x5484, 0x3C40, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000,
+};
+
+const u16 bcm43xx_tab_noisescaleg1[] = {
+ 0x6C77, 0x5162, 0x3B40, 0x3335, /* 0 */
+ 0x2F2D, 0x2A2A, 0x2527, 0x1F21,
+ 0x1A1D, 0x1719, 0x1616, 0x1414,
+ 0x1414, 0x1400, 0x1414, 0x1614,
+ 0x1716, 0x1A19, 0x1F1D, 0x2521, /* 16 */
+ 0x2A27, 0x2F2A, 0x332D, 0x3B35,
+ 0x5140, 0x6C62, 0x0077,
+};
+
+const u16 bcm43xx_tab_noisescaleg2[] = {
+ 0xD8DD, 0xCBD4, 0xBCC0, 0XB6B7, /* 0 */
+ 0xB2B0, 0xADAD, 0xA7A9, 0x9FA1,
+ 0x969B, 0x9195, 0x8F8F, 0x8A8A,
+ 0x8A8A, 0x8A00, 0x8A8A, 0x8F8A,
+ 0x918F, 0x9695, 0x9F9B, 0xA7A1, /* 16 */
+ 0xADA9, 0xB2AD, 0xB6B0, 0xBCB7,
+ 0xCBC0, 0xD8D4, 0x00DD,
+};
+
+const u16 bcm43xx_tab_noisescaleg3[] = {
+ 0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4, /* 0 */
+ 0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4,
+ 0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4,
+ 0xA4A4, 0xA400, 0xA4A4, 0xA4A4,
+ 0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4, /* 16 */
+ 0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4,
+ 0xA4A4, 0xA4A4, 0x00A4,
+};
+
+const u16 bcm43xx_tab_sigmasqr1[] = {
+ 0x007A, 0x0075, 0x0071, 0x006C, /* 0 */
+ 0x0067, 0x0063, 0x005E, 0x0059,
+ 0x0054, 0x0050, 0x004B, 0x0046,
+ 0x0042, 0x003D, 0x003D, 0x003D,
+ 0x003D, 0x003D, 0x003D, 0x003D, /* 16 */
+ 0x003D, 0x003D, 0x003D, 0x003D,
+ 0x003D, 0x003D, 0x0000, 0x003D,
+ 0x003D, 0x003D, 0x003D, 0x003D,
+ 0x003D, 0x003D, 0x003D, 0x003D, /* 32 */
+ 0x003D, 0x003D, 0x003D, 0x003D,
+ 0x0042, 0x0046, 0x004B, 0x0050,
+ 0x0054, 0x0059, 0x005E, 0x0063,
+ 0x0067, 0x006C, 0x0071, 0x0075, /* 48 */
+ 0x007A,
+};
+
+const u16 bcm43xx_tab_sigmasqr2[] = {
+ 0x00DE, 0x00DC, 0x00DA, 0x00D8, /* 0 */
+ 0x00D6, 0x00D4, 0x00D2, 0x00CF,
+ 0x00CD, 0x00CA, 0x00C7, 0x00C4,
+ 0x00C1, 0x00BE, 0x00BE, 0x00BE,
+ 0x00BE, 0x00BE, 0x00BE, 0x00BE, /* 16 */
+ 0x00BE, 0x00BE, 0x00BE, 0x00BE,
+ 0x00BE, 0x00BE, 0x0000, 0x00BE,
+ 0x00BE, 0x00BE, 0x00BE, 0x00BE,
+ 0x00BE, 0x00BE, 0x00BE, 0x00BE, /* 32 */
+ 0x00BE, 0x00BE, 0x00BE, 0x00BE,
+ 0x00C1, 0x00C4, 0x00C7, 0x00CA,
+ 0x00CD, 0x00CF, 0x00D2, 0x00D4,
+ 0x00D6, 0x00D8, 0x00DA, 0x00DC, /* 48 */
+ 0x00DE,
+};
+
+
+static inline void assert_sizes(void)
+{
+ BUILD_BUG_ON(BCM43xx_TAB_ROTOR_SIZE != ARRAY_SIZE(bcm43xx_tab_rotor));
+ BUILD_BUG_ON(BCM43xx_TAB_RETARD_SIZE != ARRAY_SIZE(bcm43xx_tab_retard));
+ BUILD_BUG_ON(BCM43xx_TAB_FINEFREQA_SIZE != ARRAY_SIZE(bcm43xx_tab_finefreqa));
+ BUILD_BUG_ON(BCM43xx_TAB_FINEFREQG_SIZE != ARRAY_SIZE(bcm43xx_tab_finefreqg));
+ BUILD_BUG_ON(BCM43xx_TAB_NOISEA2_SIZE != ARRAY_SIZE(bcm43xx_tab_noisea2));
+ BUILD_BUG_ON(BCM43xx_TAB_NOISEA3_SIZE != ARRAY_SIZE(bcm43xx_tab_noisea3));
+ BUILD_BUG_ON(BCM43xx_TAB_NOISEG1_SIZE != ARRAY_SIZE(bcm43xx_tab_noiseg1));
+ BUILD_BUG_ON(BCM43xx_TAB_NOISEG2_SIZE != ARRAY_SIZE(bcm43xx_tab_noiseg2));
+ BUILD_BUG_ON(BCM43xx_TAB_NOISESCALEG_SIZE != ARRAY_SIZE(bcm43xx_tab_noisescaleg1));
+ BUILD_BUG_ON(BCM43xx_TAB_NOISESCALEG_SIZE != ARRAY_SIZE(bcm43xx_tab_noisescaleg2));
+ BUILD_BUG_ON(BCM43xx_TAB_NOISESCALEG_SIZE != ARRAY_SIZE(bcm43xx_tab_noisescaleg3));
+ BUILD_BUG_ON(BCM43xx_TAB_SIGMASQR_SIZE != ARRAY_SIZE(bcm43xx_tab_sigmasqr1));
+ BUILD_BUG_ON(BCM43xx_TAB_SIGMASQR_SIZE != ARRAY_SIZE(bcm43xx_tab_sigmasqr2));
+}
+
+
+u16 bcm43xx_ofdmtab_read16(struct bcm43xx_wldev *dev, u16 table, u16 offset)
+{
+ assert_sizes();
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_OTABLECTL, table + offset);
+ return bcm43xx_phy_read(dev, BCM43xx_PHY_OTABLEI);
+}
+
+void bcm43xx_ofdmtab_write16(struct bcm43xx_wldev *dev, u16 table,
+ u16 offset, u16 value)
+{
+ bcm43xx_phy_write(dev, BCM43xx_PHY_OTABLECTL, table + offset);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_OTABLEI, value);
+}
+
+u32 bcm43xx_ofdmtab_read32(struct bcm43xx_wldev *dev, u16 table, u16 offset)
+{
+ u32 ret;
+
+ bcm43xx_phy_write(dev, BCM43xx_PHY_OTABLECTL, table + offset);
+ ret = bcm43xx_phy_read(dev, BCM43xx_PHY_OTABLEQ);
+ ret <<= 16;
+ ret |= bcm43xx_phy_read(dev, BCM43xx_PHY_OTABLEI);
+
+ return ret;
+}
+
+void bcm43xx_ofdmtab_write32(struct bcm43xx_wldev *dev, u16 table,
+ u16 offset, u32 value)
+{
+ bcm43xx_phy_write(dev, BCM43xx_PHY_OTABLECTL, table + offset);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_OTABLEI, value);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_OTABLEQ, (value >> 16));
+}
+
+u16 bcm43xx_gtab_read(struct bcm43xx_wldev *dev, u16 table, u16 offset)
+{
+ bcm43xx_phy_write(dev, BCM43xx_PHY_GTABCTL, table + offset);
+ return bcm43xx_phy_read(dev, BCM43xx_PHY_GTABDATA);
+}
+
+void bcm43xx_gtab_write(struct bcm43xx_wldev *dev, u16 table,
+ u16 offset, u16 value)
+{
+ bcm43xx_phy_write(dev, BCM43xx_PHY_GTABCTL, table + offset);
+ bcm43xx_phy_write(dev, BCM43xx_PHY_GTABDATA, value);
+}
--- /dev/null
+#ifndef BCM43xx_TABLES_H_
+#define BCM43xx_TABLES_H_
+
+#define BCM43xx_TAB_ROTOR_SIZE 53
+extern const u32 bcm43xx_tab_rotor[];
+#define BCM43xx_TAB_RETARD_SIZE 53
+extern const u32 bcm43xx_tab_retard[];
+#define BCM43xx_TAB_FINEFREQA_SIZE 256
+extern const u16 bcm43xx_tab_finefreqa[];
+#define BCM43xx_TAB_FINEFREQG_SIZE 256
+extern const u16 bcm43xx_tab_finefreqg[];
+#define BCM43xx_TAB_NOISEA2_SIZE 8
+extern const u16 bcm43xx_tab_noisea2[];
+#define BCM43xx_TAB_NOISEA3_SIZE 8
+extern const u16 bcm43xx_tab_noisea3[];
+#define BCM43xx_TAB_NOISEG1_SIZE 8
+extern const u16 bcm43xx_tab_noiseg1[];
+#define BCM43xx_TAB_NOISEG2_SIZE 8
+extern const u16 bcm43xx_tab_noiseg2[];
+#define BCM43xx_TAB_NOISESCALEG_SIZE 27
+extern const u16 bcm43xx_tab_noisescaleg1[];
+extern const u16 bcm43xx_tab_noisescaleg2[];
+extern const u16 bcm43xx_tab_noisescaleg3[];
+#define BCM43xx_TAB_SIGMASQR_SIZE 53
+extern const u16 bcm43xx_tab_sigmasqr1[];
+extern const u16 bcm43xx_tab_sigmasqr2[];
+
+#endif /* BCM43xx_TABLES_H_ */
--- /dev/null
+/*
+
+ Broadcom BCM43xx wireless driver
+
+ Transmission (TX/RX) related functions.
+
+ Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
+ Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
+ Copyright (C) 2005, 2006 Michael Buesch <mb@bu3sch.de>
+ Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
+ Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; see the file COPYING. If not, write to
+ the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+ Boston, MA 02110-1301, USA.
+
+*/
+
+#include "bcm43xx_xmit.h"
+#include "bcm43xx_phy.h"
+#include "bcm43xx_dma.h"
+#include "bcm43xx_pio.h"
+
+
+/* Extract the bitrate out of a CCK PLCP header. */
+static u8 bcm43xx_plcp_get_bitrate_cck(struct bcm43xx_plcp_hdr6 *plcp)
+{
+ switch (plcp->raw[0]) {
+ case 0x0A:
+ return BCM43xx_CCK_RATE_1MB;
+ case 0x14:
+ return BCM43xx_CCK_RATE_2MB;
+ case 0x37:
+ return BCM43xx_CCK_RATE_5MB;
+ case 0x6E:
+ return BCM43xx_CCK_RATE_11MB;
+ }
+ assert(0);
+ return 0;
+}
+
+/* Extract the bitrate out of an OFDM PLCP header. */
+static u8 bcm43xx_plcp_get_bitrate_ofdm(struct bcm43xx_plcp_hdr6 *plcp)
+{
+ switch (plcp->raw[0] & 0xF) {
+ case 0xB:
+ return BCM43xx_OFDM_RATE_6MB;
+ case 0xF:
+ return BCM43xx_OFDM_RATE_9MB;
+ case 0xA:
+ return BCM43xx_OFDM_RATE_12MB;
+ case 0xE:
+ return BCM43xx_OFDM_RATE_18MB;
+ case 0x9:
+ return BCM43xx_OFDM_RATE_24MB;
+ case 0xD:
+ return BCM43xx_OFDM_RATE_36MB;
+ case 0x8:
+ return BCM43xx_OFDM_RATE_48MB;
+ case 0xC:
+ return BCM43xx_OFDM_RATE_54MB;
+ }
+ assert(0);
+ return 0;
+}
+
+u8 bcm43xx_plcp_get_ratecode_cck(const u8 bitrate)
+{
+ switch (bitrate) {
+ case BCM43xx_CCK_RATE_1MB:
+ return 0x0A;
+ case BCM43xx_CCK_RATE_2MB:
+ return 0x14;
+ case BCM43xx_CCK_RATE_5MB:
+ return 0x37;
+ case BCM43xx_CCK_RATE_11MB:
+ return 0x6E;
+ }
+ assert(0);
+ return 0;
+}
+
+u8 bcm43xx_plcp_get_ratecode_ofdm(const u8 bitrate)
+{
+ switch (bitrate) {
+ case BCM43xx_OFDM_RATE_6MB:
+ return 0xB;
+ case BCM43xx_OFDM_RATE_9MB:
+ return 0xF;
+ case BCM43xx_OFDM_RATE_12MB:
+ return 0xA;
+ case BCM43xx_OFDM_RATE_18MB:
+ return 0xE;
+ case BCM43xx_OFDM_RATE_24MB:
+ return 0x9;
+ case BCM43xx_OFDM_RATE_36MB:
+ return 0xD;
+ case BCM43xx_OFDM_RATE_48MB:
+ return 0x8;
+ case BCM43xx_OFDM_RATE_54MB:
+ return 0xC;
+ }
+ assert(0);
+ return 0;
+}
+
+void bcm43xx_generate_plcp_hdr(struct bcm43xx_plcp_hdr4 *plcp,
+ const u16 octets, const u8 bitrate)
+{
+ __le32 *data = &(plcp->data);
+ __u8 *raw = plcp->raw;
+
+ if (bcm43xx_is_ofdm_rate(bitrate)) {
+ *data = bcm43xx_plcp_get_ratecode_ofdm(bitrate);
+ assert(!(octets & 0xF000));
+ *data |= (octets << 5);
+ *data = cpu_to_le32(*data);
+ } else {
+ u32 plen;
+
+ plen = octets * 16 / bitrate;
+ if ((octets * 16 % bitrate) > 0) {
+ plen++;
+ if ((bitrate == BCM43xx_CCK_RATE_11MB)
+ && ((octets * 8 % 11) < 4)) {
+ raw[1] = 0x84;
+ } else
+ raw[1] = 0x04;
+ } else
+ raw[1] = 0x04;
+ *data |= cpu_to_le32(plen << 16);
+ raw[0] = bcm43xx_plcp_get_ratecode_cck(bitrate);
+ }
+}
+
+static u8 bcm43xx_calc_fallback_rate(u8 bitrate)
+{
+ switch (bitrate) {
+ case BCM43xx_CCK_RATE_1MB:
+ return BCM43xx_CCK_RATE_1MB;
+ case BCM43xx_CCK_RATE_2MB:
+ return BCM43xx_CCK_RATE_1MB;
+ case BCM43xx_CCK_RATE_5MB:
+ return BCM43xx_CCK_RATE_2MB;
+ case BCM43xx_CCK_RATE_11MB:
+ return BCM43xx_CCK_RATE_5MB;
+ case BCM43xx_OFDM_RATE_6MB:
+ return BCM43xx_CCK_RATE_5MB;
+ case BCM43xx_OFDM_RATE_9MB:
+ return BCM43xx_OFDM_RATE_6MB;
+ case BCM43xx_OFDM_RATE_12MB:
+ return BCM43xx_OFDM_RATE_9MB;
+ case BCM43xx_OFDM_RATE_18MB:
+ return BCM43xx_OFDM_RATE_12MB;
+ case BCM43xx_OFDM_RATE_24MB:
+ return BCM43xx_OFDM_RATE_18MB;
+ case BCM43xx_OFDM_RATE_36MB:
+ return BCM43xx_OFDM_RATE_24MB;
+ case BCM43xx_OFDM_RATE_48MB:
+ return BCM43xx_OFDM_RATE_36MB;
+ case BCM43xx_OFDM_RATE_54MB:
+ return BCM43xx_OFDM_RATE_48MB;
+ }
+ assert(0);
+ return 0;
+}
+
+static void generate_txhdr_fw4(struct bcm43xx_wldev *dev,
+ struct bcm43xx_txhdr_fw4 *txhdr,
+ const unsigned char *fragment_data,
+ unsigned int fragment_len,
+ const struct ieee80211_tx_control *txctl,
+ u16 cookie)
+{
+ const struct bcm43xx_phy *phy = &dev->phy;
+ const struct ieee80211_hdr *wlhdr = (const struct ieee80211_hdr *)fragment_data;
+ int use_encryption = ((!(txctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) &&
+ (txctl->key_idx >= 0));
+ u16 fctl = le16_to_cpu(wlhdr->frame_control);
+ u8 rate, rate_fb;
+ int rate_ofdm, rate_fb_ofdm;
+ unsigned int plcp_fragment_len;
+ u32 mac_ctl = 0;
+ u16 phy_ctl = 0;
+ u8 extra_ft = 0;
+
+ memset(txhdr, 0, sizeof(*txhdr));
+
+ rate = txctl->tx_rate;
+ rate_ofdm = bcm43xx_is_ofdm_rate(rate);
+ rate_fb = (txctl->alt_retry_rate == -1) ? rate : txctl->alt_retry_rate;
+ rate_fb_ofdm = bcm43xx_is_ofdm_rate(rate_fb);
+
+ if (rate_ofdm)
+ txhdr->phy_rate = bcm43xx_plcp_get_ratecode_ofdm(rate);
+ else
+ txhdr->phy_rate = bcm43xx_plcp_get_ratecode_cck(rate);
+ txhdr->mac_frame_ctl = wlhdr->frame_control;
+ memcpy(txhdr->tx_receiver, wlhdr->addr1, 6);
+
+ /* Calculate duration for fallback rate */
+ if ((rate_fb == rate) ||
+ (wlhdr->duration_id & cpu_to_le16(0x8000)) ||
+ (wlhdr->duration_id == cpu_to_le16(0))) {
+ /* If the fallback rate equals the normal rate or the
+ * dur_id field contains an AID, CFP magic or 0,
+ * use the original dur_id field. */
+ txhdr->dur_fb = wlhdr->duration_id;
+ } else {
+ int fbrate_base100kbps = BCM43xx_RATE_TO_BASE100KBPS(rate_fb);
+ txhdr->dur_fb = ieee80211_generic_frame_duration(dev->wl->hw,
+ fragment_len,
+ fbrate_base100kbps);
+ }
+
+ plcp_fragment_len = fragment_len + FCS_LEN;
+ if (use_encryption) {
+ u8 key_idx = (u16)(txctl->key_idx);
+ struct bcm43xx_key *key;
+ int wlhdr_len;
+ size_t iv_len;
+
+ assert(key_idx < dev->max_nr_keys);
+ key = &(dev->key[key_idx]);
+
+ if (key->enabled) {
+ /* Hardware appends ICV. */
+ plcp_fragment_len += txctl->icv_len;
+
+ key_idx = bcm43xx_kidx_to_fw(dev, key_idx);
+ mac_ctl |= (key_idx << BCM43xx_TX4_MAC_KEYIDX_SHIFT) &
+ BCM43xx_TX4_MAC_KEYIDX;
+ mac_ctl |= (key->algorithm << BCM43xx_TX4_MAC_KEYALG_SHIFT) &
+ BCM43xx_TX4_MAC_KEYALG;
+ wlhdr_len = ieee80211_get_hdrlen(fctl);
+ iv_len = min((size_t)txctl->iv_len,
+ ARRAY_SIZE(txhdr->iv));
+ memcpy(txhdr->iv, ((u8 *)wlhdr) + wlhdr_len, iv_len);
+ }
+ }
+ bcm43xx_generate_plcp_hdr((struct bcm43xx_plcp_hdr4 *)(&txhdr->plcp),
+ plcp_fragment_len, rate);
+ bcm43xx_generate_plcp_hdr((struct bcm43xx_plcp_hdr4 *)(&txhdr->plcp_fb),
+ plcp_fragment_len, rate_fb);
+
+ /* Extra Frame Types */
+ if (rate_fb_ofdm)
+ extra_ft |= BCM43xx_TX4_EFT_FBOFDM;
+
+ /* Set channel radio code. Note that the micrcode ORs 0x100 to
+ * this value before comparing it to the value in SHM, if this
+ * is a 5Ghz packet.
+ */
+ txhdr->chan_radio_code = phy->channel;
+
+ /* PHY TX Control word */
+ if (rate_ofdm)
+ phy_ctl |= BCM43xx_TX4_PHY_OFDM;
+ if (dev->short_preamble)
+ phy_ctl |= BCM43xx_TX4_PHY_SHORTPRMBL;
+ switch (txctl->antenna_sel_tx) {
+ case 0:
+ phy_ctl |= BCM43xx_TX4_PHY_ANTLAST;
+ break;
+ case 1:
+ phy_ctl |= BCM43xx_TX4_PHY_ANT0;
+ break;
+ case 2:
+ phy_ctl |= BCM43xx_TX4_PHY_ANT1;
+ break;
+ default:
+ assert(0);
+ }
+
+ /* MAC control */
+ if (!(txctl->flags & IEEE80211_TXCTL_NO_ACK))
+ mac_ctl |= BCM43xx_TX4_MAC_ACK;
+ if (!(((fctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_CTL) &&
+ ((fctl & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_PSPOLL)))
+ mac_ctl |= BCM43xx_TX4_MAC_HWSEQ;
+ if (txctl->flags & IEEE80211_TXCTL_FIRST_FRAGMENT)
+ mac_ctl |= BCM43xx_TX4_MAC_STMSDU;
+ if (phy->type == BCM43xx_PHYTYPE_A)
+ mac_ctl |= BCM43xx_TX4_MAC_5GHZ;
+
+ /* Generate the RTS or CTS-to-self frame */
+ if ((txctl->flags & IEEE80211_TXCTL_USE_RTS_CTS) ||
+ (txctl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT)) {
+ unsigned int len;
+ struct ieee80211_hdr *hdr;
+ int rts_rate, rts_rate_fb;
+ int rts_rate_ofdm, rts_rate_fb_ofdm;
+
+ rts_rate = txctl->rts_cts_rate;
+ rts_rate_ofdm = bcm43xx_is_ofdm_rate(rts_rate);
+ rts_rate_fb = bcm43xx_calc_fallback_rate(rts_rate);
+ rts_rate_fb_ofdm = bcm43xx_is_ofdm_rate(rts_rate_fb);
+
+ if (txctl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
+ ieee80211_ctstoself_get(dev->wl->hw,
+ fragment_data, fragment_len, txctl,
+ (struct ieee80211_cts *)(txhdr->rts_frame));
+ mac_ctl |= BCM43xx_TX4_MAC_SENDCTS;
+ len = sizeof(struct ieee80211_cts);
+ } else {
+ ieee80211_rts_get(dev->wl->hw,
+ fragment_data, fragment_len, txctl,
+ (struct ieee80211_rts *)(txhdr->rts_frame));
+ mac_ctl |= BCM43xx_TX4_MAC_SENDRTS;
+ len = sizeof(struct ieee80211_rts);
+ }
+ len += FCS_LEN;
+ bcm43xx_generate_plcp_hdr((struct bcm43xx_plcp_hdr4 *)(&txhdr->rts_plcp),
+ len, rts_rate);
+ bcm43xx_generate_plcp_hdr((struct bcm43xx_plcp_hdr4 *)(&txhdr->rts_plcp_fb),
+ len, rts_rate_fb);
+ hdr = (struct ieee80211_hdr *)(&txhdr->rts_frame);
+ txhdr->rts_dur_fb = hdr->duration_id;
+ if (rts_rate_ofdm) {
+ extra_ft |= BCM43xx_TX4_EFT_RTSOFDM;
+ txhdr->phy_rate_rts = bcm43xx_plcp_get_ratecode_ofdm(rts_rate);
+ } else
+ txhdr->phy_rate_rts = bcm43xx_plcp_get_ratecode_cck(rts_rate);
+ if (rts_rate_fb_ofdm)
+ extra_ft |= BCM43xx_TX4_EFT_RTSFBOFDM;
+ mac_ctl |= BCM43xx_TX4_MAC_LONGFRAME;
+ }
+
+ /* Magic cookie */
+ txhdr->cookie = cpu_to_le16(cookie);
+
+ /* Apply the bitfields */
+ txhdr->mac_ctl = cpu_to_le32(mac_ctl);
+ txhdr->phy_ctl = cpu_to_le16(phy_ctl);
+ txhdr->extra_ft = extra_ft;
+}
+
+void bcm43xx_generate_txhdr(struct bcm43xx_wldev *dev,
+ u8 *txhdr,
+ const unsigned char *fragment_data,
+ unsigned int fragment_len,
+ const struct ieee80211_tx_control *txctl,
+ u16 cookie)
+{
+ generate_txhdr_fw4(dev, (struct bcm43xx_txhdr_fw4 *)txhdr,
+ fragment_data, fragment_len,
+ txctl, cookie);
+}
+
+static s8 bcm43xx_rssi_postprocess(struct bcm43xx_wldev *dev,
+ u8 in_rssi, int ofdm,
+ int adjust_2053, int adjust_2050)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ s32 tmp;
+
+ switch (phy->radio_ver) {
+ case 0x2050:
+ if (ofdm) {
+ tmp = in_rssi;
+ if (tmp > 127)
+ tmp -= 256;
+ tmp *= 73;
+ tmp /= 64;
+ if (adjust_2050)
+ tmp += 25;
+ else
+ tmp -= 3;
+ } else {
+ if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_RSSI) {
+ if (in_rssi > 63)
+ in_rssi = 63;
+ tmp = phy->nrssi_lt[in_rssi];
+ tmp = 31 - tmp;
+ tmp *= -131;
+ tmp /= 128;
+ tmp -= 57;
+ } else {
+ tmp = in_rssi;
+ tmp = 31 - tmp;
+ tmp *= -149;
+ tmp /= 128;
+ tmp -= 68;
+ }
+ if (phy->type == BCM43xx_PHYTYPE_G &&
+ adjust_2050)
+ tmp += 25;
+ }
+ break;
+ case 0x2060:
+ if (in_rssi > 127)
+ tmp = in_rssi - 256;
+ else
+ tmp = in_rssi;
+ break;
+ default:
+ tmp = in_rssi;
+ tmp -= 11;
+ tmp *= 103;
+ tmp /= 64;
+ if (adjust_2053)
+ tmp -= 109;
+ else
+ tmp -= 83;
+ }
+
+ return (s8)tmp;
+}
+
+//TODO
+#if 0
+static s8 bcm43xx_rssinoise_postprocess(struct bcm43xx_wldev *dev,
+ u8 in_rssi)
+{
+ struct bcm43xx_phy *phy = &dev->phy;
+ s8 ret;
+
+ if (phy->type == BCM43xx_PHYTYPE_A) {
+ //TODO: Incomplete specs.
+ ret = 0;
+ } else
+ ret = bcm43xx_rssi_postprocess(dev, in_rssi, 0, 1, 1);
+
+ return ret;
+}
+#endif
+
+void bcm43xx_rx(struct bcm43xx_wldev *dev,
+ struct sk_buff *skb,
+ const void *_rxhdr)
+{
+ struct ieee80211_rx_status status;
+ struct bcm43xx_plcp_hdr6 *plcp;
+ struct ieee80211_hdr *wlhdr;
+ const struct bcm43xx_rxhdr_fw4 *rxhdr = _rxhdr;
+ u16 fctl;
+ u16 phystat0, phystat3, chanstat, mactime;
+ u32 macstat;
+ u16 chanid;
+ u8 jssi;
+ int padding;
+
+ memset(&status, 0, sizeof(status));
+
+ /* Get metadata about the frame from the header. */
+ phystat0 = le16_to_cpu(rxhdr->phy_status0);
+ phystat3 = le16_to_cpu(rxhdr->phy_status3);
+ jssi = rxhdr->jssi;
+ macstat = le32_to_cpu(rxhdr->mac_status);
+ mactime = le16_to_cpu(rxhdr->mac_time);
+ chanstat = le16_to_cpu(rxhdr->channel);
+
+ if (macstat & BCM43xx_RX_MAC_FCSERR)
+ dev->wl->ieee_stats.dot11FCSErrorCount++;
+
+ /* Skip PLCP and padding */
+ padding = (macstat & BCM43xx_RX_MAC_PADDING) ? 2 : 0;
+ plcp = (struct bcm43xx_plcp_hdr6 *)(skb->data + padding);
+ skb_pull(skb, sizeof(struct bcm43xx_plcp_hdr6) + padding);
+ /* The skb contains the Wireless Header + payload data now */
+ wlhdr = (struct ieee80211_hdr *)(skb->data);
+ fctl = le16_to_cpu(wlhdr->frame_control);
+
+ skb_trim(skb, skb->len - FCS_LEN);
+
+ if ((macstat & BCM43xx_RX_MAC_DEC) &&
+ !(macstat & BCM43xx_RX_MAC_DECERR)) {
+ unsigned int keyidx;
+ int wlhdr_len;
+ int iv_len;
+ int icv_len;
+
+ keyidx = ((macstat & BCM43xx_RX_MAC_KEYIDX)
+ >> BCM43xx_RX_MAC_KEYIDX_SHIFT);
+ /* We must adjust the key index here. We want the "physical"
+ * key index, but the ucode passed it slightly different.
+ */
+ keyidx = bcm43xx_kidx_to_raw(dev, keyidx);
+ assert(keyidx < dev->max_nr_keys);
+
+ if (dev->key[keyidx].algorithm != BCM43xx_SEC_ALGO_NONE) {
+ /* Remove PROTECTED flag to mark it as decrypted. */
+ assert(fctl & IEEE80211_FCTL_PROTECTED);
+ fctl &= ~IEEE80211_FCTL_PROTECTED;
+ wlhdr->frame_control = cpu_to_le16(fctl);
+
+ wlhdr_len = ieee80211_get_hdrlen(fctl);
+ if (skb->data[wlhdr_len + 3] & (1 << 5)) {
+ /* The Ext-IV Bit is set in the "KeyID"
+ * octet of the IV.
+ */
+ iv_len = 8;
+ icv_len = 8;
+ } else {
+ iv_len = 4;
+ icv_len = 4;
+ }
+
+ /* Remove the IV */
+ memmove(skb->data + iv_len, skb->data, wlhdr_len);
+ skb_pull(skb, iv_len);
+ /* Remove the ICV */
+ skb_trim(skb, skb->len - icv_len);
+
+ status.flag |= RX_FLAG_DECRYPTED;
+ }
+ }
+
+ status.ssi = bcm43xx_rssi_postprocess(dev, jssi,
+ (phystat0 & BCM43xx_RX_PHYST0_OFDM),
+ (phystat0 & BCM43xx_RX_PHYST0_GAINCTL),
+ (phystat3 & BCM43xx_RX_PHYST3_TRSTATE));
+ status.noise = dev->stats.link_noise;
+ status.signal = jssi; /* this looks wrong, but is what mac80211 wants */
+ if (phystat0 & BCM43xx_RX_PHYST0_OFDM)
+ status.rate = bcm43xx_plcp_get_bitrate_ofdm(plcp);
+ else
+ status.rate = bcm43xx_plcp_get_bitrate_cck(plcp);
+ status.antenna = !!(phystat0 & BCM43xx_RX_PHYST0_ANT);
+ status.mactime = mactime;
+
+ chanid = (chanstat & BCM43xx_RX_CHAN_ID) >> BCM43xx_RX_CHAN_ID_SHIFT;
+ switch (chanstat & BCM43xx_RX_CHAN_PHYTYPE) {
+ case BCM43xx_PHYTYPE_A:
+ status.phymode = MODE_IEEE80211A;
+ status.freq = chanid;
+ status.channel = bcm43xx_freq_to_channel_a(chanid);
+ break;
+ case BCM43xx_PHYTYPE_B:
+ status.phymode = MODE_IEEE80211B;
+ status.freq = chanid + 2400;
+ status.channel = bcm43xx_freq_to_channel_bg(chanid + 2400);
+ break;
+ case BCM43xx_PHYTYPE_G:
+ status.phymode = MODE_IEEE80211G;
+ status.freq = chanid + 2400;
+ status.channel = bcm43xx_freq_to_channel_bg(chanid + 2400);
+ break;
+ default:
+ assert(0);
+ }
+
+ dev->stats.last_rx = jiffies;
+ ieee80211_rx_irqsafe(dev->wl->hw, skb, &status);
+}
+
+void bcm43xx_handle_txstatus(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_txstatus *status)
+{
+ bcm43xx_debugfs_log_txstat(dev, status);
+
+ if (status->intermediate)
+ return;
+ if (status->for_ampdu)
+ return;
+ if (!status->acked)
+ dev->wl->ieee_stats.dot11ACKFailureCount++;
+ if (status->rts_count) {
+ if (status->rts_count == 0xF) //FIXME
+ dev->wl->ieee_stats.dot11RTSFailureCount++;
+ else
+ dev->wl->ieee_stats.dot11RTSSuccessCount++;
+ }
+
+ if (bcm43xx_using_pio(dev))
+ bcm43xx_pio_handle_txstatus(dev, status);
+ else
+ bcm43xx_dma_handle_txstatus(dev, status);
+}
+
+/* Handle TX status report as received through DMA/PIO queues */
+void bcm43xx_handle_hwtxstatus(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_hwtxstatus *hw)
+{
+ struct bcm43xx_txstatus status;
+ u8 tmp;
+
+ status.cookie = le16_to_cpu(hw->cookie);
+ status.seq = le16_to_cpu(hw->seq);
+ status.phy_stat = hw->phy_stat;
+ tmp = hw->count;
+ status.frame_count = (tmp >> 4);
+ status.rts_count = (tmp & 0x0F);
+ tmp = hw->flags;
+ status.supp_reason = ((tmp & 0x1C) >> 2);
+ status.pm_indicated = !!(tmp & 0x80);
+ status.intermediate = !!(tmp & 0x40);
+ status.for_ampdu = !!(tmp & 0x20);
+ status.acked = !!(tmp & 0x02);
+
+ bcm43xx_handle_txstatus(dev, &status);
+}
--- /dev/null
+#ifndef BCM43xx_XMIT_H_
+#define BCM43xx_XMIT_H_
+
+#include "bcm43xx_main.h"
+
+
+#define _bcm43xx_declare_plcp_hdr(size) \
+ struct bcm43xx_plcp_hdr##size { \
+ union { \
+ __le32 data; \
+ __u8 raw[size]; \
+ } __attribute__((__packed__)); \
+ } __attribute__((__packed__))
+
+/* struct bcm43xx_plcp_hdr4 */
+_bcm43xx_declare_plcp_hdr(4);
+/* struct bcm43xx_plcp_hdr6 */
+_bcm43xx_declare_plcp_hdr(6);
+
+#undef _bcm43xx_declare_plcp_hdr
+
+
+/* TX header for v4 firmware */
+struct bcm43xx_txhdr_fw4 {
+ __le32 mac_ctl; /* MAC TX control */
+ __le16 mac_frame_ctl; /* Copy of the FrameControl field */
+ __le16 tx_fes_time_norm; /* TX FES Time Normal */
+ __le16 phy_ctl; /* PHY TX control */
+ __le16 phy_ctl_0; /* Unused */
+ __le16 phy_ctl_1; /* Unused */
+ __le16 phy_ctl_rts_0; /* Unused */
+ __le16 phy_ctl_rts_1; /* Unused */
+ __u8 phy_rate; /* PHY rate */
+ __u8 phy_rate_rts; /* PHY rate for RTS/CTS */
+ __u8 extra_ft; /* Extra Frame Types */
+ __u8 chan_radio_code; /* Channel Radio Code */
+ __u8 iv[16]; /* Encryption IV */
+ __u8 tx_receiver[6]; /* TX Frame Receiver address */
+ __le16 tx_fes_time_fb; /* TX FES Time Fallback */
+ struct bcm43xx_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP */
+ __le16 rts_dur_fb; /* RTS fallback duration */
+ struct bcm43xx_plcp_hdr6 plcp_fb; /* Fallback PLCP */
+ __le16 dur_fb; /* Fallback duration */
+ __le16 mm_dur_time; /* Unused */
+ __le16 mm_dur_time_fb; /* Unused */
+ __le32 time_stamp; /* Timestamp */
+ PAD_BYTES(2);
+ __le16 cookie; /* TX frame cookie */
+ __le16 tx_status; /* TX status */
+ struct bcm43xx_plcp_hdr6 rts_plcp; /* RTS PLCP */
+ __u8 rts_frame[16]; /* The RTS frame (if used) */
+ PAD_BYTES(2);
+ struct bcm43xx_plcp_hdr6 plcp; /* Main PLCP */
+} __attribute__((__packed__));
+
+/* MAC TX control */
+#define BCM43xx_TX4_MAC_KEYIDX 0x0FF00000 /* Security key index */
+#define BCM43xx_TX4_MAC_KEYIDX_SHIFT 20
+#define BCM43xx_TX4_MAC_KEYALG 0x00070000 /* Security key algorithm */
+#define BCM43xx_TX4_MAC_KEYALG_SHIFT 16
+#define BCM43xx_TX4_MAC_LIFETIME 0x00001000
+#define BCM43xx_TX4_MAC_FRAMEBURST 0x00000800
+#define BCM43xx_TX4_MAC_SENDCTS 0x00000400
+#define BCM43xx_TX4_MAC_AMPDU 0x00000300
+#define BCM43xx_TX4_MAC_AMPDU_SHIFT 8
+#define BCM43xx_TX4_MAC_5GHZ 0x00000080
+#define BCM43xx_TX4_MAC_IGNPMQ 0x00000020
+#define BCM43xx_TX4_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */
+#define BCM43xx_TX4_MAC_STMSDU 0x00000008 /* Start MSDU */
+#define BCM43xx_TX4_MAC_SENDRTS 0x00000004
+#define BCM43xx_TX4_MAC_LONGFRAME 0x00000002
+#define BCM43xx_TX4_MAC_ACK 0x00000001
+
+/* Extra Frame Types */
+#define BCM43xx_TX4_EFT_FBOFDM 0x0001 /* Data frame fallback rate type */
+#define BCM43xx_TX4_EFT_RTSOFDM 0x0004 /* RTS/CTS rate type */
+#define BCM43xx_TX4_EFT_RTSFBOFDM 0x0010 /* RTS/CTS fallback rate type */
+
+/* PHY TX control word */
+#define BCM43xx_TX4_PHY_OFDM 0x0001 /* Data frame rate type */
+#define BCM43xx_TX4_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
+#define BCM43xx_TX4_PHY_ANT 0x03C0 /* Antenna selection */
+#define BCM43xx_TX4_PHY_ANT0 0x0000 /* Use antenna 0 */
+#define BCM43xx_TX4_PHY_ANT1 0x0100 /* Use antenna 1 */
+#define BCM43xx_TX4_PHY_ANTLAST 0x0300 /* Use last used antenna */
+
+
+
+void bcm43xx_generate_txhdr(struct bcm43xx_wldev *dev,
+ u8 *txhdr,
+ const unsigned char *fragment_data,
+ unsigned int fragment_len,
+ const struct ieee80211_tx_control *txctl,
+ u16 cookie);
+
+
+/* Transmit Status */
+struct bcm43xx_txstatus {
+ u16 cookie; /* The cookie from the txhdr */
+ u16 seq; /* Sequence number */
+ u8 phy_stat; /* PHY TX status */
+ u8 frame_count; /* Frame transmit count */
+ u8 rts_count; /* RTS transmit count */
+ u8 supp_reason; /* Suppression reason */
+ /* flags */
+ u8 pm_indicated; /* PM mode indicated to AP */
+ u8 intermediate; /* Intermediate status notification (not final) */
+ u8 for_ampdu; /* Status is for an AMPDU (afterburner) */
+ u8 acked; /* Wireless ACK received */
+};
+
+/* txstatus supp_reason values */
+enum {
+ BCM43xx_TXST_SUPP_NONE, /* Not suppressed */
+ BCM43xx_TXST_SUPP_PMQ, /* Suppressed due to PMQ entry */
+ BCM43xx_TXST_SUPP_FLUSH, /* Suppressed due to flush request */
+ BCM43xx_TXST_SUPP_PREV, /* Previous fragment failed */
+ BCM43xx_TXST_SUPP_CHAN, /* Channel mismatch */
+ BCM43xx_TXST_SUPP_LIFE, /* Lifetime expired */
+ BCM43xx_TXST_SUPP_UNDER, /* Buffer underflow */
+ BCM43xx_TXST_SUPP_ABNACK, /* Afterburner NACK */
+};
+
+/* Transmit Status as received through DMA/PIO on old chips */
+struct bcm43xx_hwtxstatus {
+ PAD_BYTES(4);
+ __le16 cookie;
+ u8 flags;
+ u8 count;
+ PAD_BYTES(2);
+ __le16 seq;
+ u8 phy_stat;
+ PAD_BYTES(1);
+} __attribute__((__packed__));
+
+
+/* Receive header for v4 firmware. */
+struct bcm43xx_rxhdr_fw4 {
+ __le16 frame_len; /* Frame length */
+ PAD_BYTES(2);
+ __le16 phy_status0; /* PHY RX Status 0 */
+ __u8 jssi; /* PHY RX Status 1: JSSI */
+ __u8 sig_qual; /* PHY RX Status 1: Signal Quality */
+ __le16 phy_status2; /* PHY RX Status 2 */
+ __le16 phy_status3; /* PHY RX Status 3 */
+ __le32 mac_status; /* MAC RX status */
+ __le16 mac_time;
+ __le16 channel;
+} __attribute__((__packed__));
+
+
+/* PHY RX Status 0 */
+#define BCM43xx_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */
+#define BCM43xx_RX_PHYST0_PLCPHCF 0x0200
+#define BCM43xx_RX_PHYST0_PLCPFV 0x0100
+#define BCM43xx_RX_PHYST0_SHORTPRMBL 0x0080 /* Received with Short Preamble */
+#define BCM43xx_RX_PHYST0_LCRS 0x0040
+#define BCM43xx_RX_PHYST0_ANT 0x0020 /* Antenna */
+#define BCM43xx_RX_PHYST0_UNSRATE 0x0010
+#define BCM43xx_RX_PHYST0_CLIP 0x000C
+#define BCM43xx_RX_PHYST0_CLIP_SHIFT 2
+#define BCM43xx_RX_PHYST0_FTYPE 0x0003 /* Frame type */
+#define BCM43xx_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */
+#define BCM43xx_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */
+#define BCM43xx_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */
+#define BCM43xx_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */
+
+/* PHY RX Status 2 */
+#define BCM43xx_RX_PHYST2_LNAG 0xC000 /* LNA Gain */
+#define BCM43xx_RX_PHYST2_LNAG_SHIFT 14
+#define BCM43xx_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */
+#define BCM43xx_RX_PHYST2_PNAG_SHIFT 10
+#define BCM43xx_RX_PHYST2_FOFF 0x03FF /* F offset */
+
+/* PHY RX Status 3 */
+#define BCM43xx_RX_PHYST3_DIGG 0x1800 /* DIG Gain */
+#define BCM43xx_RX_PHYST3_DIGG_SHIFT 11
+#define BCM43xx_RX_PHYST3_TRSTATE 0x0400 /* TR state */
+
+/* MAC RX Status */
+#define BCM43xx_RX_MAC_BEACONSENT 0x00008000 /* Beacon send flag */
+#define BCM43xx_RX_MAC_KEYIDX 0x000007E0 /* Key index */
+#define BCM43xx_RX_MAC_KEYIDX_SHIFT 5
+#define BCM43xx_RX_MAC_DECERR 0x00000010 /* Decrypt error */
+#define BCM43xx_RX_MAC_DEC 0x00000008 /* Decryption attempted */
+#define BCM43xx_RX_MAC_PADDING 0x00000004 /* Pad bytes present */
+#define BCM43xx_RX_MAC_RESP 0x00000002 /* Response frame transmitted */
+#define BCM43xx_RX_MAC_FCSERR 0x00000001 /* FCS error */
+
+/* RX channel */
+#define BCM43xx_RX_CHAN_GAIN 0xFC00 /* Gain */
+#define BCM43xx_RX_CHAN_GAIN_SHIFT 10
+#define BCM43xx_RX_CHAN_ID 0x03FC /* Channel ID */
+#define BCM43xx_RX_CHAN_ID_SHIFT 2
+#define BCM43xx_RX_CHAN_PHYTYPE 0x0003 /* PHY type */
+
+
+
+u8 bcm43xx_plcp_get_ratecode_cck(const u8 bitrate);
+u8 bcm43xx_plcp_get_ratecode_ofdm(const u8 bitrate);
+
+void bcm43xx_generate_plcp_hdr(struct bcm43xx_plcp_hdr4 *plcp,
+ const u16 octets, const u8 bitrate);
+
+void bcm43xx_rx(struct bcm43xx_wldev *dev,
+ struct sk_buff *skb,
+ const void *_rxhdr);
+
+void bcm43xx_handle_txstatus(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_txstatus *status);
+
+void bcm43xx_handle_hwtxstatus(struct bcm43xx_wldev *dev,
+ const struct bcm43xx_hwtxstatus *hw);
+
+
+/* Helper functions for converting the key-table index from "firmware-format"
+ * to "raw-format" and back. The firmware API changed for this at some revision.
+ * We need to account for that here. */
+static inline
+int bcm43xx_new_kidx_api(struct bcm43xx_wldev *dev)
+{
+ /* FIXME: Not sure the change was at rev 351 */
+ return (dev->fw.rev >= 351);
+}
+static inline
+u8 bcm43xx_kidx_to_fw(struct bcm43xx_wldev *dev, u8 raw_kidx)
+{
+ u8 firmware_kidx;
+ if (bcm43xx_new_kidx_api(dev)) {
+ firmware_kidx = raw_kidx;
+ } else {
+ if (raw_kidx >= 4) /* Is per STA key? */
+ firmware_kidx = raw_kidx - 4;
+ else
+ firmware_kidx = raw_kidx; /* TX default key */
+ }
+ return firmware_kidx;
+}
+static inline
+u8 bcm43xx_kidx_to_raw(struct bcm43xx_wldev *dev, u8 firmware_kidx)
+{
+ u8 raw_kidx;
+ if (bcm43xx_new_kidx_api(dev))
+ raw_kidx = firmware_kidx;
+ else
+ raw_kidx = firmware_kidx + 4; /* RX default keys or per STA keys */
+ return raw_kidx;
+}
+
+#endif /* BCM43xx_XMIT_H_ */
projects / openwrt.git / commitdiff