- * MikroTik RouterBOARD 750 support
+ * MikroTik RouterBOARD 750/750GL support
*
* Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
*
*
* Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
*
+static struct rb7xx_nand_platform_data rb750_nand_data;
static struct platform_device rb750_nand_device = {
.name = "rb750-nand",
.id = -1,
static struct platform_device rb750_nand_device = {
.name = "rb750-nand",
.id = -1,
+ .dev = {
+ .platform_data = &rb750_nand_data,
+ }
};
int rb750_latch_change(u32 mask_clr, u32 mask_set)
};
int rb750_latch_change(u32 mask_clr, u32 mask_set)
}
EXPORT_SYMBOL_GPL(rb750_latch_change);
}
EXPORT_SYMBOL_GPL(rb750_latch_change);
-void rb750_nand_pins_enable(void)
+static void rb750_nand_enable_pins(void)
+ rb750_latch_change(RB750_LVC573_LE, 0);
ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE,
AR724X_GPIO_FUNC_SPI_EN);
}
ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE,
AR724X_GPIO_FUNC_SPI_EN);
}
-EXPORT_SYMBOL_GPL(rb750_nand_pins_enable);
-void rb750_nand_pins_disable(void)
+static void rb750_nand_disable_pins(void)
{
ath79_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN,
AR724X_GPIO_FUNC_JTAG_DISABLE);
{
ath79_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN,
AR724X_GPIO_FUNC_JTAG_DISABLE);
+ rb750_latch_change(0, RB750_LVC573_LE);
+}
+
+static void rb750_nand_latch_change(u32 clear, u32 set)
+{
+ rb750_latch_change(clear, set);
-EXPORT_SYMBOL_GPL(rb750_nand_pins_disable);
static void __init rb750_setup(void)
{
static void __init rb750_setup(void)
{
ath79_register_eth(0);
platform_device_register(&rb750_leds_device);
ath79_register_eth(0);
platform_device_register(&rb750_leds_device);
+
+ rb750_nand_data.nce_line = RB750_NAND_NCE;
+ rb750_nand_data.enable_pins = rb750_nand_enable_pins;
+ rb750_nand_data.disable_pins = rb750_nand_disable_pins;
+ rb750_nand_data.latch_change = rb750_nand_latch_change;
platform_device_register(&rb750_nand_device);
}
platform_device_register(&rb750_nand_device);
}
#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3)
#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4)
#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5)
#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3)
#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4)
#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5)
+#define RB750_NAND_NCE BIT(RB750_GPIO_NAND_NCE)
#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE)
#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE)
struct rb750_led_data *leds;
};
struct rb750_led_data *leds;
};
+struct rb7xx_nand_platform_data {
+ u32 nce_line;
+
+ void (*enable_pins)(void);
+ void (*disable_pins)(void);
+ void (*latch_change)(u32, u32);
+};
+
int rb750_latch_change(u32 mask_clr, u32 mask_set);
int rb750_latch_change(u32 mask_clr, u32 mask_set);
-void rb750_nand_pins_enable(void);
-void rb750_nand_pins_disable(void);
#endif /* _MACH_RB750_H */
\ No newline at end of file
#endif /* _MACH_RB750_H */
\ No newline at end of file
#define RB750_NAND_NRE BIT(RB750_GPIO_NAND_NRE)
#define RB750_NAND_NWE BIT(RB750_GPIO_NAND_NWE)
#define RB750_NAND_RDY BIT(RB750_GPIO_NAND_RDY)
#define RB750_NAND_NRE BIT(RB750_GPIO_NAND_NRE)
#define RB750_NAND_NWE BIT(RB750_GPIO_NAND_NWE)
#define RB750_NAND_RDY BIT(RB750_GPIO_NAND_RDY)
-#define RB750_NAND_NCE BIT(RB750_GPIO_NAND_NCE)
#define RB750_NAND_DATA_SHIFT 1
#define RB750_NAND_DATA_BITS (0xff << RB750_NAND_DATA_SHIFT)
#define RB750_NAND_INPUT_BITS (RB750_NAND_DATA_BITS | RB750_NAND_RDY)
#define RB750_NAND_OUTPUT_BITS (RB750_NAND_ALE | RB750_NAND_CLE | \
#define RB750_NAND_DATA_SHIFT 1
#define RB750_NAND_DATA_BITS (0xff << RB750_NAND_DATA_SHIFT)
#define RB750_NAND_INPUT_BITS (RB750_NAND_DATA_BITS | RB750_NAND_RDY)
#define RB750_NAND_OUTPUT_BITS (RB750_NAND_ALE | RB750_NAND_CLE | \
- RB750_NAND_NRE | RB750_NAND_NWE | \
- RB750_NAND_NCE)
+ RB750_NAND_NRE | RB750_NAND_NWE)
struct rb750_nand_info {
struct nand_chip chip;
struct mtd_info mtd;
struct rb750_nand_info {
struct nand_chip chip;
struct mtd_info mtd;
+ struct rb7xx_nand_platform_data *pdata;
+static inline struct rb750_nand_info *mtd_to_rbinfo(struct mtd_info *mtd)
+{
+ return container_of(mtd, struct rb750_nand_info, mtd);
+}
+
/*
* We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
* will not be able to find the kernel that we load.
/*
* We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
* will not be able to find the kernel that we load.
static void rb750_nand_select_chip(struct mtd_info *mtd, int chip)
{
static void rb750_nand_select_chip(struct mtd_info *mtd, int chip)
{
+ struct rb750_nand_info *rbinfo = mtd_to_rbinfo(mtd);
void __iomem *base = ath79_gpio_base;
void __iomem *base = ath79_gpio_base;
- func = __raw_readl(base + AR71XX_GPIO_REG_FUNC);
- /* disable latch */
- rb750_latch_change(RB750_LVC573_LE, 0);
-
- rb750_nand_pins_enable();
+ rbinfo->pdata->enable_pins();
/* set input mode for data lines */
t = __raw_readl(base + AR71XX_GPIO_REG_OE);
/* set input mode for data lines */
t = __raw_readl(base + AR71XX_GPIO_REG_OE);
(void) __raw_readl(base + AR71XX_GPIO_REG_SET);
/* activate CE line */
(void) __raw_readl(base + AR71XX_GPIO_REG_SET);
/* activate CE line */
- __raw_writel(RB750_NAND_NCE, base + AR71XX_GPIO_REG_CLEAR);
+ __raw_writel(rbinfo->pdata->nce_line,
+ base + AR71XX_GPIO_REG_CLEAR);
} else {
/* deactivate CE line */
} else {
/* deactivate CE line */
- __raw_writel(RB750_NAND_NCE, base + AR71XX_GPIO_REG_SET);
+ __raw_writel(rbinfo->pdata->nce_line,
+ base + AR71XX_GPIO_REG_SET);
/* flush write */
(void) __raw_readl(base + AR71XX_GPIO_REG_SET);
/* flush write */
(void) __raw_readl(base + AR71XX_GPIO_REG_SET);
__raw_writel(t | RB750_NAND_IO0 | RB750_NAND_RDY,
base + AR71XX_GPIO_REG_OE);
__raw_writel(t | RB750_NAND_IO0 | RB750_NAND_RDY,
base + AR71XX_GPIO_REG_OE);
- rb750_nand_pins_disable();
-
- /* enable latch */
- rb750_latch_change(0, RB750_LVC573_LE);
+ rbinfo->pdata->disable_pins();
return rb750_nand_read_verify(NULL, len, buf);
}
return rb750_nand_read_verify(NULL, len, buf);
}
-static void __init rb750_nand_gpio_init(void)
+static void __init rb750_nand_gpio_init(struct rb750_nand_info *info)
{
void __iomem *base = ath79_gpio_base;
u32 out;
{
void __iomem *base = ath79_gpio_base;
u32 out;
/* setup output lines */
t = __raw_readl(base + AR71XX_GPIO_REG_OE);
/* setup output lines */
t = __raw_readl(base + AR71XX_GPIO_REG_OE);
- __raw_writel(t | RB750_NAND_OUTPUT_BITS, base + AR71XX_GPIO_REG_OE);
+ t |= RB750_NAND_OUTPUT_BITS;
+ t |= info->pdata->nce_line;
+ __raw_writel(t, base + AR71XX_GPIO_REG_OE);
- rb750_latch_change(~out & RB750_NAND_IO0, out & RB750_NAND_IO0);
+ info->pdata->latch_change(~out & RB750_NAND_IO0, out & RB750_NAND_IO0);
}
static int __devinit rb750_nand_probe(struct platform_device *pdev)
{
struct rb750_nand_info *info;
}
static int __devinit rb750_nand_probe(struct platform_device *pdev)
{
struct rb750_nand_info *info;
+ struct rb7xx_nand_platform_data *pdata;
int ret;
printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n");
int ret;
printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n");
- rb750_nand_gpio_init();
+ pdata = pdev->dev.platform_data;
+ if (!pdata)
+ return -EINVAL;
info = kzalloc(sizeof(*info), GFP_KERNEL);
if (!info)
info = kzalloc(sizeof(*info), GFP_KERNEL);
if (!info)
info->chip.ecc.mode = NAND_ECC_SOFT;
info->chip.options |= NAND_NO_AUTOINCR;
info->chip.ecc.mode = NAND_ECC_SOFT;
info->chip.options |= NAND_NO_AUTOINCR;
platform_set_drvdata(pdev, info);
platform_set_drvdata(pdev, info);
+ rb750_nand_gpio_init(info);
+
ret = nand_scan_ident(&info->mtd, 1, NULL);
if (ret) {
ret = -ENXIO;
ret = nand_scan_ident(&info->mtd, 1, NULL);
if (ret) {
ret = -ENXIO;