core/i2c/i2c.h

   1 /*****************************************************************************
   2  *   i2c.h:  Header file for NXP LPC11xx Family Microprocessors
   3  *
   4  *   Copyright(C) 2006, NXP Semiconductor
   5  *   Parts of this code are (C) 2010, MyVoice CAD/CAM Services
   6  *   All rights reserved.
   7  *
   8  *   History
   9  *   2006.07.19  ver 1.00    Preliminary version, first Release
  10  *   2010.07.19  ver 1.10    Rob Jansen - MyVoice CAD/CAM Services
  11  *                           Updated to reflect new code
  12  *   2011.02.19  ver 1.20    KTownsend - microBuilder.eu
  13  *                           - Added slave mode status values to
  14  *                             I2C_IRQHandler
  15  *
  16 ******************************************************************************/
  17 #ifndef __I2C_H
  18 #define __I2C_H
  19
  20 #include "projectconfig.h"
  21
  22 /*
  23  * These are states returned by the I2CEngine:
  24  *
  25  * IDLE     - is never returned but only used internally
  26  * PENDING  - is never returned but only used internally in the I2C functions
  27  * ACK      - The transaction finished and the slave returned ACK (on all bytes)
  28  * NACK     - The transaction is aborted since the slave returned a NACK
  29  * SLA_NACK - The transaction is aborted since the slave returned a NACK on the SLA
  30  *            this can be intentional (e.g. an 24LC08 EEPROM states it is busy)
  31  *            or the slave is not available/accessible at all.
  32  * ARB_LOSS - Arbitration loss during any part of the transaction.
  33  *            This could only happen in a multi master system or could also
  34  *            identify a hardware problem in the system.
  35  */
  36 #define I2CSTATE_IDLE       0x000
  37 #define I2CSTATE_PENDING    0x001
  38 #define I2CSTATE_ACK        0x101
  39 #define I2CSTATE_NACK       0x102
  40 #define I2CSTATE_SLA_NACK   0x103
  41 #define I2CSTATE_ARB_LOSS   0x104
  42
  43 #define FAST_MODE_PLUS      0
  44
  45 #define I2C_BUFSIZE         64
  46 #define MAX_TIMEOUT         0x00FFFFFF
  47
  48 #define I2CMASTER           0x01
  49 #define I2CSLAVE            0x02
  50
  51 #define SLAVE_ADDR          0xA0
  52 #define READ_WRITE          0x01
  53
  54 #define RD_BIT              0x01
  55
  56 #define I2C_GENERALCALL     0x00        /* General Call Address (to 'ping' I2C bus for devices) */
  57
  58 #define I2C_IDLE            0
  59 #define I2C_STARTED         1
  60 #define I2C_RESTARTED       2
  61 #define I2C_REPEATED_START  3
  62 #define DATA_ACK            4
  63 #define DATA_NACK           5
  64 #define I2C_WR_STARTED      6
  65 #define I2C_RD_STARTED      7
  66
  67 /* I2C Control Set Register */
  68 #define I2CONSET_I2EN       0x00000040  /* I2C Interface Enable */
  69 #define I2CONSET_AA         0x00000004  /* Assert acknowledge flag */
  70 #define I2CONSET_SI         0x00000008  /* I2C interrupt flag */
  71 #define I2CONSET_STO        0x00000010  /* STOP flag */
  72 #define I2CONSET_STA        0x00000020  /* START flag */
  73
  74 /* I2C Control clear Register */
  75 #define I2CONCLR_AAC        0x00000004  /* Assert acklnowedge clear bit*/
  76 #define I2CONCLR_SIC        0x00000008  /* I2C interrupt clear bit */
  77 #define I2CONCLR_STAC       0x00000020  /* START flag clear bit */
  78 #define I2CONCLR_I2ENC      0x00000040  /* I2C interface disable bit */
  79
  80 #define I2DAT_I2C           0x00000000  /* I2C Data Reg */
  81 #define I2ADR_I2C           0x00000000  /* I2C Slave Address Reg */
  82
  83 /* SCLH and SCLL = I2C PCLK High/Low cycles for I2C clock and
  84   determine the data rate/duty cycle for I2C:
  85
  86    I2CBitFrequency = I2CPCLK / (I2CSCLH + I2CSCLL)
  87
  88    Standard Mode   (100KHz) = CFG_CPU_CCLK / 200000
  89    Fast Mode       (400KHz) = CFG_CPU_CCLK / 800000
  90    Fast- Mode Plus (1MHz)   = CFG_CPU_CCLK / 2000000       */
  91
  92 #define I2SCLH_SCLH       CFG_CPU_CCLK / 800000  /* Standard Mode I2C SCL Duty Cycle High (400KHz) */
  93 #define I2SCLL_SCLL       CFG_CPU_CCLK / 800000  /* Fast Mode I2C SCL Duty Cycle Low (400KHz) */
  94 #define I2SCLH_HS_SCLH    CFG_CPU_CCLK / 2000000  /* Fast Plus I2C SCL Duty Cycle High Reg */
  95 #define I2SCLL_HS_SCLL    CFG_CPU_CCLK / 2000000  /* Fast Plus I2C SCL Duty Cycle Low Reg */
  96
  97 extern volatile uint8_t I2CMasterBuffer[I2C_BUFSIZE];    // Master Mode
  98 extern volatile uint8_t I2CSlaveBuffer[I2C_BUFSIZE];     // Master Mode
  99 // extern volatile uint8_t I2CWrBuffer[I2C_BUFSIZE];        // Slave Mode
 100 // extern volatile uint8_t I2CRdBuffer[I2C_BUFSIZE];        // Slave Mode
 101 extern volatile uint32_t I2CReadLength, I2CWriteLength;
 102
 103 extern void I2C_IRQHandler( void );
 104 extern uint32_t i2cInit( uint32_t I2cMode );
 105 extern uint32_t i2cEngine( void );
 106
 107 #endif /* end __I2C_H */
 108 /****************************************************************************
 109 **                            End Of File
 110 *****************************************************************************/