drivers/rf/chibi/chb_drvr.h

   1 /*******************************************************************
   2     Copyright (C) 2009 FreakLabs
   3     All rights reserved.
   4
   5     Redistribution and use in source and binary forms, with or without
   6     modification, are permitted provided that the following conditions
   7     are met:
   8
   9     1. Redistributions of source code must retain the above copyright
  10        notice, this list of conditions and the following disclaimer.
  11     2. Redistributions in binary form must reproduce the above copyright
  12        notice, this list of conditions and the following disclaimer in the
  13        documentation and/or other materials provided with the distribution.
  14     3. Neither the name of the the copyright holder nor the names of its contributors
  15        may be used to endorse or promote products derived from this software
  16        without specific prior written permission.
  17
  18     THIS SOFTWARE IS PROVIDED BY THE THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' AND
  19     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20     IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21     ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
  22     FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23     DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24     OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26     LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27     OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28     SUCH DAMAGE.
  29
  30     Originally written by Christopher Wang aka Akiba.
  31     Please post support questions to the FreakLabs forum.
  32
  33 *******************************************************************/
  34 #ifndef CHIBI_DRVR_H
  35 #define CHIBI_DRVR_H
  36
  37 #include "types.h"
  38 #include "projectconfig.h"
  39 #include "core/gpio/gpio.h"
  40
  41 #define CHB_CC1190_PRESENT      0       /// Set to 1 if CC1190 is being used
  42 #define CHB_CHINA               0
  43 #define CHB_EEPROM_IEEE_ADDR    CFG_CHIBI_EEPROM_IEEEADDR
  44 #define CHB_EEPROM_SHORT_ADDR   CFG_CHIBI_EEPROM_SHORTADDR
  45 #define CHB_AT86RF212_VER_NUM   0x01
  46 #define CHB_AT86RF212_PART_NUM  0x07
  47 // #define CHB_BPSK                0       // set to 1 if want to use BPSK rather than OQPSK
  48
  49 #define CHB_SPI_CMD_RW      0xC0    /**<  Register Write (short mode). */
  50 #define CHB_SPI_CMD_RR      0x80    /**<  Register Read (short mode). */
  51 #define CHB_SPI_CMD_FW      0x60    /**<  Frame Transmit Mode (long mode). */
  52 #define CHB_SPI_CMD_FR      0x20    /**<  Frame Receive Mode (long mode). */
  53 #define CHB_SPI_CMD_SW      0x40    /**<  SRAM Write. */
  54 #define CHB_SPI_CMD_SR      0x00    /**<  SRAM Read. */
  55 #define CHB_SPI_CMD_RADDRM  0x7F    /**<  Register Address Mask. */
  56
  57 #define CHB_IRQ_BAT_LOW_MASK        0x80  /**< Mask for the BAT_LOW interrupt. */
  58 #define CHB_IRQ_TRX_UR_MASK         0x40  /**< Mask for the TRX_UR interrupt. */
  59 #define CHB_IRQ_TRX_END_MASK        0x08  /**< Mask for the TRX_END interrupt. */
  60 #define CHB_IRQ_RX_START_MASK       0x04  /**< Mask for the RX_START interrupt. */
  61 #define CHB_IRQ_PLL_UNLOCK_MASK     0x02  /**< Mask for the PLL_UNLOCK interrupt. */
  62 #define CHB_IRQ_PLL_LOCK_MASK       0x01  /**< Mask for the PLL_LOCK interrupt. */
  63
  64 #define CHB_EINTPORT          1
  65 #define CHB_EINTPIN           8
  66 #define CHB_EINTPIN_IOCONREG  IOCON_PIO1_8
  67 #define CHB_RSTPORT           1
  68 #define CHB_RSTPIN            9
  69 #define CHB_RSTPIN_IOCONREG   IOCON_PIO1_9
  70 #define CHB_SLPTRPORT         1
  71 #define CHB_SLPTRPIN          10
  72 #define CHB_SLPTRPIN_IOCONREG IOCON_PIO1_10
  73
  74 // if CC1190 present, set up the ports and pins for high gain mode control
  75 #if (CHB_CC1190_PRESENT)
  76     #define CHB_CC1190_HGM_PORT     1
  77     #define CHB_CC1190_HGM_PIN      11
  78     #define CHB_CC1190_HGM_IOCONREG IOCON_PIO1_11
  79 #endif
  80
  81 //#define CHB_DDR_SLPTR       DDRF
  82 //#define CHB_DDR_RST         DDRF
  83 //#define CHB_RADIO_IRQ       INT6_vect
  84 //#define CHB_RADIO_IRQ_PIN   INT6
  85
  86 #define CHB_ENTER_CRIT()    __disable_irq()
  87 #define CHB_LEAVE_CRIT()    __enable_irq()
  88 #define CHB_RST_ENABLE()    do {gpioSetValue(CHB_RSTPORT, CHB_RSTPIN, 0); } while (0)
  89 #define CHB_RST_DISABLE()   do {gpioSetValue(CHB_RSTPORT, CHB_RSTPIN, 1); } while (0)
  90 #define CHB_SLPTR_ENABLE()  do {gpioSetValue(CHB_SLPTRPORT, CHB_SLPTRPIN, 1); } while (0)
  91 #define CHB_SLPTR_DISABLE() do {gpioSetValue(CHB_SLPTRPORT, CHB_SLPTRPIN, 0); } while (0)
  92
  93 // CCA constants
  94 enum
  95 {
  96     CCA_ED                    = 1,    /**< Use energy detection above threshold mode. */
  97     CCA_CARRIER_SENSE         = 2,    /**< Use carrier sense mode. */
  98     CCA_CARRIER_SENSE_WITH_ED = 3     /**< Use a combination of both energy detection and carrier sense. */
  99 };
 100
 101 // configuration parameters
 102 enum
 103 {
 104     CHB_CHANNEL             = 1,        // Replaced in projectconfig.h with CFG_CHIBI_CHANNEL
 105     CHB_PAN_ID              = 0x1234,   // Replaced in projectconfig.h with CFG_CHIBI_PANID
 106     CHB_TX_PWR              = 0x0,
 107     CHB_SHORT_ADDR          = 0x0,
 108     CHB_IEEE_ADDR           = 0x0,
 109     CHB_MAX_FRAME_RETRIES   = 3,
 110     CHB_MAX_CSMA_RETRIES    = 4,
 111     CHB_CCA_MODE            = CCA_ED,
 112     CHB_MIN_BE              = 3,
 113     CHB_MAX_BE              = 5,
 114     CHB_CCA_ED_THRES        = 0x7,
 115     CHB_CSMA_SEED0          = 0,
 116     CHB_CSMA_SEED1          = 0,
 117     CHB_FRM_VER             = 1         // accept 802.15.4 ver 0 or 1 frames
 118 };
 119
 120 // register addresses
 121 enum
 122 {
 123     TRX_STATUS              = 0x01,
 124     TRX_STATE               = 0x02,
 125     TRX_CTRL_0              = 0x03,
 126     TRX_CTRL_1              = 0x04,
 127     PHY_TX_PWR              = 0x05,
 128     PHY_RSSI                = 0x06,
 129     PHY_ED_LEVEL            = 0x07,
 130     PHY_CC_CCA              = 0x08,
 131     CCA_THRES               = 0x09,
 132     RX_CTRL                 = 0x0a,
 133     SFD_VALUE               = 0x0b,
 134     TRX_CTRL_2              = 0x0c,
 135     ANT_DIV                 = 0x0d,
 136     IRQ_MASK                = 0x0e,
 137     IRQ_STATUS              = 0x0f,
 138     VREG_CTRL               = 0x10,
 139     BATMON                  = 0x11,
 140     XOSC_CTRL               = 0x12,
 141     CC_CTRL_0               = 0x13,
 142     CC_CTRL_1               = 0x14,
 143     RX_SYN                  = 0x15,
 144     RF_CTRL_0               = 0x16,
 145     XAH_CTRL_1              = 0x17,
 146     FTN_CTRL                = 0x18,
 147     RF_CTRL_1               = 0x19,
 148     PLL_CF                  = 0x1a,
 149     PLL_DCU                 = 0x1b,
 150     PART_NUM                = 0x1c,
 151     VERSION_NUM             = 0x1d,
 152     MAN_ID_0                = 0x1e,
 153     MAN_ID_1                = 0x1f,
 154     SHORT_ADDR_0            = 0x20,
 155     SHORT_ADDR_1            = 0x21,
 156     PAN_ID_0                = 0x22,
 157     PAN_ID_1                = 0x23,
 158     IEEE_ADDR_0             = 0x24,
 159     IEEE_ADDR_1             = 0x25,
 160     IEEE_ADDR_2             = 0x26,
 161     IEEE_ADDR_3             = 0x27,
 162     IEEE_ADDR_4             = 0x28,
 163     IEEE_ADDR_5             = 0x29,
 164     IEEE_ADDR_6             = 0x2a,
 165     IEEE_ADDR_7             = 0x2b,
 166     XAH_CTRL_0              = 0x2c,
 167     CSMA_SEED_0             = 0x2d,
 168     CSMA_SEED_1             = 0x2e,
 169     CSMA_BE                 = 0x2f
 170 };
 171
 172 // random defines
 173 enum
 174 {
 175     CHB_MAX_FRAME_RETRIES_POS   = 4,
 176     CHB_MAX_CSMA_RETIRES_POS    = 1,
 177     CHB_CSMA_SEED1_POS          = 0,
 178     CHB_CCA_MODE_POS            = 5,
 179     CHB_AUTO_CRC_POS            = 5,
 180     CHB_TRX_END_POS             = 3,
 181     CHB_TRAC_STATUS_POS         = 5,
 182     CHB_FVN_POS                 = 6,
 183     CHB_OQPSK_TX_OFFSET         = 2,
 184     CHB_BPSK_TX_OFFSET          = 3,
 185     CHB_MIN_FRAME_LENGTH        = 3,
 186     CHB_MAX_FRAME_LENGTH        = 0x7f,
 187     CHB_PA_EXT_EN_POS           = 7
 188 };
 189
 190 // transceiver timing
 191 enum{
 192     TIME_RST_PULSE_WIDTH        = 1,
 193     TIME_P_ON_TO_CLKM_AVAIL     = 380,
 194     TIME_SLEEP_TO_TRX_OFF       = 240,
 195     TIME_TRX_OFF_TO_SLEEP       = 35,
 196     TIME_PLL_ON_TRX_OFF         = 1,
 197     TIME_TRX_OFF_RX_ON          = 110,
 198     TIME_RX_ON_TRX_OFF          = 1,
 199     TIME_PLL_ON_RX_ON           = 1,
 200     TIME_RX_ON_PLL_ON           = 1,
 201     TIME_PLL_LOCK_TIME          = 110,
 202     TIME_BUSY_TX_PLL_ON         = 32,
 203     TIME_ALL_STATES_TRX_OFF     = 1,
 204     TIME_RESET_TRX_OFF          = 26,
 205     TIME_TRX_IRQ_DELAY          = 9,
 206     TIME_TRX_OFF_PLL_ON         = 110,
 207     TIME_IRQ_PROCESSING_DLY     = 32
 208 };
 209
 210 // trac status
 211 enum{
 212     TRAC_SUCCESS               = 0,
 213     TRAC_SUCCESS_DATA_PENDING  = 1,
 214     TRAC_WAIT_FOR_ACK          = 2,
 215     TRAC_CHANNEL_ACCESS_FAIL   = 3,
 216     TRAC_NO_ACK                = 5,
 217     TRAC_INVALID               = 7
 218 };
 219
 220 // radio statuses
 221 enum{
 222     RADIO_SUCCESS = 0x40,                       /**< The requested service was performed successfully. */
 223     RADIO_UNSUPPORTED_DEVICE,                   /**< The connected device is not an Atmel AT86RF212. */
 224     RADIO_INVALID_ARGUMENT,                     /**< One or more of the supplied function arguments are invalid. */
 225     RADIO_TIMED_OUT,                            /**< The requested service timed out. */
 226     RADIO_WRONG_STATE,                          /**< The end-user tried to do an invalid state transition. */
 227     RADIO_BUSY_STATE,                           /**< The radio transceiver is busy receiving or transmitting. */
 228     RADIO_STATE_TRANSITION_FAILED,              /**< The requested state transition could not be completed. */
 229     RADIO_CCA_IDLE,                             /**< Channel is clear, available to transmit a new frame. */
 230     RADIO_CCA_BUSY,                             /**< Channel busy. */
 231     RADIO_TRX_BUSY,                             /**< Transceiver is busy receiving or transmitting data. */
 232     RADIO_BAT_LOW,                              /**< Measured battery voltage is lower than voltage threshold. */
 233     RADIO_BAT_OK,                               /**< Measured battery voltage is above the voltage threshold. */
 234     RADIO_CRC_FAILED,                           /**< The CRC failed for the actual frame. */
 235     RADIO_CHANNEL_ACCESS_FAILURE,               /**< The channel access failed during the auto mode. */
 236     RADIO_NO_ACK,                               /**< No acknowledge frame was received. */
 237 };
 238
 239 // transceiver commands
 240 enum
 241 {
 242     CMD_NOP                 = 0,
 243     CMD_TX_START            = 2,
 244     CMD_FORCE_TRX_OFF       = 3,
 245     CMD_FORCE_PLL_ON        = 4,
 246     CMD_RX_ON               = 6,
 247     CMD_TRX_OFF             = 8,
 248     CMD_PLL_ON              = 9,
 249     CMD_RX_AACK_ON          = 22,
 250     CMD_TX_ARET_ON          = 25
 251 };
 252
 253 // transceiver states
 254 enum
 255 {
 256     P_ON               = 0,
 257     BUSY_RX            = 1,
 258     BUSY_TX            = 2,
 259     RX_ON              = 6,
 260     TRX_OFF            = 8,
 261     PLL_ON             = 9,
 262     SLEEP              = 15,
 263     BUSY_RX_AACK       = 17,
 264     BUSY_TX_ARET       = 18,
 265     RX_AACK_ON         = 22,
 266     TX_ARET_ON         = 25,
 267     RX_ON_NOCLK        = 28,
 268     RX_AACK_ON_NOCLK   = 29,
 269     BUSY_RX_AACK_NOCLK = 30,
 270     TRANS_IN_PROG      = 31
 271 };
 272
 273 // transceiver interrupt register
 274 enum
 275 {
 276     IRQ_PLL_LOCK                = 0,
 277     IRQ_PLL_UNLOCK              = 1,
 278     IRQ_RX_START                = 2,
 279     IRQ_TRX_END                 = 3,
 280     IRQ_CCA_ED_READY            = 4,
 281     IRQ_AMI                     = 5,
 282     IRQ_TRX_UR                  = 6,
 283     IRQ_BAT_LOW                 = 7
 284 };
 285
 286 // transceiver modes
 287 enum
 288 {
 289     OQPSK_868MHZ    = 0,
 290     OQPSK_915MHZ    = 1,
 291     OQPSK_780MHZ    = 2,
 292     BPSK40_915MHZ   = 3,
 293     BPSK20_868MHZ   = 4
 294 };
 295
 296 // See Table 7-15 for details
 297 enum
 298 {
 299   CHB_PWR_EU1_2DBM   = 0x63,    // EU (868MHz) Linearized PA mode
 300   CHB_PWR_EU1_1DBM   = 0x64,    // Note: BPSK 20kbit/s only!
 301   CHB_PWR_EU1_0DBM   = 0x65,
 302   CHB_PWR_EU2_5DBM   = 0xE7,    // EU (868MHz) Boost mode (but > supply current)
 303   CHB_PWR_EU2_4DBM   = 0xE8,    // 4-5dBM BPSK 20 kbit/s only!
 304   CHB_PWR_EU2_3DBM   = 0xE9,    // 0-3dBM O-QPSK 100/200/400 kbit/s or BPSK
 305   CHB_PWR_EU2_2DBM   = 0xEA,
 306   CHB_PWR_EU2_1DBM   = 0xCB,
 307   CHB_PWR_EU2_0DBM   = 0xAB,
 308   CHB_PWR_NA_10DBM   = 0xC0,    // North America (915MHz)
 309   CHB_PWR_NA_9DBM    = 0xA1,
 310   CHB_PWR_NA_8DBM    = 0x81,
 311   CHB_PWR_NA_7DBM    = 0x82,
 312   CHB_PWR_NA_6DBM    = 0x83,
 313   CHB_PWR_NA_5DBM    = 0x60,
 314   CHB_PWR_NA_4DBM    = 0x61,
 315   CHB_PWR_NA_3DBM    = 0x41,
 316   CHB_PWR_NA_2DBM    = 0x42,
 317   CHB_PWR_NA_1DBM    = 0x22,
 318   CHB_PWR_NA_0DBM    = 0x23,
 319   CHB_PWR_CHINA_5DBM = 0xE7,    // China (780MHz)
 320   CHB_PWR_CHINA_4DBM = 0xE8,
 321   CHB_PWR_CHINA_3DBM = 0xE9,
 322   CHB_PWR_CHINA_2DBM = 0xEA,
 323   CHB_PWR_CHINA_1DBM = 0xCA,
 324   CHB_PWR_CHINA_0DBM = 0xAA
 325 };
 326
 327 // define receive state based on promiscuous mode setting
 328 #if (CFG_CHIBI_PROMISCUOUS == 1)
 329     #define RX_STATE RX_ON
 330 #else
 331     #define RX_STATE RX_AACK_ON
 332 #endif
 333 // init
 334 void chb_drvr_init();
 335
 336 // data access
 337 U8 chb_reg_read(U8 addr);
 338 U16 chb_reg_read16(U8 addr);
 339 void chb_reg_write(U8 addr, U8 val);
 340 void chb_reg_write16(U8 addr, U16 val);
 341 void chb_reg_write64(U8 addr, U8 *val);
 342 void chb_reg_read_mod_write(U8 addr, U8 val, U8 mask);
 343 void chb_frame_write(U8 *hdr, U8 hdr_len, U8 *data, U8 data_len);
 344
 345 // general configuration
 346 void chb_set_mode(U8 mode);
 347 U8 chb_set_channel(U8 channel);
 348 void chb_set_pwr(U8 val);
 349 void chb_set_ieee_addr(U8 *addr);
 350 void chb_get_ieee_addr(U8 *addr);
 351 void chb_set_short_addr(U16 addr);
 352 U16 chb_get_short_addr();
 353 U8 chb_set_state(U8 state);
 354
 355 // Power management
 356 void chb_sleep(U8 enb);
 357
 358 // data transmit
 359 U8 chb_tx(U8 *hdr, U8 *data, U8 len);
 360
 361 #if (CHB_CC1190_PRESENT)
 362     void chb_set_hgm(U8 enb);
 363 #endif
 364
 365 #ifdef CHB_DEBUG
 366 // sram access
 367 void chb_sram_read(U8 addr, U8 len, U8 *data);
 368 void chb_sram_write(U8 addr, U8 len, U8 *data);
 369 #endif
 370
 371 void chb_ISR_Handler (void);
 372
 373 #endif
 374