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[hackover2013-badge-firmware.git] / lpc134x.h
1 /**************************************************************************/
2 /*!
3 @file lpc134x.h
4 @author K. Townsend (microBuilder.eu)
5 @date 22 March 2010
6 @version 0.10
7
8 @section DESCRIPTION
9
10 LPC1343 header file, based on V0.10 of the LPC1343 User Manual.
11
12 @section LICENSE
13
14 Software License Agreement (BSD License)
15
16 Copyright (c) 2010, microBuilder SARL
17 All rights reserved.
18
19 Redistribution and use in source and binary forms, with or without
20 modification, are permitted provided that the following conditions are met:
21 1. Redistributions of source code must retain the above copyright
22 notice, this list of conditions and the following disclaimer.
23 2. Redistributions in binary form must reproduce the above copyright
24 notice, this list of conditions and the following disclaimer in the
25 documentation and/or other materials provided with the distribution.
26 3. Neither the name of the copyright holders nor the
27 names of its contributors may be used to endorse or promote products
28 derived from this software without specific prior written permission.
29
30 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
31 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
34 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41 /**************************************************************************/
42
43 #ifndef _LPC134X_H_
44 #define _LPC134X_H_
45
46 #include "sysdefs.h"
47 #include "projectconfig.h"
48
49 /*##############################################################################
50 ## System Control Block
51 ##############################################################################*/
52
53 #define SCB_BASE_ADDRESS (*(pREG32 (0x40048000))) // System control block base address
54
55 #define SCB_MEMREMAP (*(pREG32 (0x40048000))) // System memory remap
56 #define SCB_PRESETCTRL (*(pREG32 (0x40048004))) // Peripheral reset control
57 #define SCB_PLLCTRL (*(pREG32 (0x40048008))) // System PLL control
58 #define SCB_PLLSTAT (*(pREG32 (0x4004800C))) // System PLL status
59 #define SCB_USBPLLCTRL (*(pREG32 (0x40048010))) // USB PLL control
60 #define SCB_USBPLLSTAT (*(pREG32 (0x40048014))) // USB PLL status
61 #define SCB_SYSOSCCTRL (*(pREG32 (0x40048020))) // System oscillator control
62 #define SCB_WDTOSCCTRL (*(pREG32 (0x40048024))) // Watchdog oscillator control
63 #define SCB_IRCCTRL (*(pREG32 (0x40048028))) // IRC control
64 #define SCB_RESETSTAT (*(pREG32 (0x40048030))) // System reset status register
65 #define SCB_PLLCLKSEL (*(pREG32 (0x40048040))) // System PLL clock source select
66 #define SCB_PLLCLKUEN (*(pREG32 (0x40048044))) // System PLL clock source update enable
67 #define SCB_USBPLLCLKSEL (*(pREG32 (0x40048048))) // USB PLL clock source select
68 #define SCB_USBPLLCLKUEN (*(pREG32 (0x4004804C))) // USB PLL clock source update enable
69 #define SCB_MAINCLKSEL (*(pREG32 (0x40048070))) // Main clock source select
70 #define SCB_MAINCLKUEN (*(pREG32 (0x40048074))) // Main clock source update enable
71 #define SCB_SYSAHBCLKDIV (*(pREG32 (0x40048078))) // System AHB clock divider
72 #define SCB_SYSAHBCLKCTRL (*(pREG32 (0x40048080))) // System AHB clock control
73 #define SCB_SSP0CLKDIV (*(pREG32 (0x40048094))) // SSP0 clock divider
74 #define SCB_UARTCLKDIV (*(pREG32 (0x40048098))) // UART clock divider
75 #define SCB_SYSTICKCLKDIV (*(pREG32 (0x400480B0))) // System tick clock divider
76 #define SCB_USBCLKSEL (*(pREG32 (0x400480C0))) // USB clock source select
77 #define SCB_USBCLKUEN (*(pREG32 (0x400480C4))) // USB clock source update enable
78 #define SCB_USBCLKDIV (*(pREG32 (0x400480C8))) // USB clock divider
79 #define SCB_WDTCLKSEL (*(pREG32 (0x400480D0))) // Watchdog clock source select
80 #define SCB_WDTCLKUEN (*(pREG32 (0x400480D4))) // Watchdog clock source update enable
81 #define SCB_WDTCLKDIV (*(pREG32 (0x400480D8))) // Watchdog clock divider
82 #define SCB_CLKOUTCLKSEL (*(pREG32 (0x400480E0))) // CLKOUT clock source select
83 #define SCB_CLKOUTCLKUEN (*(pREG32 (0x400480E4))) // CLKOUT clock source update enable
84 #define SCB_CLKOUTCLKDIV (*(pREG32 (0x400480E8))) // CLKOUT clock divider
85 #define SCB_PIOPORCAP0 (*(pREG32 (0x40048100))) // POR captured PIO status 0
86 #define SCB_PIOPORCAP1 (*(pREG32 (0x40048104))) // POR captured PIO status 1
87 #define SCB_BODCTRL (*(pREG32 (0x40048150))) // Brown-out detector control
88 #define SCB_SYSTICKCCAL (*(pREG32 (0x40048158))) // System tick counter calibration
89 #define SCB_STARTAPRP0 (*(pREG32 (0x40048200))) // Start logic edge control register 0; bottom 32 interrupts
90 #define SCB_STARTERP0 (*(pREG32 (0x40048204))) // Start logic signal enable register 0; bottom 32 interrupts
91 #define SCB_STARTRSRP0CLR (*(pREG32 (0x40048208))) // Start logic reset register 0; bottom 32 interrupts
92 #define SCB_STARTSRP0 (*(pREG32 (0x4004820C))) // Start logic status register 0; bottom 32 interrupts
93 #define SCB_STARTAPRP1 (*(pREG32 (0x40048210))) // Start logic edge control register 1; top 8 interrupts
94 #define SCB_STARTERP1 (*(pREG32 (0x40048214))) // Start logic signal enable register 1; top 8 interrupts
95 #define SCB_STARTRSRP1CLR (*(pREG32 (0x40048218))) // Start logic reset register 1; top 8 interrupts
96 #define SCB_STARTSRP1 (*(pREG32 (0x4004821C))) // Start logic status register 1; top 8 interrupts
97 #define SCB_PDSLEEPCFG (*(pREG32 (0x40048230))) // Power-down states in Deep-sleep mode
98 #define SCB_PDAWAKECFG (*(pREG32 (0x40048234))) // Power-down states after wake-up from Deep-sleep mode
99 #define SCB_PDRUNCFG (*(pREG32 (0x40048238))) // Power-down configuration register
100 #define SCB_DEVICEID (*(pREG32 (0x400483F4))) // Device ID
101 #define SCB_MMFAR (*(pREG32 (0xE000ED34))) // Memory Manage Address Register (MMAR)
102 #define SCB_BFAR (*(pREG32 (0xE000ED38))) // Bus Fault Manage Address Register (BFAR)
103 #define SCB_DEMCR (*(pREG32 (0xE000EDFC)))
104
105 /* CPU ID Base Register */
106 #define SCB_CPUID (*(pREG32 (0xE000ED00)))
107 #define SCB_CPUID_REVISION_MASK ((unsigned int) 0x0000000F) // Revision Code
108 #define SCB_CPUID_PARTNO_MASK ((unsigned int) 0x0000FFF0) // Part Number
109 #define SCB_CPUID_CONSTANT_MASK ((unsigned int) 0x000F0000) // Constant
110 #define SCB_CPUID_VARIANT_MASK ((unsigned int) 0x00F00000) // Variant
111 #define SCB_CPUID_IMPLEMENTER_MASK ((unsigned int) 0xFF000000) // Implementer
112
113 /* System Control Register */
114
115 #define SCB_SCR (*(pREG32 (0xE000ED10)))
116 #define SCB_SCR_SLEEPONEXIT_MASK ((unsigned int) 0x00000002) // Enable sleep on exit
117 #define SCB_SCR_SLEEPONEXIT ((unsigned int) 0x00000002)
118 #define SCB_SCR_SLEEPDEEP_MASK ((unsigned int) 0x00000004)
119 #define SCB_SCR_SLEEPDEEP ((unsigned int) 0x00000004) // Enable deep sleep
120 #define SCB_SCR_SEVONPEND_MASK ((unsigned int) 0x00000010) // Wake up from WFE is new int is pended regardless of priority
121 #define SCB_SCR_SEVONPEND ((unsigned int) 0x00000010)
122
123 /* Application Interrupt and Reset Control Register */
124
125 #define SCB_AIRCR (*(pREG32 (0xE000ED0C)))
126 #define SCB_AIRCR_VECTKEY_VALUE ((unsigned int) 0x05FA0000) // Vect key needs to be set to 05FA for reset to work
127 #define SCB_AIRCR_VECTKEY_MASK ((unsigned int) 0xFFFF0000)
128 #define SCB_AIRCR_ENDIANESS ((unsigned int) 0x00008000) // Read Endianness (1=Big, 0=Little)
129 #define SCB_AIRCR_ENDIANESS_MASK ((unsigned int) 0x00008000)
130 #define SCB_AIRCR_PRIGROUP ((unsigned int) 0x00000700)
131 #define SCB_AIRCR_PRIGROUP_MASK ((unsigned int) 0x00000700)
132 #define SCB_AIRCR_SYSRESETREQ ((unsigned int) 0x00000004) // Request system reset
133 #define SCB_AIRCR_SYSRESETREQ_MASK ((unsigned int) 0x00000004)
134 #define SCB_AIRCR_VECTCLRACTIVE ((unsigned int) 0x00000002) // Used to prevent accidental reset
135 #define SCB_AIRCR_VECTCLRACTIVE_MASK ((unsigned int) 0x00000002)
136 #define SCB_AIRCR_VECTRESET ((unsigned int) 0x00000001)
137 #define SCB_AIRCR_VECTRESET_MASK ((unsigned int) 0x00000001)
138
139 /* Memory Management Fault Status Register */
140
141 #define SCB_MMFSR (*(pREG32 (0xE000ED28)))
142 #define SCB_MMFSR_IACCVIOL_MASK ((unsigned int) 0x00000001) // Instruction access violation
143 #define SCB_MMFSR_IACCVIOL ((unsigned int) 0x00000001)
144 #define SCB_MMFSR_DACCVIOL_MASK ((unsigned int) 0x00000002) // Data access violation
145 #define SCB_MMFSR_DACCVIOL ((unsigned int) 0x00000002)
146 #define SCB_MMFSR_MUNSTKERR_MASK ((unsigned int) 0x00000008) // Unstacking error
147 #define SCB_MMFSR_MUNSTKERR ((unsigned int) 0x00000008)
148 #define SCB_MMFSR_MSTKERR_MASK ((unsigned int) 0x00000010) // Stacking error
149 #define SCB_MMFSR_MSTKERR ((unsigned int) 0x00000010)
150 #define SCB_MMFSR_MMARVALID_MASK ((unsigned int) 0x00000080) // Indicates MMAR is valid
151 #define SCB_MMFSR_MMARVALID ((unsigned int) 0x00000080)
152
153 /* Bus Fault Status Register */
154
155 #define SCB_BFSR (*(pREG32 (0xE000ED29)))
156 #define SCB_BFSR_IBUSERR_MASK ((unsigned int) 0x00000001) // Instruction access violation
157 #define SCB_BFSR_IBUSERR ((unsigned int) 0x00000001)
158 #define SCB_BFSR_PRECISERR_MASK ((unsigned int) 0x00000002) // Precise data access violation
159 #define SCB_BFSR_PRECISERR ((unsigned int) 0x00000002)
160 #define SCB_BFSR_IMPRECISERR_MASK ((unsigned int) 0x00000004) // Imprecise data access violation
161 #define SCB_BFSR_IMPRECISERR ((unsigned int) 0x00000004)
162 #define SCB_BFSR_UNSTKERR_MASK ((unsigned int) 0x00000008) // Unstacking error
163 #define SCB_BFSR_UNSTKERR ((unsigned int) 0x00000008)
164 #define SCB_BFSR_STKERR_MASK ((unsigned int) 0x00000010) // Stacking error
165 #define SCB_BFSR_STKERR ((unsigned int) 0x00000010)
166 #define SCB_BFSR_BFARVALID_MASK ((unsigned int) 0x00000080) // Indicates BFAR is valid
167 #define SCB_BFSR_BFARVALID ((unsigned int) 0x00000080)
168
169 /* Usage Fault Status Register */
170
171 #define SCB_UFSR (*(pREG32 (0xE000ED2A)))
172 #define SCB_UFSR_UNDEFINSTR_MASK ((unsigned int) 0x00000001) // Attempt to execute an undefined instruction
173 #define SCB_UFSR_UNDEFINSTR ((unsigned int) 0x00000001)
174 #define SCB_UFSR_INVSTATE_MASK ((unsigned int) 0x00000002) // Attempt to switch to invalid state (i.e. ARM)
175 #define SCB_UFSR_INVSTATE ((unsigned int) 0x00000002)
176 #define SCB_UFSR_INVPC_MASK ((unsigned int) 0x00000004) // Attempt to do exception with bad value in EXC_RETURN number
177 #define SCB_UFSR_INVPC ((unsigned int) 0x00000004)
178 #define SCB_UFSR_NOCP_MASK ((unsigned int) 0x00000008) // Attempt to execute a coprocessor instruction
179 #define SCB_UFSR_NOCP ((unsigned int) 0x00000008)
180 #define SCB_UFSR_UNALIGNED_MASK ((unsigned int) 0x00000100) // Unaligned access
181 #define SCB_UFSR_UNALIGNED ((unsigned int) 0x00000100)
182 #define SCB_UFSR_DIVBYZERO_MASK ((unsigned int) 0x00000200) // Divide by zero
183 #define SCB_UFSR_DIVBYZERO ((unsigned int) 0x00000200)
184
185 /* Hard Fault Status Register */
186
187 #define SCB_HFSR (*(pREG32 (0xE000ED2C)))
188 #define SCB_HFSR_VECTTBL_MASK ((unsigned int) 0x00000002) // Hard fault caused by failed vector fetch
189 #define SCB_HFSR_VECTTBL ((unsigned int) 0x00000002)
190 #define SCB_HFSR_FORCED_MASK ((unsigned int) 0x40000000) // Hard fault taken because of bus/mem man/usage fault
191 #define SCB_HFSR_FORCED ((unsigned int) 0x40000000)
192 #define SCB_HFSR_DEBUGEVT_MASK ((unsigned int) 0x80000000) // Hard fault triggered by debug event
193 #define SCB_HFSR_DEBUGEVT ((unsigned int) 0x80000000)
194
195 /* Debug Fault Status Register */
196
197 #define SCB_DFSR (*(pREG32 (0xE000ED30)))
198 #define SCB_DFSR_HALTED_MASK ((unsigned int) 0x00000001) // Halt requested in NVIC
199 #define SCB_DFSR_HALTED ((unsigned int) 0x00000001)
200 #define SCB_DFSR_BKPT_MASK ((unsigned int) 0x00000002) // BKPT instruction executed
201 #define SCB_DFSR_BKPT ((unsigned int) 0x00000002)
202 #define SCB_DFSR_DWTTRAP_MASK ((unsigned int) 0x00000004) // DWT match occurred
203 #define SCB_DFSR_DWTTRAP ((unsigned int) 0x00000004)
204 #define SCB_DFSR_VCATCH_MASK ((unsigned int) 0x00000008) // Vector fetch occurred
205 #define SCB_DFSR_VCATCH ((unsigned int) 0x00000008)
206 #define SCB_DFSR_EXTERNAL_MASK ((unsigned int) 0x00000010) // EDBGRQ signal asserted
207 #define SCB_DFSR_EXTERNAL ((unsigned int) 0x00000010)
208
209 /* SCB_MEMREMAP (System memory remap register)
210 The system memory remap register selects whether the ARM interrupt vectors are read
211 from the boot ROM, the flash, or the SRAM. */
212
213 #define SCB_MEMREMAP_MODE_BOOTLOADER ((unsigned int) 0x00000000) // Interrupt vectors are remapped to Boot ROM
214 #define SCB_MEMREMAP_MODE_RAM ((unsigned int) 0x00000001) // Interrupt vectors are remapped to Static ROM
215 #define SCB_MEMREMAP_MODE_FLASH ((unsigned int) 0x00000002) // Interrupt vectors are not remapped and reside in Flash
216 #define SCB_MEMREMAP_MASK ((unsigned int) 0x00000003)
217
218 /* PRESETCTRL (Peripheral reset control register) */
219
220 #define SCB_PRESETCTRL_SSP0_RESETENABLED ((unsigned int) 0x00000000)
221 #define SCB_PRESETCTRL_SSP0_RESETDISABLED ((unsigned int) 0x00000001)
222 #define SCB_PRESETCTRL_SSP0_MASK ((unsigned int) 0x00000001)
223 #define SCB_PRESETCTRL_I2C_RESETENABLED ((unsigned int) 0x00000000)
224 #define SCB_PRESETCTRL_I2C_RESETDISABLED ((unsigned int) 0x00000002)
225 #define SCB_PRESETCTRL_I2C_MASK ((unsigned int) 0x00000002)
226
227 /* SYSPLLCTRL (System PLL control register)
228 This register connects and enables the system PLL and configures the PLL multiplier and
229 divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various
230 clock sources. The input frequency is multiplied up to a high frequency, then divided down
231 to provide the actual clock used by the CPU, peripherals, and optionally the USB
232 subsystem. Note that the USB subsystem has its own dedicated PLL. The PLL can
233 produce a clock up to the maximum allowed for the CPU, which is 72 MHz. */
234
235 #define SCB_PLLCTRL_MSEL_1 ((unsigned int) 0x00000000)
236 #define SCB_PLLCTRL_MSEL_2 ((unsigned int) 0x00000001)
237 #define SCB_PLLCTRL_MSEL_3 ((unsigned int) 0x00000002)
238 #define SCB_PLLCTRL_MSEL_4 ((unsigned int) 0x00000003)
239 #define SCB_PLLCTRL_MSEL_5 ((unsigned int) 0x00000004)
240 #define SCB_PLLCTRL_MSEL_6 ((unsigned int) 0x00000005)
241 #define SCB_PLLCTRL_MSEL_7 ((unsigned int) 0x00000006)
242 #define SCB_PLLCTRL_MSEL_8 ((unsigned int) 0x00000007)
243 #define SCB_PLLCTRL_MSEL_9 ((unsigned int) 0x00000008)
244 #define SCB_PLLCTRL_MSEL_10 ((unsigned int) 0x00000009)
245 #define SCB_PLLCTRL_MSEL_11 ((unsigned int) 0x0000000A)
246 #define SCB_PLLCTRL_MSEL_12 ((unsigned int) 0x0000000B)
247 #define SCB_PLLCTRL_MSEL_13 ((unsigned int) 0x0000000C)
248 #define SCB_PLLCTRL_MSEL_14 ((unsigned int) 0x0000000D)
249 #define SCB_PLLCTRL_MSEL_15 ((unsigned int) 0x0000000E)
250 #define SCB_PLLCTRL_MSEL_16 ((unsigned int) 0x0000000F)
251 #define SCB_PLLCTRL_MSEL_17 ((unsigned int) 0x00000010)
252 #define SCB_PLLCTRL_MSEL_18 ((unsigned int) 0x00000011)
253 #define SCB_PLLCTRL_MSEL_19 ((unsigned int) 0x00000012)
254 #define SCB_PLLCTRL_MSEL_20 ((unsigned int) 0x00000013)
255 #define SCB_PLLCTRL_MSEL_21 ((unsigned int) 0x00000014)
256 #define SCB_PLLCTRL_MSEL_22 ((unsigned int) 0x00000015)
257 #define SCB_PLLCTRL_MSEL_23 ((unsigned int) 0x00000016)
258 #define SCB_PLLCTRL_MSEL_24 ((unsigned int) 0x00000017)
259 #define SCB_PLLCTRL_MSEL_25 ((unsigned int) 0x00000018)
260 #define SCB_PLLCTRL_MSEL_26 ((unsigned int) 0x00000019)
261 #define SCB_PLLCTRL_MSEL_27 ((unsigned int) 0x0000001A)
262 #define SCB_PLLCTRL_MSEL_28 ((unsigned int) 0x0000001B)
263 #define SCB_PLLCTRL_MSEL_29 ((unsigned int) 0x0000001C)
264 #define SCB_PLLCTRL_MSEL_30 ((unsigned int) 0x0000001D)
265 #define SCB_PLLCTRL_MSEL_31 ((unsigned int) 0x0000001E)
266 #define SCB_PLLCTRL_MSEL_32 ((unsigned int) 0x0000001F)
267 #define SCB_PLLCTRL_MSEL_MASK ((unsigned int) 0x0000001F)
268 #define SCB_PLLCTRL_PSEL_2 ((unsigned int) 0x00000000)
269 #define SCB_PLLCTRL_PSEL_4 ((unsigned int) 0x00000020)
270 #define SCB_PLLCTRL_PSEL_8 ((unsigned int) 0x00000040)
271 #define SCB_PLLCTRL_PSEL_16 ((unsigned int) 0x00000060)
272 #define SCB_PLLCTRL_PSEL_BIT (5)
273 #define SCB_PLLCTRL_PSEL_MASK ((unsigned int) 0x00000060)
274 #define SCB_PLLCTRL_DIRECT_MASK ((unsigned int) 0x00000080) // Direct CCO clock output control
275 #define SCB_PLLCTRL_BYPASS_MASK ((unsigned int) 0x00000100) // Input clock bypass control
276 #define SCB_PLLCTRL_MASK ((unsigned int) 0x000001FF)
277
278 /* SYSPLLSTAT (System PLL status register)
279 This register is a Read-only register and supplies the PLL lock status */
280
281 #define SCB_PLLSTAT_LOCK ((unsigned int) 0x00000001) // 0 = PLL not locked, 1 = PLL locked
282 #define SCB_PLLSTAT_LOCK_MASK ((unsigned int) 0x00000001)
283
284 /* USBPLLCTRL (USB PLL control register)
285 The USB PLL is identical to the system PLL and is used to provide a dedicated clock to
286 the USB block if available. The USB PLL should be always connected to the system
287 oscillator to produce a stable USB clock. */
288
289 #define SCB_USBPLLCTRL_MULT_1 ((unsigned int) 0x00000000)
290 #define SCB_USBPLLCTRL_MULT_2 ((unsigned int) 0x00000001)
291 #define SCB_USBPLLCTRL_MULT_3 ((unsigned int) 0x00000002)
292 #define SCB_USBPLLCTRL_MULT_4 ((unsigned int) 0x00000003)
293 #define SCB_USBPLLCTRL_MULT_5 ((unsigned int) 0x00000004)
294 #define SCB_USBPLLCTRL_MULT_6 ((unsigned int) 0x00000005)
295 #define SCB_USBPLLCTRL_MULT_7 ((unsigned int) 0x00000006)
296 #define SCB_USBPLLCTRL_MULT_8 ((unsigned int) 0x00000007)
297 #define SCB_USBPLLCTRL_MULT_9 ((unsigned int) 0x00000008)
298 #define SCB_USBPLLCTRL_MULT_10 ((unsigned int) 0x00000009)
299 #define SCB_USBPLLCTRL_MULT_11 ((unsigned int) 0x0000000A)
300 #define SCB_USBPLLCTRL_MULT_12 ((unsigned int) 0x0000000B)
301 #define SCB_USBPLLCTRL_MULT_13 ((unsigned int) 0x0000000C)
302 #define SCB_USBPLLCTRL_MULT_14 ((unsigned int) 0x0000000D)
303 #define SCB_USBPLLCTRL_MULT_15 ((unsigned int) 0x0000000E)
304 #define SCB_USBPLLCTRL_MULT_16 ((unsigned int) 0x0000000F)
305 #define SCB_USBPLLCTRL_MULT_17 ((unsigned int) 0x00000010)
306 #define SCB_USBPLLCTRL_MULT_18 ((unsigned int) 0x00000011)
307 #define SCB_USBPLLCTRL_MULT_19 ((unsigned int) 0x00000012)
308 #define SCB_USBPLLCTRL_MULT_20 ((unsigned int) 0x00000013)
309 #define SCB_USBPLLCTRL_MULT_21 ((unsigned int) 0x00000014)
310 #define SCB_USBPLLCTRL_MULT_22 ((unsigned int) 0x00000015)
311 #define SCB_USBPLLCTRL_MULT_23 ((unsigned int) 0x00000016)
312 #define SCB_USBPLLCTRL_MULT_24 ((unsigned int) 0x00000017)
313 #define SCB_USBPLLCTRL_MULT_25 ((unsigned int) 0x00000018)
314 #define SCB_USBPLLCTRL_MULT_26 ((unsigned int) 0x00000019)
315 #define SCB_USBPLLCTRL_MULT_27 ((unsigned int) 0x0000001A)
316 #define SCB_USBPLLCTRL_MULT_28 ((unsigned int) 0x0000001B)
317 #define SCB_USBPLLCTRL_MULT_29 ((unsigned int) 0x0000001C)
318 #define SCB_USBPLLCTRL_MULT_30 ((unsigned int) 0x0000001D)
319 #define SCB_USBPLLCTRL_MULT_31 ((unsigned int) 0x0000001E)
320 #define SCB_USBPLLCTRL_MULT_32 ((unsigned int) 0x0000001F)
321 #define SCB_USBPLLCTRL_MULT_MASK ((unsigned int) 0x0000001F)
322 #define SCB_USBPLLCTRL_DIV_2 ((unsigned int) 0x00000000)
323 #define SCB_USBPLLCTRL_DIV_4 ((unsigned int) 0x00000020)
324 #define SCB_USBPLLCTRL_DIV_8 ((unsigned int) 0x00000040)
325 #define SCB_USBPLLCTRL_DIV_16 ((unsigned int) 0x00000060)
326 #define SCB_USBPLLCTRL_DIV_BIT (5)
327 #define SCB_USBPLLCTRL_DIV_MASK ((unsigned int) 0x00000060)
328 #define SCB_USBPLLCTRL_DIRECT_MASK ((unsigned int) 0x00000080) // Direct CCO clock output control
329 #define SCB_USBPLLCTRL_BYPASS_MASK ((unsigned int) 0x00000100) // Input clock bypass control
330 #define SCB_USBPLLCTRL_MASK ((unsigned int) 0x000001FF)
331
332 /* USBPLLSTAT (System PLL status register)
333 This register is a Read-only register and supplies the PLL lock status. */
334
335 #define SCB_USBPLLSTAT_LOCK ((unsigned int) 0x00000001) // 0 = PLL not locked, 1 = PLL locked
336 #define SCB_USBPLLSTAT_LOCK_MASK ((unsigned int) 0x00000001)
337
338 /* SYSOSCCTRL (System oscillator control register)
339 This register configures the frequency range for the system oscillator. */
340
341 #define SCB_SYSOSCCTRL_BYPASS_DISABLED ((unsigned int) 0x00000000) // Oscillator is not bypassed.
342 #define SCB_SYSOSCCTRL_BYPASS_ENABLED ((unsigned int) 0x00000001) // Bypass enabled
343 #define SCB_SYSOSCCTRL_BYPASS_MASK ((unsigned int) 0x00000001)
344 #define SCB_SYSOSCCTRL_FREQRANGE_1TO20MHZ ((unsigned int) 0x00000000) // 1-20 MHz frequency range
345 #define SCB_SYSOSCCTRL_FREQRANGE_15TO25MHZ ((unsigned int) 0x00000002) // 15-25 MHz frequency range
346 #define SCB_SYSOSCCTRL_FREQRANGE_MASK ((unsigned int) 0x00000002)
347
348 /* WDTOSCTRL (Watchdog oscillator control register)
349 This register configures the watchdog oscillator. The oscillator consists of an analog and a
350 digital part. The analog part contains the oscillator function and generates an analog clock
351 (Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the
352 required output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can
353 be adjusted with the FREQSEL bits between 500 kHz and 3.7 MHz. With the digital part
354 Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.*/
355
356 #define SCB_WDTOSCCTRL_DIVSEL_DIV2 ((unsigned int) 0x00000000) // Reset value
357 #define SCB_WDTOSCCTRL_DIVSEL_DIV4 ((unsigned int) 0x00000001)
358 #define SCB_WDTOSCCTRL_DIVSEL_DIV6 ((unsigned int) 0x00000002)
359 #define SCB_WDTOSCCTRL_DIVSEL_DIV8 ((unsigned int) 0x00000003)
360 #define SCB_WDTOSCCTRL_DIVSEL_DIV10 ((unsigned int) 0x00000004)
361 #define SCB_WDTOSCCTRL_DIVSEL_DIV12 ((unsigned int) 0x00000005)
362 #define SCB_WDTOSCCTRL_DIVSEL_DIV14 ((unsigned int) 0x00000006)
363 #define SCB_WDTOSCCTRL_DIVSEL_DIV16 ((unsigned int) 0x00000007)
364 #define SCB_WDTOSCCTRL_DIVSEL_DIV18 ((unsigned int) 0x00000008)
365 #define SCB_WDTOSCCTRL_DIVSEL_DIV20 ((unsigned int) 0x00000009)
366 #define SCB_WDTOSCCTRL_DIVSEL_DIV22 ((unsigned int) 0x0000000A)
367 #define SCB_WDTOSCCTRL_DIVSEL_DIV24 ((unsigned int) 0x0000000B)
368 #define SCB_WDTOSCCTRL_DIVSEL_DIV26 ((unsigned int) 0x0000000C)
369 #define SCB_WDTOSCCTRL_DIVSEL_DIV28 ((unsigned int) 0x0000000D)
370 #define SCB_WDTOSCCTRL_DIVSEL_DIV30 ((unsigned int) 0x0000000E)
371 #define SCB_WDTOSCCTRL_DIVSEL_DIV32 ((unsigned int) 0x0000000F)
372 #define SCB_WDTOSCCTRL_DIVSEL_DIV34 ((unsigned int) 0x00000010)
373 #define SCB_WDTOSCCTRL_DIVSEL_DIV36 ((unsigned int) 0x00000011)
374 #define SCB_WDTOSCCTRL_DIVSEL_DIV38 ((unsigned int) 0x00000012)
375 #define SCB_WDTOSCCTRL_DIVSEL_DIV40 ((unsigned int) 0x00000013)
376 #define SCB_WDTOSCCTRL_DIVSEL_DIV42 ((unsigned int) 0x00000014)
377 #define SCB_WDTOSCCTRL_DIVSEL_DIV44 ((unsigned int) 0x00000015)
378 #define SCB_WDTOSCCTRL_DIVSEL_DIV46 ((unsigned int) 0x00000016)
379 #define SCB_WDTOSCCTRL_DIVSEL_DIV48 ((unsigned int) 0x00000017)
380 #define SCB_WDTOSCCTRL_DIVSEL_DIV50 ((unsigned int) 0x00000018)
381 #define SCB_WDTOSCCTRL_DIVSEL_DIV52 ((unsigned int) 0x00000019)
382 #define SCB_WDTOSCCTRL_DIVSEL_DIV54 ((unsigned int) 0x0000001A)
383 #define SCB_WDTOSCCTRL_DIVSEL_DIV56 ((unsigned int) 0x0000001B)
384 #define SCB_WDTOSCCTRL_DIVSEL_DIV58 ((unsigned int) 0x0000001C)
385 #define SCB_WDTOSCCTRL_DIVSEL_DIV60 ((unsigned int) 0x0000001D)
386 #define SCB_WDTOSCCTRL_DIVSEL_DIV62 ((unsigned int) 0x0000001E)
387 #define SCB_WDTOSCCTRL_DIVSEL_DIV64 ((unsigned int) 0x0000001F)
388 #define SCB_WDTOSCCTRL_DIVSEL_MASK ((unsigned int) 0x0000001F)
389 #define SCB_WDTOSCCTRL_FREQSEL_0_5MHZ ((unsigned int) 0x00000020)
390 #define SCB_WDTOSCCTRL_FREQSEL_0_8MHZ ((unsigned int) 0x00000040)
391 #define SCB_WDTOSCCTRL_FREQSEL_1_1MHZ ((unsigned int) 0x00000060)
392 #define SCB_WDTOSCCTRL_FREQSEL_1_4MHZ ((unsigned int) 0x00000080)
393 #define SCB_WDTOSCCTRL_FREQSEL_1_6MHZ ((unsigned int) 0x000000A0) // Reset value
394 #define SCB_WDTOSCCTRL_FREQSEL_1_8MHZ ((unsigned int) 0x000000C0)
395 #define SCB_WDTOSCCTRL_FREQSEL_2_0MHZ ((unsigned int) 0x000000E0)
396 #define SCB_WDTOSCCTRL_FREQSEL_2_2MHZ ((unsigned int) 0x00000100)
397 #define SCB_WDTOSCCTRL_FREQSEL_2_4MHZ ((unsigned int) 0x00000120)
398 #define SCB_WDTOSCCTRL_FREQSEL_2_6MHZ ((unsigned int) 0x00000140)
399 #define SCB_WDTOSCCTRL_FREQSEL_2_7MHZ ((unsigned int) 0x00000160)
400 #define SCB_WDTOSCCTRL_FREQSEL_2_9MHZ ((unsigned int) 0x00000180)
401 #define SCB_WDTOSCCTRL_FREQSEL_3_1MHZ ((unsigned int) 0x000001A0)
402 #define SCB_WDTOSCCTRL_FREQSEL_3_2MHZ ((unsigned int) 0x000001C0)
403 #define SCB_WDTOSCCTRL_FREQSEL_3_4MHZ ((unsigned int) 0x000001E0)
404 #define SCB_WDTOSCCTRL_FREQSEL_MASK ((unsigned int) 0x000001E0)
405
406 /* IRCCTRL (Internal resonant crystal control register)
407 This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset
408 and written by the boot code on start-up. */
409
410 #define SCB_IRCCTRL_MASK ((unsigned int) 0x000000FF)
411
412 /* SYSRSTSTAT (System reset status register)
413 The SYSRSTSTAT register shows the source of the latest reset event. The bits are
414 cleared by writing a one to any of the bits. The POR event clears all other bits in this
415 register, but if another reset signal (e.g., EXTRST) remains asserted after the POR signal
416 is negated, then its bit is set to detected. */
417
418 #define SCB_RESETSTAT_POR_MASK ((unsigned int) 0x00000001) // POR reset status
419 #define SCB_RESETSTAT_EXTRST_MASK ((unsigned int) 0x00000002) // Status of the external reset pin
420 #define SCB_RESETSTAT_WDT_MASK ((unsigned int) 0x00000004) // Status of the watchdog reset
421 #define SCB_RESETSTAT_BOD_MASK ((unsigned int) 0x00000008) // Status of the brown-out detect reset
422 #define SCB_RESETSTAT_SYSRST_MASK ((unsigned int) 0x00000010) // Status of the software system reset
423 #define SCB_RESETSTAT_MASK ((unsigned int) 0x00000010)
424
425 /* SYSPLLCLKSEL (System PLL clock source select register)
426 This register selects the clock source for the system PLL. The SYSPLLCLKUEN register
427 must be toggled from LOW to HIGH for the update to take effect.
428 Remark: The system oscillator must be selected if the system PLL is used to generate a
429 48 MHz clock to the USB block.
430 */
431
432 #define SCB_CLKSEL_SOURCE_INTERNALOSC ((unsigned int) 0x00000000)
433 #define SCB_CLKSEL_SOURCE_MAINOSC ((unsigned int) 0x00000001)
434 #define SCB_CLKSEL_SOURCE_RTCOSC ((unsigned int) 0x00000002)
435 #define SCB_CLKSEL_SOURCE_MASK ((unsigned int) 0x00000002)
436
437 /* SYSPLLUEN (System PLL clock source update enable register)
438 This register updates the clock source of the system PLL with the new input clock after the
439 SYSPLLCLKSEL register has been written to. In order for the update to take effect, first
440 write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN. */
441
442 #define SCB_PLLCLKUEN_DISABLE ((unsigned int) 0x00000000)
443 #define SCB_PLLCLKUEN_UPDATE ((unsigned int) 0x00000001)
444 #define SCB_PLLCLKUEN_MASK ((unsigned int) 0x00000001)
445
446 /* USBPLLCLKSEL (USB PLL clock source select register)
447 his register selects the clock source for the dedicated USB PLL. The SYSPLLCLKUEN
448 register must be toggled from LOW to HIGH for the update to take effect.
449 Remark: Always select the system oscillator to produce a stable 48 MHz clock for
450 the USB block. */
451
452 #define SCB_USBPLLCLKSEL_SOURCE_INTERNALOSC ((unsigned int) 0x00000000) // Do NOT use (even though this is the default value)
453 #define SCB_USBPLLCLKSEL_SOURCE_MAINOSC ((unsigned int) 0x00000001) // Main oscillator should always be used for USB clock
454 #define SCB_USBPLLCLKSEL_SOURCE_MASK ((unsigned int) 0x00000002)
455
456 /* USBPLLUEN (USB PLL clock source update enable register)
457 This register updates the clock source of the USB PLL with the new input clock after the
458 USBPLLCLKSEL register has been written to. In order for the update to take effect at the
459 USB PLL input, first write a zero to the USBPLLUEN register and then write a one to
460 USBPLLUEN. */
461
462 #define SCB_USBPLLCLKUEN_DISABLE ((unsigned int) 0x00000000)
463 #define SCB_USBPLLCLKUEN_UPDATE ((unsigned int) 0x00000001)
464 #define SCB_USBPLLCLKUEN_MASK ((unsigned int) 0x00000001)
465
466 /* MAINCLKSEL (Main clock source select register)
467 This register selects the main system clock which can be either the output from the
468 system PLL or the IRC, system, or Watchdog oscillators directly. The main system clock
469 clocks the core, the peripherals, and optionally the USB block.
470 The MAINCLKUEN register must be toggled from LOW to HIGH for the update to take effect.*/
471
472 #define SCB_MAINCLKSEL_SOURCE_INTERNALOSC ((unsigned int) 0x00000000) // Use IRC oscillator for main clock source
473 #define SCB_MAINCLKSEL_SOURCE_INPUTCLOCK ((unsigned int) 0x00000001) // Use Input clock to system PLL for main clock source
474 #define SCB_MAINCLKSEL_SOURCE_WDTOSC ((unsigned int) 0x00000002) // Use watchdog oscillator for main clock source
475 #define SCB_MAINCLKSEL_SOURCE_SYSPLLCLKOUT ((unsigned int) 0x00000003) // Use system PLL clock out for main clock source
476 #define SCB_MAINCLKSEL_MASK ((unsigned int) 0x00000003)
477
478 /* MAINCLKUEN (Main clock source update enable register)
479 This register updates the clock source of the main clock with the new input clock after the
480 MAINCLKSEL register has been written to. In order for the update to take effect, first write
481 a zero to the MAINUEN register and then write a one to MAINCLKUEN. */
482
483 #define SCB_MAINCLKUEN_DISABLE ((unsigned int) 0x00000000)
484 #define SCB_MAINCLKUEN_UPDATE ((unsigned int) 0x00000001)
485 #define SCB_MAINCLKUEN_MASK ((unsigned int) 0x00000001)
486
487 /* SYSAHBCLKDIV (System AHB clock divider register)
488 This register divides the main clock to provide the system clock to the core, memories,
489 and the peripherals. The system clock can be shut down completely by setting the DIV
490 bits to 0x0. */
491
492 #define SCB_SYSAHBCLKDIV_DISABLE ((unsigned int) 0x00000000) // 0 will shut the system clock down completely
493 #define SCB_SYSAHBCLKDIV_DIV1 ((unsigned int) 0x00000001) // 1, 2 or 4 are the most common values
494 #define SCB_SYSAHBCLKDIV_DIV2 ((unsigned int) 0x00000002)
495 #define SCB_SYSAHBCLKDIV_DIV4 ((unsigned int) 0x00000004)
496 #define SCB_SYSAHBCLKDIV_MASK ((unsigned int) 0x000000FF) // AHB clock divider can be from 0 to 255
497
498 /* AHBCLKCTRL (System AHB clock control register)
499 The AHBCLKCTRL register enables the clocks to individual system and peripheral blocks.
500 The system clock (sys_ahb_clk[0], bit 0 in the AHBCLKCTRL register) provides the clock
501 for the AHB to APB bridge, the AHB matrix, the ARM Cortex-M3, the Syscon block, and
502 the PMU. This clock cannot be disabled. */
503
504 #define SCB_SYSAHBCLKCTRL_SYS ((unsigned int) 0x00000001) // Enables clock for AHB and APB bridges, FCLK, HCLK, SysCon and PMU
505 #define SCB_SYSAHBCLKCTRL_SYS_MASK ((unsigned int) 0x00000001)
506 #define SCB_SYSAHBCLKCTRL_ROM ((unsigned int) 0x00000002) // Enables clock for ROM
507 #define SCB_SYSAHBCLKCTRL_ROM_MASK ((unsigned int) 0x00000002)
508 #define SCB_SYSAHBCLKCTRL_RAM ((unsigned int) 0x00000004) // Enables clock for SRAM
509 #define SCB_SYSAHBCLKCTRL_RAM_MASK ((unsigned int) 0x00000004)
510 #define SCB_SYSAHBCLKCTRL_FLASH1 ((unsigned int) 0x00000008) // Enables clock for flash1
511 #define SCB_SYSAHBCLKCTRL_FLASH1_MASK ((unsigned int) 0x00000008)
512 #define SCB_SYSAHBCLKCTRL_FLASH2 ((unsigned int) 0x00000010) // Enables clock for flash2
513 #define SCB_SYSAHBCLKCTRL_FLASH2_MASK ((unsigned int) 0x00000010)
514 #define SCB_SYSAHBCLKCTRL_I2C ((unsigned int) 0x00000020) // Enables clock for I2C
515 #define SCB_SYSAHBCLKCTRL_I2C_MASK ((unsigned int) 0x00000020)
516 #define SCB_SYSAHBCLKCTRL_GPIO ((unsigned int) 0x00000040) // Enables clock for GPIO
517 #define SCB_SYSAHBCLKCTRL_GPIO_MASK ((unsigned int) 0x00000040)
518 #define SCB_SYSAHBCLKCTRL_CT16B0 ((unsigned int) 0x00000080) // Enables clock for 16-bit counter/timer 0
519 #define SCB_SYSAHBCLKCTRL_CT16B0_MASK ((unsigned int) 0x00000080)
520 #define SCB_SYSAHBCLKCTRL_CT16B1 ((unsigned int) 0x00000100) // Enables clock for 16-bit counter/timer 1
521 #define SCB_SYSAHBCLKCTRL_CT16B1_MASK ((unsigned int) 0x00000100)
522 #define SCB_SYSAHBCLKCTRL_CT32B0 ((unsigned int) 0x00000200) // Enables clock for 32-bit counter/timer 0
523 #define SCB_SYSAHBCLKCTRL_CT32B0_MASK ((unsigned int) 0x00000200)
524 #define SCB_SYSAHBCLKCTRL_CT32B1 ((unsigned int) 0x00000400) // Enables clock for 32-bit counter/timer 1
525 #define SCB_SYSAHBCLKCTRL_CT32B1_MASK ((unsigned int) 0x00000400)
526 #define SCB_SYSAHBCLKCTRL_SSP0 ((unsigned int) 0x00000800) // Enables clock for SSP0
527 #define SCB_SYSAHBCLKCTRL_SSP0_MASK ((unsigned int) 0x00000800)
528 #define SCB_SYSAHBCLKCTRL_UART ((unsigned int) 0x00001000) // Enables clock for UART. UART pins must be configured
529 #define SCB_SYSAHBCLKCTRL_UART_MASK ((unsigned int) 0x00001000) // in the IOCON block before the UART clock can be enabled.
530 #define SCB_SYSAHBCLKCTRL_ADC ((unsigned int) 0x00002000) // Enables clock for ADC
531 #define SCB_SYSAHBCLKCTRL_ADC_MASK ((unsigned int) 0x00002000)
532 #define SCB_SYSAHBCLKCTRL_USB_REG ((unsigned int) 0x00004000) // Enables clock for USB_REG
533 #define SCB_SYSAHBCLKCTRL_USB_REG_MASK ((unsigned int) 0x00004000)
534 #define SCB_SYSAHBCLKCTRL_WDT ((unsigned int) 0x00008000) // Enables clock for watchdog timer
535 #define SCB_SYSAHBCLKCTRL_WDT_MASK ((unsigned int) 0x00008000)
536 #define SCB_SYSAHBCLKCTRL_IOCON ((unsigned int) 0x00010000) // Enables clock for IO configuration block
537 #define SCB_SYSAHBCLKCTRL_IOCON_MASK ((unsigned int) 0x00010000)
538 #define SCB_SYSAHBCLKCTRL_ALL_MASK ((unsigned int) 0x0001FFFF)
539
540 /* SSP0CLKDIV (SSP0 clock divider register)
541 This register configures the SSP0 peripheral clock SSP_PCLK. The SSP_PCLK can be
542 shut down by setting the DIV bits to 0x0. It can be set from 1..255. */
543
544 #define SCB_SSP0CLKDIV_DISABLE ((unsigned int) 0x00000000)
545 #define SCB_SSP0CLKDIV_DIV1 ((unsigned int) 0x00000001) // Divide SSP0 clock by 1 (can be set from 1..255)
546 #define SCB_SSP0CLKDIV_DIV2 ((unsigned int) 0x00000002)
547 #define SCB_SSP0CLKDIV_DIV3 ((unsigned int) 0x00000003)
548 #define SCB_SSP0CLKDIV_DIV4 ((unsigned int) 0x00000004)
549 #define SCB_SSP0CLKDIV_DIV6 ((unsigned int) 0x00000006)
550 #define SCB_SSP0CLKDIV_DIV10 ((unsigned int) 0x0000000A)
551 #define SCB_SSP0CLKDIV_DIV12 ((unsigned int) 0x0000000C)
552 #define SCB_SSP0CLKDIV_DIV20 ((unsigned int) 0x00000014)
553 #define SCB_SSP0CLKDIV_DIV40 ((unsigned int) 0x00000028)
554 #define SCB_SSP0CLKDIV_MASK ((unsigned int) 0x000000FF)
555
556 /* UARTCLKDIV (UART clock divider register)
557 This register configures the UART peripheral. The UART_PCLK can be shut down by
558 setting the DIV bits to 0x0.
559 Remark: Note that the UART pins must be configured in the IOCON block before the
560 UART clock can be enabled. */
561
562 #define SCB_UARTCLKDIV_DISABLE ((unsigned int) 0x00000000)
563 #define SCB_UARTCLKDIV_DIV1 ((unsigned int) 0x00000001) // Divide UART clock by 1 (can be set from 1..255)
564 #define SCB_UARTCLKDIV_DIV2 ((unsigned int) 0x00000002)
565 #define SCB_UARTCLKDIV_DIV4 ((unsigned int) 0x00000004)
566 #define SCB_UARTCLKDIV_MASK ((unsigned int) 0x000000FF)
567
568 /* SYSTICKCLKDIV (SYSTICK clock divider register)
569 This register configures the SYSTICK peripheral clock. The SYSTICK timer clock can be
570 shut down by setting the DIV bits to 0x0. */
571
572 #define SCB_SYSTICKCLKDIV_DISABLE ((unsigned int) 0x00000000)
573 #define SCB_SYSTICKCLKDIV_DIV1 ((unsigned int) 0x00000001) // Divide SYSTICK clock by 1 (can be set from 1..255)
574 #define SCB_SYSTICKCLKDIV_DIV2 ((unsigned int) 0x00000002) // Divide SYSTICK clock by 2
575 #define SCB_SYSTICKCLKDIV_DIV4 ((unsigned int) 0x00000004) // Divide SYSTICK clock by 4
576 #define SCB_SYSTICKCLKDIV_DIV8 ((unsigned int) 0x00000008) // Divide SYSTICK clock by 8
577 #define SCB_SYSTICKCLKDIV_MASK ((unsigned int) 0x000000FF)
578
579 /* USBCLKSEL (USB clock source select register)
580 This register selects the clock source for the USB usb_clk. The clock source can be either
581 the USB PLL output or the main clock, and the clock can be further divided by the
582 USBCLKDIV register to obtain a 48 MHz clock. The USBCLKUEN register must be toggled from
583 LOW to HIGH for the update to take effect. */
584
585 #define SCB_USBCLKSEL_SOURCE_USBPLLOUT ((unsigned int) 0x00000000) // USB PLL output
586 #define SCB_USBCLKSEL_SOURCE_INPUTCLOCK ((unsigned int) 0x00000001) // Use the main clock
587 #define SCB_USBCLKSEL_MASK ((unsigned int) 0x00000003)
588
589 /* USBCLKUEN (USB clock source update enable register)
590 This register updates the clock source of the USB with the new input clock after the
591 USBCLKSEL register has been written to. In order for the update to take effect, first write
592 a zero to the USBCLKUEN register and then write a one to USBCLKUEN. */
593
594 #define SCB_USBCLKUEN_DISABLE ((unsigned int) 0x00000000)
595 #define SCB_USBCLKUEN_UPDATE ((unsigned int) 0x00000001)
596 #define SCB_USBCLKUEN_MASK ((unsigned int) 0x00000001)
597
598 /* USBCLKDIV (USB clock divider register)
599 This register allows the USB clock usb_clk to be divided to 48 MHz. The usb_clk can be
600 shut down by setting the DIV bits to 0x0. */
601
602 #define SCB_USBCLKDIV_DISABLE ((unsigned int) 0x00000000)
603 #define SCB_USBCLKDIV_DIV1 ((unsigned int) 0x00000001) // Divide USB clock by 1 (can be set from 1..255)
604 #define SCB_USBCLKDIV_MASK ((unsigned int) 0x000000FF)
605
606 /* WDTCLKSEL (WDT clock source select register)
607 This register selects the clock source for the watchdog timer. The WDTCLKUEN register
608 must be toggled from LOW to HIGH for the update to take effect. */
609
610 #define SCB_WDTCLKSEL_SOURCE_INTERNALOSC ((unsigned int) 0x00000000) // Use the internal oscillator
611 #define SCB_WDTCLKSEL_SOURCE_INPUTCLOCK ((unsigned int) 0x00000001) // Use the main clock
612 #define SCB_WDTCLKSEL_SOURCE_WATCHDOGOSC ((unsigned int) 0x00000002) // Use the watchdog oscillator
613 #define SCB_WDTCLKSEL_MASK ((unsigned int) 0x00000003)
614
615 /* WDTCLKUEN (WDT clock source update enable register)
616 This register updates the clock source of the watchdog timer with the new input clock after
617 the WDTCLKSEL register has been written to. In order for the update to take effect at the
618 input of the watchdog timer, first write a zero to the WDTCLKUEN register and then write
619 a one to WDTCLKUEN. */
620
621 #define SCB_WDTCLKUEN_DISABLE ((unsigned int) 0x00000000)
622 #define SCB_WDTCLKUEN_UPDATE ((unsigned int) 0x00000001)
623 #define SCB_WDTCLKUEN_MASK ((unsigned int) 0x00000001)
624
625 /* WDTCLKDIV (WDT clock divider register)
626 This register determines the divider values for the watchdog clock wdt_clk. */
627
628 #define SCB_WDTCLKDIV_DISABLE ((unsigned int) 0x00000000)
629 #define SCB_WDTCLKDIV_DIV1 ((unsigned int) 0x00000001) // Divide clock by 1 (can be set from 1..255)
630 #define SCB_WDTCLKDIV_MASK ((unsigned int) 0x000000FF)
631
632 /* CLKOUTCLKSEL (CLKOUT clock source select register)
633 This register configures the clkout_clk signal to be output on the CLKOUT pin. All three
634 oscillators and the main clock can be selected for the clkout_clk clock.
635 The CLKOUTCLKUEN register must be toggled from LOW to HIGH for the update to take effect. */
636
637 #define SCB_CLKOUTCLKSEL_SOURCE_USBPLLOUT ((unsigned int) 0x00000000) // USB PLL output
638 #define SCB_CLKOUTCLKSEL_SOURCE_INPUTCLOCK ((unsigned int) 0x00000001) // Use the main clock
639 #define SCB_CLKOUTCLKSEL_MASK ((unsigned int) 0x00000003)
640
641 /* CLKOUTUEN (CLKOUT clock source update enable register)
642 This register updates the clock source of the CLKOUT pin with the new clock after the
643 CLKOUTCLKSEL register has been written to. In order for the update to take effect at the
644 input of the CLKOUT pin, first write a zero to the CLKCLKUEN register and then write a
645 one to CLKCLKUEN. */
646
647 #define SCB_CLKOUTCLKUEN_DISABLE ((unsigned int) 0x00000000)
648 #define SCB_CLKOUTCLKUEN_UPDATE ((unsigned int) 0x00000001)
649 #define SCB_CLKOUTCLKUEN_MASK ((unsigned int) 0x00000001)
650
651 /* CLKOUTCLKDIV (CLKOUT clock divider register)
652 This register determines the divider value for the clkout_clk signal on the CLKOUT pin. */
653
654 #define SCB_CLKOUTCLKDIV_DISABLE ((unsigned int) 0x00000000)
655 #define SCB_CLKOUTCLKDIV_DIV1 ((unsigned int) 0x00000001) // Divide clock by 1 (can be set from 1..255)
656 #define SCB_CLKOUTCLKDIV_MASK ((unsigned int) 0x000000FF)
657
658
659 /* PIOPORCAP0 (POR captured PIO status register 0)
660 The PIOPORCAP0 register captures the state (HIGH or LOW) of the PIO pins of ports 0,1,
661 and 2 (pins PIO2_0 to PIO2_7) at power-on-reset. Each bit represents the reset state of
662 one GPIO pin. This register is a read-only status register. */
663
664 #define SCB_PIOPORCAP0_PIO0_0 ((unsigned int) 0x00000001)
665 #define SCB_PIOPORCAP0_PIO0_0_MASK ((unsigned int) 0x00000001)
666 #define SCB_PIOPORCAP0_PIO0_1 ((unsigned int) 0x00000002)
667 #define SCB_PIOPORCAP0_PIO0_1_MASK ((unsigned int) 0x00000002)
668 #define SCB_PIOPORCAP0_PIO0_2 ((unsigned int) 0x00000004)
669 #define SCB_PIOPORCAP0_PIO0_2_MASK ((unsigned int) 0x00000004)
670 #define SCB_PIOPORCAP0_PIO0_3 ((unsigned int) 0x00000008)
671 #define SCB_PIOPORCAP0_PIO0_3_MASK ((unsigned int) 0x00000008)
672 #define SCB_PIOPORCAP0_PIO0_4 ((unsigned int) 0x00000010)
673 #define SCB_PIOPORCAP0_PIO0_4_MASK ((unsigned int) 0x00000010)
674 #define SCB_PIOPORCAP0_PIO0_5 ((unsigned int) 0x00000020)
675 #define SCB_PIOPORCAP0_PIO0_5_MASK ((unsigned int) 0x00000020)
676 #define SCB_PIOPORCAP0_PIO0_6 ((unsigned int) 0x00000040)
677 #define SCB_PIOPORCAP0_PIO0_6_MASK ((unsigned int) 0x00000040)
678 #define SCB_PIOPORCAP0_PIO0_7 ((unsigned int) 0x00000080)
679 #define SCB_PIOPORCAP0_PIO0_7_MASK ((unsigned int) 0x00000080)
680 #define SCB_PIOPORCAP0_PIO0_8 ((unsigned int) 0x00000100)
681 #define SCB_PIOPORCAP0_PIO0_8_MASK ((unsigned int) 0x00000100)
682 #define SCB_PIOPORCAP0_PIO0_9 ((unsigned int) 0x00000200)
683 #define SCB_PIOPORCAP0_PIO0_9_MASK ((unsigned int) 0x00000200)
684 #define SCB_PIOPORCAP0_PIO0_10 ((unsigned int) 0x00000400)
685 #define SCB_PIOPORCAP0_PIO0_10_MASK ((unsigned int) 0x00000400)
686 #define SCB_PIOPORCAP0_PIO0_11 ((unsigned int) 0x00000800)
687 #define SCB_PIOPORCAP0_PIO0_11_MASK ((unsigned int) 0x00000800)
688 #define SCB_PIOPORCAP0_PIO1_0 ((unsigned int) 0x00001000)
689 #define SCB_PIOPORCAP0_PIO1_0_MASK ((unsigned int) 0x00001000)
690 #define SCB_PIOPORCAP0_PIO1_1 ((unsigned int) 0x00002000)
691 #define SCB_PIOPORCAP0_PIO1_1_MASK ((unsigned int) 0x00002000)
692 #define SCB_PIOPORCAP0_PIO1_2 ((unsigned int) 0x00004000)
693 #define SCB_PIOPORCAP0_PIO1_2_MASK ((unsigned int) 0x00004000)
694 #define SCB_PIOPORCAP0_PIO1_3 ((unsigned int) 0x00008000)
695 #define SCB_PIOPORCAP0_PIO1_3_MASK ((unsigned int) 0x00008000)
696 #define SCB_PIOPORCAP0_PIO1_4 ((unsigned int) 0x00010000)
697 #define SCB_PIOPORCAP0_PIO1_4_MASK ((unsigned int) 0x00010000)
698 #define SCB_PIOPORCAP0_PIO1_5 ((unsigned int) 0x00020000)
699 #define SCB_PIOPORCAP0_PIO1_5_MASK ((unsigned int) 0x00020000)
700 #define SCB_PIOPORCAP0_PIO1_6 ((unsigned int) 0x00040000)
701 #define SCB_PIOPORCAP0_PIO1_6_MASK ((unsigned int) 0x00040000)
702 #define SCB_PIOPORCAP0_PIO1_7 ((unsigned int) 0x00080000)
703 #define SCB_PIOPORCAP0_PIO1_7_MASK ((unsigned int) 0x00080000)
704 #define SCB_PIOPORCAP0_PIO1_8 ((unsigned int) 0x00100000)
705 #define SCB_PIOPORCAP0_PIO1_8_MASK ((unsigned int) 0x00100000)
706 #define SCB_PIOPORCAP0_PIO1_9 ((unsigned int) 0x00200000)
707 #define SCB_PIOPORCAP0_PIO1_9_MASK ((unsigned int) 0x00200000)
708 #define SCB_PIOPORCAP0_PIO1_10 ((unsigned int) 0x00400000)
709 #define SCB_PIOPORCAP0_PIO1_10_MASK ((unsigned int) 0x00400000)
710 #define SCB_PIOPORCAP0_PIO1_11 ((unsigned int) 0x00800000)
711 #define SCB_PIOPORCAP0_PIO1_11_MASK ((unsigned int) 0x00800000)
712 #define SCB_PIOPORCAP0_PIO2_0 ((unsigned int) 0x01000000)
713 #define SCB_PIOPORCAP0_PIO2_0_MASK ((unsigned int) 0x01000000)
714 #define SCB_PIOPORCAP0_PIO2_1 ((unsigned int) 0x02000000)
715 #define SCB_PIOPORCAP0_PIO2_1_MASK ((unsigned int) 0x02000000)
716 #define SCB_PIOPORCAP0_PIO2_2 ((unsigned int) 0x04000000)
717 #define SCB_PIOPORCAP0_PIO2_2_MASK ((unsigned int) 0x04000000)
718 #define SCB_PIOPORCAP0_PIO2_3 ((unsigned int) 0x08000000)
719 #define SCB_PIOPORCAP0_PIO2_3_MASK ((unsigned int) 0x08000000)
720 #define SCB_PIOPORCAP0_PIO2_4 ((unsigned int) 0x10000000)
721 #define SCB_PIOPORCAP0_PIO2_4_MASK ((unsigned int) 0x10000000)
722 #define SCB_PIOPORCAP0_PIO2_5 ((unsigned int) 0x20000000)
723 #define SCB_PIOPORCAP0_PIO2_5_MASK ((unsigned int) 0x20000000)
724 #define SCB_PIOPORCAP0_PIO2_6 ((unsigned int) 0x40000000)
725 #define SCB_PIOPORCAP0_PIO2_6_MASK ((unsigned int) 0x40000000)
726 #define SCB_PIOPORCAP0_PIO2_7 ((unsigned int) 0x80000000)
727 #define SCB_PIOPORCAP0_PIO2_7_MASK ((unsigned int) 0x80000000)
728
729 /* PIOPORCAP1 (POR captured PIO status register 1)
730 The PIOPORCAP1 register captures the state (HIGH or LOW) of the PIO pins of port 2
731 (PIO2_8 to PIO2_11) and port 3 at power-on-reset. Each bit represents the reset state of
732 one PIO pin. This register is a read-only status register. */
733
734 #define SCB_PIOPORCAP1_PIO2_8 ((unsigned int) 0x00000001)
735 #define SCB_PIOPORCAP1_PIO2_8_MASK ((unsigned int) 0x00000001)
736 #define SCB_PIOPORCAP1_PIO2_9 ((unsigned int) 0x00000002)
737 #define SCB_PIOPORCAP1_PIO2_9_MASK ((unsigned int) 0x00000002)
738 #define SCB_PIOPORCAP1_PIO2_10 ((unsigned int) 0x00000004)
739 #define SCB_PIOPORCAP1_PIO2_10_MASK ((unsigned int) 0x00000004)
740 #define SCB_PIOPORCAP1_PIO2_11 ((unsigned int) 0x00000008)
741 #define SCB_PIOPORCAP1_PIO2_11_MASK ((unsigned int) 0x00000008)
742 #define SCB_PIOPORCAP1_PIO3_0 ((unsigned int) 0x00000010)
743 #define SCB_PIOPORCAP1_PIO3_0_MASK ((unsigned int) 0x00000010)
744 #define SCB_PIOPORCAP1_PIO3_1 ((unsigned int) 0x00000020)
745 #define SCB_PIOPORCAP1_PIO3_1_MASK ((unsigned int) 0x00000020)
746 #define SCB_PIOPORCAP1_PIO3_2 ((unsigned int) 0x00000040)
747 #define SCB_PIOPORCAP1_PIO3_2_MASK ((unsigned int) 0x00000040)
748 #define SCB_PIOPORCAP1_PIO3_3 ((unsigned int) 0x00000080)
749 #define SCB_PIOPORCAP1_PIO3_3_MASK ((unsigned int) 0x00000080)
750 #define SCB_PIOPORCAP1_PIO3_4 ((unsigned int) 0x00000100)
751 #define SCB_PIOPORCAP1_PIO3_4_MASK ((unsigned int) 0x00000100)
752 #define SCB_PIOPORCAP1_PIO3_5 ((unsigned int) 0x00000200)
753 #define SCB_PIOPORCAP1_PIO3_5_MASK ((unsigned int) 0x00000200)
754
755 /* BODCTRL (Brown-out detection control register)
756 The BOD control register selects four separate threshold values for sending a BOD
757 interrupt to the NVIC. Only one level is allowed for forced reset. */
758
759 #define SCB_BODCTRL_RSTLEVEL_MASK ((unsigned int) 0x00000003)
760 #define SCB_BODCTRL_INTLEVEL_1_69V_1_84V ((unsigned int) 0x00000000)
761 #define SCB_BODCTRL_INTLEVEL_2_29V_2_44V ((unsigned int) 0x00000004)
762 #define SCB_BODCTRL_INTLEVEL_2_59V_2_74V ((unsigned int) 0x00000008)
763 #define SCB_BODCTRL_INTLEVEL_2_87V_2_98V ((unsigned int) 0x0000000C)
764 #define SCB_BODCTRL_INTLEVEL_MASK ((unsigned int) 0x0000000C)
765 #define SCB_BODCTRL_RSTENABLE_DISABLE ((unsigned int) 0x00000000)
766 #define SCB_BODCTRL_RSTENABLE_ENABLE ((unsigned int) 0x00000010)
767 #define SCB_BODCTRL_RSTENABLE_MASK ((unsigned int) 0x00000010)
768
769 /* SYSTCKCAL (System tick counter calibration register) */
770
771 #define SCB_SYSTICKCCAL_MASK ((unsigned int) 0x03FFFFFF) // Undefined as of v0.07 of the LPC1343 User Manual
772
773 /* STARTAPRP0 (Start logic edge control register 0)
774 The STARTAPRP0 register controls the start logic inputs of ports 0 (PIO0_0 to PIO0_11)
775 and 1 (PIO1_0 to PIO1_11) and the lower 8 inputs of port 2 (PIO2_0 to PIO2_7). This
776 register selects a falling or rising edge on the corresponding PIO input to produce a falling
777 or rising clock edge, respectively, for the start logic (see Section 3\969.3).
778 Every bit in the STARTAPRP0 register controls one port input and is connected to one
779 wake-up interrupt in the NVIC. Bit 0 in the STARTAPRP0 register corresponds to interrupt
780 0, bit 1 to interrupt 1, etc.. The bottom 32 interrupts are contained this register,
781 the top 8 interrupts are contained in the STARTAPRP1 register for total of 40 wake-up
782 interrupts.
783 Remark: Each interrupt connected to a start logic input must be enabled in the NVIC if the
784 corresponding PIO pin is used to wake up the chip from Deep-sleep mode. */
785
786 #define SCB_STARTAPRP0_APRPIO0_0 ((unsigned int) 0x00000001)
787 #define SCB_STARTAPRP0_APRPIO0_0_MASK ((unsigned int) 0x00000001)
788 #define SCB_STARTAPRP0_APRPIO0_1 ((unsigned int) 0x00000002)
789 #define SCB_STARTAPRP0_APRPIO0_1_MASK ((unsigned int) 0x00000002)
790 #define SCB_STARTAPRP0_APRPIO0_2 ((unsigned int) 0x00000004)
791 #define SCB_STARTAPRP0_APRPIO0_2_MASK ((unsigned int) 0x00000004)
792 #define SCB_STARTAPRP0_APRPIO0_3 ((unsigned int) 0x00000008)
793 #define SCB_STARTAPRP0_APRPIO0_3_MASK ((unsigned int) 0x00000008)
794 #define SCB_STARTAPRP0_APRPIO0_4 ((unsigned int) 0x00000010)
795 #define SCB_STARTAPRP0_APRPIO0_4_MASK ((unsigned int) 0x00000010)
796 #define SCB_STARTAPRP0_APRPIO0_5 ((unsigned int) 0x00000020)
797 #define SCB_STARTAPRP0_APRPIO0_5_MASK ((unsigned int) 0x00000020)
798 #define SCB_STARTAPRP0_APRPIO0_6 ((unsigned int) 0x00000040)
799 #define SCB_STARTAPRP0_APRPIO0_6_MASK ((unsigned int) 0x00000040)
800 #define SCB_STARTAPRP0_APRPIO0_7 ((unsigned int) 0x00000080)
801 #define SCB_STARTAPRP0_APRPIO0_7_MASK ((unsigned int) 0x00000080)
802 #define SCB_STARTAPRP0_APRPIO0_8 ((unsigned int) 0x00000100)
803 #define SCB_STARTAPRP0_APRPIO0_8_MASK ((unsigned int) 0x00000100)
804 #define SCB_STARTAPRP0_APRPIO0_9 ((unsigned int) 0x00000200)
805 #define SCB_STARTAPRP0_APRPIO0_9_MASK ((unsigned int) 0x00000200)
806 #define SCB_STARTAPRP0_APRPIO0_10 ((unsigned int) 0x00000400)
807 #define SCB_STARTAPRP0_APRPIO0_10_MASK ((unsigned int) 0x00000400)
808 #define SCB_STARTAPRP0_APRPIO0_11 ((unsigned int) 0x00000800)
809 #define SCB_STARTAPRP0_APRPIO0_11_MASK ((unsigned int) 0x00000800)
810 #define SCB_STARTAPRP0_APRPIO1_0 ((unsigned int) 0x00001000)
811 #define SCB_STARTAPRP0_APRPIO1_0_MASK ((unsigned int) 0x00001000)
812 #define SCB_STARTAPRP0_APRPIO1_1 ((unsigned int) 0x00002000)
813 #define SCB_STARTAPRP0_APRPIO1_1_MASK ((unsigned int) 0x00002000)
814 #define SCB_STARTAPRP0_APRPIO1_2 ((unsigned int) 0x00004000)
815 #define SCB_STARTAPRP0_APRPIO1_2_MASK ((unsigned int) 0x00004000)
816 #define SCB_STARTAPRP0_APRPIO1_3 ((unsigned int) 0x00008000)
817 #define SCB_STARTAPRP0_APRPIO1_3_MASK ((unsigned int) 0x00008000)
818 #define SCB_STARTAPRP0_APRPIO1_4 ((unsigned int) 0x00010000)
819 #define SCB_STARTAPRP0_APRPIO1_4_MASK ((unsigned int) 0x00010000)
820 #define SCB_STARTAPRP0_APRPIO1_5 ((unsigned int) 0x00020000)
821 #define SCB_STARTAPRP0_APRPIO1_5_MASK ((unsigned int) 0x00020000)
822 #define SCB_STARTAPRP0_APRPIO1_6 ((unsigned int) 0x00040000)
823 #define SCB_STARTAPRP0_APRPIO1_6_MASK ((unsigned int) 0x00040000)
824 #define SCB_STARTAPRP0_APRPIO1_7 ((unsigned int) 0x00080000)
825 #define SCB_STARTAPRP0_APRPIO1_7_MASK ((unsigned int) 0x00080000)
826 #define SCB_STARTAPRP0_APRPIO1_8 ((unsigned int) 0x00100000)
827 #define SCB_STARTAPRP0_APRPIO1_8_MASK ((unsigned int) 0x00100000)
828 #define SCB_STARTAPRP0_APRPIO1_9 ((unsigned int) 0x00200000)
829 #define SCB_STARTAPRP0_APRPIO1_9_MASK ((unsigned int) 0x00200000)
830 #define SCB_STARTAPRP0_APRPIO1_10 ((unsigned int) 0x00400000)
831 #define SCB_STARTAPRP0_APRPIO1_10_MASK ((unsigned int) 0x00400000)
832 #define SCB_STARTAPRP0_APRPIO1_11 ((unsigned int) 0x00800000)
833 #define SCB_STARTAPRP0_APRPIO1_11_MASK ((unsigned int) 0x00800000)
834 #define SCB_STARTAPRP0_APRPIO2_0 ((unsigned int) 0x01000000)
835 #define SCB_STARTAPRP0_APRPIO2_0_MASK ((unsigned int) 0x01000000)
836 #define SCB_STARTAPRP0_APRPIO2_1 ((unsigned int) 0x02000000)
837 #define SCB_STARTAPRP0_APRPIO2_1_MASK ((unsigned int) 0x02000000)
838 #define SCB_STARTAPRP0_APRPIO2_2 ((unsigned int) 0x04000000)
839 #define SCB_STARTAPRP0_APRPIO2_2_MASK ((unsigned int) 0x04000000)
840 #define SCB_STARTAPRP0_APRPIO2_3 ((unsigned int) 0x08000000)
841 #define SCB_STARTAPRP0_APRPIO2_3_MASK ((unsigned int) 0x08000000)
842 #define SCB_STARTAPRP0_APRPIO2_4 ((unsigned int) 0x10000000)
843 #define SCB_STARTAPRP0_APRPIO2_4_MASK ((unsigned int) 0x10000000)
844 #define SCB_STARTAPRP0_APRPIO2_5 ((unsigned int) 0x20000000)
845 #define SCB_STARTAPRP0_APRPIO2_5_MASK ((unsigned int) 0x20000000)
846 #define SCB_STARTAPRP0_APRPIO2_6 ((unsigned int) 0x40000000)
847 #define SCB_STARTAPRP0_APRPIO2_6_MASK ((unsigned int) 0x40000000)
848 #define SCB_STARTAPRP0_APRPIO2_7 ((unsigned int) 0x80000000)
849 #define SCB_STARTAPRP0_APRPIO2_7_MASK ((unsigned int) 0x80000000)
850 #define SCB_STARTAPRP0_MASK ((unsigned int) 0xFFFFFFFF)
851
852 /* STARTERP0 (Start logic signal enable register 0)
853 This STARTERP0 register enables or disables the start signal bits in the start logic. */
854
855 #define SCB_STARTERP0_ERPIO0_0 ((unsigned int) 0x00000001)
856 #define SCB_STARTERP0_ERPIO0_0_MASK ((unsigned int) 0x00000001)
857 #define SCB_STARTERP0_ERPIO0_1 ((unsigned int) 0x00000002)
858 #define SCB_STARTERP0_ERPIO0_1_MASK ((unsigned int) 0x00000002)
859 #define SCB_STARTERP0_ERPIO0_2 ((unsigned int) 0x00000004)
860 #define SCB_STARTERP0_ERPIO0_2_MASK ((unsigned int) 0x00000004)
861 #define SCB_STARTERP0_ERPIO0_3 ((unsigned int) 0x00000008)
862 #define SCB_STARTERP0_ERPIO0_3_MASK ((unsigned int) 0x00000008)
863 #define SCB_STARTERP0_ERPIO0_4 ((unsigned int) 0x00000010)
864 #define SCB_STARTERP0_ERPIO0_4_MASK ((unsigned int) 0x00000010)
865 #define SCB_STARTERP0_ERPIO0_5 ((unsigned int) 0x00000020)
866 #define SCB_STARTERP0_ERPIO0_5_MASK ((unsigned int) 0x00000020)
867 #define SCB_STARTERP0_ERPIO0_6 ((unsigned int) 0x00000040)
868 #define SCB_STARTERP0_ERPIO0_6_MASK ((unsigned int) 0x00000040)
869 #define SCB_STARTERP0_ERPIO0_7 ((unsigned int) 0x00000080)
870 #define SCB_STARTERP0_ERPIO0_7_MASK ((unsigned int) 0x00000080)
871 #define SCB_STARTERP0_ERPIO0_8 ((unsigned int) 0x00000100)
872 #define SCB_STARTERP0_ERPIO0_8_MASK ((unsigned int) 0x00000100)
873 #define SCB_STARTERP0_ERPIO0_9 ((unsigned int) 0x00000200)
874 #define SCB_STARTERP0_ERPIO0_9_MASK ((unsigned int) 0x00000200)
875 #define SCB_STARTERP0_ERPIO0_10 ((unsigned int) 0x00000400)
876 #define SCB_STARTERP0_ERPIO0_10_MASK ((unsigned int) 0x00000400)
877 #define SCB_STARTERP0_ERPIO0_11 ((unsigned int) 0x00000800)
878 #define SCB_STARTERP0_ERPIO0_11_MASK ((unsigned int) 0x00000800)
879 #define SCB_STARTERP0_ERPIO1_0 ((unsigned int) 0x00001000)
880 #define SCB_STARTERP0_ERPIO1_0_MASK ((unsigned int) 0x00001000)
881 #define SCB_STARTERP0_ERPIO1_1 ((unsigned int) 0x00002000)
882 #define SCB_STARTERP0_ERPIO1_1_MASK ((unsigned int) 0x00002000)
883 #define SCB_STARTERP0_ERPIO1_2 ((unsigned int) 0x00004000)
884 #define SCB_STARTERP0_ERPIO1_2_MASK ((unsigned int) 0x00004000)
885 #define SCB_STARTERP0_ERPIO1_3 ((unsigned int) 0x00008000)
886 #define SCB_STARTERP0_ERPIO1_3_MASK ((unsigned int) 0x00008000)
887 #define SCB_STARTERP0_ERPIO1_4 ((unsigned int) 0x00010000)
888 #define SCB_STARTERP0_ERPIO1_4_MASK ((unsigned int) 0x00010000)
889 #define SCB_STARTERP0_ERPIO1_5 ((unsigned int) 0x00020000)
890 #define SCB_STARTERP0_ERPIO1_5_MASK ((unsigned int) 0x00020000)
891 #define SCB_STARTERP0_ERPIO1_6 ((unsigned int) 0x00040000)
892 #define SCB_STARTERP0_ERPIO1_6_MASK ((unsigned int) 0x00040000)
893 #define SCB_STARTERP0_ERPIO1_7 ((unsigned int) 0x00080000)
894 #define SCB_STARTERP0_ERPIO1_7_MASK ((unsigned int) 0x00080000)
895 #define SCB_STARTERP0_ERPIO1_8 ((unsigned int) 0x00100000)
896 #define SCB_STARTERP0_ERPIO1_8_MASK ((unsigned int) 0x00100000)
897 #define SCB_STARTERP0_ERPIO1_9 ((unsigned int) 0x00200000)
898 #define SCB_STARTERP0_ERPIO1_9_MASK ((unsigned int) 0x00200000)
899 #define SCB_STARTERP0_ERPIO1_10 ((unsigned int) 0x00400000)
900 #define SCB_STARTERP0_ERPIO1_10_MASK ((unsigned int) 0x00400000)
901 #define SCB_STARTERP0_ERPIO1_11 ((unsigned int) 0x00800000)
902 #define SCB_STARTERP0_ERPIO1_11_MASK ((unsigned int) 0x00800000)
903 #define SCB_STARTERP0_ERPIO2_0 ((unsigned int) 0x01000000)
904 #define SCB_STARTERP0_ERPIO2_0_MASK ((unsigned int) 0x01000000)
905 #define SCB_STARTERP0_ERPIO2_1 ((unsigned int) 0x02000000)
906 #define SCB_STARTERP0_ERPIO2_1_MASK ((unsigned int) 0x02000000)
907 #define SCB_STARTERP0_ERPIO2_2 ((unsigned int) 0x04000000)
908 #define SCB_STARTERP0_ERPIO2_2_MASK ((unsigned int) 0x04000000)
909 #define SCB_STARTERP0_ERPIO2_3 ((unsigned int) 0x08000000)
910 #define SCB_STARTERP0_ERPIO2_3_MASK ((unsigned int) 0x08000000)
911 #define SCB_STARTERP0_ERPIO2_4 ((unsigned int) 0x10000000)
912 #define SCB_STARTERP0_ERPIO2_4_MASK ((unsigned int) 0x10000000)
913 #define SCB_STARTERP0_ERPIO2_5 ((unsigned int) 0x20000000)
914 #define SCB_STARTERP0_ERPIO2_5_MASK ((unsigned int) 0x20000000)
915 #define SCB_STARTERP0_ERPIO2_6 ((unsigned int) 0x40000000)
916 #define SCB_STARTERP0_ERPIO2_6_MASK ((unsigned int) 0x40000000)
917 #define SCB_STARTERP0_ERPIO2_7 ((unsigned int) 0x80000000)
918 #define SCB_STARTERP0_ERPIO2_7_MASK ((unsigned int) 0x80000000)
919 #define SCB_STARTERP0_MASK ((unsigned int) 0xFFFFFFFF)
920
921 /* STARTRSRP0CLR (Start logic reset register 0)
922 Writing a one to a bit in the STARTRSRP0CLR register resets the start logic state. The
923 start-up logic uses the input signals to generate a clock edge for registering a start
924 signal. This clock edge (falling or rising) sets the interrupt for waking up from
925 Deep-sleep mode. Therefore, the start-up logic states must be cleared before being used. */
926
927 #define SCB_STARTRSRP0CLR_RSRPIO0_0 ((unsigned int) 0x00000001)
928 #define SCB_STARTRSRP0CLR_RSRPIO0_0_MASK ((unsigned int) 0x00000001)
929 #define SCB_STARTRSRP0CLR_RSRPIO0_1 ((unsigned int) 0x00000002)
930 #define SCB_STARTRSRP0CLR_RSRPIO0_1_MASK ((unsigned int) 0x00000002)
931 #define SCB_STARTRSRP0CLR_RSRPIO0_2 ((unsigned int) 0x00000004)
932 #define SCB_STARTRSRP0CLR_RSRPIO0_2_MASK ((unsigned int) 0x00000004)
933 #define SCB_STARTRSRP0CLR_RSRPIO0_3 ((unsigned int) 0x00000008)
934 #define SCB_STARTRSRP0CLR_RSRPIO0_3_MASK ((unsigned int) 0x00000008)
935 #define SCB_STARTRSRP0CLR_RSRPIO0_4 ((unsigned int) 0x00000010)
936 #define SCB_STARTRSRP0CLR_RSRPIO0_4_MASK ((unsigned int) 0x00000010)
937 #define SCB_STARTRSRP0CLR_RSRPIO0_5 ((unsigned int) 0x00000020)
938 #define SCB_STARTRSRP0CLR_RSRPIO0_5_MASK ((unsigned int) 0x00000020)
939 #define SCB_STARTRSRP0CLR_RSRPIO0_6 ((unsigned int) 0x00000040)
940 #define SCB_STARTRSRP0CLR_RSRPIO0_6_MASK ((unsigned int) 0x00000040)
941 #define SCB_STARTRSRP0CLR_RSRPIO0_7 ((unsigned int) 0x00000080)
942 #define SCB_STARTRSRP0CLR_RSRPIO0_7_MASK ((unsigned int) 0x00000080)
943 #define SCB_STARTRSRP0CLR_RSRPIO0_8 ((unsigned int) 0x00000100)
944 #define SCB_STARTRSRP0CLR_RSRPIO0_8_MASK ((unsigned int) 0x00000100)
945 #define SCB_STARTRSRP0CLR_RSRPIO0_9 ((unsigned int) 0x00000200)
946 #define SCB_STARTRSRP0CLR_RSRPIO0_9_MASK ((unsigned int) 0x00000200)
947 #define SCB_STARTRSRP0CLR_RSRPIO0_10 ((unsigned int) 0x00000400)
948 #define SCB_STARTRSRP0CLR_RSRPIO0_10_MASK ((unsigned int) 0x00000400)
949 #define SCB_STARTRSRP0CLR_RSRPIO0_11 ((unsigned int) 0x00000800)
950 #define SCB_STARTRSRP0CLR_RSRPIO0_11_MASK ((unsigned int) 0x00000800)
951 #define SCB_STARTRSRP0CLR_RSRPIO1_0 ((unsigned int) 0x00001000)
952 #define SCB_STARTRSRP0CLR_RSRPIO1_0_MASK ((unsigned int) 0x00001000)
953 #define SCB_STARTRSRP0CLR_RSRPIO1_1 ((unsigned int) 0x00002000)
954 #define SCB_STARTRSRP0CLR_RSRPIO1_1_MASK ((unsigned int) 0x00002000)
955 #define SCB_STARTRSRP0CLR_RSRPIO1_2 ((unsigned int) 0x00004000)
956 #define SCB_STARTRSRP0CLR_RSRPIO1_2_MASK ((unsigned int) 0x00004000)
957 #define SCB_STARTRSRP0CLR_RSRPIO1_3 ((unsigned int) 0x00008000)
958 #define SCB_STARTRSRP0CLR_RSRPIO1_3_MASK ((unsigned int) 0x00008000)
959 #define SCB_STARTRSRP0CLR_RSRPIO1_4 ((unsigned int) 0x00010000)
960 #define SCB_STARTRSRP0CLR_RSRPIO1_4_MASK ((unsigned int) 0x00010000)
961 #define SCB_STARTRSRP0CLR_RSRPIO1_5 ((unsigned int) 0x00020000)
962 #define SCB_STARTRSRP0CLR_RSRPIO1_5_MASK ((unsigned int) 0x00020000)
963 #define SCB_STARTRSRP0CLR_RSRPIO1_6 ((unsigned int) 0x00040000)
964 #define SCB_STARTRSRP0CLR_RSRPIO1_6_MASK ((unsigned int) 0x00040000)
965 #define SCB_STARTRSRP0CLR_RSRPIO1_7 ((unsigned int) 0x00080000)
966 #define SCB_STARTRSRP0CLR_RSRPIO1_7_MASK ((unsigned int) 0x00080000)
967 #define SCB_STARTRSRP0CLR_RSRPIO1_8 ((unsigned int) 0x00100000)
968 #define SCB_STARTRSRP0CLR_RSRPIO1_8_MASK ((unsigned int) 0x00100000)
969 #define SCB_STARTRSRP0CLR_RSRPIO1_9 ((unsigned int) 0x00200000)
970 #define SCB_STARTRSRP0CLR_RSRPIO1_9_MASK ((unsigned int) 0x00200000)
971 #define SCB_STARTRSRP0CLR_RSRPIO1_10 ((unsigned int) 0x00400000)
972 #define SCB_STARTRSRP0CLR_RSRPIO1_10_MASK ((unsigned int) 0x00400000)
973 #define SCB_STARTRSRP0CLR_RSRPIO1_11 ((unsigned int) 0x00800000)
974 #define SCB_STARTRSRP0CLR_RSRPIO1_11_MASK ((unsigned int) 0x00800000)
975 #define SCB_STARTRSRP0CLR_RSRPIO2_0 ((unsigned int) 0x01000000)
976 #define SCB_STARTRSRP0CLR_RSRPIO2_0_MASK ((unsigned int) 0x01000000)
977 #define SCB_STARTRSRP0CLR_RSRPIO2_1 ((unsigned int) 0x02000000)
978 #define SCB_STARTRSRP0CLR_RSRPIO2_1_MASK ((unsigned int) 0x02000000)
979 #define SCB_STARTRSRP0CLR_RSRPIO2_2 ((unsigned int) 0x04000000)
980 #define SCB_STARTRSRP0CLR_RSRPIO2_2_MASK ((unsigned int) 0x04000000)
981 #define SCB_STARTRSRP0CLR_RSRPIO2_3 ((unsigned int) 0x08000000)
982 #define SCB_STARTRSRP0CLR_RSRPIO2_3_MASK ((unsigned int) 0x08000000)
983 #define SCB_STARTRSRP0CLR_RSRPIO2_4 ((unsigned int) 0x10000000)
984 #define SCB_STARTRSRP0CLR_RSRPIO2_4_MASK ((unsigned int) 0x10000000)
985 #define SCB_STARTRSRP0CLR_RSRPIO2_5 ((unsigned int) 0x20000000)
986 #define SCB_STARTRSRP0CLR_RSRPIO2_5_MASK ((unsigned int) 0x20000000)
987 #define SCB_STARTRSRP0CLR_RSRPIO2_6 ((unsigned int) 0x40000000)
988 #define SCB_STARTRSRP0CLR_RSRPIO2_6_MASK ((unsigned int) 0x40000000)
989 #define SCB_STARTRSRP0CLR_RSRPIO2_7 ((unsigned int) 0x80000000)
990 #define SCB_STARTRSRP0CLR_RSRPIO2_7_MASK ((unsigned int) 0x80000000)
991 #define SCB_STARTRSRP0CLR_MASK ((unsigned int) 0xFFFFFFFF)
992
993 /* (Start logic status register 0)
994 This register reflects the status of the enabled start signal bits. Each bit
995 (if enabled) reflects the state of the start logic, i.e. whether or not a
996 wake-up signal has been received for a given pin. */
997
998 #define SCB_STARTSRP0_SRPIO0_0 ((unsigned int) 0x00000001)
999 #define SCB_STARTSRP0_SRPIO0_0_MASK ((unsigned int) 0x00000001)
1000 #define SCB_STARTSRP0_SRPIO0_1 ((unsigned int) 0x00000002)
1001 #define SCB_STARTSRP0_SRPIO0_1_MASK ((unsigned int) 0x00000002)
1002 #define SCB_STARTSRP0_SRPIO0_2 ((unsigned int) 0x00000004)
1003 #define SCB_STARTSRP0_SRPIO0_2_MASK ((unsigned int) 0x00000004)
1004 #define SCB_STARTSRP0_SRPIO0_3 ((unsigned int) 0x00000008)
1005 #define SCB_STARTSRP0_SRPIO0_3_MASK ((unsigned int) 0x00000008)
1006 #define SCB_STARTSRP0_SRPIO0_4 ((unsigned int) 0x00000010)
1007 #define SCB_STARTSRP0_SRPIO0_4_MASK ((unsigned int) 0x00000010)
1008 #define SCB_STARTSRP0_SRPIO0_5 ((unsigned int) 0x00000020)
1009 #define SCB_STARTSRP0_SRPIO0_5_MASK ((unsigned int) 0x00000020)
1010 #define SCB_STARTSRP0_SRPIO0_6 ((unsigned int) 0x00000040)
1011 #define SCB_STARTSRP0_SRPIO0_6_MASK ((unsigned int) 0x00000040)
1012 #define SCB_STARTSRP0_SRPIO0_7 ((unsigned int) 0x00000080)
1013 #define SCB_STARTSRP0_SRPIO0_7_MASK ((unsigned int) 0x00000080)
1014 #define SCB_STARTSRP0_SRPIO0_8 ((unsigned int) 0x00000100)
1015 #define SCB_STARTSRP0_SRPIO0_8_MASK ((unsigned int) 0x00000100)
1016 #define SCB_STARTSRP0_SRPIO0_9 ((unsigned int) 0x00000200)
1017 #define SCB_STARTSRP0_SRPIO0_9_MASK ((unsigned int) 0x00000200)
1018 #define SCB_STARTSRP0_SRPIO0_10 ((unsigned int) 0x00000400)
1019 #define SCB_STARTSRP0_SRPIO0_10_MASK ((unsigned int) 0x00000400)
1020 #define SCB_STARTSRP0_SRPIO0_11 ((unsigned int) 0x00000800)
1021 #define SCB_STARTSRP0_SRPIO0_11_MASK ((unsigned int) 0x00000800)
1022 #define SCB_STARTSRP0_SRPIO1_0 ((unsigned int) 0x00001000)
1023 #define SCB_STARTSRP0_SRPIO1_0_MASK ((unsigned int) 0x00001000)
1024 #define SCB_STARTSRP0_SRPIO1_1 ((unsigned int) 0x00002000)
1025 #define SCB_STARTSRP0_SRPIO1_1_MASK ((unsigned int) 0x00002000)
1026 #define SCB_STARTSRP0_SRPIO1_2 ((unsigned int) 0x00004000)
1027 #define SCB_STARTSRP0_SRPIO1_2_MASK ((unsigned int) 0x00004000)
1028 #define SCB_STARTSRP0_SRPIO1_3 ((unsigned int) 0x00008000)
1029 #define SCB_STARTSRP0_SRPIO1_3_MASK ((unsigned int) 0x00008000)
1030 #define SCB_STARTSRP0_SRPIO1_4 ((unsigned int) 0x00010000)
1031 #define SCB_STARTSRP0_SRPIO1_4_MASK ((unsigned int) 0x00010000)
1032 #define SCB_STARTSRP0_SRPIO1_5 ((unsigned int) 0x00020000)
1033 #define SCB_STARTSRP0_SRPIO1_5_MASK ((unsigned int) 0x00020000)
1034 #define SCB_STARTSRP0_SRPIO1_6 ((unsigned int) 0x00040000)
1035 #define SCB_STARTSRP0_SRPIO1_6_MASK ((unsigned int) 0x00040000)
1036 #define SCB_STARTSRP0_SRPIO1_7 ((unsigned int) 0x00080000)
1037 #define SCB_STARTSRP0_SRPIO1_7_MASK ((unsigned int) 0x00080000)
1038 #define SCB_STARTSRP0_SRPIO1_8 ((unsigned int) 0x00100000)
1039 #define SCB_STARTSRP0_SRPIO1_8_MASK ((unsigned int) 0x00100000)
1040 #define SCB_STARTSRP0_SRPIO1_9 ((unsigned int) 0x00200000)
1041 #define SCB_STARTSRP0_SRPIO1_9_MASK ((unsigned int) 0x00200000)
1042 #define SCB_STARTSRP0_SRPIO1_10 ((unsigned int) 0x00400000)
1043 #define SCB_STARTSRP0_SRPIO1_10_MASK ((unsigned int) 0x00400000)
1044 #define SCB_STARTSRP0_SRPIO1_11 ((unsigned int) 0x00800000)
1045 #define SCB_STARTSRP0_SRPIO1_11_MASK ((unsigned int) 0x00800000)
1046 #define SCB_STARTSRP0_SRPIO2_0 ((unsigned int) 0x01000000)
1047 #define SCB_STARTSRP0_SRPIO2_0_MASK ((unsigned int) 0x01000000)
1048 #define SCB_STARTSRP0_SRPIO2_1 ((unsigned int) 0x02000000)
1049 #define SCB_STARTSRP0_SRPIO2_1_MASK ((unsigned int) 0x02000000)
1050 #define SCB_STARTSRP0_SRPIO2_2 ((unsigned int) 0x04000000)
1051 #define SCB_STARTSRP0_SRPIO2_2_MASK ((unsigned int) 0x04000000)
1052 #define SCB_STARTSRP0_SRPIO2_3 ((unsigned int) 0x08000000)
1053 #define SCB_STARTSRP0_SRPIO2_3_MASK ((unsigned int) 0x08000000)
1054 #define SCB_STARTSRP0_SRPIO2_4 ((unsigned int) 0x10000000)
1055 #define SCB_STARTSRP0_SRPIO2_4_MASK ((unsigned int) 0x10000000)
1056 #define SCB_STARTSRP0_SRPIO2_5 ((unsigned int) 0x20000000)
1057 #define SCB_STARTSRP0_SRPIO2_5_MASK ((unsigned int) 0x20000000)
1058 #define SCB_STARTSRP0_SRPIO2_6 ((unsigned int) 0x40000000)
1059 #define SCB_STARTSRP0_SRPIO2_6_MASK ((unsigned int) 0x40000000)
1060 #define SCB_STARTSRP0_SRPIO2_7 ((unsigned int) 0x80000000)
1061 #define SCB_STARTSRP0_SRPIO2_7_MASK ((unsigned int) 0x80000000)
1062 #define SCB_STARTSRP0_MASK ((unsigned int) 0xFFFFFFFF)
1063
1064
1065 /* STARTAPRP1 (Start logic edge control register 1)
1066 The STARTAPRP1 register controls the start logic inputs of ports 2 (PIO2_8 to PIO2_11)
1067 and 3 (PIO3_0 to PIO3_3). This register selects a falling or rising edge on the
1068 corresponding PIO input to produce a falling or rising clock edge, respectively, for the
1069 start-up logic.
1070 Every bit in the STARTAPRP1 register controls one port input and is connected to one
1071 wake-up interrupt in the NVIC. Bit 0 in the STARTAPRP1 register corresponds to interrupt
1072 32, bit 1 to interrupt 33, up to bit 7 corresponding to interrupt 39.
1073 Remark: Each interrupt connected to a start logic input must be enabled in the NVIC if the
1074 corresponding PIO pin is used to wake up the chip from Deep-sleep mode.*/
1075
1076 #define SCB_STARTAPRP1_APRPIO2_8 ((unsigned int) 0x00000001)
1077 #define SCB_STARTAPRP1_APRPIO2_8_MASK ((unsigned int) 0x00000001)
1078 #define SCB_STARTAPRP1_APRPIO2_8 ((unsigned int) 0x00000001)
1079 #define SCB_STARTAPRP1_APRPIO2_9_MASK ((unsigned int) 0x00000002)
1080 #define SCB_STARTAPRP1_APRPIO2_10 ((unsigned int) 0x00000004)
1081 #define SCB_STARTAPRP1_APRPIO2_10_MASK ((unsigned int) 0x00000004)
1082 #define SCB_STARTAPRP1_APRPIO2_11 ((unsigned int) 0x00000008)
1083 #define SCB_STARTAPRP1_APRPIO2_11_MASK ((unsigned int) 0x00000008)
1084 #define SCB_STARTAPRP1_APRPIO3_0 ((unsigned int) 0x00000010)
1085 #define SCB_STARTAPRP1_APRPIO3_0_MASK ((unsigned int) 0x00000010)
1086 #define SCB_STARTAPRP1_APRPIO3_1 ((unsigned int) 0x00000020)
1087 #define SCB_STARTAPRP1_APRPIO3_1_MASK ((unsigned int) 0x00000020)
1088 #define SCB_STARTAPRP1_APRPIO3_2 ((unsigned int) 0x00000040)
1089 #define SCB_STARTAPRP1_APRPIO3_2_MASK ((unsigned int) 0x00000040)
1090 #define SCB_STARTAPRP1_APRPIO3_3 ((unsigned int) 0x00000080)
1091 #define SCB_STARTAPRP1_APRPIO3_3_MASK ((unsigned int) 0x00000080)
1092 #define SCB_STARTAPRP1_MASK ((unsigned int) 0x000000FF)
1093
1094 /* STARTERP1 (Start logic signal enable register 1)
1095 This STARTERP1 register enables or disables the start signal bits in the start logic. */
1096
1097 #define SCB_STARTERP1_ERPIO2_8 ((unsigned int) 0x00000001)
1098 #define SCB_STARTERP1_ERPIO2_8_MASK ((unsigned int) 0x00000001)
1099 #define SCB_STARTERP1_ERPIO2_8 ((unsigned int) 0x00000001)
1100 #define SCB_STARTERP1_ERPIO2_9_MASK ((unsigned int) 0x00000002)
1101 #define SCB_STARTERP1_ERPIO2_10 ((unsigned int) 0x00000004)
1102 #define SCB_STARTERP1_ERPIO2_10_MASK ((unsigned int) 0x00000004)
1103 #define SCB_STARTERP1_ERPIO2_11 ((unsigned int) 0x00000008)
1104 #define SCB_STARTERP1_ERPIO2_11_MASK ((unsigned int) 0x00000008)
1105 #define SCB_STARTERP1_ERPIO3_0 ((unsigned int) 0x00000010)
1106 #define SCB_STARTERP1_ERPIO3_0_MASK ((unsigned int) 0x00000010)
1107 #define SCB_STARTERP1_ERPIO3_1 ((unsigned int) 0x00000020)
1108 #define SCB_STARTERP1_ERPIO3_1_MASK ((unsigned int) 0x00000020)
1109 #define SCB_STARTERP1_ERPIO3_2 ((unsigned int) 0x00000040)
1110 #define SCB_STARTERP1_ERPIO3_2_MASK ((unsigned int) 0x00000040)
1111 #define SCB_STARTERP1_ERPIO3_3 ((unsigned int) 0x00000080)
1112 #define SCB_STARTERP1_ERPIO3_3_MASK ((unsigned int) 0x00000080)
1113 #define SCB_STARTERP1_MASK ((unsigned int) 0x000000FF)
1114
1115 /* (Start logic reset register 1)
1116 Writing a one to a bit in the STARTRSRP1CLR register resets the start logic state. The
1117 start-up logic uses the input signals to generate a clock edge for registering a start
1118 signal. This clock edge (falling or rising) sets the interrupt for waking up from
1119 Deep-sleep mode. Therefore, the start-up logic states must be cleared before being used. */
1120
1121 #define SCB_STARTRSRP1CLR_RSRPIO2_8 ((unsigned int) 0x00000001)
1122 #define SCB_STARTRSRP1CLR_RSRPIO2_8_MASK ((unsigned int) 0x00000001)
1123 #define SCB_STARTRSRP1CLR_RSRPIO2_8 ((unsigned int) 0x00000001)
1124 #define SCB_STARTRSRP1CLR_RSRPIO2_9_MASK ((unsigned int) 0x00000002)
1125 #define SCB_STARTRSRP1CLR_RSRPIO2_10 ((unsigned int) 0x00000004)
1126 #define SCB_STARTRSRP1CLR_RSRPIO2_10_MASK ((unsigned int) 0x00000004)
1127 #define SCB_STARTRSRP1CLR_RSRPIO2_11 ((unsigned int) 0x00000008)
1128 #define SCB_STARTRSRP1CLR_RSRPIO2_11_MASK ((unsigned int) 0x00000008)
1129 #define SCB_STARTRSRP1CLR_RSRPIO3_0 ((unsigned int) 0x00000010)
1130 #define SCB_STARTRSRP1CLR_RSRPIO3_0_MASK ((unsigned int) 0x00000010)
1131 #define SCB_STARTRSRP1CLR_RSRPIO3_1 ((unsigned int) 0x00000020)
1132 #define SCB_STARTRSRP1CLR_RSRPIO3_1_MASK ((unsigned int) 0x00000020)
1133 #define SCB_STARTRSRP1CLR_RSRPIO3_2 ((unsigned int) 0x00000040)
1134 #define SCB_STARTRSRP1CLR_RSRPIO3_2_MASK ((unsigned int) 0x00000040)
1135 #define SCB_STARTRSRP1CLR_RSRPIO3_3 ((unsigned int) 0x00000080)
1136 #define SCB_STARTRSRP1CLR_RSRPIO3_3_MASK ((unsigned int) 0x00000080)
1137 #define SCB_STARTRSRP1CLR_MASK ((unsigned int) 0x000000FF)
1138
1139 /* STARTSRP1 (Start logic status register 1)
1140 This register reflects the status of the enabled start signals. */
1141
1142 #define SCB_STARTSRP1_SRPIO2_8 ((unsigned int) 0x00000001)
1143 #define SCB_STARTSRP1_SRPIO2_8_MASK ((unsigned int) 0x00000001)
1144 #define SCB_STARTSRP1_SRPIO2_8 ((unsigned int) 0x00000001)
1145 #define SCB_STARTSRP1_SRPIO2_9_MASK ((unsigned int) 0x00000002)
1146 #define SCB_STARTSRP1_SRPIO2_10 ((unsigned int) 0x00000004)
1147 #define SCB_STARTSRP1_SRPIO2_10_MASK ((unsigned int) 0x00000004)
1148 #define SCB_STARTSRP1_SRPIO2_11 ((unsigned int) 0x00000008)
1149 #define SCB_STARTSRP1_SRPIO2_11_MASK ((unsigned int) 0x00000008)
1150 #define SCB_STARTSRP1_SRPIO3_0 ((unsigned int) 0x00000010)
1151 #define SCB_STARTSRP1_SRPIO3_0_MASK ((unsigned int) 0x00000010)
1152 #define SCB_STARTSRP1_SRPIO3_1 ((unsigned int) 0x00000020)
1153 #define SCB_STARTSRP1_SRPIO3_1_MASK ((unsigned int) 0x00000020)
1154 #define SCB_STARTSRP1_SRPIO3_2 ((unsigned int) 0x00000040)
1155 #define SCB_STARTSRP1_SRPIO3_2_MASK ((unsigned int) 0x00000040)
1156 #define SCB_STARTSRP1_SRPIO3_3 ((unsigned int) 0x00000080)
1157 #define SCB_STARTSRP1_SRPIO3_3_MASK ((unsigned int) 0x00000080)
1158 #define SCB_STARTSRP1_MASK ((unsigned int) 0x000000FF)
1159
1160 /* PDSLEEPCFG (Deep-sleep mode configuration register)
1161 The bits in this register can be programmed to indicate the state the chip must enter when
1162 the Deep-sleep mode is asserted by the ARM. The value of the PDSLEEPCFG register
1163 will be automatically loaded into the PDRUNCFG register when the Sleep mode is
1164 entered. */
1165
1166 #define SCB_PDSLEEPCFG_IRCOUT_PD ((unsigned int) 0x00000001)
1167 #define SCB_PDSLEEPCFG_IRCOUT_PD_MASK ((unsigned int) 0x00000001)
1168 #define SCB_PDSLEEPCFG_IRC_PD ((unsigned int) 0x00000002)
1169 #define SCB_PDSLEEPCFG_IRC_PD_MASK ((unsigned int) 0x00000002)
1170 #define SCB_PDSLEEPCFG_FLASH_PD ((unsigned int) 0x00000004)
1171 #define SCB_PDSLEEPCFG_FLASH_PD_MASK ((unsigned int) 0x00000004)
1172 #define SCB_PDSLEEPCFG_BOD_PD ((unsigned int) 0x00000008)
1173 #define SCB_PDSLEEPCFG_BOD_PD_MASK ((unsigned int) 0x00000008)
1174 #define SCB_PDSLEEPCFG_ADC_PD ((unsigned int) 0x00000010)
1175 #define SCB_PDSLEEPCFG_ADC_PD_MASK ((unsigned int) 0x00000010)
1176 #define SCB_PDSLEEPCFG_SYSOSC_PD ((unsigned int) 0x00000020)
1177 #define SCB_PDSLEEPCFG_SYSOSC_PD_MASK ((unsigned int) 0x00000020)
1178 #define SCB_PDSLEEPCFG_WDTOSC_PD ((unsigned int) 0x00000040)
1179 #define SCB_PDSLEEPCFG_WDTOSC_PD_MASK ((unsigned int) 0x00000040)
1180 #define SCB_PDSLEEPCFG_SYSPLL_PD ((unsigned int) 0x00000080)
1181 #define SCB_PDSLEEPCFG_SYSPLL_PD_MASK ((unsigned int) 0x00000080)
1182 #define SCB_PDSLEEPCFG_USBPLL_PD ((unsigned int) 0x00000100)
1183 #define SCB_PDSLEEPCFG_USBPLL_PD_MASK ((unsigned int) 0x00000100)
1184 #define SCB_PDSLEEPCFG_USBPAD_PD ((unsigned int) 0x00000400)
1185 #define SCB_PDSLEEPCFG_USBPAD_PD_MASK ((unsigned int) 0x00000400)
1186
1187 /* PDAWAKECFG (Wake-up configuration register)
1188 The bits in this register can be programmed to indicate the state the chip must enter when
1189 it is waking up from Deep-sleep mode. */
1190
1191 #define SCB_PDAWAKECFG_IRCOUT_PD ((unsigned int) 0x00000001)
1192 #define SCB_PDAWAKECFG_IRCOUT_PD_MASK ((unsigned int) 0x00000001)
1193 #define SCB_PDAWAKECFG_IRC_PD ((unsigned int) 0x00000002)
1194 #define SCB_PDAWAKECFG_IRC_PD_MASK ((unsigned int) 0x00000002)
1195 #define SCB_PDAWAKECFG_FLASH_PD ((unsigned int) 0x00000004)
1196 #define SCB_PDAWAKECFG_FLASH_PD_MASK ((unsigned int) 0x00000004)
1197 #define SCB_PDAWAKECFG_BOD_PD ((unsigned int) 0x00000008)
1198 #define SCB_PDAWAKECFG_BOD_PD_MASK ((unsigned int) 0x00000008)
1199 #define SCB_PDAWAKECFG_ADC_PD ((unsigned int) 0x00000010)
1200 #define SCB_PDAWAKECFG_ADC_PD_MASK ((unsigned int) 0x00000010)
1201 #define SCB_PDAWAKECFG_SYSOSC_PD ((unsigned int) 0x00000020)
1202 #define SCB_PDAWAKECFG_SYSOSC_PD_MASK ((unsigned int) 0x00000020)
1203 #define SCB_PDAWAKECFG_WDTOSC_PD ((unsigned int) 0x00000040)
1204 #define SCB_PDAWAKECFG_WDTOSC_PD_MASK ((unsigned int) 0x00000040)
1205 #define SCB_PDAWAKECFG_SYSPLL_PD ((unsigned int) 0x00000080)
1206 #define SCB_PDAWAKECFG_SYSPLL_PD_MASK ((unsigned int) 0x00000080)
1207 #define SCB_PDAWAKECFG_USBPLL_PD ((unsigned int) 0x00000100)
1208 #define SCB_PDAWAKECFG_USBPLL_PD_MASK ((unsigned int) 0x00000100)
1209 #define SCB_PDAWAKECFG_USBPAD_PD ((unsigned int) 0x00000400)
1210 #define SCB_PDAWAKECFG_USBPAD_PD_MASK ((unsigned int) 0x00000400)
1211
1212 /* PDRUNCFG (Power-down configuration register)
1213 The bits in the PDRUNCFG register control the power to the various analog blocks. This
1214 register can be written to at any time while the chip is running, and a write will take effect
1215 immediately with the exception of the power-down signal to the IRC. Setting a 1 powers-down
1216 a peripheral and 0 enables it. */
1217
1218 #define SCB_PDRUNCFG_IRCOUT ((unsigned int) 0x00000001) // IRC oscillator output power-down
1219 #define SCB_PDRUNCFG_IRCOUT_MASK ((unsigned int) 0x00000001)
1220 #define SCB_PDRUNCFG_IRC ((unsigned int) 0x00000002) // IRC oscillator power-down
1221 #define SCB_PDRUNCFG_IRC_MASK ((unsigned int) 0x00000002)
1222 #define SCB_PDRUNCFG_FLASH ((unsigned int) 0x00000004) // Flash power-down
1223 #define SCB_PDRUNCFG_FLASH_MASK ((unsigned int) 0x00000004)
1224 #define SCB_PDRUNCFG_BOD ((unsigned int) 0x00000008) // Brown-out detector power-down
1225 #define SCB_PDRUNCFG_BOD_MASK ((unsigned int) 0x00000008)
1226 #define SCB_PDRUNCFG_ADC ((unsigned int) 0x00000010) // ADC power-down
1227 #define SCB_PDRUNCFG_ADC_MASK ((unsigned int) 0x00000010)
1228 #define SCB_PDRUNCFG_SYSOSC ((unsigned int) 0x00000020) // System oscillator power-down
1229 #define SCB_PDRUNCFG_SYSOSC_MASK ((unsigned int) 0x00000020)
1230 #define SCB_PDRUNCFG_WDTOSC ((unsigned int) 0x00000040) // Watchdog oscillator power-down
1231 #define SCB_PDRUNCFG_WDTOSC_MASK ((unsigned int) 0x00000040)
1232 #define SCB_PDRUNCFG_SYSPLL ((unsigned int) 0x00000080) // System PLL power-down
1233 #define SCB_PDRUNCFG_SYSPLL_MASK ((unsigned int) 0x00000080)
1234 #define SCB_PDRUNCFG_USBPLL ((unsigned int) 0x00000100) // USB PLL power-down
1235 #define SCB_PDRUNCFG_USBPLL_MASK ((unsigned int) 0x00000100)
1236 #define SCB_PDRUNCFG_USBPAD ((unsigned int) 0x00000400) // USB PHY power-down
1237 #define SCB_PDRUNCFG_USBPAD_MASK ((unsigned int) 0x00000400)
1238
1239 /* DEVICE_ID (Device ID Register)
1240 This device ID register is a read-only register and contains the device ID for each
1241 LPC13xx part. This register is also read by the ISP/IAP commands. */
1242
1243 #define SCB_DEVICEID_LPC1311FHN33 ((unsigned int) 0x2C42502B)
1244 #define SCB_DEVICEID_LPC1313FHN33 ((unsigned int) 0x2C40102B)
1245 #define SCB_DEVICEID_LPC1313FBD48 ((unsigned int) 0x2C40102B)
1246 #define SCB_DEVICEID_LPC1342FHN33 ((unsigned int) 0x3D01402B)
1247 #define SCB_DEVICEID_LPC1343FHN33 ((unsigned int) 0x3D00002B)
1248 #define SCB_DEVICEID_LPC1343FBD48 ((unsigned int) 0x3D00002B)
1249
1250 /*##############################################################################
1251 ## Data Watchpoint and Trace Unit (DWT)
1252 ##############################################################################*/
1253 // For more information, see Cortex-M3 Technical Reference Manual 8.3
1254 // This block is optional and not all comparators or functionality may
1255 // be present on all chips, though basic DWT functionality is present
1256 // on the LPC1343 since CYCNT works
1257
1258 #define DWT_CTRL (*(pREG32 (0xE0001000))) // Control register
1259 #define DWT_CYCCNT (*(pREG32 (0xE0001004))) // Cycle counter (useful for rough performance testing)
1260 #define DWT_CPICNT (*(pREG32 (0xE0001008))) // CPI Count Register
1261 #define DWT_EXCCNT (*(pREG32 (0xE000100C))) // Exception overhead count register
1262 #define DWT_SLEEPCNT (*(pREG32 (0xE0001010))) // Sleep count register
1263 #define DWT_LSUCNT (*(pREG32 (0xE0001014))) // LSU count register
1264 #define DWT_FOLDCNT (*(pREG32 (0xE0001018))) // Folder-instruction count register
1265 #define DWT_PCSR (*(pREG32 (0xE000101C))) // Program counter sample register
1266 #define DWT_COMP0 (*(pREG32 (0xE0001020))) // Comparator register 0
1267 #define DWT_MASK0 (*(pREG32 (0xE0001024))) // Mask register 0
1268 #define DWT_FUNCTION0 (*(pREG32 (0xE0001028))) // Function register 0
1269 #define DWT_COMP1 (*(pREG32 (0xE0001030))) // Comparator register 1
1270 #define DWT_MASK1 (*(pREG32 (0xE0001034))) // Mask register 1
1271 #define DWT_FUNCTION1 (*(pREG32 (0xE0001038))) // Function register 1
1272 #define DWT_COMP2 (*(pREG32 (0xE0001040))) // Comparator register 2
1273 #define DWT_MASK2 (*(pREG32 (0xE0001044))) // Mask register 2
1274 #define DWT_FUNCTION2 (*(pREG32 (0xE0001048))) // Function register 2
1275 #define DWT_COMP3 (*(pREG32 (0xE0001050))) // Comparator register 3
1276 #define DWT_MASK3 (*(pREG32 (0xE0001054))) // Mask register 3
1277 #define DWT_FUNCTION3 (*(pREG32 (0xE0001058))) // Function register 3
1278
1279 /*##############################################################################
1280 ## Power Management Unit (PMU)
1281 ##############################################################################*/
1282
1283 #define PMU_BASE_ADDRESS (0x40038000)
1284
1285 #define PMU_PMUCTRL (*(pREG32 (0x40038000))) // Power control register
1286 #define PMU_GPREG0 (*(pREG32 (0x40038004))) // General purpose register 0
1287 #define PMU_GPREG1 (*(pREG32 (0x40038008))) // General purpose register 1
1288 #define PMU_GPREG2 (*(pREG32 (0x4003800C))) // General purpose register 2
1289 #define PMU_GPREG3 (*(pREG32 (0x40038010))) // General purpose register 3
1290 #define PMU_GPREG4 (*(pREG32 (0x40038014))) // General purpose register 4
1291
1292 #define PMU_PMUCTRL_DPDEN_MASK ((unsigned int) 0x00000002) // Deep power-down enable
1293 #define PMU_PMUCTRL_DPDEN_DEEPPOWERDOWN ((unsigned int) 0x00000002) // WFI will enter deep power-down mode
1294 #define PMU_PMUCTRL_DPDEN_SLEEP ((unsigned int) 0x00000000) // WFI will enter sleep mode
1295 #define PMU_PMUCTRL_DPDFLAG_MASK ((unsigned int) 0x00000800) // Deep power-down flag
1296 #define PMU_PMUCTRL_DPDFLAG ((unsigned int) 0x00000800)
1297
1298 /* GPREG0..3 (General purpose registers 0 to 3)
1299 The general purpose registers retain data through the Deep power-down mode when
1300 power is still applied to the VDD(3V3) pin but the chip has entered Deep power-down mode.
1301 Only a \93cold\94 boot when all power has been completely removed from the chip will reset
1302 the general purpose registers. */
1303
1304 #define PMU_GPREG0_GPDATA_MASK ((unsigned int) 0xFFFFFFFF)
1305 #define PMU_GPREG1_GPDATA_MASK ((unsigned int) 0xFFFFFFFF)
1306 #define PMU_GPREG2_GPDATA_MASK ((unsigned int) 0xFFFFFFFF)
1307 #define PMU_GPREG3_GPDATA_MASK ((unsigned int) 0xFFFFFFFF)
1308
1309 /* GPREG4 (General purpose register 4)
1310 The general purpose register 4 retains data through the Deep power-down mode when
1311 power is still applied to the VDD(3V3) pin but the chip has entered Deep power-down mode.
1312 Only a \93cold\94 boot, when all power has been completely removed from the chip, will reset
1313 the general purpose registers.
1314
1315 Remark: If the external voltage applied on pin VDD(3V3) drops below <tbd> V, the
1316 hysteresis of the WAKEUP input pin has to be disabled in order for the chip to wake up
1317 from Deep power-down mode. */
1318
1319 #define PMU_GPREG4_GPDATA_MASK ((unsigned int) 0xFFFFF800)
1320 #define PMU_GPREG4_WAKEUPHYS_MASK ((unsigned int) 0x00000400)
1321 #define PMU_GPREG4_WAKEUPHYS_HYSTERESISENABLED ((unsigned int) 0x00000400)
1322 #define PMU_GPREG4_WAKEUPHYS_HYSTERESISDISABLED ((unsigned int) 0x00000000)
1323 #define PMU_GPREG4_GPDATA_MASK ((unsigned int) 0xFFFFF800)
1324
1325 /*##############################################################################
1326 ## I/O Control (IOCON)
1327 ##############################################################################*/
1328
1329 #define IOCON_BASE_ADDRESS (0x40044000)
1330
1331 /* Values that should be common to all pins, though they are also defined
1332 on the individual pin level in case they change with a pin on any future
1333 device */
1334
1335 #define IOCON_COMMON_FUNC_MASK ((unsigned int) 0x00000007)
1336 #define IOCON_COMMON_MODE_MASK ((unsigned int) 0x00000018)
1337 #define IOCON_COMMON_MODE_INACTIVE ((unsigned int) 0x00000000)
1338 #define IOCON_COMMON_MODE_PULLDOWN ((unsigned int) 0x00000008)
1339 #define IOCON_COMMON_MODE_PULLUP ((unsigned int) 0x00000010)
1340 #define IOCON_COMMON_MODE_REPEATER ((unsigned int) 0x00000018)
1341 #define IOCON_COMMON_HYS_MASK ((unsigned int) 0x00000020)
1342 #define IOCON_COMMON_HYS_DISABLE ((unsigned int) 0x00000000)
1343 #define IOCON_COMMON_HYS_ENABLE ((unsigned int) 0x00000020)
1344
1345 #define IOCON_PIO2_6 (*(pREG32 (0x40044000)))
1346 #define IOCON_PIO2_6_FUNC_MASK ((unsigned int) 0x00000007)
1347 #define IOCON_PIO2_6_FUNC_GPIO ((unsigned int) 0x00000000)
1348 #define IOCON_PIO2_6_MODE_MASK ((unsigned int) 0x00000018)
1349 #define IOCON_PIO2_6_MODE_INACTIVE ((unsigned int) 0x00000000)
1350 #define IOCON_PIO2_6_MODE_PULLDOWN ((unsigned int) 0x00000008)
1351 #define IOCON_PIO2_6_MODE_PULLUP ((unsigned int) 0x00000010)
1352 #define IOCON_PIO2_6_MODE_REPEATER ((unsigned int) 0x00000018)
1353 #define IOCON_PIO2_6_HYS_MASK ((unsigned int) 0x00000020)
1354 #define IOCON_PIO2_6_HYS_DISABLE ((unsigned int) 0x00000000)
1355 #define IOCON_PIO2_6_HYS_ENABLE ((unsigned int) 0x00000020)
1356
1357 #define IOCON_PIO2_0 (*(pREG32 (0x40044008)))
1358 #define IOCON_PIO2_0_FUNC_MASK ((unsigned int) 0x00000007)
1359 #define IOCON_PIO2_0_FUNC_GPIO ((unsigned int) 0x00000000)
1360 #define IOCON_PIO2_0_FUNC_DTR ((unsigned int) 0x00000001)
1361 #define IOCON_PIO2_0_MODE_MASK ((unsigned int) 0x00000018)
1362 #define IOCON_PIO2_0_MODE_INACTIVE ((unsigned int) 0x00000000)
1363 #define IOCON_PIO2_0_MODE_PULLDOWN ((unsigned int) 0x00000008)
1364 #define IOCON_PIO2_0_MODE_PULLUP ((unsigned int) 0x00000010)
1365 #define IOCON_PIO2_0_MODE_REPEATER ((unsigned int) 0x00000018)
1366 #define IOCON_PIO2_0_HYS_MASK ((unsigned int) 0x00000020)
1367 #define IOCON_PIO2_0_HYS_DISABLE ((unsigned int) 0x00000000)
1368 #define IOCON_PIO2_0_HYS_ENABLE ((unsigned int) 0x00000020)
1369
1370 #define IOCON_nRESET_PIO0_0 (*(pREG32 (0x4004400C)))
1371 #define IOCON_nRESET_PIO0_0_FUNC_MASK ((unsigned int) 0x00000007)
1372 #define IOCON_nRESET_PIO0_0_FUNC_RESET ((unsigned int) 0x00000000)
1373 #define IOCON_nRESET_PIO0_0_FUNC_GPIO ((unsigned int) 0x00000001)
1374 #define IOCON_nRESET_PIO0_0_MODE_MASK ((unsigned int) 0x00000018)
1375 #define IOCON_nRESET_PIO0_0_MODE_INACTIVE ((unsigned int) 0x00000000)
1376 #define IOCON_nRESET_PIO0_0_MODE_PULLDOWN ((unsigned int) 0x00000008)
1377 #define IOCON_nRESET_PIO0_0_MODE_PULLUP ((unsigned int) 0x00000010)
1378 #define IOCON_nRESET_PIO0_0_MODE_REPEATER ((unsigned int) 0x00000018)
1379 #define IOCON_nRESET_PIO0_0_HYS_MASK ((unsigned int) 0x00000020)
1380 #define IOCON_nRESET_PIO0_0_HYS_DISABLE ((unsigned int) 0x00000000)
1381 #define IOCON_nRESET_PIO0_0_HYS_ENABLE ((unsigned int) 0x00000020)
1382
1383 #define IOCON_PIO0_1 (*(pREG32 (0x40044010)))
1384 #define IOCON_PIO0_1_FUNC_MASK ((unsigned int) 0x00000007)
1385 #define IOCON_PIO0_1_FUNC_GPIO ((unsigned int) 0x00000000)
1386 #define IOCON_PIO0_1_FUNC_CLKOUT ((unsigned int) 0x00000001)
1387 #define IOCON_PIO0_1_FUNC_CT32B0_MAT2 ((unsigned int) 0x00000002)
1388 #define IOCON_PIO0_1_FUNC_USB_FTOGGLE ((unsigned int) 0x00000003)
1389 #define IOCON_PIO0_1_MODE_MASK ((unsigned int) 0x00000018)
1390 #define IOCON_PIO0_1_MODE_INACTIVE ((unsigned int) 0x00000000)
1391 #define IOCON_PIO0_1_MODE_PULLDOWN ((unsigned int) 0x00000008)
1392 #define IOCON_PIO0_1_MODE_PULLUP ((unsigned int) 0x00000010)
1393 #define IOCON_PIO0_1_MODE_REPEATER ((unsigned int) 0x00000018)
1394 #define IOCON_PIO0_1_HYS_MASK ((unsigned int) 0x00000020)
1395 #define IOCON_PIO0_1_HYS_DISABLE ((unsigned int) 0x00000000)
1396 #define IOCON_PIO0_1_HYS_ENABLE ((unsigned int) 0x00000020)
1397
1398 #define IOCON_PIO1_8 (*(pREG32 (0x40044014)))
1399 #define IOCON_PIO1_8_FUNC_MASK ((unsigned int) 0x00000007)
1400 #define IOCON_PIO1_8_FUNC_GPIO ((unsigned int) 0x00000000)
1401 #define IOCON_PIO1_8_FUNC_CT16B1_CAP0 ((unsigned int) 0x00000001)
1402 #define IOCON_PIO1_8_MODE_MASK ((unsigned int) 0x00000018)
1403 #define IOCON_PIO1_8_MODE_INACTIVE ((unsigned int) 0x00000000)
1404 #define IOCON_PIO1_8_MODE_PULLDOWN ((unsigned int) 0x00000008)
1405 #define IOCON_PIO1_8_MODE_PULLUP ((unsigned int) 0x00000010)
1406 #define IOCON_PIO1_8_MODE_REPEATER ((unsigned int) 0x00000018)
1407 #define IOCON_PIO1_8_HYS_MASK ((unsigned int) 0x00000020)
1408 #define IOCON_PIO1_8_HYS_DISABLE ((unsigned int) 0x00000000)
1409 #define IOCON_PIO1_8_HYS_ENABLE ((unsigned int) 0x00000020)
1410
1411 #define IOCON_PIO0_2 (*(pREG32 (0x4004401C)))
1412 #define IOCON_PIO0_2_FUNC_MASK ((unsigned int) 0x00000007)
1413 #define IOCON_PIO0_2_FUNC_GPIO ((unsigned int) 0x00000000)
1414 #define IOCON_PIO0_2_FUNC_SSEL ((unsigned int) 0x00000001)
1415 #define IOCON_PIO0_2_FUNC_CT16B0_CAP0 ((unsigned int) 0x00000002)
1416 #define IOCON_PIO0_2_MODE_MASK ((unsigned int) 0x00000018)
1417 #define IOCON_PIO0_2_MODE_INACTIVE ((unsigned int) 0x00000000)
1418 #define IOCON_PIO0_2_MODE_PULLDOWN ((unsigned int) 0x00000008)
1419 #define IOCON_PIO0_2_MODE_PULLUP ((unsigned int) 0x00000010)
1420 #define IOCON_PIO0_2_MODE_REPEATER ((unsigned int) 0x00000018)
1421 #define IOCON_PIO0_2_HYS_MASK ((unsigned int) 0x00000020)
1422 #define IOCON_PIO0_2_HYS_DISABLE ((unsigned int) 0x00000000)
1423 #define IOCON_PIO0_2_HYS_ENABLE ((unsigned int) 0x00000020)
1424
1425 #define IOCON_PIO2_7 (*(pREG32 (0x40044020)))
1426 #define IOCON_PIO2_7_FUNC_MASK ((unsigned int) 0x00000007)
1427 #define IOCON_PIO2_7_FUNC_GPIO ((unsigned int) 0x00000000)
1428 #define IOCON_PIO2_7_MODE_MASK ((unsigned int) 0x00000018)
1429 #define IOCON_PIO2_7_MODE_INACTIVE ((unsigned int) 0x00000000)
1430 #define IOCON_PIO2_7_MODE_PULLDOWN ((unsigned int) 0x00000008)
1431 #define IOCON_PIO2_7_MODE_PULLUP ((unsigned int) 0x00000010)
1432 #define IOCON_PIO2_7_MODE_REPEATER ((unsigned int) 0x00000018)
1433 #define IOCON_PIO2_7_HYS_MASK ((unsigned int) 0x00000020)
1434 #define IOCON_PIO2_7_HYS_DISABLE ((unsigned int) 0x00000000)
1435 #define IOCON_PIO2_7_HYS_ENABLE ((unsigned int) 0x00000020)
1436
1437 #define IOCON_PIO2_8 (*(pREG32 (0x40044024)))
1438 #define IOCON_PIO2_8_FUNC_MASK ((unsigned int) 0x00000007)
1439 #define IOCON_PIO2_8_FUNC_GPIO ((unsigned int) 0x00000000)
1440 #define IOCON_PIO2_8_MODE_MASK ((unsigned int) 0x00000018)
1441 #define IOCON_PIO2_8_MODE_INACTIVE ((unsigned int) 0x00000000)
1442 #define IOCON_PIO2_8_MODE_PULLDOWN ((unsigned int) 0x00000008)
1443 #define IOCON_PIO2_8_MODE_PULLUP ((unsigned int) 0x00000010)
1444 #define IOCON_PIO2_8_MODE_REPEATER ((unsigned int) 0x00000018)
1445 #define IOCON_PIO2_8_HYS_MASK ((unsigned int) 0x00000020)
1446 #define IOCON_PIO2_8_HYS_DISABLE ((unsigned int) 0x00000000)
1447 #define IOCON_PIO2_8_HYS_ENABLE ((unsigned int) 0x00000020)
1448
1449 #define IOCON_PIO2_1 (*(pREG32 (0x40044028)))
1450 #define IOCON_PIO2_1_FUNC_MASK ((unsigned int) 0x00000007)
1451 #define IOCON_PIO2_1_FUNC_GPIO ((unsigned int) 0x00000000)
1452 #define IOCON_PIO2_1_FUNC_DSR ((unsigned int) 0x00000001)
1453 #define IOCON_PIO2_1_MODE_MASK ((unsigned int) 0x00000018)
1454 #define IOCON_PIO2_1_MODE_INACTIVE ((unsigned int) 0x00000000)
1455 #define IOCON_PIO2_1_MODE_PULLDOWN ((unsigned int) 0x00000008)
1456 #define IOCON_PIO2_1_MODE_PULLUP ((unsigned int) 0x00000010)
1457 #define IOCON_PIO2_1_MODE_REPEATER ((unsigned int) 0x00000018)
1458 #define IOCON_PIO2_1_HYS_MASK ((unsigned int) 0x00000020)
1459 #define IOCON_PIO2_1_HYS_DISABLE ((unsigned int) 0x00000000)
1460 #define IOCON_PIO2_1_HYS_ENABLE ((unsigned int) 0x00000020)
1461
1462 #define IOCON_PIO0_3 (*(pREG32 (0x4004402C)))
1463 #define IOCON_PIO0_3_FUNC_MASK ((unsigned int) 0x00000007)
1464 #define IOCON_PIO0_3_FUNC_GPIO ((unsigned int) 0x00000000)
1465 #define IOCON_PIO0_3_FUNC_USB_VBUS ((unsigned int) 0x00000001)
1466 #define IOCON_PIO0_3_MODE_MASK ((unsigned int) 0x00000018)
1467 #define IOCON_PIO0_3_MODE_INACTIVE ((unsigned int) 0x00000000)
1468 #define IOCON_PIO0_3_MODE_PULLDOWN ((unsigned int) 0x00000008)
1469 #define IOCON_PIO0_3_MODE_PULLUP ((unsigned int) 0x00000010)
1470 #define IOCON_PIO0_3_MODE_REPEATER ((unsigned int) 0x00000018)
1471 #define IOCON_PIO0_3_HYS_MASK ((unsigned int) 0x00000020)
1472 #define IOCON_PIO0_3_HYS_DISABLE ((unsigned int) 0x00000000)
1473 #define IOCON_PIO0_3_HYS_ENABLE ((unsigned int) 0x00000020)
1474
1475 #define IOCON_PIO0_4 (*(pREG32 (0x40044030)))
1476 #define IOCON_PIO0_4_FUNC_MASK ((unsigned int) 0x00000007)
1477 #define IOCON_PIO0_4_FUNC_GPIO ((unsigned int) 0x00000000)
1478 #define IOCON_PIO0_4_FUNC_I2CSCL ((unsigned int) 0x00000001)
1479 #define IOCON_PIO0_4_I2CMODE_MASK ((unsigned int) 0x00000300)
1480 #define IOCON_PIO0_4_I2CMODE_STANDARDI2C ((unsigned int) 0x00000000)
1481 #define IOCON_PIO0_4_I2CMODE_STANDARDIO ((unsigned int) 0x00000100)
1482 #define IOCON_PIO0_4_I2CMODE_FASTPLUSI2C ((unsigned int) 0x00000200)
1483
1484 #define IOCON_PIO0_5 (*(pREG32 (0x40044034)))
1485 #define IOCON_PIO0_5_FUNC_MASK ((unsigned int) 0x00000007)
1486 #define IOCON_PIO0_5_FUNC_GPIO ((unsigned int) 0x00000000)
1487 #define IOCON_PIO0_5_FUNC_I2CSDA ((unsigned int) 0x00000001)
1488 #define IOCON_PIO0_5_I2CMODE_MASK ((unsigned int) 0x00000300)
1489 #define IOCON_PIO0_5_I2CMODE_STANDARDI2C ((unsigned int) 0x00000000)
1490 #define IOCON_PIO0_5_I2CMODE_STANDARDIO ((unsigned int) 0x00000100)
1491 #define IOCON_PIO0_5_I2CMODE_FASTPLUSI2C ((unsigned int) 0x00000200)
1492
1493 #define IOCON_PIO1_9 (*(pREG32 (0x40044038)))
1494 #define IOCON_PIO1_9_FUNC_MASK ((unsigned int) 0x00000007)
1495 #define IOCON_PIO1_9_FUNC_GPIO ((unsigned int) 0x00000000)
1496 #define IOCON_PIO1_9_FUNC_CT16B1_MAT0 ((unsigned int) 0x00000001)
1497 #define IOCON_PIO1_9_MODE_MASK ((unsigned int) 0x00000018)
1498 #define IOCON_PIO1_9_MODE_INACTIVE ((unsigned int) 0x00000000)
1499 #define IOCON_PIO1_9_MODE_PULLDOWN ((unsigned int) 0x00000008)
1500 #define IOCON_PIO1_9_MODE_PULLUP ((unsigned int) 0x00000010)
1501 #define IOCON_PIO1_9_MODE_REPEATER ((unsigned int) 0x00000018)
1502 #define IOCON_PIO1_9_HYS_MASK ((unsigned int) 0x00000020)
1503 #define IOCON_PIO1_9_HYS_DISABLE ((unsigned int) 0x00000000)
1504 #define IOCON_PIO1_9_HYS_ENABLE ((unsigned int) 0x00000020)
1505
1506 #define IOCON_PIO3_4 (*(pREG32 (0x4004403C)))
1507 #define IOCON_PIO3_4_FUNC_MASK ((unsigned int) 0x00000007)
1508 #define IOCON_PIO3_4_FUNC_GPIO ((unsigned int) 0x00000000)
1509 #define IOCON_PIO3_4_MODE_MASK ((unsigned int) 0x00000018)
1510 #define IOCON_PIO3_4_MODE_INACTIVE ((unsigned int) 0x00000000)
1511 #define IOCON_PIO3_4_MODE_PULLDOWN ((unsigned int) 0x00000008)
1512 #define IOCON_PIO3_4_MODE_PULLUP ((unsigned int) 0x00000010)
1513 #define IOCON_PIO3_4_MODE_REPEATER ((unsigned int) 0x00000018)
1514 #define IOCON_PIO3_4_HYS_MASK ((unsigned int) 0x00000020)
1515 #define IOCON_PIO3_4_HYS_DISABLE ((unsigned int) 0x00000000)
1516 #define IOCON_PIO3_4_HYS_ENABLE ((unsigned int) 0x00000020)
1517
1518 #define IOCON_PIO2_4 (*(pREG32 (0x40044040)))
1519 #define IOCON_PIO2_4_FUNC_MASK ((unsigned int) 0x00000007)
1520 #define IOCON_PIO2_4_FUNC_GPIO ((unsigned int) 0x00000000)
1521 #define IOCON_PIO2_4_MODE_MASK ((unsigned int) 0x00000018)
1522 #define IOCON_PIO2_4_MODE_INACTIVE ((unsigned int) 0x00000000)
1523 #define IOCON_PIO2_4_MODE_PULLDOWN ((unsigned int) 0x00000008)
1524 #define IOCON_PIO2_4_MODE_PULLUP ((unsigned int) 0x00000010)
1525 #define IOCON_PIO2_4_MODE_REPEATER ((unsigned int) 0x00000018)
1526 #define IOCON_PIO2_4_HYS_MASK ((unsigned int) 0x00000020)
1527 #define IOCON_PIO2_4_HYS_DISABLE ((unsigned int) 0x00000000)
1528 #define IOCON_PIO2_4_HYS_ENABLE ((unsigned int) 0x00000020)
1529
1530 #define IOCON_PIO2_5 (*(pREG32 (0x40044044)))
1531 #define IOCON_PIO2_5_FUNC_MASK ((unsigned int) 0x00000007)
1532 #define IOCON_PIO2_5_FUNC_GPIO ((unsigned int) 0x00000000)
1533 #define IOCON_PIO2_5_MODE_MASK ((unsigned int) 0x00000018)
1534 #define IOCON_PIO2_5_MODE_INACTIVE ((unsigned int) 0x00000000)
1535 #define IOCON_PIO2_5_MODE_PULLDOWN ((unsigned int) 0x00000008)
1536 #define IOCON_PIO2_5_MODE_PULLUP ((unsigned int) 0x00000010)
1537 #define IOCON_PIO2_5_MODE_REPEATER ((unsigned int) 0x00000018)
1538 #define IOCON_PIO2_5_HYS_MASK ((unsigned int) 0x00000020)
1539 #define IOCON_PIO2_5_HYS_DISABLE ((unsigned int) 0x00000000)
1540 #define IOCON_PIO2_5_HYS_ENABLE ((unsigned int) 0x00000020)
1541
1542 #define IOCON_PIO3_5 (*(pREG32 (0x40044048)))
1543 #define IOCON_PIO3_5_FUNC_MASK ((unsigned int) 0x00000007)
1544 #define IOCON_PIO3_5_FUNC_GPIO ((unsigned int) 0x00000000)
1545 #define IOCON_PIO3_5_MODE_MASK ((unsigned int) 0x00000018)
1546 #define IOCON_PIO3_5_MODE_INACTIVE ((unsigned int) 0x00000000)
1547 #define IOCON_PIO3_5_MODE_PULLDOWN ((unsigned int) 0x00000008)
1548 #define IOCON_PIO3_5_MODE_PULLUP ((unsigned int) 0x00000010)
1549 #define IOCON_PIO3_5_MODE_REPEATER ((unsigned int) 0x00000018)
1550 #define IOCON_PIO3_5_HYS_MASK ((unsigned int) 0x00000020)
1551 #define IOCON_PIO3_5_HYS_DISABLE ((unsigned int) 0x00000000)
1552 #define IOCON_PIO3_5_HYS_ENABLE ((unsigned int) 0x00000020)
1553
1554 #define IOCON_PIO0_6 (*(pREG32 (0x4004404C)))
1555 #define IOCON_PIO0_6_FUNC_MASK ((unsigned int) 0x00000007)
1556 #define IOCON_PIO0_6_FUNC_GPIO ((unsigned int) 0x00000000)
1557 #define IOCON_PIO0_6_FUNC_USB_CONNECT ((unsigned int) 0x00000001)
1558 #define IOCON_PIO0_6_FUNC_SCK ((unsigned int) 0x00000002)
1559 #define IOCON_PIO0_6_MODE_MASK ((unsigned int) 0x00000018)
1560 #define IOCON_PIO0_6_MODE_INACTIVE ((unsigned int) 0x00000000)
1561 #define IOCON_PIO0_6_MODE_PULLDOWN ((unsigned int) 0x00000008)
1562 #define IOCON_PIO0_6_MODE_PULLUP ((unsigned int) 0x00000010)
1563 #define IOCON_PIO0_6_MODE_REPEATER ((unsigned int) 0x00000018)
1564 #define IOCON_PIO0_6_HYS_MASK ((unsigned int) 0x00000020)
1565 #define IOCON_PIO0_6_HYS_DISABLE ((unsigned int) 0x00000000)
1566 #define IOCON_PIO0_6_HYS_ENABLE ((unsigned int) 0x00000020)
1567
1568
1569 #define IOCON_PIO0_7 (*(pREG32 (0x40044050)))
1570 #define IOCON_PIO0_7_FUNC_MASK ((unsigned int) 0x00000007)
1571 #define IOCON_PIO0_7_FUNC_GPIO ((unsigned int) 0x00000000)
1572 #define IOCON_PIO0_7_FUNC_CTS ((unsigned int) 0x00000001)
1573 #define IOCON_PIO0_7_MODE_MASK ((unsigned int) 0x00000018)
1574 #define IOCON_PIO0_7_MODE_INACTIVE ((unsigned int) 0x00000000)
1575 #define IOCON_PIO0_7_MODE_PULLDOWN ((unsigned int) 0x00000008)
1576 #define IOCON_PIO0_7_MODE_PULLUP ((unsigned int) 0x00000010)
1577 #define IOCON_PIO0_7_MODE_REPEATER ((unsigned int) 0x00000018)
1578 #define IOCON_PIO0_7_HYS_MASK ((unsigned int) 0x00000020)
1579 #define IOCON_PIO0_7_HYS_DISABLE ((unsigned int) 0x00000000)
1580 #define IOCON_PIO0_7_HYS_ENABLE ((unsigned int) 0x00000020)
1581
1582 #define IOCON_PIO2_9 (*(pREG32 (0x40044054)))
1583 #define IOCON_PIO2_9_FUNC_MASK ((unsigned int) 0x00000007)
1584 #define IOCON_PIO2_9_FUNC_GPIO ((unsigned int) 0x00000000)
1585 #define IOCON_PIO2_9_MODE_MASK ((unsigned int) 0x00000018)
1586 #define IOCON_PIO2_9_MODE_INACTIVE ((unsigned int) 0x00000000)
1587 #define IOCON_PIO2_9_MODE_PULLDOWN ((unsigned int) 0x00000008)
1588 #define IOCON_PIO2_9_MODE_PULLUP ((unsigned int) 0x00000010)
1589 #define IOCON_PIO2_9_MODE_REPEATER ((unsigned int) 0x00000018)
1590 #define IOCON_PIO2_9_HYS_MASK ((unsigned int) 0x00000020)
1591 #define IOCON_PIO2_9_HYS_DISABLE ((unsigned int) 0x00000000)
1592 #define IOCON_PIO2_9_HYS_ENABLE ((unsigned int) 0x00000020)
1593
1594 #define IOCON_PIO2_10 (*(pREG32 (0x40044058)))
1595 #define IOCON_PIO2_10_FUNC_MASK ((unsigned int) 0x00000007)
1596 #define IOCON_PIO2_10_FUNC_GPIO ((unsigned int) 0x00000000)
1597 #define IOCON_PIO2_10_MODE_MASK ((unsigned int) 0x00000018)
1598 #define IOCON_PIO2_10_MODE_INACTIVE ((unsigned int) 0x00000000)
1599 #define IOCON_PIO2_10_MODE_PULLDOWN ((unsigned int) 0x00000008)
1600 #define IOCON_PIO2_10_MODE_PULLUP ((unsigned int) 0x00000010)
1601 #define IOCON_PIO2_10_MODE_REPEATER ((unsigned int) 0x00000018)
1602 #define IOCON_PIO2_10_HYS_MASK ((unsigned int) 0x00000020)
1603 #define IOCON_PIO2_10_HYS_DISABLE ((unsigned int) 0x00000000)
1604 #define IOCON_PIO2_10_HYS_ENABLE ((unsigned int) 0x00000020)
1605
1606 #define IOCON_PIO2_2 (*(pREG32 (0x4004405C)))
1607 #define IOCON_PIO2_2_FUNC_MASK ((unsigned int) 0x00000007)
1608 #define IOCON_PIO2_2_FUNC_GPIO ((unsigned int) 0x00000000)
1609 #define IOCON_PIO2_2_FUNC_DCD ((unsigned int) 0x00000001)
1610 #define IOCON_PIO2_2_MODE_MASK ((unsigned int) 0x00000018)
1611 #define IOCON_PIO2_2_MODE_INACTIVE ((unsigned int) 0x00000000)
1612 #define IOCON_PIO2_2_MODE_PULLDOWN ((unsigned int) 0x00000008)
1613 #define IOCON_PIO2_2_MODE_PULLUP ((unsigned int) 0x00000010)
1614 #define IOCON_PIO2_2_MODE_REPEATER ((unsigned int) 0x00000018)
1615 #define IOCON_PIO2_2_HYS_MASK ((unsigned int) 0x00000020)
1616 #define IOCON_PIO2_2_HYS_DISABLE ((unsigned int) 0x00000000)
1617 #define IOCON_PIO2_2_HYS_ENABLE ((unsigned int) 0x00000020)
1618
1619 #define IOCON_PIO0_8 (*(pREG32 (0x40044060)))
1620 #define IOCON_PIO0_8_FUNC_MASK ((unsigned int) 0x00000007)
1621 #define IOCON_PIO0_8_FUNC_GPIO ((unsigned int) 0x00000000)
1622 #define IOCON_PIO0_8_FUNC_MISO0 ((unsigned int) 0x00000001)
1623 #define IOCON_PIO0_8_FUNC_CT16B0_MAT0 ((unsigned int) 0x00000002)
1624 #define IOCON_PIO0_8_MODE_MASK ((unsigned int) 0x00000018)
1625 #define IOCON_PIO0_8_MODE_INACTIVE ((unsigned int) 0x00000000)
1626 #define IOCON_PIO0_8_MODE_PULLDOWN ((unsigned int) 0x00000008)
1627 #define IOCON_PIO0_8_MODE_PULLUP ((unsigned int) 0x00000010)
1628 #define IOCON_PIO0_8_MODE_REPEATER ((unsigned int) 0x00000018)
1629 #define IOCON_PIO0_8_HYS_MASK ((unsigned int) 0x00000020)
1630 #define IOCON_PIO0_8_HYS_DISABLE ((unsigned int) 0x00000000)
1631 #define IOCON_PIO0_8_HYS_ENABLE ((unsigned int) 0x00000020)
1632
1633 #define IOCON_PIO0_9 (*(pREG32 (0x40044064)))
1634 #define IOCON_PIO0_9_FUNC_MASK ((unsigned int) 0x00000007)
1635 #define IOCON_PIO0_9_FUNC_GPIO ((unsigned int) 0x00000000)
1636 #define IOCON_PIO0_9_FUNC_MOSI0 ((unsigned int) 0x00000001)
1637 #define IOCON_PIO0_9_FUNC_CT16B0_MAT1 ((unsigned int) 0x00000002)
1638 #define IOCON_PIO0_9_FUNC_SWO ((unsigned int) 0x00000003)
1639 #define IOCON_PIO0_9_MODE_MASK ((unsigned int) 0x00000018)
1640 #define IOCON_PIO0_9_MODE_INACTIVE ((unsigned int) 0x00000000)
1641 #define IOCON_PIO0_9_MODE_PULLDOWN ((unsigned int) 0x00000008)
1642 #define IOCON_PIO0_9_MODE_PULLUP ((unsigned int) 0x00000010)
1643 #define IOCON_PIO0_9_MODE_REPEATER ((unsigned int) 0x00000018)
1644 #define IOCON_PIO0_9_HYS_MASK ((unsigned int) 0x00000020)
1645 #define IOCON_PIO0_9_HYS_DISABLE ((unsigned int) 0x00000000)
1646 #define IOCON_PIO0_9_HYS_ENABLE ((unsigned int) 0x00000020)
1647
1648 #define IOCON_JTAG_TCK_PIO0_10 (*(pREG32 (0x40044068)))
1649 #define IOCON_JTAG_TCK_PIO0_10_FUNC_MASK ((unsigned int) 0x00000007)
1650 #define IOCON_JTAG_TCK_PIO0_10_FUNC_SWCLK ((unsigned int) 0x00000000)
1651 #define IOCON_JTAG_TCK_PIO0_10_FUNC_GPIO ((unsigned int) 0x00000001)
1652 #define IOCON_JTAG_TCK_PIO0_10_FUNC_SCK ((unsigned int) 0x00000002)
1653 #define IOCON_JTAG_TCK_PIO0_10_FUNC_CT16B0_MAT2 ((unsigned int) 0x00000003)
1654 #define IOCON_JTAG_TCK_PIO0_10_MODE_MASK ((unsigned int) 0x00000018)
1655 #define IOCON_JTAG_TCK_PIO0_10_MODE_INACTIVE ((unsigned int) 0x00000000)
1656 #define IOCON_JTAG_TCK_PIO0_10_MODE_PULLDOWN ((unsigned int) 0x00000008)
1657 #define IOCON_JTAG_TCK_PIO0_10_MODE_PULLUP ((unsigned int) 0x00000010)
1658 #define IOCON_JTAG_TCK_PIO0_10_MODE_REPEATER ((unsigned int) 0x00000018)
1659 #define IOCON_JTAG_TCK_PIO0_10_HYS_MASK ((unsigned int) 0x00000020)
1660 #define IOCON_JTAG_TCK_PIO0_10_HYS_DISABLE ((unsigned int) 0x00000000)
1661 #define IOCON_JTAG_TCK_PIO0_10_HYS_ENABLE ((unsigned int) 0x00000020)
1662
1663 #define IOCON_PIO1_10 (*(pREG32 (0x4004406C)))
1664 #define IOCON_PIO1_10_FUNC_MASK ((unsigned int) 0x00000007)
1665 #define IOCON_PIO1_10_FUNC_GPIO ((unsigned int) 0x00000000)
1666 #define IOCON_PIO1_10_FUNC_AD6 ((unsigned int) 0x00000001)
1667 #define IOCON_PIO1_10_FUNC_CT16B1_MAT1 ((unsigned int) 0x00000002)
1668 #define IOCON_PIO1_10_MODE_MASK ((unsigned int) 0x00000018)
1669 #define IOCON_PIO1_10_MODE_INACTIVE ((unsigned int) 0x00000000)
1670 #define IOCON_PIO1_10_MODE_PULLDOWN ((unsigned int) 0x00000008)
1671 #define IOCON_PIO1_10_MODE_PULLUP ((unsigned int) 0x00000010)
1672 #define IOCON_PIO1_10_MODE_REPEATER ((unsigned int) 0x00000018)
1673 #define IOCON_PIO1_10_HYS_MASK ((unsigned int) 0x00000020)
1674 #define IOCON_PIO1_10_HYS_DISABLE ((unsigned int) 0x00000000)
1675 #define IOCON_PIO1_10_HYS_ENABLE ((unsigned int) 0x00000020)
1676 #define IOCON_PIO1_10_ADMODE_MASK ((unsigned int) 0x00000080)
1677 #define IOCON_PIO1_10_ADMODE_ANALOG ((unsigned int) 0x00000000)
1678 #define IOCON_PIO1_10_ADMODE_DIGITAL ((unsigned int) 0x00000080)
1679
1680 #define IOCON_PIO2_11 (*(pREG32 (0x40044070)))
1681 #define IOCON_PIO2_11_FUNC_MASK ((unsigned int) 0x00000007)
1682 #define IOCON_PIO2_11_FUNC_GPIO ((unsigned int) 0x00000000)
1683 #define IOCON_PIO2_11_FUNC_SCK0 ((unsigned int) 0x00000001)
1684 #define IOCON_PIO2_11_MODE_MASK ((unsigned int) 0x00000018)
1685 #define IOCON_PIO2_11_MODE_INACTIVE ((unsigned int) 0x00000000)
1686 #define IOCON_PIO2_11_MODE_PULLDOWN ((unsigned int) 0x00000008)
1687 #define IOCON_PIO2_11_MODE_PULLUP ((unsigned int) 0x00000010)
1688 #define IOCON_PIO2_11_MODE_REPEATER ((unsigned int) 0x00000018)
1689 #define IOCON_PIO2_11_HYS_MASK ((unsigned int) 0x00000020)
1690 #define IOCON_PIO2_11_HYS_DISABLE ((unsigned int) 0x00000000)
1691 #define IOCON_PIO2_11_HYS_ENABLE ((unsigned int) 0x00000020)
1692
1693 #define IOCON_JTAG_TDI_PIO0_11 (*(pREG32 (0x40044074)))
1694 #define IOCON_JTAG_TDI_PIO0_11_FUNC_MASK ((unsigned int) 0x00000007)
1695 #define IOCON_JTAG_TDI_PIO0_11_FUNC_TDI ((unsigned int) 0x00000000)
1696 #define IOCON_JTAG_TDI_PIO0_11_FUNC_GPIO ((unsigned int) 0x00000001)
1697 #define IOCON_JTAG_TDI_PIO0_11_FUNC_AD0 ((unsigned int) 0x00000002)
1698 #define IOCON_JTAG_TDI_PIO0_11_FUNC_CT32B0_MAT3 ((unsigned int) 0x00000003)
1699 #define IOCON_JTAG_TDI_PIO0_11_MODE_MASK ((unsigned int) 0x00000018)
1700 #define IOCON_JTAG_TDI_PIO0_11_MODE_INACTIVE ((unsigned int) 0x00000000)
1701 #define IOCON_JTAG_TDI_PIO0_11_MODE_PULLDOWN ((unsigned int) 0x00000008)
1702 #define IOCON_JTAG_TDI_PIO0_11_MODE_PULLUP ((unsigned int) 0x00000010)
1703 #define IOCON_JTAG_TDI_PIO0_11_MODE_REPEATER ((unsigned int) 0x00000018)
1704 #define IOCON_JTAG_TDI_PIO0_11_HYS_MASK ((unsigned int) 0x00000020)
1705 #define IOCON_JTAG_TDI_PIO0_11_HYS_DISABLE ((unsigned int) 0x00000000)
1706 #define IOCON_JTAG_TDI_PIO0_11_HYS_ENABLE ((unsigned int) 0x00000020)
1707 #define IOCON_JTAG_TDI_PIO0_11_ADMODE_MASK ((unsigned int) 0x00000080)
1708 #define IOCON_JTAG_TDI_PIO0_11_ADMODE_ANALOG ((unsigned int) 0x00000000)
1709 #define IOCON_JTAG_TDI_PIO0_11_ADMODE_DIGITAL ((unsigned int) 0x00000080)
1710
1711 #define IOCON_JTAG_TMS_PIO1_0 (*(pREG32 (0x40044078)))
1712 #define IOCON_JTAG_TMS_PIO1_0_FUNC_MASK ((unsigned int) 0x00000007)
1713 #define IOCON_JTAG_TMS_PIO1_0_FUNC_TMS ((unsigned int) 0x00000000)
1714 #define IOCON_JTAG_TMS_PIO1_0_FUNC_GPIO ((unsigned int) 0x00000001)
1715 #define IOCON_JTAG_TMS_PIO1_0_FUNC_AD1 ((unsigned int) 0x00000002)
1716 #define IOCON_JTAG_TMS_PIO1_0_FUNC_CT32B1_CAP0 ((unsigned int) 0x00000003)
1717 #define IOCON_JTAG_TMS_PIO1_0_MODE_MASK ((unsigned int) 0x00000018)
1718 #define IOCON_JTAG_TMS_PIO1_0_MODE_INACTIVE ((unsigned int) 0x00000000)
1719 #define IOCON_JTAG_TMS_PIO1_0_MODE_PULLDOWN ((unsigned int) 0x00000008)
1720 #define IOCON_JTAG_TMS_PIO1_0_MODE_PULLUP ((unsigned int) 0x00000010)
1721 #define IOCON_JTAG_TMS_PIO1_0_MODE_REPEATER ((unsigned int) 0x00000018)
1722 #define IOCON_JTAG_TMS_PIO1_0_HYS_MASK ((unsigned int) 0x00000020)
1723 #define IOCON_JTAG_TMS_PIO1_0_HYS_DISABLE ((unsigned int) 0x00000000)
1724 #define IOCON_JTAG_TMS_PIO1_0_HYS_ENABLE ((unsigned int) 0x00000020)
1725 #define IOCON_JTAG_TMS_PIO1_0_ADMODE_MASK ((unsigned int) 0x00000080)
1726 #define IOCON_JTAG_TMS_PIO1_0_ADMODE_ANALOG ((unsigned int) 0x00000000)
1727 #define IOCON_JTAG_TMS_PIO1_0_ADMODE_DIGITAL ((unsigned int) 0x00000080)
1728
1729 #define IOCON_JTAG_TDO_PIO1_1 (*(pREG32 (0x4004407C)))
1730 #define IOCON_JTAG_TDO_PIO1_1_FUNC_MASK ((unsigned int) 0x00000007)
1731 #define IOCON_JTAG_TDO_PIO1_1_FUNC_TDO ((unsigned int) 0x00000000)
1732 #define IOCON_JTAG_TDO_PIO1_1_FUNC_GPIO ((unsigned int) 0x00000001)
1733 #define IOCON_JTAG_TDO_PIO1_1_FUNC_AD2 ((unsigned int) 0x00000002)
1734 #define IOCON_JTAG_TDO_PIO1_1_FUNC_CT32B1_MAT0 ((unsigned int) 0x00000003)
1735 #define IOCON_JTAG_TDO_PIO1_1_MODE_MASK ((unsigned int) 0x00000018)
1736 #define IOCON_JTAG_TDO_PIO1_1_MODE_INACTIVE ((unsigned int) 0x00000000)
1737 #define IOCON_JTAG_TDO_PIO1_1_MODE_PULLDOWN ((unsigned int) 0x00000008)
1738 #define IOCON_JTAG_TDO_PIO1_1_MODE_PULLUP ((unsigned int) 0x00000010)
1739 #define IOCON_JTAG_TDO_PIO1_1_MODE_REPEATER ((unsigned int) 0x00000018)
1740 #define IOCON_JTAG_TDO_PIO1_1_HYS_MASK ((unsigned int) 0x00000020)
1741 #define IOCON_JTAG_TDO_PIO1_1_HYS_DISABLE ((unsigned int) 0x00000000)
1742 #define IOCON_JTAG_TDO_PIO1_1_HYS_ENABLE ((unsigned int) 0x00000020)
1743 #define IOCON_JTAG_TDO_PIO1_1_ADMODE_MASK ((unsigned int) 0x00000080)
1744 #define IOCON_JTAG_TDO_PIO1_1_ADMODE_ANALOG ((unsigned int) 0x00000000)
1745 #define IOCON_JTAG_TDO_PIO1_1_ADMODE_DIGITAL ((unsigned int) 0x00000080)
1746
1747 #define IOCON_JTAG_nTRST_PIO1_2 (*(pREG32 (0x40044080)))
1748 #define IOCON_JTAG_nTRST_PIO1_2_FUNC_MASK ((unsigned int) 0x00000007)
1749 #define IOCON_JTAG_nTRST_PIO1_2_FUNC_TRST ((unsigned int) 0x00000000)
1750 #define IOCON_JTAG_nTRST_PIO1_2_FUNC_GPIO ((unsigned int) 0x00000001)
1751 #define IOCON_JTAG_nTRST_PIO1_2_FUNC_AD3 ((unsigned int) 0x00000002)
1752 #define IOCON_JTAG_nTRST_PIO1_2_FUNC_CT32B1_MAT1 ((unsigned int) 0x00000003)
1753 #define IOCON_JTAG_nTRST_PIO1_2_MODE_MASK ((unsigned int) 0x00000018)
1754 #define IOCON_JTAG_nTRST_PIO1_2_MODE_INACTIVE ((unsigned int) 0x00000000)
1755 #define IOCON_JTAG_nTRST_PIO1_2_MODE_PULLDOWN ((unsigned int) 0x00000008)
1756 #define IOCON_JTAG_nTRST_PIO1_2_MODE_PULLUP ((unsigned int) 0x00000010)
1757 #define IOCON_JTAG_nTRST_PIO1_2_MODE_REPEATER ((unsigned int) 0x00000018)
1758 #define IOCON_JTAG_nTRST_PIO1_2_HYS_MASK ((unsigned int) 0x00000020)
1759 #define IOCON_JTAG_nTRST_PIO1_2_HYS_DISABLE ((unsigned int) 0x00000000)
1760 #define IOCON_JTAG_nTRST_PIO1_2_HYS_ENABLE ((unsigned int) 0x00000020)
1761 #define IOCON_JTAG_nTRST_PIO1_2_ADMODE_MASK ((unsigned int) 0x00000080)
1762 #define IOCON_JTAG_nTRST_PIO1_2_ADMODE_ANALOG ((unsigned int) 0x00000000)
1763 #define IOCON_JTAG_nTRST_PIO1_2_ADMODE_DIGITAL ((unsigned int) 0x00000080)
1764
1765 #define IOCON_PIO3_0 (*(pREG32 (0x40044084)))
1766 #define IOCON_PIO3_0_FUNC_MASK ((unsigned int) 0x00000007)
1767 #define IOCON_PIO3_0_FUNC_GPIO ((unsigned int) 0x00000000)
1768 #define IOCON_PIO3_0_MODE_MASK ((unsigned int) 0x00000018)
1769 #define IOCON_PIO3_0_MODE_INACTIVE ((unsigned int) 0x00000000)
1770 #define IOCON_PIO3_0_MODE_PULLDOWN ((unsigned int) 0x00000008)
1771 #define IOCON_PIO3_0_MODE_PULLUP ((unsigned int) 0x00000010)
1772 #define IOCON_PIO3_0_MODE_REPEATER ((unsigned int) 0x00000018)
1773 #define IOCON_PIO3_0_HYS_MASK ((unsigned int) 0x00000020)
1774 #define IOCON_PIO3_0_HYS_DISABLE ((unsigned int) 0x00000000)
1775 #define IOCON_PIO3_0_HYS_ENABLE ((unsigned int) 0x00000020)
1776
1777 #define IOCON_PIO3_1 (*(pREG32 (0x40044088)))
1778 #define IOCON_PIO3_1_FUNC_MASK ((unsigned int) 0x00000007)
1779 #define IOCON_PIO3_1_FUNC_GPIO ((unsigned int) 0x00000000)
1780 #define IOCON_PIO3_1_MODE_MASK ((unsigned int) 0x00000018)
1781 #define IOCON_PIO3_1_MODE_INACTIVE ((unsigned int) 0x00000000)
1782 #define IOCON_PIO3_1_MODE_PULLDOWN ((unsigned int) 0x00000008)
1783 #define IOCON_PIO3_1_MODE_PULLUP ((unsigned int) 0x00000010)
1784 #define IOCON_PIO3_1_MODE_REPEATER ((unsigned int) 0x00000018)
1785 #define IOCON_PIO3_1_HYS_MASK ((unsigned int) 0x00000020)
1786 #define IOCON_PIO3_1_HYS_DISABLE ((unsigned int) 0x00000000)
1787 #define IOCON_PIO3_1_HYS_ENABLE ((unsigned int) 0x00000020)
1788
1789 #define IOCON_PIO2_3 (*(pREG32 (0x4004408C)))
1790 #define IOCON_PIO2_3_FUNC_MASK 0x7
1791 #define IOCON_PIO2_3_MODE_MASK 0x18
1792 #define IOCON_PIO2_3_HYS_MASK 0x20
1793 #define IOCON_PIO2_3_HYS 0x20
1794
1795 #define IOCON_SWDIO_PIO1_3 (*(pREG32 (0x40044090)))
1796 #define IOCON_SWDIO_PIO1_3_FUNC_MASK ((unsigned int) 0x00000007)
1797 #define IOCON_SWDIO_PIO1_3_FUNC_SWDIO ((unsigned int) 0x00000000)
1798 #define IOCON_SWDIO_PIO1_3_FUNC_GPIO ((unsigned int) 0x00000001)
1799 #define IOCON_SWDIO_PIO1_3_FUNC_AD4 ((unsigned int) 0x00000002)
1800 #define IOCON_SWDIO_PIO1_3_FUNC_CT32B1_MAT2 ((unsigned int) 0x00000003)
1801 #define IOCON_SWDIO_PIO1_3_HYS_MASK ((unsigned int) 0x00000020)
1802 #define IOCON_SWDIO_PIO1_3_HYS_DISABLE ((unsigned int) 0x00000000)
1803 #define IOCON_SWDIO_PIO1_3_HYS_ENABLE ((unsigned int) 0x00000020)
1804 #define IOCON_SWDIO_PIO1_3_ADMODE_MASK ((unsigned int) 0x00000080)
1805 #define IOCON_SWDIO_PIO1_3_ADMODE_ANALOG ((unsigned int) 0x00000000)
1806 #define IOCON_SWDIO_PIO1_3_ADMODE_DIGITAL ((unsigned int) 0x00000080)
1807
1808 #define IOCON_PIO1_4 (*(pREG32 (0x40044094)))
1809 #define IOCON_PIO1_4_FUNC_MASK ((unsigned int) 0x00000007)
1810 #define IOCON_PIO1_4_FUNC_GPIO ((unsigned int) 0x00000000)
1811 #define IOCON_PIO1_4_FUNC_AD5 ((unsigned int) 0x00000001)
1812 #define IOCON_PIO1_4_FUNC_CT32B1_MAT3 ((unsigned int) 0x00000002)
1813 #define IOCON_PIO1_4_MODE_MASK ((unsigned int) 0x00000018)
1814 #define IOCON_PIO1_4_MODE_INACTIVE ((unsigned int) 0x00000000)
1815 #define IOCON_PIO1_4_MODE_PULLDOWN ((unsigned int) 0x00000008)
1816 #define IOCON_PIO1_4_MODE_PULLUP ((unsigned int) 0x00000010)
1817 #define IOCON_PIO1_4_MODE_REPEATER ((unsigned int) 0x00000018)
1818 #define IOCON_PIO1_4_HYS_MASK ((unsigned int) 0x00000020)
1819 #define IOCON_PIO1_4_HYS_DISABLE ((unsigned int) 0x00000000)
1820 #define IOCON_PIO1_4_HYS_ENABLE ((unsigned int) 0x00000020)
1821 #define IOCON_PIO1_4_ADMODE_MASK ((unsigned int) 0x00000080)
1822 #define IOCON_PIO1_4_ADMODE_ANALOG ((unsigned int) 0x00000000)
1823 #define IOCON_PIO1_4_ADMODE_DIGITAL ((unsigned int) 0x00000080)
1824
1825 #define IOCON_PIO1_11 (*(pREG32 (0x40044098)))
1826 #define IOCON_PIO1_11_FUNC_MASK ((unsigned int) 0x00000007)
1827 #define IOCON_PIO1_11_FUNC_GPIO ((unsigned int) 0x00000000)
1828 #define IOCON_PIO1_11_FUNC_AD7 ((unsigned int) 0x00000001)
1829 #define IOCON_PIO1_11_MODE_MASK ((unsigned int) 0x00000018)
1830 #define IOCON_PIO1_11_MODE_INACTIVE ((unsigned int) 0x00000000)
1831 #define IOCON_PIO1_11_MODE_PULLDOWN ((unsigned int) 0x00000008)
1832 #define IOCON_PIO1_11_MODE_PULLUP ((unsigned int) 0x00000010)
1833 #define IOCON_PIO1_11_MODE_REPEATER ((unsigned int) 0x00000018)
1834 #define IOCON_PIO1_11_HYS_MASK ((unsigned int) 0x00000020)
1835 #define IOCON_PIO1_11_HYS_DISABLE ((unsigned int) 0x00000000)
1836 #define IOCON_PIO1_11_HYS_ENABLE ((unsigned int) 0x00000020)
1837 #define IOCON_PIO1_11_ADMODE_MASK ((unsigned int) 0x00000080)
1838 #define IOCON_PIO1_11_ADMODE_ANALOG ((unsigned int) 0x00000000)
1839 #define IOCON_PIO1_11_ADMODE_DIGITAL ((unsigned int) 0x00000080)
1840
1841 #define IOCON_PIO3_2 (*(pREG32 (0x4004409C)))
1842 #define IOCON_PIO3_2_FUNC_MASK ((unsigned int) 0x00000007)
1843 #define IOCON_PIO3_2_FUNC_GPIO ((unsigned int) 0x00000000)
1844 #define IOCON_PIO3_2_MODE_MASK ((unsigned int) 0x00000018)
1845 #define IOCON_PIO3_2_MODE_INACTIVE ((unsigned int) 0x00000000)
1846 #define IOCON_PIO3_2_MODE_PULLDOWN ((unsigned int) 0x00000008)
1847 #define IOCON_PIO3_2_MODE_PULLUP ((unsigned int) 0x00000010)
1848 #define IOCON_PIO3_2_MODE_REPEATER ((unsigned int) 0x00000018)
1849 #define IOCON_PIO3_2_HYS_MASK ((unsigned int) 0x00000020)
1850 #define IOCON_PIO3_2_HYS_DISABLE ((unsigned int) 0x00000000)
1851 #define IOCON_PIO3_2_HYS_ENABLE ((unsigned int) 0x00000020)
1852
1853 #define IOCON_PIO1_5 (*(pREG32 (0x400440A0)))
1854 #define IOCON_PIO1_5_FUNC_MASK ((unsigned int) 0x00000007)
1855 #define IOCON_PIO1_5_FUNC_GPIO ((unsigned int) 0x00000000)
1856 #define IOCON_PIO1_5_FUNC_RTS ((unsigned int) 0x00000001)
1857 #define IOCON_PIO1_5_FUNC_CT32B0_CAP0 ((unsigned int) 0x00000002)
1858 #define IOCON_PIO1_5_MODE_MASK ((unsigned int) 0x00000018)
1859 #define IOCON_PIO1_5_MODE_INACTIVE ((unsigned int) 0x00000000)
1860 #define IOCON_PIO1_5_MODE_PULLDOWN ((unsigned int) 0x00000008)
1861 #define IOCON_PIO1_5_MODE_PULLUP ((unsigned int) 0x00000010)
1862 #define IOCON_PIO1_5_MODE_REPEATER ((unsigned int) 0x00000018)
1863 #define IOCON_PIO1_5_HYS_MASK ((unsigned int) 0x00000020)
1864 #define IOCON_PIO1_5_HYS_DISABLE ((unsigned int) 0x00000000)
1865 #define IOCON_PIO1_5_HYS_ENABLE ((unsigned int) 0x00000020)
1866
1867 #define IOCON_PIO1_6 (*(pREG32 (0x400440A4)))
1868 #define IOCON_PIO1_6_FUNC_MASK ((unsigned int) 0x00000007)
1869 #define IOCON_PIO1_6_FUNC_GPIO ((unsigned int) 0x00000000)
1870 #define IOCON_PIO1_6_FUNC_UART_RXD ((unsigned int) 0x00000001)
1871 #define IOCON_PIO1_6_FUNC_CT32B0_MAT0 ((unsigned int) 0x00000002)
1872 #define IOCON_PIO1_6_MODE_MASK ((unsigned int) 0x00000018)
1873 #define IOCON_PIO1_6_MODE_INACTIVE ((unsigned int) 0x00000000)
1874 #define IOCON_PIO1_6_MODE_PULLDOWN ((unsigned int) 0x00000008)
1875 #define IOCON_PIO1_6_MODE_PULLUP ((unsigned int) 0x00000010)
1876 #define IOCON_PIO1_6_MODE_REPEATER ((unsigned int) 0x00000018)
1877 #define IOCON_PIO1_6_HYS_MASK ((unsigned int) 0x00000020)
1878 #define IOCON_PIO1_6_HYS_DISABLE ((unsigned int) 0x00000000)
1879 #define IOCON_PIO1_6_HYS_ENABLE ((unsigned int) 0x00000020)
1880
1881 #define IOCON_PIO1_7 (*(pREG32 (0x400440A8)))
1882 #define IOCON_PIO1_7_FUNC_MASK ((unsigned int) 0x00000007)
1883 #define IOCON_PIO1_7_FUNC_GPIO ((unsigned int) 0x00000000)
1884 #define IOCON_PIO1_7_FUNC_UART_TXD ((unsigned int) 0x00000001)
1885 #define IOCON_PIO1_7_FUNC_CT32B0_MAT1 ((unsigned int) 0x00000002)
1886 #define IOCON_PIO1_7_MODE_MASK ((unsigned int) 0x00000018)
1887 #define IOCON_PIO1_7_MODE_INACTIVE ((unsigned int) 0x00000000)
1888 #define IOCON_PIO1_7_MODE_PULLDOWN ((unsigned int) 0x00000008)
1889 #define IOCON_PIO1_7_MODE_PULLUP ((unsigned int) 0x00000010)
1890 #define IOCON_PIO1_7_MODE_REPEATER ((unsigned int) 0x00000018)
1891 #define IOCON_PIO1_7_HYS_MASK ((unsigned int) 0x00000020)
1892 #define IOCON_PIO1_7_HYS_DISABLE ((unsigned int) 0x00000000)
1893 #define IOCON_PIO1_7_HYS_ENABLE ((unsigned int) 0x00000020)
1894
1895 #define IOCON_PIO3_3 (*(pREG32 (0x400440AC)))
1896 #define IOCON_PIO3_3_FUNC_MASK ((unsigned int) 0x00000007)
1897 #define IOCON_PIO3_3_FUNC_GPIO ((unsigned int) 0x00000000)
1898 #define IOCON_PIO3_3_MODE_MASK ((unsigned int) 0x00000018)
1899 #define IOCON_PIO3_3_MODE_INACTIVE ((unsigned int) 0x00000000)
1900 #define IOCON_PIO3_3_MODE_PULLDOWN ((unsigned int) 0x00000008)
1901 #define IOCON_PIO3_3_MODE_PULLUP ((unsigned int) 0x00000010)
1902 #define IOCON_PIO3_3_MODE_REPEATER ((unsigned int) 0x00000018)
1903 #define IOCON_PIO3_3_HYS_MASK ((unsigned int) 0x00000020)
1904 #define IOCON_PIO3_3_HYS_DISABLE ((unsigned int) 0x00000000)
1905 #define IOCON_PIO3_3_HYS_ENABLE ((unsigned int) 0x00000020)
1906
1907 #define IOCON_SCKLOC (*(pREG32 (0x400440B0)))
1908 #define IOCON_SCKLOC_SCKPIN_MASK ((unsigned int) 0x00000003)
1909 #define IOCON_SCKLOC_SCKPIN_PIO0_10 ((unsigned int) 0x00000000) // Set SCK function to pin 0.10
1910 #define IOCON_SCKLOC_SCKPIN_PIO2_11 ((unsigned int) 0x00000001) // Set SCK function to pin 2.11
1911 #define IOCON_SCKLOC_SCKPIN_PIO0_6 ((unsigned int) 0x00000003) // Set SCK function to pin 0.6
1912
1913 /*##############################################################################
1914 ## Nested Vectored Interrupt Controller
1915 ##############################################################################*/
1916
1917 #define NVIC_BASE_ADDRESS (0xE000E100)
1918
1919 typedef struct
1920 {
1921 volatile uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
1922 uint32_t RESERVED0[24];
1923 volatile uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
1924 uint32_t RSERVED1[24];
1925 volatile uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
1926 uint32_t RESERVED2[24];
1927 volatile uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
1928 uint32_t RESERVED3[24];
1929 volatile uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
1930 uint32_t RESERVED4[56];
1931 volatile uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
1932 uint32_t RESERVED5[644];
1933 volatile uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
1934 } NVIC_Type;
1935
1936 #define NVIC ((NVIC_Type *) NVIC_BASE_ADDRESS)
1937
1938 static inline void __enable_irq() { __asm volatile ("cpsie i"); }
1939 static inline void __disable_irq() { __asm volatile ("cpsid i"); }
1940
1941 typedef enum IRQn
1942 {
1943 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
1944 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
1945 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
1946 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
1947 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
1948 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
1949 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
1950 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
1951 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
1952
1953 /****** LPC13xx Specific Interrupt Numbers *******************************************************/
1954 WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */
1955 WAKEUP1_IRQn = 1, /*!< There are 40 pins in total for LPC17xx */
1956 WAKEUP2_IRQn = 2,
1957 WAKEUP3_IRQn = 3,
1958 WAKEUP4_IRQn = 4,
1959 WAKEUP5_IRQn = 5,
1960 WAKEUP6_IRQn = 6,
1961 WAKEUP7_IRQn = 7,
1962 WAKEUP8_IRQn = 8,
1963 WAKEUP9_IRQn = 9,
1964 WAKEUP10_IRQn = 10,
1965 WAKEUP11_IRQn = 11,
1966 WAKEUP12_IRQn = 12,
1967 WAKEUP13_IRQn = 13,
1968 WAKEUP14_IRQn = 14,
1969 WAKEUP15_IRQn = 15,
1970 WAKEUP16_IRQn = 16,
1971 WAKEUP17_IRQn = 17,
1972 WAKEUP18_IRQn = 18,
1973 WAKEUP19_IRQn = 19,
1974 WAKEUP20_IRQn = 20,
1975 WAKEUP21_IRQn = 21,
1976 WAKEUP22_IRQn = 22,
1977 WAKEUP23_IRQn = 23,
1978 WAKEUP24_IRQn = 24,
1979 WAKEUP25_IRQn = 25,
1980 WAKEUP26_IRQn = 26,
1981 WAKEUP27_IRQn = 27,
1982 WAKEUP28_IRQn = 28,
1983 WAKEUP29_IRQn = 29,
1984 WAKEUP30_IRQn = 30,
1985 WAKEUP31_IRQn = 31,
1986 WAKEUP32_IRQn = 32,
1987 WAKEUP33_IRQn = 33,
1988 WAKEUP34_IRQn = 34,
1989 WAKEUP35_IRQn = 35,
1990 WAKEUP36_IRQn = 36,
1991 WAKEUP37_IRQn = 37,
1992 WAKEUP38_IRQn = 38,
1993 WAKEUP39_IRQn = 39,
1994 I2C_IRQn = 40, /*!< I2C Interrupt */
1995 TIMER_16_0_IRQn = 41, /*!< 16-bit Timer0 Interrupt */
1996 TIMER_16_1_IRQn = 42, /*!< 16-bit Timer1 Interrupt */
1997 TIMER_32_0_IRQn = 43, /*!< 32-bit Timer0 Interrupt */
1998 TIMER_32_1_IRQn = 44, /*!< 32-bit Timer1 Interrupt */
1999 SSP_IRQn = 45, /*!< SSP Interrupt */
2000 UART_IRQn = 46, /*!< UART Interrupt */
2001 USB_IRQn = 47, /*!< USB Regular Interrupt */
2002 USB_FIQn = 48, /*!< USB Fast Interrupt */
2003 ADC_IRQn = 49, /*!< A/D Converter Interrupt */
2004 WDT_IRQn = 50, /*!< Watchdog timer Interrupt */
2005 BOD_IRQn = 51, /*!< Brown Out Detect(BOD) Interrupt */
2006 EINT3_IRQn = 53, /*!< External Interrupt 3 Interrupt */
2007 EINT2_IRQn = 54, /*!< External Interrupt 2 Interrupt */
2008 EINT1_IRQn = 55, /*!< External Interrupt 1 Interrupt */
2009 EINT0_IRQn = 56, /*!< External Interrupt 0 Interrupt */
2010 } IRQn_t;
2011
2012 static inline void NVIC_EnableIRQ(IRQn_t IRQn)
2013 {
2014 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
2015 }
2016
2017 static inline void NVIC_DisableIRQ(IRQn_t IRQn)
2018 {
2019 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
2020 }
2021
2022 /*##############################################################################
2023 ## GPIO - General Purpose I/O
2024 ##############################################################################*/
2025
2026 #define GPIO_GPIO0_BASE (0x50000000)
2027 #define GPIO_GPIO1_BASE (0x50010000)
2028 #define GPIO_GPIO2_BASE (0x50020000)
2029 #define GPIO_GPIO3_BASE (0x50030000)
2030
2031 #define GPIO_GPIO0DATA (*(pREG32 (0x50003FFC))) // Port data register
2032 #define GPIO_GPIO0DIR (*(pREG32 (0x50008000))) // Data direction register
2033 #define GPIO_GPIO0IS (*(pREG32 (0x50008004))) // Interrupt sense register
2034 #define GPIO_GPIO0IBE (*(pREG32 (0x50008008))) // Interrupt both edges register
2035 #define GPIO_GPIO0IEV (*(pREG32 (0x5000800C))) // Interrupt event register
2036 #define GPIO_GPIO0IE (*(pREG32 (0x50008010))) // Interrupt mask register
2037 #define GPIO_GPIO0RIS (*(pREG32 (0x50008014))) // Raw interrupt status register
2038 #define GPIO_GPIO0MIS (*(pREG32 (0x50008018))) // Masked interrupt status register
2039 #define GPIO_GPIO0IC (*(pREG32 (0x5000801C))) // Interrupt clear register
2040
2041 #define GPIO_GPIO1DATA (*(pREG32 (0x50013FFC))) // Port data register
2042 #define GPIO_GPIO1DIR (*(pREG32 (0x50018000))) // Data direction register
2043 #define GPIO_GPIO1IS (*(pREG32 (0x50018004))) // Interrupt sense register
2044 #define GPIO_GPIO1IBE (*(pREG32 (0x50018008))) // Interrupt both edges register
2045 #define GPIO_GPIO1IEV (*(pREG32 (0x5001800C))) // Interrupt event register
2046 #define GPIO_GPIO1IE (*(pREG32 (0x50018010))) // Interrupt mask register
2047 #define GPIO_GPIO1RIS (*(pREG32 (0x50018014))) // Raw interrupt status register
2048 #define GPIO_GPIO1MIS (*(pREG32 (0x50018018))) // Masked interrupt status register
2049 #define GPIO_GPIO1IC (*(pREG32 (0x5001801C))) // Interrupt clear register
2050
2051 #define GPIO_GPIO2DATA (*(pREG32 (0x50023FFC))) // Port data register
2052 #define GPIO_GPIO2DIR (*(pREG32 (0x50028000))) // Data direction register
2053 #define GPIO_GPIO2IS (*(pREG32 (0x50028004))) // Interrupt sense register
2054 #define GPIO_GPIO2IBE (*(pREG32 (0x50028008))) // Interrupt both edges register
2055 #define GPIO_GPIO2IEV (*(pREG32 (0x5002800C))) // Interrupt event register
2056 #define GPIO_GPIO2IE (*(pREG32 (0x50028010))) // Interrupt mask register
2057 #define GPIO_GPIO2RIS (*(pREG32 (0x50028014))) // Raw interrupt status register
2058 #define GPIO_GPIO2MIS (*(pREG32 (0x50028018))) // Masked interrupt status register
2059 #define GPIO_GPIO2IC (*(pREG32 (0x5002801C))) // Interrupt clear register
2060
2061 #define GPIO_GPIO3DATA (*(pREG32 (0x50033FFC))) // Port data register
2062 #define GPIO_GPIO3DIR (*(pREG32 (0x50038000))) // Data direction register
2063 #define GPIO_GPIO3IS (*(pREG32 (0x50038004))) // Interrupt sense register
2064 #define GPIO_GPIO3IBE (*(pREG32 (0x50038008))) // Interrupt both edges register
2065 #define GPIO_GPIO3IEV (*(pREG32 (0x5003800C))) // Interrupt event register
2066 #define GPIO_GPIO3IE (*(pREG32 (0x50038010))) // Interrupt mask register
2067 #define GPIO_GPIO3RIS (*(pREG32 (0x50038014))) // Raw interrupt status register
2068 #define GPIO_GPIO3MIS (*(pREG32 (0x50038018))) // Masked interrupt status register
2069 #define GPIO_GPIO3IC (*(pREG32 (0x5003801C))) // Interrupt clear register
2070
2071 #define GPIO_IO_P0 ((unsigned int) 0x00000001)
2072 #define GPIO_IO_P1 ((unsigned int) 0x00000002)
2073 #define GPIO_IO_P2 ((unsigned int) 0x00000004)
2074 #define GPIO_IO_P3 ((unsigned int) 0x00000008)
2075 #define GPIO_IO_P4 ((unsigned int) 0x00000010)
2076 #define GPIO_IO_P5 ((unsigned int) 0x00000020)
2077 #define GPIO_IO_P6 ((unsigned int) 0x00000040)
2078 #define GPIO_IO_P7 ((unsigned int) 0x00000080)
2079 #define GPIO_IO_P8 ((unsigned int) 0x00000100)
2080 #define GPIO_IO_P9 ((unsigned int) 0x00000200)
2081 #define GPIO_IO_P10 ((unsigned int) 0x00000400)
2082 #define GPIO_IO_P11 ((unsigned int) 0x00000800)
2083 #define GPIO_IO_ALL ((unsigned int) 0x00000FFF)
2084
2085 /*##############################################################################
2086 ## USB
2087 ##############################################################################*/
2088
2089 /* USB registers are defined in USB code */
2090 #define USB_BASE_ADDRESS (0x40020000)
2091
2092 /* USB Device Interrupt Status Register */
2093 #define USB_DEVINTST (*(pREG32 (0x40020000)))
2094 #define USB_DEVINTST_FRAME_MASK ((unsigned int) 0x00000001)
2095 #define USB_DEVINTST_FRAME ((unsigned int) 0x00000001) // Frame interrupt
2096 #define USB_DEVINTST_EP0_MASK ((unsigned int) 0x00000002)
2097 #define USB_DEVINTST_EP0 ((unsigned int) 0x00000002) // USB core interrupt for EP0
2098 #define USB_DEVINTST_EP1_MASK ((unsigned int) 0x00000004)
2099 #define USB_DEVINTST_EP1 ((unsigned int) 0x00000004) // USB core interrupt for EP1
2100 #define USB_DEVINTST_EP2_MASK ((unsigned int) 0x00000008)
2101 #define USB_DEVINTST_EP2 ((unsigned int) 0x00000008) // USB core interrupt for EP2
2102 #define USB_DEVINTST_EP3_MASK ((unsigned int) 0x00000010)
2103 #define USB_DEVINTST_EP3 ((unsigned int) 0x00000010) // USB core interrupt for EP3
2104 #define USB_DEVINTST_EP4_MASK ((unsigned int) 0x00000020)
2105 #define USB_DEVINTST_EP4 ((unsigned int) 0x00000020) // USB core interrupt for EP4
2106 #define USB_DEVINTST_EP5_MASK ((unsigned int) 0x00000040)
2107 #define USB_DEVINTST_EP5 ((unsigned int) 0x00000040) // USB core interrupt for EP5
2108 #define USB_DEVINTST_EP6_MASK ((unsigned int) 0x00000080)
2109 #define USB_DEVINTST_EP6 ((unsigned int) 0x00000080) // USB core interrupt for EP6
2110 #define USB_DEVINTST_EP7_MASK ((unsigned int) 0x00000100)
2111 #define USB_DEVINTST_EP7 ((unsigned int) 0x00000100) // USB core interrupt for EP7
2112 #define USB_DEVINTST_DEV_STAT_MASK ((unsigned int) 0x00000200)
2113 #define USB_DEVINTST_DEV_STAT ((unsigned int) 0x00000200)
2114 #define USB_DEVINTST_CC_EMPTY_MASK ((unsigned int) 0x00000400)
2115 #define USB_DEVINTST_CC_EMPTY ((unsigned int) 0x00000400)
2116 #define USB_DEVINTST_CD_FULL_MASK ((unsigned int) 0x00000800)
2117 #define USB_DEVINTST_CD_FULL ((unsigned int) 0x00000800)
2118 #define USB_DEVINTST_RxENDPKT_MASK ((unsigned int) 0x00001000)
2119 #define USB_DEVINTST_RxENDPKT ((unsigned int) 0x00001000)
2120 #define USB_DEVINTST_TxENDPKT_MASK ((unsigned int) 0x00002000)
2121 #define USB_DEVINTST_TxENDPKT ((unsigned int) 0x00002000)
2122
2123 /* USB Device Interrupt Enable Register */
2124 #define USB_DEVINTEN (*(pREG32 (0x40020004)))
2125 #define USB_DEVINTEN_FRAME_MASK ((unsigned int) 0x00000001)
2126 #define USB_DEVINTEN_FRAME ((unsigned int) 0x00000001)
2127 #define USB_DEVINTEN_EP0_MASK ((unsigned int) 0x00000002)
2128 #define USB_DEVINTEN_EP0 ((unsigned int) 0x00000002)
2129 #define USB_DEVINTEN_EP1_MASK ((unsigned int) 0x00000004)
2130 #define USB_DEVINTEN_EP1 ((unsigned int) 0x00000004)
2131 #define USB_DEVINTEN_EP2_MASK ((unsigned int) 0x00000008)
2132 #define USB_DEVINTEN_EP2 ((unsigned int) 0x00000008)
2133 #define USB_DEVINTEN_EP3_MASK ((unsigned int) 0x00000010)
2134 #define USB_DEVINTEN_EP3 ((unsigned int) 0x00000010)
2135 #define USB_DEVINTEN_EP4_MASK ((unsigned int) 0x00000020)
2136 #define USB_DEVINTEN_EP4 ((unsigned int) 0x00000020)
2137 #define USB_DEVINTEN_EP5_MASK ((unsigned int) 0x00000040)
2138 #define USB_DEVINTEN_EP5 ((unsigned int) 0x00000040)
2139 #define USB_DEVINTEN_EP6_MASK ((unsigned int) 0x00000080)
2140 #define USB_DEVINTEN_EP6 ((unsigned int) 0x00000080)
2141 #define USB_DEVINTEN_EP7_MASK ((unsigned int) 0x00000100)
2142 #define USB_DEVINTEN_EP7 ((unsigned int) 0x00000100)
2143 #define USB_DEVINTEN_DEV_STAT_MASK ((unsigned int) 0x00000200)
2144 #define USB_DEVINTEN_DEV_STAT ((unsigned int) 0x00000200)
2145 #define USB_DEVINTEN_CC_EMPTY_MASK ((unsigned int) 0x00000400)
2146 #define USB_DEVINTEN_CC_EMPTY ((unsigned int) 0x00000400)
2147 #define USB_DEVINTEN_CD_FULL_MASK ((unsigned int) 0x00000800)
2148 #define USB_DEVINTEN_CD_FULL ((unsigned int) 0x00000800)
2149 #define USB_DEVINTEN_RxENDPKT_MASK ((unsigned int) 0x00001000)
2150 #define USB_DEVINTEN_RxENDPKT ((unsigned int) 0x00001000)
2151 #define USB_DEVINTEN_TxENDPKT_MASK ((unsigned int) 0x00002000)
2152 #define USB_DEVINTEN_TxENDPKT ((unsigned int) 0x00002000)
2153
2154 /* USB Device Interrupt Clear Register */
2155 #define USB_DEVINTCLR (*(pREG32 (0x40020008)))
2156 #define USB_DEVINTCLR_FRAME_MASK ((unsigned int) 0x00000001)
2157 #define USB_DEVINTCLR_FRAME ((unsigned int) 0x00000001)
2158 #define USB_DEVINTCLR_EP0_MASK ((unsigned int) 0x00000002)
2159 #define USB_DEVINTCLR_EP0 ((unsigned int) 0x00000002)
2160 #define USB_DEVINTCLR_EP1_MASK ((unsigned int) 0x00000004)
2161 #define USB_DEVINTCLR_EP1 ((unsigned int) 0x00000004)
2162 #define USB_DEVINTCLR_EP2_MASK ((unsigned int) 0x00000008)
2163 #define USB_DEVINTCLR_EP2 ((unsigned int) 0x00000008)
2164 #define USB_DEVINTCLR_EP3_MASK ((unsigned int) 0x00000010)
2165 #define USB_DEVINTCLR_EP3 ((unsigned int) 0x00000010)
2166 #define USB_DEVINTCLR_EP4_MASK ((unsigned int) 0x00000020)
2167 #define USB_DEVINTCLR_EP4 ((unsigned int) 0x00000020)
2168 #define USB_DEVINTCLR_EP5_MASK ((unsigned int) 0x00000040)
2169 #define USB_DEVINTCLR_EP5 ((unsigned int) 0x00000040)
2170 #define USB_DEVINTCLR_EP6_MASK ((unsigned int) 0x00000080)
2171 #define USB_DEVINTCLR_EP6 ((unsigned int) 0x00000080)
2172 #define USB_DEVINTCLR_EP7_MASK ((unsigned int) 0x00000100)
2173 #define USB_DEVINTCLR_EP7 ((unsigned int) 0x00000100)
2174 #define USB_DEVINTCLR_DEV_STAT_MASK ((unsigned int) 0x00000200)
2175 #define USB_DEVINTCLR_DEV_STAT ((unsigned int) 0x00000200)
2176 #define USB_DEVINTCLR_CC_EMPTY_MASK ((unsigned int) 0x00000400)
2177 #define USB_DEVINTCLR_CC_EMPTY ((unsigned int) 0x00000400)
2178 #define USB_DEVINTCLR_CD_FULL_MASK ((unsigned int) 0x00000800)
2179 #define USB_DEVINTCLR_CD_FULL ((unsigned int) 0x00000800)
2180 #define USB_DEVINTCLR_RxENDPKT_MASK ((unsigned int) 0x00001000)
2181 #define USB_DEVINTCLR_RxENDPKT ((unsigned int) 0x00001000)
2182 #define USB_DEVINTCLR_TxENDPKT_MASK ((unsigned int) 0x00002000)
2183 #define USB_DEVINTCLR_TxENDPKT ((unsigned int) 0x00002000)
2184
2185 /* USB Device Interrupt Set Register */
2186 #define USB_DEVINTSET (*(pREG32 (0x4002000C)))
2187 #define USB_DEVINTSET_FRAME_MASK ((unsigned int) 0x00000001)
2188 #define USB_DEVINTSET_FRAME ((unsigned int) 0x00000001)
2189 #define USB_DEVINTSET_EP0_MASK ((unsigned int) 0x00000002)
2190 #define USB_DEVINTSET_EP0 ((unsigned int) 0x00000002)
2191 #define USB_DEVINTSET_EP1_MASK ((unsigned int) 0x00000004)
2192 #define USB_DEVINTSET_EP1 ((unsigned int) 0x00000004)
2193 #define USB_DEVINTSET_EP2_MASK ((unsigned int) 0x00000008)
2194 #define USB_DEVINTSET_EP2 ((unsigned int) 0x00000008)
2195 #define USB_DEVINTSET_EP3_MASK ((unsigned int) 0x00000010)
2196 #define USB_DEVINTSET_EP3 ((unsigned int) 0x00000010)
2197 #define USB_DEVINTSET_EP4_MASK ((unsigned int) 0x00000020)
2198 #define USB_DEVINTSET_EP4 ((unsigned int) 0x00000020)
2199 #define USB_DEVINTSET_EP5_MASK ((unsigned int) 0x00000040)
2200 #define USB_DEVINTSET_EP5 ((unsigned int) 0x00000040)
2201 #define USB_DEVINTSET_EP6_MASK ((unsigned int) 0x00000080)
2202 #define USB_DEVINTSET_EP6 ((unsigned int) 0x00000080)
2203 #define USB_DEVINTSET_EP7_MASK ((unsigned int) 0x00000100)
2204 #define USB_DEVINTSET_EP7 ((unsigned int) 0x00000100)
2205 #define USB_DEVINTSET_DEV_STAT_MASK ((unsigned int) 0x00000200)
2206 #define USB_DEVINTSET_DEV_STAT ((unsigned int) 0x00000200)
2207 #define USB_DEVINTSET_CC_EMPTY_MASK ((unsigned int) 0x00000400)
2208 #define USB_DEVINTSET_CC_EMPTY ((unsigned int) 0x00000400)
2209 #define USB_DEVINTSET_CD_FULL_MASK ((unsigned int) 0x00000800)
2210 #define USB_DEVINTSET_CD_FULL ((unsigned int) 0x00000800)
2211 #define USB_DEVINTSET_RxENDPKT_MASK ((unsigned int) 0x00001000)
2212 #define USB_DEVINTSET_RxENDPKT ((unsigned int) 0x00001000)
2213 #define USB_DEVINTSET_TxENDPKT_MASK ((unsigned int) 0x00002000)
2214 #define USB_DEVINTSET_TxENDPKT ((unsigned int) 0x00002000)
2215
2216 /* USB Command Code Register */
2217 #define USB_CMDCODE (*(pREG32 (0x40020010)))
2218 #define USB_CMDCODE_CMD_PHASE_WRITE ((unsigned int) 0x00000100)
2219 #define USB_CMDCODE_CMD_PHASE_READ ((unsigned int) 0x00000200)
2220 #define USB_CMDCODE_CMD_PHASE_COMMAND ((unsigned int) 0x00000500)
2221 #define USB_CMDCODE_CMD_PHASE_MASK ((unsigned int) 0x0000FF00)
2222 #define USB_CMDCODE_CMD_CODE_MASK ((unsigned int) 0x00FF0000)
2223 #define USB_CMDCODE_CMD_WDATA_MASK ((unsigned int) 0x00FF0000)
2224
2225 /* USB Command Data Register */
2226 #define USB_CMDDATA (*(pREG32 (0x40020014)))
2227 #define USB_CMDDATA_CMD_RDATA_MASK ((unsigned int) 0x000000FF)
2228
2229 /* USB Receive Data Register */
2230 #define USB_RXDATA (*(pREG32 (0x40020018)))
2231
2232 /* USB Transmit Data Register */
2233 #define USB_TXDATA (*(pREG32 (0x4002001C)))
2234
2235 /* USB Receive Packet Length Register */
2236 #define USB_RXPLEN (*(pREG32 (0x40020020)))
2237 #define USB_RXPLEN_PKT_LNGTH_MASK ((unsigned int) 0x000003FF)
2238 #define USB_RXPLEN_DV_MASK ((unsigned int) 0x00000400)
2239 #define USB_RXPLEN_DV ((unsigned int) 0x00000400)
2240
2241 /* USB Transmit Packet Length Register */
2242 #define USB_TXPLEN (*(pREG32 (0x40020024)))
2243 #define USB_TXPLEN_PKT_LNGTH_MASK 0x3FF
2244
2245 /* USB Control Register */
2246 #define USB_CTRL (*(pREG32 (0x40020028)))
2247 #define USB_CTRL_RD_EN_MASK ((unsigned int) 0x00000001)
2248 #define USB_CTRL_RD_EN ((unsigned int) 0x00000001)
2249 #define USB_CTRL_WR_EN_MASK ((unsigned int) 0x00000002)
2250 #define USB_CTRL_WR_EN ((unsigned int) 0x00000002)
2251 #define USB_CTRL_LOG_ENDPOINT_MASK ((unsigned int) 0x0000003C)
2252
2253 /* USB Device FIQ Select Register */
2254 #define USB_DEVFIQSEL (*(pREG32 (0x4002002C)))
2255 #define USB_DEVFIQSEL_FRAME_MASK ((unsigned int) 0x00000001)
2256 #define USB_DEVFIQSEL_FRAME ((unsigned int) 0x00000001)
2257 #define USB_DEVFIQSEL_BULKOUT_MASK ((unsigned int) 0x00000002)
2258 #define USB_DEVFIQSEL_BULKOUT ((unsigned int) 0x00000002)
2259 #define USB_DEVFIQSEL_BULKIN_MASK ((unsigned int) 0x00000004)
2260 #define USB_DEVFIQSEL_BULKIN ((unsigned int) 0x00000004)
2261
2262 /*##############################################################################
2263 ## UART
2264 ##############################################################################*/
2265
2266 #define UART_BASE_ADDRESS (0x40008000)
2267
2268 #define UART_U0RBR (*(pREG32 (0x40008000))) // Receive buffer
2269 #define UART_U0THR (*(pREG32 (0x40008000))) // Transmitter holding register
2270 #define UART_U0DLL (*(pREG32 (0x40008000))) // Divisor latch LSB
2271 #define UART_U0DLM (*(pREG32 (0x40008004))) // Divisor latch MSB
2272 #define UART_U0IER (*(pREG32 (0x40008004))) // Interrupt enable
2273 #define UART_U0IIR (*(pREG32 (0x40008008))) // Interrupt identification
2274 #define UART_U0FCR (*(pREG32 (0x40008008))) // FIFO control
2275 #define UART_U0MCR (*(pREG32 (0x40008010))) // Modem control
2276 #define UART_U0LCR (*(pREG32 (0x4000800C))) // Line control
2277 #define UART_U0LSR (*(pREG32 (0x40008014))) // Line status
2278 #define UART_U0MSR (*(pREG32 (0x40008018))) // Modem status
2279 #define UART_U0SCR (*(pREG32 (0x4000801C))) // Scratch pad
2280 #define UART_U0ACR (*(pREG32 (0x40008020))) // Auto-baud control
2281 #define UART_U0FDR (*(pREG32 (0x40008028))) // Fractional divider
2282 #define UART_U0TER (*(pREG32 (0x40008030))) // Transmit enable
2283 #define UART_U0RS485CTRL (*(pREG32 (0x4000804C))) // RS485 control register
2284 #define UART_U0RS485ADRMATCH (*(pREG32 (0x40008050))) // RS485 address match
2285 #define UART_U0RS485DLY (*(pREG32 (0x40008054))) // RS485 Delay value
2286 #define UART_U0FIFOLVL (*(pREG32 (0x40008058))) // UART FIFO level
2287
2288 #define UART_U0RBR_MASK ((unsigned int) 0x000000FF)
2289
2290 #define UART_U0IER_RBR_Interrupt_MASK ((unsigned int) 0x00000001) // Enables the received data available interrupt
2291 #define UART_U0IER_RBR_Interrupt_Enabled ((unsigned int) 0x00000001)
2292 #define UART_U0IER_RBR_Interrupt_Disabled ((unsigned int) 0x00000000)
2293 #define UART_U0IER_THRE_Interrupt_MASK ((unsigned int) 0x00000002) // Enables the THRE interrupt
2294 #define UART_U0IER_THRE_Interrupt_Enabled ((unsigned int) 0x00000002)
2295 #define UART_U0IER_THRE_Interrupt_Disabled ((unsigned int) 0x00000000)
2296 #define UART_U0IER_RLS_Interrupt_MASK ((unsigned int) 0x00000004) // Enables the Rx line status interrupt
2297 #define UART_U0IER_RLS_Interrupt_Enabled ((unsigned int) 0x00000004)
2298 #define UART_U0IER_RLS_Interrupt_Disabled ((unsigned int) 0x00000000)
2299 #define UART_U0IER_ABEOIntEn_MASK ((unsigned int) 0x00000100) // End of auto-baud interrupt
2300 #define UART_U0IER_ABEOIntEn_Enabled ((unsigned int) 0x00000100)
2301 #define UART_U0IER_ABEOIntEn_Disabled ((unsigned int) 0x00000000)
2302 #define UART_U0IER_ABTOIntEn_MASK ((unsigned int) 0x00000200) // Auto-baud timeout interrupt
2303 #define UART_U0IER_ABTOIntEn_Enabled ((unsigned int) 0x00000200)
2304 #define UART_U0IER_ABTOIntEn_Disabled ((unsigned int) 0x00000000)
2305
2306 #define UART_U0IIR_IntStatus_MASK ((unsigned int) 0x00000001) // Interrupt status
2307 #define UART_U0IIR_IntStatus_InterruptPending ((unsigned int) 0x00000001)
2308 #define UART_U0IIR_IntStatus_NoInterruptPending ((unsigned int) 0x00000000)
2309 #define UART_U0IIR_IntId_MASK ((unsigned int) 0x0000000E) // Interrupt identification
2310 #define UART_U0IIR_IntId_RLS ((unsigned int) 0x00000006) // Receive line status
2311 #define UART_U0IIR_IntId_RDA ((unsigned int) 0x00000004) // Receive data available
2312 #define UART_U0IIR_IntId_CTI ((unsigned int) 0x0000000C) // Character time-out indicator
2313 #define UART_U0IIR_IntId_THRE ((unsigned int) 0x00000002) // THRE interrupt
2314 #define UART_U0IIR_IntId_MODEM ((unsigned int) 0x00000000) // Modem interrupt
2315 #define UART_U0IIR_FIFO_Enable_MASK ((unsigned int) 0x000000C0)
2316 #define UART_U0IIR_ABEOInt_MASK ((unsigned int) 0x00000100) // End of auto-baud interrupt
2317 #define UART_U0IIR_ABEOInt ((unsigned int) 0x00000100)
2318 #define UART_U0IIR_ABTOInt_MASK ((unsigned int) 0x00000200) // Auto-baud time-out interrupt
2319 #define UART_U0IIR_ABTOInt ((unsigned int) 0x00000200)
2320
2321 #define UART_U0FCR_FIFO_Enable_MASK ((unsigned int) 0x00000001) // UART FIFOs enabled/disabled
2322 #define UART_U0FCR_FIFO_Enabled ((unsigned int) 0x00000001)
2323 #define UART_U0FCR_FIFO_Disabled ((unsigned int) 0x00000000)
2324 #define UART_U0FCR_Rx_FIFO_Reset_MASK ((unsigned int) 0x00000002)
2325 #define UART_U0FCR_Rx_FIFO_Reset ((unsigned int) 0x00000002) // Clear Rx FIFO
2326 #define UART_U0FCR_Tx_FIFO_Reset_MASK ((unsigned int) 0x00000004)
2327 #define UART_U0FCR_Tx_FIFO_Reset ((unsigned int) 0x00000004) // Clear Tx FIFO
2328 #define UART_U0FCR_Rx_Trigger_Level_Select_MASK ((unsigned int) 0x000000C0) // Chars written before before interrupt
2329 #define UART_U0FCR_Rx_Trigger_Level_Select_1Char ((unsigned int) 0x00000000)
2330 #define UART_U0FCR_Rx_Trigger_Level_Select_4Char ((unsigned int) 0x00000040)
2331 #define UART_U0FCR_Rx_Trigger_Level_Select_8Char ((unsigned int) 0x00000080)
2332 #define UART_U0FCR_Rx_Trigger_Level_Select_12Char ((unsigned int) 0x000000C0)
2333
2334 #define UART_U0MCR_DTR_Control_MASK ((unsigned int) 0x00000001) // Source for modem output pin DTR
2335 #define UART_U0MCR_DTR_Control ((unsigned int) 0x00000001)
2336 #define UART_U0MCR_RTS_Control_MASK ((unsigned int) 0x00000002) // Source for modem output pin RTS
2337 #define UART_U0MCR_RTS_Control ((unsigned int) 0x00000002)
2338 #define UART_U0MCR_Loopback_Mode_Select_MASK ((unsigned int) 0x00000010) // Diagnostic loopback mode
2339 #define UART_U0MCR_Loopback_Mode_Select_Enabled ((unsigned int) 0x00000010)
2340 #define UART_U0MCR_Loopback_Mode_Select_Disabled ((unsigned int) 0x00000000)
2341 #define UART_U0MCR_RTSen_MASK ((unsigned int) 0x00000040) // Disable auto-rts flow control
2342 #define UART_U0MCR_RTSen_Enabled ((unsigned int) 0x00000040)
2343 #define UART_U0MCR_RTSen_Disabled ((unsigned int) 0x00000000)
2344 #define UART_U0MCR_CTSen_MASK ((unsigned int) 0x00000080) // Disable auto-cts flow control
2345 #define UART_U0MCR_CTSen_Enabled ((unsigned int) 0x00000080)
2346 #define UART_U0MCR_CTSen_Disabled ((unsigned int) 0x00000000)
2347
2348 #define UART_U0LCR_Word_Length_Select_MASK ((unsigned int) 0x00000003) // Word Length Selector
2349 #define UART_U0LCR_Word_Length_Select_5Chars ((unsigned int) 0x00000000)
2350 #define UART_U0LCR_Word_Length_Select_6Chars ((unsigned int) 0x00000001)
2351 #define UART_U0LCR_Word_Length_Select_7Chars ((unsigned int) 0x00000002)
2352 #define UART_U0LCR_Word_Length_Select_8Chars ((unsigned int) 0x00000003)
2353 #define UART_U0LCR_Stop_Bit_Select_MASK ((unsigned int) 0x00000004) // Stop bit select
2354 #define UART_U0LCR_Stop_Bit_Select_1Bits ((unsigned int) 0x00000000)
2355 #define UART_U0LCR_Stop_Bit_Select_2Bits ((unsigned int) 0x00000004)
2356 #define UART_U0LCR_Parity_Enable_MASK ((unsigned int) 0x00000008) // Parity enable
2357 #define UART_U0LCR_Parity_Enabled ((unsigned int) 0x00000008)
2358 #define UART_U0LCR_Parity_Disabled ((unsigned int) 0x00000000)
2359 #define UART_U0LCR_Parity_Select_MASK ((unsigned int) 0x00000030) // Parity select
2360 #define UART_U0LCR_Parity_Select_OddParity ((unsigned int) 0x00000000)
2361 #define UART_U0LCR_Parity_Select_EvenParity ((unsigned int) 0x00000010)
2362 #define UART_U0LCR_Parity_Select_Forced1 ((unsigned int) 0x00000020)
2363 #define UART_U0LCR_Parity_Select_Forced0 ((unsigned int) 0x00000030)
2364 #define UART_U0LCR_Break_Control_MASK ((unsigned int) 0x00000040) // Break transmission control
2365 #define UART_U0LCR_Break_Control_Enabled ((unsigned int) 0x00000040)
2366 #define UART_U0LCR_Break_Control_Disabled ((unsigned int) 0x00000000)
2367 #define UART_U0LCR_Divisor_Latch_Access_MASK ((unsigned int) 0x00000080) // Divisor latch access
2368 #define UART_U0LCR_Divisor_Latch_Access_Enabled ((unsigned int) 0x00000080)
2369 #define UART_U0LCR_Divisor_Latch_Access_Disabled ((unsigned int) 0x00000000)
2370
2371 #define UART_U0LSR_RDR_MASK ((unsigned int) 0x00000001) // Receiver data ready
2372 #define UART_U0LSR_RDR_EMPTY ((unsigned int) 0x00000000) // U0RBR is empty
2373 #define UART_U0LSR_RDR_DATA ((unsigned int) 0x00000001) // U0RBR contains valid data
2374 #define UART_U0LSR_OE_MASK ((unsigned int) 0x00000002) // Overrun error
2375 #define UART_U0LSR_OE ((unsigned int) 0x00000002)
2376 #define UART_U0LSR_PE_MASK ((unsigned int) 0x00000004) // Parity error
2377 #define UART_U0LSR_PE ((unsigned int) 0x00000004)
2378 #define UART_U0LSR_FE_MASK ((unsigned int) 0x00000008) // Framing error
2379 #define UART_U0LSR_FE ((unsigned int) 0x00000008)
2380 #define UART_U0LSR_BI_MASK ((unsigned int) 0x00000010) // Break interrupt
2381 #define UART_U0LSR_BI ((unsigned int) 0x00000010)
2382 #define UART_U0LSR_THRE_MASK ((unsigned int) 0x00000020) // Transmitter holding register empty
2383 #define UART_U0LSR_THRE ((unsigned int) 0x00000020)
2384 #define UART_U0LSR_TEMT_MASK ((unsigned int) 0x00000040) // Transmitter empty
2385 #define UART_U0LSR_TEMT ((unsigned int) 0x00000040)
2386 #define UART_U0LSR_RXFE_MASK ((unsigned int) 0x00000080) // Error in Rx FIFO
2387 #define UART_U0LSR_RXFE ((unsigned int) 0x00000080)
2388
2389 #define UART_U0MSR_Delta_CTS_MASK ((unsigned int) 0x00000001) // State change of input CTS
2390 #define UART_U0MSR_Delta_CTS ((unsigned int) 0x00000001)
2391 #define UART_U0MSR_Delta_DSR_MASK ((unsigned int) 0x00000002) // State change of input DSR
2392 #define UART_U0MSR_Delta_DSR ((unsigned int) 0x00000002)
2393 #define UART_U0MSR_Trailing_Edge_RI_MASK ((unsigned int) 0x00000004) // Low to high transition of input RI
2394 #define UART_U0MSR_Trailing_Edge_RI ((unsigned int) 0x00000004)
2395 #define UART_U0MSR_Delta_DCD_MASK ((unsigned int) 0x00000008) // State change of input DCD
2396 #define UART_U0MSR_Delta_DCD ((unsigned int) 0x00000008)
2397 #define UART_U0MSR_CTS_MASK ((unsigned int) 0x00000010) // Clear to send state
2398 #define UART_U0MSR_CTS ((unsigned int) 0x00000010)
2399 #define UART_U0MSR_DSR_MASK ((unsigned int) 0x00000020) // Data set ready state
2400 #define UART_U0MSR_DSR ((unsigned int) 0x00000020)
2401 #define UART_U0MSR_RI_MASK ((unsigned int) 0x00000040) // Ring indicator state
2402 #define UART_U0MSR_RI ((unsigned int) 0x00000040)
2403 #define UART_U0MSR_DCD_MASK ((unsigned int) 0x00000080) // Data carrier detect state
2404 #define UART_U0MSR_DCD ((unsigned int) 0x00000080)
2405
2406 #define UART_U0ACR_Start_MASK ((unsigned int) 0x00000001) // Auto-baud start/stop
2407 #define UART_U0ACR_Start ((unsigned int) 0x00000001)
2408 #define UART_U0ACR_Stop ((unsigned int) 0x00000000)
2409 #define UART_U0ACR_Mode_MASK ((unsigned int) 0x00000002) // Auto-baud mode select
2410 #define UART_U0ACR_Mode_Mode1 ((unsigned int) 0x00000000)
2411 #define UART_U0ACR_Mode_Mode2 ((unsigned int) 0x00000002)
2412 #define UART_U0ACR_AutoRestart_MASK ((unsigned int) 0x00000004)
2413 #define UART_U0ACR_AutoRestart_NoRestart ((unsigned int) 0x00000000)
2414 #define UART_U0ACR_AutoRestart_Restart ((unsigned int) 0x00000004) // Restart in case of time-out
2415 #define UART_U0ACR_ABEOIntClr_MASK ((unsigned int) 0x00000100) // End of auto-baud interrupt clear bit
2416 #define UART_U0ACR_ABEOIntClr ((unsigned int) 0x00000100)
2417 #define UART_U0ACR_ABTOIntClr_MASK ((unsigned int) 0x00000200) // Auto-baud timeout interrupt clear bit
2418 #define UART_U0ACR_ABTOIntClr ((unsigned int) 0x00000200)
2419
2420 #define UART_U0FDR_DIVADDVAL_MASK ((unsigned int) 0x0000000F) // Fractional divider: prescaler register
2421 #define UART_U0FDR_MULVAL_MASK ((unsigned int) 0x000000F0) // Fractional divider: prescaler multiplier
2422
2423 #define UART_U0TER_TXEN_MASK ((unsigned int) 0x00000080) // UART transmit enable
2424 #define UART_U0TER_TXEN_Enabled ((unsigned int) 0x00000080)
2425 #define UART_U0TER_TXEN_Disabled ((unsigned int) 0x00000000)
2426
2427 #define UART_U0RS485CTRL_NMMEN_MASK ((unsigned int) 0x00000001) // Normal multi-drop mode
2428 #define UART_U0RS485CTRL_NMMEN ((unsigned int) 0x00000001)
2429 #define UART_U0RS485CTRL_RXDIS_MASK ((unsigned int) 0x00000002) // Receiver
2430 #define UART_U0RS485CTRL_RXDIS ((unsigned int) 0x00000002)
2431 #define UART_U0RS485CTRL_AADEN_MASK ((unsigned int) 0x00000004) // Auto-address detect
2432 #define UART_U0RS485CTRL_AADEN ((unsigned int) 0x00000004)
2433 #define UART_U0RS485CTRL_SEL_MASK ((unsigned int) 0x00000008)
2434 #define UART_U0RS485CTRL_SEL_RTS ((unsigned int) 0x00000000) // Use RTS for direction control
2435 #define UART_U0RS485CTRL_SEL_DTS ((unsigned int) 0x00000008) // Use DTS for direction control
2436 #define UART_U0RS485CTRL_DCTRL_MASK ((unsigned int) 0x00000010) // Enable/Disable auto-direction control
2437 #define UART_U0RS485CTRL_DCTRL_Disabled ((unsigned int) 0x00000000)
2438 #define UART_U0RS485CTRL_DCTRL_Enabled ((unsigned int) 0x00000010)
2439 #define UART_U0RS485CTRL_OINV_MASK ((unsigned int) 0x00000020) // Reverse polarity of direction control signal on RTS/DTR pin
2440 #define UART_U0RS485CTRL_OINV_Normal ((unsigned int) 0x00000000)
2441 #define UART_U0RS485CTRL_OINV_Inverted ((unsigned int) 0x00000020)
2442
2443 #define UART_U0FIFOLVL_RXFIFOLVL_MASK ((unsigned int) 0x0000000F)
2444 #define UART_U0FIFOLVL_RXFIFOLVL_Empty ((unsigned int) 0x00000000)
2445 #define UART_U0FIFOLVL_RXFIFOLVL_Full ((unsigned int) 0x0000000F)
2446 #define UART_U0FIFOLVL_TXFIFOLVL_MASK ((unsigned int) 0x00000F00)
2447 #define UART_U0FIFOLVL_TXFIFOLVL_Empty ((unsigned int) 0x00000000)
2448 #define UART_U0FIFOLVL_TXFIFOLVL_Full ((unsigned int) 0x00000F00)
2449
2450 /*##############################################################################
2451 ## SSP - Synchronous Serial Port
2452 ##############################################################################*/
2453
2454 #define SSP_SSP0_BASE_ADDRESS (0x40040000)
2455
2456 #define SSP_SSP0CR0 (*(pREG32 (0x40040000))) // Control register 0
2457 #define SSP_SSP0CR1 (*(pREG32 (0x40040004))) // Control register 1
2458 #define SSP_SSP0DR (*(pREG32 (0x40040008))) // Data register
2459 #define SSP_SSP0SR (*(pREG32 (0x4004000C))) // Status register
2460 #define SSP_SSP0CPSR (*(pREG32 (0x40040010))) // Clock prescale register
2461 #define SSP_SSP0IMSC (*(pREG32 (0x40040014))) // Interrupt mask set/clear register
2462 #define SSP_SSP0RIS (*(pREG32 (0x40040018))) // Raw interrupt status register
2463 #define SSP_SSP0MIS (*(pREG32 (0x4004001C))) // Masked interrupt status register
2464 #define SSP_SSP0ICR (*(pREG32 (0x40040020))) // SSPICR interrupt clear register
2465
2466 /* SSP0CR0 (SSP0 Control Register 0)
2467 This register controls the basic operation of the SSP controller. */
2468
2469 #define SSP_SSP0CR0_DSS_MASK ((unsigned int) 0x0000000F) // Data size select
2470 #define SSP_SSP0CR0_DSS_4BIT ((unsigned int) 0x00000003)
2471 #define SSP_SSP0CR0_DSS_5BIT ((unsigned int) 0x00000004)
2472 #define SSP_SSP0CR0_DSS_6BIT ((unsigned int) 0x00000005)
2473 #define SSP_SSP0CR0_DSS_7BIT ((unsigned int) 0x00000006)
2474 #define SSP_SSP0CR0_DSS_8BIT ((unsigned int) 0x00000007)
2475 #define SSP_SSP0CR0_DSS_9BIT ((unsigned int) 0x00000008)
2476 #define SSP_SSP0CR0_DSS_10BIT ((unsigned int) 0x00000009)
2477 #define SSP_SSP0CR0_DSS_11BIT ((unsigned int) 0x0000000A)
2478 #define SSP_SSP0CR0_DSS_12BIT ((unsigned int) 0x0000000B)
2479 #define SSP_SSP0CR0_DSS_13BIT ((unsigned int) 0x0000000C)
2480 #define SSP_SSP0CR0_DSS_14BIT ((unsigned int) 0x0000000D)
2481 #define SSP_SSP0CR0_DSS_15BIT ((unsigned int) 0x0000000E)
2482 #define SSP_SSP0CR0_DSS_16BIT ((unsigned int) 0x0000000F)
2483 #define SSP_SSP0CR0_FRF_MASK ((unsigned int) 0x00000030) // Frame format
2484 #define SSP_SSP0CR0_FRF_SPI ((unsigned int) 0x00000000)
2485 #define SSP_SSP0CR0_FRF_TI ((unsigned int) 0x00000010)
2486 #define SSP_SSP0CR0_FRF_MWIRE ((unsigned int) 0x00000020)
2487 #define SSP_SSP0CR0_CPOL_MASK ((unsigned int) 0x00000040) // Clock out polarity
2488 #define SSP_SSP0CR0_CPOL_LOW ((unsigned int) 0x00000000)
2489 #define SSP_SSP0CR0_CPOL_HIGH ((unsigned int) 0x00000040)
2490 #define SSP_SSP0CR0_CPHA_MASK ((unsigned int) 0x00000080) // Clock out phase
2491 #define SSP_SSP0CR0_CPHA_FIRST ((unsigned int) 0x00000000)
2492 #define SSP_SSP0CR0_CPHA_SECOND ((unsigned int) 0x00000080)
2493
2494 /* Serial Clock Rate. The number of prescaler-output clocks per
2495 bit on the bus, minus one. Given that CPSDVSR is the
2496 prescale divider, and the APB clock PCLK clocks the
2497 prescaler, the bit frequency is PCLK / (CPSDVSR \97 [SCR+1]). */
2498
2499 #define SSP_SSP0CR0_SCR_MASK ((unsigned int) 0x0000FF00) // Serial clock rate
2500 #define SSP_SSP0CR0_SCR_1 ((unsigned int) 0x00000100)
2501 #define SSP_SSP0CR0_SCR_2 ((unsigned int) 0x00000200)
2502 #define SSP_SSP0CR0_SCR_3 ((unsigned int) 0x00000300)
2503 #define SSP_SSP0CR0_SCR_4 ((unsigned int) 0x00000400)
2504 #define SSP_SSP0CR0_SCR_5 ((unsigned int) 0x00000500)
2505 #define SSP_SSP0CR0_SCR_6 ((unsigned int) 0x00000600)
2506 #define SSP_SSP0CR0_SCR_7 ((unsigned int) 0x00000700)
2507 #define SSP_SSP0CR0_SCR_8 ((unsigned int) 0x00000800)
2508 #define SSP_SSP0CR0_SCR_9 ((unsigned int) 0x00000900)
2509 #define SSP_SSP0CR0_SCR_10 ((unsigned int) 0x00000A00)
2510 #define SSP_SSP0CR0_SCR_11 ((unsigned int) 0x00000B00)
2511 #define SSP_SSP0CR0_SCR_12 ((unsigned int) 0x00000C00)
2512 #define SSP_SSP0CR0_SCR_13 ((unsigned int) 0x00000D00)
2513 #define SSP_SSP0CR0_SCR_14 ((unsigned int) 0x00000E00)
2514 #define SSP_SSP0CR0_SCR_15 ((unsigned int) 0x00000F00)
2515 #define SSP_SSP0CR0_SCR_16 ((unsigned int) 0x00001000)
2516
2517 /* SSP0CR1 (SSP0 Control Register 1)
2518 This register controls certain aspects of the operation of the SSP controller. */
2519
2520 #define SSP_SSP0CR1_LBM_MASK ((unsigned int) 0x00000001) // Loop back mode
2521 #define SSP_SSP0CR1_LBM_NORMAL ((unsigned int) 0x00000000)
2522 #define SSP_SSP0CR1_LBM_INVERTED ((unsigned int) 0x00000001) // MISO/MOSI are reversed
2523 #define SSP_SSP0CR1_SSE_MASK ((unsigned int) 0x00000002) // SSP enable
2524 #define SSP_SSP0CR1_SSE_DISABLED ((unsigned int) 0x00000000)
2525 #define SSP_SSP0CR1_SSE_ENABLED ((unsigned int) 0x00000002)
2526 #define SSP_SSP0CR1_MS_MASK ((unsigned int) 0x00000004) // Master/Slave Mode
2527 #define SSP_SSP0CR1_MS_MASTER ((unsigned int) 0x00000000)
2528 #define SSP_SSP0CR1_MS_SLAVE ((unsigned int) 0x00000004)
2529 #define SSP_SSP0CR1_SOD_MASK ((unsigned int) 0x00000008) // Slave output disable
2530
2531 /* SSP0DR (SSP0 Data Register)
2532 Software can write data to be transmitted to this register, and read data that has been
2533 received. */
2534
2535 #define SSP_SSP0DR_MASK ((unsigned int) 0x0000FFFF) // Data
2536
2537 /* SSP0SR (SSP0 Status Register)
2538 This read-only register reflects the current status of the SSP controller. */
2539
2540 #define SSP_SSP0SR_TFE_MASK ((unsigned int) 0x00000001) // Transmit FIFO empty
2541 #define SSP_SSP0SR_TFE_EMPTY ((unsigned int) 0x00000001)
2542 #define SSP_SSP0SR_TFE_NOTEMPTY ((unsigned int) 0x00000000)
2543 #define SSP_SSP0SR_TNF_MASK ((unsigned int) 0x00000002) // Transmit FIFO not full
2544 #define SSP_SSP0SR_TNF_NOTFULL ((unsigned int) 0x00000002)
2545 #define SSP_SSP0SR_TNF_FULL ((unsigned int) 0x00000000)
2546 #define SSP_SSP0SR_RNE_MASK ((unsigned int) 0x00000004) // Receive FIFO not empty
2547 #define SSP_SSP0SR_RNE_NOTEMPTY ((unsigned int) 0x00000004)
2548 #define SSP_SSP0SR_RNE_EMPTY ((unsigned int) 0x00000000)
2549 #define SSP_SSP0SR_RFF_MASK ((unsigned int) 0x00000008) // Receive FIFO full
2550 #define SSP_SSP0SR_RFF_FULL ((unsigned int) 0x00000008)
2551 #define SSP_SSP0SR_RFF_NOTFULL ((unsigned int) 0x00000000)
2552 #define SSP_SSP0SR_BSY_MASK ((unsigned int) 0x00000010) // Busy Flag
2553 #define SSP_SSP0SR_BSY_IDLE ((unsigned int) 0x00000000)
2554 #define SSP_SSP0SR_BSY_BUSY ((unsigned int) 0x00000010)
2555
2556 /* SSP0CPSR (SSP0 Clock Prescale Register)
2557 This register controls the factor by which the Prescaler divides the SSP peripheral clock
2558 SSP_PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in
2559 SSP0CR0, to determine the bit clock. */
2560
2561 #define SSP_SSP0CPSR_CPSDVSR_MASK ((unsigned int) 0x000000FF)
2562 #define SSP_SSP0CPSR_CPSDVSR_DIV2 ((unsigned int) 0x00000002)
2563 #define SSP_SSP0CPSR_CPSDVSR_DIV4 ((unsigned int) 0x00000004)
2564 #define SSP_SSP0CPSR_CPSDVSR_DIV10 ((unsigned int) 0x0000000A)
2565 #define SSP_SSP0CPSR_CPSDVSR_DIV12 ((unsigned int) 0x0000000C)
2566 #define SSP_SSP0CPSR_CPSDVSR_DIV16 ((unsigned int) 0x00000010)
2567 #define SSP_SSP0CPSR_CPSDVSR_DIV20 ((unsigned int) 0x00000014)
2568
2569 /* SSP0IMSC (SSP0 Interrupt Mask Set/Clear Register)
2570 This register controls whether each of the four possible interrupt conditions in the SSP
2571 controller are enabled. Note that ARM uses the word \93masked\94 in the opposite sense from
2572 classic computer terminology, in which \93masked\94 meant \93disabled\94. ARM uses the word
2573 \93masked\94 to mean \93enabled\94. To avoid confusion we will not use the word \93masked\94. */
2574
2575 #define SSP_SSP0IMSC_RORIM_MASK ((unsigned int) 0x00000001) // Receive overrun interrupt
2576 #define SSP_SSP0IMSC_RORIM_ENBL ((unsigned int) 0x00000001)
2577 #define SSP_SSP0IMSC_RORIM_DSBL ((unsigned int) 0x00000000)
2578 #define SSP_SSP0IMSC_RTIM_MASK ((unsigned int) 0x00000002) // Receive timeout interrupt
2579 #define SSP_SSP0IMSC_RTIM_ENBL ((unsigned int) 0x00000002)
2580 #define SSP_SSP0IMSC_RTIM_DSBL ((unsigned int) 0x00000000)
2581 #define SSP_SSP0IMSC_RXIM_MASK ((unsigned int) 0x00000004) // Rx FIFO >= 1/2 full interrupt
2582 #define SSP_SSP0IMSC_RXIM_ENBL ((unsigned int) 0x00000004)
2583 #define SSP_SSP0IMSC_RXIM_DSBL ((unsigned int) 0x00000000)
2584 #define SSP_SSP0IMSC_TXIM_MASK ((unsigned int) 0x00000008) // Tx FIFO >= 1/2 empty interrupt
2585 #define SSP_SSP0IMSC_TXIM_ENBL ((unsigned int) 0x00000008)
2586 #define SSP_SSP0IMSC_TXIM_DSBL ((unsigned int) 0x00000000)
2587
2588 /* SSP0RIS (SSP0 Raw Interrupt Status Register)
2589 This read-only register contains a 1 for each interrupt condition that is asserted,
2590 regardless of whether or not the interrupt is enabled in the SSP0IMSC. */
2591
2592 #define SSP_SSP0RIS_RORRIS_MASK ((unsigned int) 0x00000001) // Frame received while Rx FIFO full
2593 #define SSP_SSP0RIS_RORRIS_RCVD ((unsigned int) 0x00000001)
2594 #define SSP_SSP0RIS_RTRIS_MASK ((unsigned int) 0x00000002) // Rx FIFO not empty no read within timeout
2595 #define SSP_SSP0RIS_RTRIS_NOTEMPTY ((unsigned int) 0x00000002)
2596 #define SSP_SSP0RIS_RXRIS_MASK ((unsigned int) 0x00000004) // Rx FIFO >= half full
2597 #define SSP_SSP0RIS_RXRIS_HALFFULL ((unsigned int) 0x00000004)
2598 #define SSP_SSP0RIS_TXRIS_MASK ((unsigned int) 0x00000008) // Tx FIF0 >= half-empty
2599 #define SSP_SSP0RIS_TXRIS_HALFEMPTY ((unsigned int) 0x00000008)
2600
2601 /* SSP0MIS (SSP0 Masked Interrupt Status Register)
2602 This read-only register contains a 1 for each interrupt condition that is asserted and
2603 enabled in the SSP0IMSC. When an SSP interrupt occurs, the interrupt service routine
2604 should read this register to determine the cause(s) of the interrupt. */
2605
2606 #define SSP_SSP0MIS_RORMIS_MASK ((unsigned int) 0x00000001) // Frame received while Rx FIFO full
2607 #define SSP_SSP0MIS_RORMIS_FRMRCVD ((unsigned int) 0x00000001)
2608 #define SSP_SSP0MIS_RTMIS_MASK ((unsigned int) 0x00000002) // Rx FIFO not empty no read withing timeout
2609 #define SSP_SSP0MIS_RTMIS_NOTEMPTY ((unsigned int) 0x00000002)
2610 #define SSP_SSP0MIS_RXMIS_MASK ((unsigned int) 0x00000004) // Rx FIFO >= half full
2611 #define SSP_SSP0MIS_RXMIS_HALFFULL ((unsigned int) 0x00000004)
2612 #define SSP_SSP0MIS_TXMIS_MASK ((unsigned int) 0x00000008) // Tx FIFO >= half-empty
2613 #define SSP_SSP0MIS_TXMIS_HALFEMPTY ((unsigned int) 0x00000008)
2614
2615 /* SSP0ICR (SSP0 Interrupt Clear Register)
2616 Software can write one or more one(s) to this write-only register, to clear the
2617 corresponding interrupt condition(s) in the SSP controller. Note that the other two interrupt
2618 conditions can be cleared by writing or reading the appropriate FIFO, or disabled by
2619 clearing the corresponding bit in SSP0IMSC. */
2620
2621 #define SSP_SSP0ICR_RORIC_MASK ((unsigned int) 0x00000001) // Clears RORIC interrupt flag
2622 #define SSP_SSP0ICR_RORIC_CLEAR ((unsigned int) 0x00000001)
2623 #define SSP_SSP0ICR_RTIC_MASK ((unsigned int) 0x00000002) // Clear Rx FIFO not empty/no read flag
2624 #define SSP_SSP0ICR_RTIC_CLEAR ((unsigned int) 0x00000002)
2625
2626 /*##############################################################################
2627 ## I2C
2628 ##############################################################################*/
2629
2630 #define I2C_BASE_ADDRESS (0x40000000)
2631
2632 #define I2C_I2CCONSET (*(pREG32 (0x40000000))) // I2C control set register
2633 #define I2C_I2CSTAT (*(pREG32 (0x40000004))) // I2C status register
2634 #define I2C_I2CDAT (*(pREG32 (0x40000008))) // I2C data register
2635 #define I2C_I2CADR0 (*(pREG32 (0x4000000C))) // I2C slave address register
2636 #define I2C_I2CSCLH (*(pREG32 (0x40000010))) // I2C SCL HIGH/LOW duty cycle register
2637 #define I2C_I2CSCLL (*(pREG32 (0x40000014)))
2638 #define I2C_I2CCONCLR (*(pREG32 (0x40000018))) // I2C control clear register
2639 #define I2C_I2CMMCTRL (*(pREG32 (0x4000001C))) // I2C monitor control register
2640 #define I2C_I2CADR1 (*(pREG32 (0x40000020))) // I2C slave address register 1
2641 #define I2C_I2CADR2 (*(pREG32 (0x40000024))) // I2C slave address register 2
2642 #define I2C_I2CADR3 (*(pREG32 (0x40000028))) // I2C slave address register 3
2643 #define I2C_I2CDATA_BUFFER (*(pREG32 (0x4000002C))) // I2C data buffer register
2644 #define I2C_I2CMASK0 (*(pREG32 (0x40000030))) // I2C mask register 0
2645 #define I2C_I2CMASK1 (*(pREG32 (0x40000034))) // I2C mask register 1
2646 #define I2C_I2CMASK2 (*(pREG32 (0x40000038))) // I2C mask register 2
2647 #define I2C_I2CMASK3 (*(pREG32 (0x4000003C))) // I2C mask register 3
2648
2649 /* I2CCONSET (I2C Control Set register)
2650 The I2CONSET registers control setting of bits in the I2CON register that controls
2651 operation of the I2C interface. Writing a one to a bit of this register causes the
2652 corresponding bit in the I2C control register to be set. Writing a zero has no effect. */
2653
2654 #define I2C_I2CCONSET_AA_MASK ((unsigned int) 0x00000004)
2655 #define I2C_I2CCONSET_AA ((unsigned int) 0x00000004) // Asset acknowlegde flag
2656 #define I2C_I2CCONSET_SI_MASK ((unsigned int) 0x00000008)
2657 #define I2C_I2CCONSET_SI ((unsigned int) 0x00000008) // I2C interrupt flag
2658 #define I2C_I2CCONSET_STO_MASK ((unsigned int) 0x00000010)
2659 #define I2C_I2CCONSET_STO ((unsigned int) 0x00000010) // Stop flag
2660 #define I2C_I2CCONSET_STA_MASK ((unsigned int) 0x00000020)
2661 #define I2C_I2CCONSET_STA ((unsigned int) 0x00000020) // Start flag
2662 #define I2C_I2CCONSET_I2EN_MASK ((unsigned int) 0x00000040)
2663 #define I2C_I2CCONSET_I2EN ((unsigned int) 0x00000040) // I2C interface enable
2664
2665 /* I2CSTAT (I2C Status register)
2666 Each I2C Status register reflects the condition of the corresponding I2C interface. The I2C
2667 Status register is Read-Only. */
2668
2669 #define I2C_I2CSTAT_Status_MASK ((unsigned int) 0x000000F8) // Status information
2670
2671 /* I2CADR0 (I2C Slave Address register)
2672 These registers are readable and writable and are only used when an I2C interface is set
2673 to slave mode. */
2674
2675 #define I2C_I2CADR0_GC_MASK ((unsigned int) 0x00000001)
2676 #define I2C_I2CADR0_GC ((unsigned int) 0x00000001) // General call enable bit
2677 #define I2C_I2CADR0_Address_MASK ((unsigned int) 0x000000FE) // I2C device address for slave mode
2678
2679 /* I2CCONCLR (I2C Control Clear register)
2680 The I2CONCLR registers control clearing of bits in the I2CON register that controls
2681 operation of the I2C interface. Writing a one to a bit of this register causes the
2682 corresponding bit in the I2C control register to be cleared. Writing a zero has no effect. */
2683
2684 #define I2C_I2CCONCLR_AAC_MASK ((unsigned int) 0x00000004) // Assert acknowledge clear bit
2685 #define I2C_I2CCONCLR_AAC ((unsigned int) 0x00000004)
2686 #define I2C_I2CCONCLR_SIC_MASK ((unsigned int) 0x00000008) // I2C interrupt clear bit
2687 #define I2C_I2CCONCLR_SIC ((unsigned int) 0x00000008)
2688 #define I2C_I2CCONCLR_STAC_MASK ((unsigned int) 0x00000020) // Start flag clear bit
2689 #define I2C_I2CCONCLR_STAC ((unsigned int) 0x00000020)
2690 #define I2C_I2CCONCLR_I2ENC_MASK ((unsigned int) 0x00000040) // I2C interface disable bit
2691 #define I2C_I2CCONCLR_I2ENC ((unsigned int) 0x00000040)
2692
2693 /* I2CMMCTRL (I2C Monitor mode control register)
2694 This register controls the Monitor mode which allows the I2C module to monitor traffic on
2695 the I2C bus without actually participating in traffic or interfering with the I2C bus. */
2696
2697 #define I2C_I2CMMCTRL_MM_ENA_MASK ((unsigned int) 0x00000001) // Monitor mode enable
2698 #define I2C_I2CMMCTRL_MM_ENA_ENABLED ((unsigned int) 0x00000001)
2699 #define I2C_I2CMMCTRL_MM_ENA_DISABLED ((unsigned int) 0x00000000)
2700 #define I2C_I2CMMCTRL_ENA_SCL_MASK ((unsigned int) 0x00000002) // SCL output enable
2701 #define I2C_I2CMMCTRL_ENA_SCL_HOLDLOW ((unsigned int) 0x00000002)
2702 #define I2C_I2CMMCTRL_ENA_SCL_FORCEHIGH ((unsigned int) 0x00000000)
2703 #define I2C_I2CMMCTRL_MATCH_ALL_MASK ((unsigned int) 0x00000008) // Select interrupt register match
2704 #define I2C_I2CMMCTRL_MATCH_ALL_NORMAL ((unsigned int) 0x00000000)
2705 #define I2C_I2CMMCTRL_MATCH_ALL_ANYADDRESS ((unsigned int) 0x00000008)
2706
2707 /* I2CADR1..3 (I2C Slave Address registers)
2708 These registers are readable and writable and are only used when an I2C interface is set
2709 to slave mode. In master mode, this register has no effect. The LSB of I2ADR is the
2710 General Call bit. When this bit is set, the General Call address (0x00) is recognized. */
2711
2712 #define I2C_I2CADR1_GC_MASK ((unsigned int) 0x00000001) // General call enable bit
2713 #define I2C_I2CADR1_GC ((unsigned int) 0x00000001)
2714 #define I2C_I2CADR1_Address_MASK ((unsigned int) 0x000000FE)
2715
2716 #define I2C_I2CADR2_GC_MASK ((unsigned int) 0x00000001) // General call enable bit
2717 #define I2C_I2CADR2_GC ((unsigned int) 0x00000001)
2718 #define I2C_I2CADR2_Address_MASK ((unsigned int) 0x000000FE)
2719
2720 #define I2C_I2CADR3_GC_MASK ((unsigned int) 0x00000001) // General call enable bit
2721 #define I2C_I2CADR3_GC ((unsigned int) 0x00000001)
2722 #define I2C_I2CADR3_Address_MASK ((unsigned int) 0x000000FE)
2723
2724 /* I2CMASK0..3 (I2C Mask registers) */
2725
2726 #define I2C_I2CMASK0_MASK_MASK ((unsigned int) 0x000000FE)
2727
2728 #define I2C_I2CMASK1_MASK_MASK ((unsigned int) 0x000000FE)
2729
2730 #define I2C_I2CMASK2_MASK_MASK ((unsigned int) 0x000000FE)
2731
2732 #define I2C_I2CMASK3_MASK_MASK ((unsigned int) 0x000000FE)
2733
2734 /*##############################################################################
2735 ## 16-Bit Timers (CT16B0/1)
2736 ##############################################################################*/
2737
2738 #define TMR_CT16B0_BASE_ADDRESS (0x4000C000)
2739
2740 #define TMR_TMR16B0IR (*(pREG32 (0x4000C000))) // Interrupt register
2741 #define TMR_TMR16B0TCR (*(pREG32 (0x4000C004))) // Timer control register
2742 #define TMR_TMR16B0TC (*(pREG32 (0x4000C008))) // Timer counter
2743 #define TMR_TMR16B0PR (*(pREG32 (0x4000C00C))) // Prescale register
2744 #define TMR_TMR16B0PC (*(pREG32 (0x4000C010))) // Prescale counter register
2745 #define TMR_TMR16B0MCR (*(pREG32 (0x4000C014))) // Match control register
2746 #define TMR_TMR16B0MR0 (*(pREG32 (0x4000C018))) // Match register 0
2747 #define TMR_TMR16B0MR1 (*(pREG32 (0x4000C01C))) // Match register 1
2748 #define TMR_TMR16B0MR2 (*(pREG32 (0x4000C020))) // Match register 2
2749 #define TMR_TMR16B0MR3 (*(pREG32 (0x4000C024))) // Match register 3
2750 #define TMR_TMR16B0CCR (*(pREG32 (0x4000C028))) // Capture control register
2751 #define TMR_TMR16B0CR0 (*(pREG32 (0x4000C02C))) // Capture register
2752 #define TMR_TMR16B0EMR (*(pREG32 (0x4000C03C))) // External match register
2753 #define TMR_TMR16B0CTCR (*(pREG32 (0x4000C070))) // Count control register
2754 #define TMR_TMR16B0PWMC (*(pREG32 (0x4000C074))) // PWM control register
2755
2756 #define TMR_TMR16B0IR_MR0_MASK ((unsigned int) 0x00000001) // Interrupt flag for match channel 0
2757 #define TMR_TMR16B0IR_MR0 ((unsigned int) 0x00000001)
2758 #define TMR_TMR16B0IR_MR1_MASK ((unsigned int) 0x00000002) // Interrupt flag for match channel 1
2759 #define TMR_TMR16B0IR_MR1 ((unsigned int) 0x00000002)
2760 #define TMR_TMR16B0IR_MR2_MASK ((unsigned int) 0x00000004) // Interrupt flag for match channel 2
2761 #define TMR_TMR16B0IR_MR2 ((unsigned int) 0x00000004)
2762 #define TMR_TMR16B0IR_MR3_MASK ((unsigned int) 0x00000008) // Interrupt flag for match channel 3
2763 #define TMR_TMR16B0IR_MR3 ((unsigned int) 0x00000008)
2764 #define TMR_TMR16B0IR_CR0_MASK ((unsigned int) 0x00000010) // Interrupt flag for capture channel 0 event
2765 #define TMR_TMR16B0IR_CR0 ((unsigned int) 0x00000010)
2766 #define TMR_TMR16B0IR_MASK_ALL ((unsigned int) 0x0000001F)
2767
2768 #define TMR_TMR16B0TCR_COUNTERENABLE_MASK ((unsigned int) 0x00000001) // Counter enable
2769 #define TMR_TMR16B0TCR_COUNTERENABLE_ENABLED ((unsigned int) 0x00000001)
2770 #define TMR_TMR16B0TCR_COUNTERENABLE_DISABLED ((unsigned int) 0x00000000)
2771 #define TMR_TMR16B0TCR_COUNTERRESET_MASK ((unsigned int) 0x00000002)
2772 #define TMR_TMR16B0TCR_COUNTERRESET_ENABLED ((unsigned int) 0x00000002)
2773 #define TMR_TMR16B0TCR_COUNTERRESET_DISABLED ((unsigned int) 0x00000000)
2774
2775 #define TMR_TMR16B0MCR_MR0_INT_MASK ((unsigned int) 0x00000001) // Interrupt on MRO
2776 #define TMR_TMR16B0MCR_MR0_INT_ENABLED ((unsigned int) 0x00000001)
2777 #define TMR_TMR16B0MCR_MR0_INT_DISABLED ((unsigned int) 0x00000000)
2778 #define TMR_TMR16B0MCR_MR0_RESET_MASK ((unsigned int) 0x00000002) // Reset on MR0
2779 #define TMR_TMR16B0MCR_MR0_RESET_ENABLED ((unsigned int) 0x00000002)
2780 #define TMR_TMR16B0MCR_MR0_RESET_DISABLED ((unsigned int) 0x00000000)
2781 #define TMR_TMR16B0MCR_MR0_STOP_MASK ((unsigned int) 0x00000004) // Stop on MR0
2782 #define TMR_TMR16B0MCR_MR0_STOP_ENABLED ((unsigned int) 0x00000004)
2783 #define TMR_TMR16B0MCR_MR0_STOP_DISABLED ((unsigned int) 0x00000000)
2784 #define TMR_TMR16B0MCR_MR1_INT_MASK ((unsigned int) 0x00000008) // Interrupt on MR1
2785 #define TMR_TMR16B0MCR_MR1_INT_ENABLED ((unsigned int) 0x00000008)
2786 #define TMR_TMR16B0MCR_MR1_INT_DISABLED ((unsigned int) 0x00000000)
2787 #define TMR_TMR16B0MCR_MR1_RESET_MASK ((unsigned int) 0x00000010) // Reset on MR1
2788 #define TMR_TMR16B0MCR_MR1_RESET_ENABLED ((unsigned int) 0x00000010)
2789 #define TMR_TMR16B0MCR_MR1_RESET_DISABLED ((unsigned int) 0x00000000)
2790 #define TMR_TMR16B0MCR_MR1_STOP_MASK ((unsigned int) 0x00000020) // Stop on MR1
2791 #define TMR_TMR16B0MCR_MR1_STOP_ENABLED ((unsigned int) 0x00000020)
2792 #define TMR_TMR16B0MCR_MR1_STOP_DISABLED ((unsigned int) 0x00000000)
2793 #define TMR_TMR16B0MCR_MR2_INT_MASK ((unsigned int) 0x00000040) // Interrupt on MR2
2794 #define TMR_TMR16B0MCR_MR2_INT_ENABLED ((unsigned int) 0x00000040)
2795 #define TMR_TMR16B0MCR_MR2_INT_DISABLED ((unsigned int) 0x00000000)
2796 #define TMR_TMR16B0MCR_MR2_RESET_MASK ((unsigned int) 0x00000080) // Reset on MR2
2797 #define TMR_TMR16B0MCR_MR2_RESET_ENABLED ((unsigned int) 0x00000080)
2798 #define TMR_TMR16B0MCR_MR2_RESET_DISABLED ((unsigned int) 0x00000000)
2799 #define TMR_TMR16B0MCR_MR2_STOP_MASK ((unsigned int) 0x00000100) // Stop on MR2
2800 #define TMR_TMR16B0MCR_MR2_STOP_ENABLED ((unsigned int) 0x00000100)
2801 #define TMR_TMR16B0MCR_MR2_STOP_DISABLED ((unsigned int) 0x00000000)
2802 #define TMR_TMR16B0MCR_MR3_INT_MASK ((unsigned int) 0x00000200) // Interrupt on MR3
2803 #define TMR_TMR16B0MCR_MR3_INT_ENABLED ((unsigned int) 0x00000200)
2804 #define TMR_TMR16B0MCR_MR3_INT_DISABLED ((unsigned int) 0x00000000)
2805 #define TMR_TMR16B0MCR_MR3_RESET_MASK ((unsigned int) 0x00000400) // Reset on MR3
2806 #define TMR_TMR16B0MCR_MR3_RESET_ENABLED ((unsigned int) 0x00000400)
2807 #define TMR_TMR16B0MCR_MR3_RESET_DISABLED ((unsigned int) 0x00000000)
2808 #define TMR_TMR16B0MCR_MR3_STOP_MASK ((unsigned int) 0x00000800) // Stop on MR3
2809 #define TMR_TMR16B0MCR_MR3_STOP_ENABLED ((unsigned int) 0x00000800)
2810 #define TMR_TMR16B0MCR_MR3_STOP_DISABLED ((unsigned int) 0x00000000)
2811
2812 #define TMR_TMR16B0CCR_CAP0RE_MASK ((unsigned int) 0x00000001) // Capture on rising edge
2813 #define TMR_TMR16B0CCR_CAP0RE_ENABLED ((unsigned int) 0x00000001)
2814 #define TMR_TMR16B0CCR_CAP0RE_DISABLED ((unsigned int) 0x00000000)
2815 #define TMR_TMR16B0CCR_CAP0FE_MASK ((unsigned int) 0x00000002) // Capture on falling edge
2816 #define TMR_TMR16B0CCR_CAP0FE_ENABLED ((unsigned int) 0x00000002)
2817 #define TMR_TMR16B0CCR_CAP0FE_DISABLED ((unsigned int) 0x00000000)
2818 #define TMR_TMR16B0CCR_CAP0I_MASK ((unsigned int) 0x00000004) // Interrupt on CAP0 event
2819 #define TMR_TMR16B0CCR_CAP0I_ENABLED ((unsigned int) 0x00000004)
2820 #define TMR_TMR16B0CCR_CAP0I_DISABLED ((unsigned int) 0x00000000)
2821
2822 #define TMR_TMR16B0EMR_EM0_MASK ((unsigned int) 0x00000001) // External match 0
2823 #define TMR_TMR16B0EMR_EM0 ((unsigned int) 0x00000001)
2824 #define TMR_TMR16B0EMR_EMC0_MASK ((unsigned int) 0x00000030)
2825 #define TMR_TMR16B0EMR_EMC0_DONOTHING ((unsigned int) 0x00000000)
2826 #define TMR_TMR16B0EMR_EMC0_LOW ((unsigned int) 0x00000010)
2827 #define TMR_TMR16B0EMR_EMC0_HIGH ((unsigned int) 0x00000020)
2828 #define TMR_TMR16B0EMR_EMC0_TOGGLE ((unsigned int) 0x00000030)
2829 #define TMR_TMR16B0EMR_EM1_MASK ((unsigned int) 0x00000002) // External match 1
2830 #define TMR_TMR16B0EMR_EM1 ((unsigned int) 0x00000002)
2831 #define TMR_TMR16B0EMR_EMC1_MASK ((unsigned int) 0x000000C0)
2832 #define TMR_TMR16B0EMR_EMC1_DONOTHING ((unsigned int) 0x00000000)
2833 #define TMR_TMR16B0EMR_EMC1_LOW ((unsigned int) 0x00000040)
2834 #define TMR_TMR16B0EMR_EMC1_HIGH ((unsigned int) 0x00000080)
2835 #define TMR_TMR16B0EMR_EMC1_TOGGLE ((unsigned int) 0x000000C0)
2836 #define TMR_TMR16B0EMR_EM2_MASK ((unsigned int) 0x00000004) // External match 2
2837 #define TMR_TMR16B0EMR_EM2 ((unsigned int) 0x00000004)
2838 #define TMR_TMR16B0EMR_EMC2_MASK ((unsigned int) 0x00000300)
2839 #define TMR_TMR16B0EMR_EMC2_DONOTHING ((unsigned int) 0x00000000)
2840 #define TMR_TMR16B0EMR_EMC2_LOW ((unsigned int) 0x00000100)
2841 #define TMR_TMR16B0EMR_EMC2_HIGH ((unsigned int) 0x00000200)
2842 #define TMR_TMR16B0EMR_EMC2_TOGGLE ((unsigned int) 0x00000300)
2843 #define TMR_TMR16B0EMR_EM3_MASK ((unsigned int) 0x00000008) // External match 3
2844 #define TMR_TMR16B0EMR_EM3 ((unsigned int) 0x00000008)
2845 #define TMR_TMR16B0EMR_EMC3_MASK ((unsigned int) 0x00000C00)
2846 #define TMR_TMR16B0EMR_EMC3_DONOTHING ((unsigned int) 0x00000000)
2847 #define TMR_TMR16B0EMR_EMC3_LOW ((unsigned int) 0x00000400)
2848 #define TMR_TMR16B0EMR_EMC3_HIGH ((unsigned int) 0x00000800)
2849 #define TMR_TMR16B0EMR_EMC3_TOGGLE ((unsigned int) 0x00000C00)
2850
2851 #define TMR_TMR16B0CTCR_CTMODE_MASK ((unsigned int) 0x00000003) // Counter/Timer mode
2852 #define TMR_TMR16B0CTCR_CTMODE_TIMER ((unsigned int) 0x00000000) // Timer Mode: Every rising PCLK edge
2853 #define TMR_TMR16B0CTCR_CTMODE_COUNTERRISING ((unsigned int) 0x00000001) // Counter: TC increments on rising edge of input
2854 #define TMR_TMR16B0CTCR_CTMODE_COUNTERFALLING ((unsigned int) 0x00000002) // Counter: TC increments on falling edge of input
2855 #define TMR_TMR16B0CTCR_CTMODE_COUNTERBOTH ((unsigned int) 0x00000003) // Counter: TC increments on both edges of input
2856 #define TMR_TMR16B0CTCR_CINPUTSELECT_MASK ((unsigned int) 0x0000000C)
2857 #define TMR_TMR16B0CTCR_CINPUTSELECT ((unsigned int) 0x00000000) // CINPUTSELECT must be set to 00
2858
2859 #define TMR_TMR16B0PWMC_PWM0_MASK ((unsigned int) 0x00000001)
2860 #define TMR_TMR16B0PWMC_PWM0_ENABLED ((unsigned int) 0x00000001) // PWM mode is enabled for CT16Bn_MAT0
2861 #define TMR_TMR16B0PWMC_PWM0_DISABLED ((unsigned int) 0x00000000)
2862 #define TMR_TMR16B0PWMC_PWM1_MASK ((unsigned int) 0x00000002)
2863 #define TMR_TMR16B0PWMC_PWM1_ENABLED ((unsigned int) 0x00000002) // PWM mode is enabled for CT16Bn_MAT1
2864 #define TMR_TMR16B0PWMC_PWM1_DISABLED ((unsigned int) 0x00000000)
2865 #define TMR_TMR16B0PWMC_PWM2_MASK ((unsigned int) 0x00000004)
2866 #define TMR_TMR16B0PWMC_PWM2_ENABLED ((unsigned int) 0x00000004) // PWM mode is enabled for CT16Bn_MAT2
2867 #define TMR_TMR16B0PWMC_PWM2_DISABLED ((unsigned int) 0x00000000)
2868 #define TMR_TMR16B0PWMC_PWM3_MASK ((unsigned int) 0x00000008)
2869 #define TMR_TMR16B0PWMC_PWM3_ENABLED ((unsigned int) 0x00000008)
2870 #define TMR_TMR16B0PWMC_PWM3_DISABLED ((unsigned int) 0x00000000)
2871
2872 #define TMR_CT16B1_BASE_ADDRESS (0x40010000)
2873
2874 #define TMR_TMR16B1IR (*(pREG32 (0x40010000))) // Interrupt register
2875 #define TMR_TMR16B1TCR (*(pREG32 (0x40010004))) // Timer control register
2876 #define TMR_TMR16B1TC (*(pREG32 (0x40010008))) // Timer counter
2877 #define TMR_TMR16B1PR (*(pREG32 (0x4001000C))) // Prescale register
2878 #define TMR_TMR16B1PC (*(pREG32 (0x40010010))) // Prescale counter register
2879 #define TMR_TMR16B1MCR (*(pREG32 (0x40010014))) // Match control register
2880 #define TMR_TMR16B1MR0 (*(pREG32 (0x40010018))) // Match register 0
2881 #define TMR_TMR16B1MR1 (*(pREG32 (0x4001001C))) // Match register 1
2882 #define TMR_TMR16B1MR2 (*(pREG32 (0x40010020))) // Match register 2
2883 #define TMR_TMR16B1MR3 (*(pREG32 (0x40010024))) // Match register 3
2884 #define TMR_TMR16B1CCR (*(pREG32 (0x40010028))) // Capture control register
2885 #define TMR_TMR16B1CR0 (*(pREG32 (0x4001002C))) // Capture register
2886 #define TMR_TMR16B1EMR (*(pREG32 (0x4001003C))) // External match register
2887 #define TMR_TMR16B1CTCR (*(pREG32 (0x40010070))) // Count control register
2888 #define TMR_TMR16B1PWMC (*(pREG32 (0x40010074))) // PWM control register
2889
2890 #define TMR_TMR16B1IR_MR0_MASK ((unsigned int) 0x00000001) // Interrupt flag for match channel 0
2891 #define TMR_TMR16B1IR_MR0 ((unsigned int) 0x00000001)
2892 #define TMR_TMR16B1IR_MR1_MASK ((unsigned int) 0x00000002) // Interrupt flag for match channel 1
2893 #define TMR_TMR16B1IR_MR1 ((unsigned int) 0x00000002)
2894 #define TMR_TMR16B1IR_MR2_MASK ((unsigned int) 0x00000004) // Interrupt flag for match channel 2
2895 #define TMR_TMR16B1IR_MR2 ((unsigned int) 0x00000004)
2896 #define TMR_TMR16B1IR_MR3_MASK ((unsigned int) 0x00000008) // Interrupt flag for match channel 3
2897 #define TMR_TMR16B1IR_MR3 ((unsigned int) 0x00000008)
2898 #define TMR_TMR16B1IR_CR0_MASK ((unsigned int) 0x00000010) // Interrupt flag for capture channel 0 event
2899 #define TMR_TMR16B1IR_CR0 ((unsigned int) 0x00000010)
2900 #define TMR_TMR16B1IR_MASK_ALL ((unsigned int) 0x0000001F)
2901
2902 #define TMR_TMR16B1TCR_COUNTERENABLE_MASK ((unsigned int) 0x00000001) // Counter enable
2903 #define TMR_TMR16B1TCR_COUNTERENABLE_ENABLED ((unsigned int) 0x00000001)
2904 #define TMR_TMR16B1TCR_COUNTERENABLE_DISABLED ((unsigned int) 0x00000000)
2905 #define TMR_TMR16B1TCR_COUNTERRESET_MASK ((unsigned int) 0x00000002)
2906 #define TMR_TMR16B1TCR_COUNTERRESET_ENABLED ((unsigned int) 0x00000002)
2907 #define TMR_TMR16B1TCR_COUNTERRESET_DISABLED ((unsigned int) 0x00000000)
2908
2909 #define TMR_TMR16B1MCR_MR0_INT_MASK ((unsigned int) 0x00000001) // Interrupt on MRO
2910 #define TMR_TMR16B1MCR_MR0_INT_ENABLED ((unsigned int) 0x00000001)
2911 #define TMR_TMR16B1MCR_MR0_INT_DISABLED ((unsigned int) 0x00000000)
2912 #define TMR_TMR16B1MCR_MR0_RESET_MASK ((unsigned int) 0x00000002) // Reset on MR0
2913 #define TMR_TMR16B1MCR_MR0_RESET_ENABLED ((unsigned int) 0x00000002)
2914 #define TMR_TMR16B1MCR_MR0_RESET_DISABLED ((unsigned int) 0x00000000)
2915 #define TMR_TMR16B1MCR_MR0_STOP_MASK ((unsigned int) 0x00000004) // Stop on MR0
2916 #define TMR_TMR16B1MCR_MR0_STOP_ENABLED ((unsigned int) 0x00000004)
2917 #define TMR_TMR16B1MCR_MR0_STOP_DISABLED ((unsigned int) 0x00000000)
2918 #define TMR_TMR16B1MCR_MR1_INT_MASK ((unsigned int) 0x00000008) // Interrupt on MR1
2919 #define TMR_TMR16B1MCR_MR1_INT_ENABLED ((unsigned int) 0x00000008)
2920 #define TMR_TMR16B1MCR_MR1_INT_DISABLED ((unsigned int) 0x00000000)
2921 #define TMR_TMR16B1MCR_MR1_RESET_MASK ((unsigned int) 0x00000010) // Reset on MR1
2922 #define TMR_TMR16B1MCR_MR1_RESET_ENABLED ((unsigned int) 0x00000010)
2923 #define TMR_TMR16B1MCR_MR1_RESET_DISABLED ((unsigned int) 0x00000000)
2924 #define TMR_TMR16B1MCR_MR1_STOP_MASK ((unsigned int) 0x00000020) // Stop on MR1
2925 #define TMR_TMR16B1MCR_MR1_STOP_ENABLED ((unsigned int) 0x00000020)
2926 #define TMR_TMR16B1MCR_MR1_STOP_DISABLED ((unsigned int) 0x00000000)
2927 #define TMR_TMR16B1MCR_MR2_INT_MASK ((unsigned int) 0x00000040) // Interrupt on MR2
2928 #define TMR_TMR16B1MCR_MR2_INT_ENABLED ((unsigned int) 0x00000040)
2929 #define TMR_TMR16B1MCR_MR2_INT_DISABLED ((unsigned int) 0x00000000)
2930 #define TMR_TMR16B1MCR_MR2_RESET_MASK ((unsigned int) 0x00000080) // Reset on MR2
2931 #define TMR_TMR16B1MCR_MR2_RESET_ENABLED ((unsigned int) 0x00000080)
2932 #define TMR_TMR16B1MCR_MR2_RESET_DISABLED ((unsigned int) 0x00000000)
2933 #define TMR_TMR16B1MCR_MR2_STOP_MASK ((unsigned int) 0x00000100) // Stop on MR2
2934 #define TMR_TMR16B1MCR_MR2_STOP_ENABLED ((unsigned int) 0x00000100)
2935 #define TMR_TMR16B1MCR_MR2_STOP_DISABLED ((unsigned int) 0x00000000)
2936 #define TMR_TMR16B1MCR_MR3_INT_MASK ((unsigned int) 0x00000200) // Interrupt on MR3
2937 #define TMR_TMR16B1MCR_MR3_INT_ENABLED ((unsigned int) 0x00000200)
2938 #define TMR_TMR16B1MCR_MR3_INT_DISABLED ((unsigned int) 0x00000000)
2939 #define TMR_TMR16B1MCR_MR3_RESET_MASK ((unsigned int) 0x00000400) // Reset on MR3
2940 #define TMR_TMR16B1MCR_MR3_RESET_ENABLED ((unsigned int) 0x00000400)
2941 #define TMR_TMR16B1MCR_MR3_RESET_DISABLED ((unsigned int) 0x00000000)
2942 #define TMR_TMR16B1MCR_MR3_STOP_MASK ((unsigned int) 0x00000800) // Stop on MR3
2943 #define TMR_TMR16B1MCR_MR3_STOP_ENABLED ((unsigned int) 0x00000800)
2944 #define TMR_TMR16B1MCR_MR3_STOP_DISABLED ((unsigned int) 0x00000000)
2945
2946 #define TMR_TMR16B1CCR_CAP0RE_MASK ((unsigned int) 0x00000001) // Capture on rising edge
2947 #define TMR_TMR16B1CCR_CAP0RE_ENABLED ((unsigned int) 0x00000001)
2948 #define TMR_TMR16B1CCR_CAP0RE_DISABLED ((unsigned int) 0x00000000)
2949 #define TMR_TMR16B1CCR_CAP0FE_MASK ((unsigned int) 0x00000002) // Capture on falling edge
2950 #define TMR_TMR16B1CCR_CAP0FE_ENABLED ((unsigned int) 0x00000002)
2951 #define TMR_TMR16B1CCR_CAP0FE_DISABLED ((unsigned int) 0x00000000)
2952 #define TMR_TMR16B1CCR_CAP0I_MASK ((unsigned int) 0x00000004) // Interrupt on CAP0 event
2953 #define TMR_TMR16B1CCR_CAP0I_ENABLED ((unsigned int) 0x00000004)
2954 #define TMR_TMR16B1CCR_CAP0I_DISABLED ((unsigned int) 0x00000000)
2955
2956 #define TMR_TMR16B1EMR_EM0_MASK ((unsigned int) 0x00000001) // External match 0
2957 #define TMR_TMR16B1EMR_EM0 ((unsigned int) 0x00000001)
2958 #define TMR_TMR16B1EMR_EMC0_MASK ((unsigned int) 0x00000030)
2959 #define TMR_TMR16B1EMR_EMC0_DONOTHING ((unsigned int) 0x00000000)
2960 #define TMR_TMR16B1EMR_EMC0_LOW ((unsigned int) 0x00000010)
2961 #define TMR_TMR16B1EMR_EMC0_HIGH ((unsigned int) 0x00000020)
2962 #define TMR_TMR16B1EMR_EMC0_TOGGLE ((unsigned int) 0x00000030)
2963 #define TMR_TMR16B1EMR_EM1_MASK ((unsigned int) 0x00000002) // External match 1
2964 #define TMR_TMR16B1EMR_EM1 ((unsigned int) 0x00000002)
2965 #define TMR_TMR16B1EMR_EMC1_MASK ((unsigned int) 0x000000C0)
2966 #define TMR_TMR16B1EMR_EMC1_DONOTHING ((unsigned int) 0x00000000)
2967 #define TMR_TMR16B1EMR_EMC1_LOW ((unsigned int) 0x00000040)
2968 #define TMR_TMR16B1EMR_EMC1_HIGH ((unsigned int) 0x00000080)
2969 #define TMR_TMR16B1EMR_EMC1_TOGGLE ((unsigned int) 0x000000C0)
2970 #define TMR_TMR16B1EMR_EM2_MASK ((unsigned int) 0x00000004) // External match 2
2971 #define TMR_TMR16B1EMR_EM2 ((unsigned int) 0x00000004)
2972 #define TMR_TMR16B1EMR_EMC2_MASK ((unsigned int) 0x00000300)
2973 #define TMR_TMR16B1EMR_EMC2_DONOTHING ((unsigned int) 0x00000000)
2974 #define TMR_TMR16B1EMR_EMC2_LOW ((unsigned int) 0x00000100)
2975 #define TMR_TMR16B1EMR_EMC2_HIGH ((unsigned int) 0x00000200)
2976 #define TMR_TMR16B1EMR_EMC2_TOGGLE ((unsigned int) 0x00000300)
2977 #define TMR_TMR16B1EMR_EM3_MASK ((unsigned int) 0x00000008) // External match 3
2978 #define TMR_TMR16B1EMR_EM3 ((unsigned int) 0x00000008)
2979 #define TMR_TMR16B1EMR_EMC3_MASK ((unsigned int) 0x00000C00)
2980 #define TMR_TMR16B1EMR_EMC3_DONOTHING ((unsigned int) 0x00000000)
2981 #define TMR_TMR16B1EMR_EMC3_LOW ((unsigned int) 0x00000400)
2982 #define TMR_TMR16B1EMR_EMC3_HIGH ((unsigned int) 0x00000800)
2983 #define TMR_TMR16B1EMR_EMC3_TOGGLE ((unsigned int) 0x00000C00)
2984
2985 #define TMR_TMR16B1CTCR_CTMODE_MASK ((unsigned int) 0x00000003) // Counter/Timer mode
2986 #define TMR_TMR16B1CTCR_CTMODE_TIMER ((unsigned int) 0x00000000) // Timer Mode: Every rising PCLK edge
2987 #define TMR_TMR16B1CTCR_CTMODE_COUNTERRISING ((unsigned int) 0x00000001) // Counter: TC increments on rising edge of input
2988 #define TMR_TMR16B1CTCR_CTMODE_COUNTERFALLING ((unsigned int) 0x00000002) // Counter: TC increments on falling edge of input
2989 #define TMR_TMR16B1CTCR_CTMODE_COUNTERBOTH ((unsigned int) 0x00000003) // Counter: TC increments on both edges of input
2990 #define TMR_TMR16B1CTCR_CINPUTSELECT_MASK ((unsigned int) 0x0000000C)
2991 #define TMR_TMR16B1CTCR_CINPUTSELECT ((unsigned int) 0x00000000) // CINPUTSELECT must be set to 00
2992
2993 #define TMR_TMR16B1PWMC_PWM0_MASK ((unsigned int) 0x00000001)
2994 #define TMR_TMR16B1PWMC_PWM0_ENABLED ((unsigned int) 0x00000001) // PWM mode is enabled for CT16Bn_MAT0
2995 #define TMR_TMR16B1PWMC_PWM0_DISABLED ((unsigned int) 0x00000000)
2996 #define TMR_TMR16B1PWMC_PWM1_MASK ((unsigned int) 0x00000002)
2997 #define TMR_TMR16B1PWMC_PWM1_ENABLED ((unsigned int) 0x00000002) // PWM mode is enabled for CT16Bn_MAT1
2998 #define TMR_TMR16B1PWMC_PWM1_DISABLED ((unsigned int) 0x00000000)
2999 #define TMR_TMR16B1PWMC_PWM2_MASK ((unsigned int) 0x00000004)
3000 #define TMR_TMR16B1PWMC_PWM2_ENABLED ((unsigned int) 0x00000004) // PWM mode is enabled for CT16Bn_MAT2
3001 #define TMR_TMR16B1PWMC_PWM2_DISABLED ((unsigned int) 0x00000000)
3002 #define TMR_TMR16B1PWMC_PWM3_MASK ((unsigned int) 0x00000008)
3003 #define TMR_TMR16B1PWMC_PWM3_ENABLED ((unsigned int) 0x00000008)
3004 #define TMR_TMR16B1PWMC_PWM3_DISABLED ((unsigned int) 0x00000000)
3005
3006 /*##############################################################################
3007 ## 32-Bit Timers (CT32B0/1)
3008 ##############################################################################*/
3009
3010 #define TMR_CT32B0_BASE_ADDRESS (0x40014000)
3011
3012 #define TMR_TMR32B0IR (*(pREG32 (0x40014000))) // Interrupt register
3013 #define TMR_TMR32B0TCR (*(pREG32 (0x40014004))) // Timer control register
3014 #define TMR_TMR32B0TC (*(pREG32 (0x40014008))) // Timer counter
3015 #define TMR_TMR32B0PR (*(pREG32 (0x4001400C))) // Prescale register
3016 #define TMR_TMR32B0PC (*(pREG32 (0x40014010))) // Prescale counter register
3017 #define TMR_TMR32B0MCR (*(pREG32 (0x40014014))) // Match control register
3018 #define TMR_TMR32B0MR0 (*(pREG32 (0x40014018))) // Match register 0
3019 #define TMR_TMR32B0MR1 (*(pREG32 (0x4001401C))) // Match register 1
3020 #define TMR_TMR32B0MR2 (*(pREG32 (0x40014020))) // Match register 2
3021 #define TMR_TMR32B0MR3 (*(pREG32 (0x40014024))) // Match register 3
3022 #define TMR_TMR32B0CCR (*(pREG32 (0x40014028))) // Capture control register
3023 #define TMR_TMR32B0CR0 (*(pREG32 (0x4001402C))) // Capture register
3024 #define TMR_TMR32B0EMR (*(pREG32 (0x4001403C))) // External match register
3025 #define TMR_TMR32B0CTCR (*(pREG32 (0x40014070))) // Count control register
3026 #define TMR_TMR32B0PWMC (*(pREG32 (0x40014074))) // PWM control register
3027
3028 #define TMR_TMR32B0IR_MR0_MASK ((unsigned int) 0x00000001) // Interrupt flag for match channel 0
3029 #define TMR_TMR32B0IR_MR0 ((unsigned int) 0x00000001)
3030 #define TMR_TMR32B0IR_MR1_MASK ((unsigned int) 0x00000002) // Interrupt flag for match channel 1
3031 #define TMR_TMR32B0IR_MR1 ((unsigned int) 0x00000002)
3032 #define TMR_TMR32B0IR_MR2_MASK ((unsigned int) 0x00000004) // Interrupt flag for match channel 2
3033 #define TMR_TMR32B0IR_MR2 ((unsigned int) 0x00000004)
3034 #define TMR_TMR32B0IR_MR3_MASK ((unsigned int) 0x00000008) // Interrupt flag for match channel 3
3035 #define TMR_TMR32B0IR_MR3 ((unsigned int) 0x00000008)
3036 #define TMR_TMR32B0IR_CR0_MASK ((unsigned int) 0x00000010) // Interrupt flag for capture channel 0 event
3037 #define TMR_TMR32B0IR_CR0 ((unsigned int) 0x00000010)
3038 #define TMR_TMR32B0IR_MASK_ALL ((unsigned int) 0x0000001F)
3039
3040 #define TMR_TMR32B0TCR_COUNTERENABLE_MASK ((unsigned int) 0x00000001) // Counter enable
3041 #define TMR_TMR32B0TCR_COUNTERENABLE_ENABLED ((unsigned int) 0x00000001)
3042 #define TMR_TMR32B0TCR_COUNTERENABLE_DISABLED ((unsigned int) 0x00000000)
3043 #define TMR_TMR32B0TCR_COUNTERRESET_MASK ((unsigned int) 0x00000002)
3044 #define TMR_TMR32B0TCR_COUNTERRESET_ENABLED ((unsigned int) 0x00000002)
3045 #define TMR_TMR32B0TCR_COUNTERRESET_DISABLED ((unsigned int) 0x00000000)
3046
3047 #define TMR_TMR32B0MCR_MR0_INT_MASK ((unsigned int) 0x00000001) // Interrupt on MRO
3048 #define TMR_TMR32B0MCR_MR0_INT_ENABLED ((unsigned int) 0x00000001)
3049 #define TMR_TMR32B0MCR_MR0_INT_DISABLED ((unsigned int) 0x00000000)
3050 #define TMR_TMR32B0MCR_MR0_RESET_MASK ((unsigned int) 0x00000002) // Reset on MR0
3051 #define TMR_TMR32B0MCR_MR0_RESET_ENABLED ((unsigned int) 0x00000002)
3052 #define TMR_TMR32B0MCR_MR0_RESET_DISABLED ((unsigned int) 0x00000000)
3053 #define TMR_TMR32B0MCR_MR0_STOP_MASK ((unsigned int) 0x00000004) // Stop on MR0
3054 #define TMR_TMR32B0MCR_MR0_STOP_ENABLED ((unsigned int) 0x00000004)
3055 #define TMR_TMR32B0MCR_MR0_STOP_DISABLED ((unsigned int) 0x00000000)
3056 #define TMR_TMR32B0MCR_MR1_INT_MASK ((unsigned int) 0x00000008) // Interrupt on MR1
3057 #define TMR_TMR32B0MCR_MR1_INT_ENABLED ((unsigned int) 0x00000008)
3058 #define TMR_TMR32B0MCR_MR1_INT_DISABLED ((unsigned int) 0x00000000)
3059 #define TMR_TMR32B0MCR_MR1_RESET_MASK ((unsigned int) 0x00000010) // Reset on MR1
3060 #define TMR_TMR32B0MCR_MR1_RESET_ENABLED ((unsigned int) 0x00000010)
3061 #define TMR_TMR32B0MCR_MR1_RESET_DISABLED ((unsigned int) 0x00000000)
3062 #define TMR_TMR32B0MCR_MR1_STOP_MASK ((unsigned int) 0x00000020) // Stop on MR1
3063 #define TMR_TMR32B0MCR_MR1_STOP_ENABLED ((unsigned int) 0x00000020)
3064 #define TMR_TMR32B0MCR_MR1_STOP_DISABLED ((unsigned int) 0x00000000)
3065 #define TMR_TMR32B0MCR_MR2_INT_MASK ((unsigned int) 0x00000040) // Interrupt on MR2
3066 #define TMR_TMR32B0MCR_MR2_INT_ENABLED ((unsigned int) 0x00000040)
3067 #define TMR_TMR32B0MCR_MR2_INT_DISABLED ((unsigned int) 0x00000000)
3068 #define TMR_TMR32B0MCR_MR2_RESET_MASK ((unsigned int) 0x00000080) // Reset on MR2
3069 #define TMR_TMR32B0MCR_MR2_RESET_ENABLED ((unsigned int) 0x00000080)
3070 #define TMR_TMR32B0MCR_MR2_RESET_DISABLED ((unsigned int) 0x00000000)
3071 #define TMR_TMR32B0MCR_MR2_STOP_MASK ((unsigned int) 0x00000100) // Stop on MR2
3072 #define TMR_TMR32B0MCR_MR2_STOP_ENABLED ((unsigned int) 0x00000100)
3073 #define TMR_TMR32B0MCR_MR2_STOP_DISABLED ((unsigned int) 0x00000000)
3074 #define TMR_TMR32B0MCR_MR3_INT_MASK ((unsigned int) 0x00000200) // Interrupt on MR3
3075 #define TMR_TMR32B0MCR_MR3_INT_ENABLED ((unsigned int) 0x00000200)
3076 #define TMR_TMR32B0MCR_MR3_INT_DISABLED ((unsigned int) 0x00000000)
3077 #define TMR_TMR32B0MCR_MR3_RESET_MASK ((unsigned int) 0x00000400) // Reset on MR3
3078 #define TMR_TMR32B0MCR_MR3_RESET_ENABLED ((unsigned int) 0x00000400)
3079 #define TMR_TMR32B0MCR_MR3_RESET_DISABLED ((unsigned int) 0x00000000)
3080 #define TMR_TMR32B0MCR_MR3_STOP_MASK ((unsigned int) 0x00000800) // Stop on MR3
3081 #define TMR_TMR32B0MCR_MR3_STOP_ENABLED ((unsigned int) 0x00000800)
3082 #define TMR_TMR32B0MCR_MR3_STOP_DISABLED ((unsigned int) 0x00000000)
3083
3084 #define TMR_TMR32B0CCR_CAP0RE_MASK ((unsigned int) 0x00000001) // Capture on rising edge
3085 #define TMR_TMR32B0CCR_CAP0RE_ENABLED ((unsigned int) 0x00000001)
3086 #define TMR_TMR32B0CCR_CAP0RE_DISABLED ((unsigned int) 0x00000000)
3087 #define TMR_TMR32B0CCR_CAP0FE_MASK ((unsigned int) 0x00000002) // Capture on falling edge
3088 #define TMR_TMR32B0CCR_CAP0FE_ENABLED ((unsigned int) 0x00000002)
3089 #define TMR_TMR32B0CCR_CAP0FE_DISABLED ((unsigned int) 0x00000000)
3090 #define TMR_TMR32B0CCR_CAP0I_MASK ((unsigned int) 0x00000004) // Interrupt on CAP0 event
3091 #define TMR_TMR32B0CCR_CAP0I_ENABLED ((unsigned int) 0x00000004)
3092 #define TMR_TMR32B0CCR_CAP0I_DISABLED ((unsigned int) 0x00000000)
3093
3094 #define TMR_TMR32B0EMR_EM0_MASK ((unsigned int) 0x00000001) // External match 0
3095 #define TMR_TMR32B0EMR_EM0 ((unsigned int) 0x00000001)
3096 #define TMR_TMR32B0EMR_EMC0_MASK ((unsigned int) 0x00000030)
3097 #define TMR_TMR32B0EMR_EMC0_DONOTHING ((unsigned int) 0x00000000)
3098 #define TMR_TMR32B0EMR_EMC0_LOW ((unsigned int) 0x00000010)
3099 #define TMR_TMR32B0EMR_EMC0_HIGH ((unsigned int) 0x00000020)
3100 #define TMR_TMR32B0EMR_EMC0_TOGGLE ((unsigned int) 0x00000030)
3101 #define TMR_TMR32B0EMR_EM1_MASK ((unsigned int) 0x00000002) // External match 1
3102 #define TMR_TMR32B0EMR_EM1 ((unsigned int) 0x00000002)
3103 #define TMR_TMR32B0EMR_EMC1_MASK ((unsigned int) 0x000000C0)
3104 #define TMR_TMR32B0EMR_EMC1_DONOTHING ((unsigned int) 0x00000000)
3105 #define TMR_TMR32B0EMR_EMC1_LOW ((unsigned int) 0x00000040)
3106 #define TMR_TMR32B0EMR_EMC1_HIGH ((unsigned int) 0x00000080)
3107 #define TMR_TMR32B0EMR_EMC1_TOGGLE ((unsigned int) 0x000000C0)
3108 #define TMR_TMR32B0EMR_EM2_MASK ((unsigned int) 0x00000004) // External match 2
3109 #define TMR_TMR32B0EMR_EM2 ((unsigned int) 0x00000004)
3110 #define TMR_TMR32B0EMR_EMC2_MASK ((unsigned int) 0x00000300)
3111 #define TMR_TMR32B0EMR_EMC2_DONOTHING ((unsigned int) 0x00000000)
3112 #define TMR_TMR32B0EMR_EMC2_LOW ((unsigned int) 0x00000100)
3113 #define TMR_TMR32B0EMR_EMC2_HIGH ((unsigned int) 0x00000200)
3114 #define TMR_TMR32B0EMR_EMC2_TOGGLE ((unsigned int) 0x00000300)
3115 #define TMR_TMR32B0EMR_EM3_MASK ((unsigned int) 0x00000008) // External match 3
3116 #define TMR_TMR32B0EMR_EM3 ((unsigned int) 0x00000008)
3117 #define TMR_TMR32B0EMR_EMC3_MASK ((unsigned int) 0x00000C00)
3118 #define TMR_TMR32B0EMR_EMC3_DONOTHING ((unsigned int) 0x00000000)
3119 #define TMR_TMR32B0EMR_EMC3_LOW ((unsigned int) 0x00000400)
3120 #define TMR_TMR32B0EMR_EMC3_HIGH ((unsigned int) 0x00000800)
3121 #define TMR_TMR32B0EMR_EMC3_TOGGLE ((unsigned int) 0x00000C00)
3122
3123 #define TMR_TMR32B0CTCR_CTMODE_MASK ((unsigned int) 0x00000003) // Counter/Timer mode
3124 #define TMR_TMR32B0CTCR_CTMODE_TIMER ((unsigned int) 0x00000000) // Timer Mode: Every rising PCLK edge
3125 #define TMR_TMR32B0CTCR_CTMODE_COUNTERRISING ((unsigned int) 0x00000001) // Counter: TC increments on rising edge of input
3126 #define TMR_TMR32B0CTCR_CTMODE_COUNTERFALLING ((unsigned int) 0x00000002) // Counter: TC increments on falling edge of input
3127 #define TMR_TMR32B0CTCR_CTMODE_COUNTERBOTH ((unsigned int) 0x00000003) // Counter: TC increments on both edges of input
3128 #define TMR_TMR32B0CTCR_CINPUTSELECT_MASK ((unsigned int) 0x0000000C)
3129 #define TMR_TMR32B0CTCR_CINPUTSELECT ((unsigned int) 0x00000000) // CINPUTSELECT must be set to 00
3130
3131 #define TMR_TMR32B0PWMC_PWM0_MASK ((unsigned int) 0x00000001)
3132 #define TMR_TMR32B0PWMC_PWM0_ENABLED ((unsigned int) 0x00000001) // PWM mode is enabled for CT32Bn_MAT0
3133 #define TMR_TMR32B0PWMC_PWM0_DISABLED ((unsigned int) 0x00000000)
3134 #define TMR_TMR32B0PWMC_PWM1_MASK ((unsigned int) 0x00000002)
3135 #define TMR_TMR32B0PWMC_PWM1_ENABLED ((unsigned int) 0x00000002) // PWM mode is enabled for CT32Bn_MAT1
3136 #define TMR_TMR32B0PWMC_PWM1_DISABLED ((unsigned int) 0x00000000)
3137 #define TMR_TMR32B0PWMC_PWM2_MASK ((unsigned int) 0x00000004)
3138 #define TMR_TMR32B0PWMC_PWM2_ENABLED ((unsigned int) 0x00000004) // PWM mode is enabled for CT32Bn_MAT2
3139 #define TMR_TMR32B0PWMC_PWM2_DISABLED ((unsigned int) 0x00000000)
3140 #define TMR_TMR32B0PWMC_PWM3_MASK ((unsigned int) 0x00000008)
3141 #define TMR_TMR32B0PWMC_PWM3_ENABLED ((unsigned int) 0x00000008) // PWM mode is enabled for CT32Bn_MAT3
3142 #define TMR_TMR32B0PWMC_PWM3_DISABLED ((unsigned int) 0x00000000)
3143
3144 #define TMR_CT32B1_BASE_ADDRESS (0x40018000)
3145
3146 #define TMR_TMR32B1IR (*(pREG32 (0x40018000))) // Interrupt register
3147 #define TMR_TMR32B1TCR (*(pREG32 (0x40018004))) // Timer control register
3148 #define TMR_TMR32B1TC (*(pREG32 (0x40018008))) // Timer counter
3149 #define TMR_TMR32B1PR (*(pREG32 (0x4001800C))) // Prescale register
3150 #define TMR_TMR32B1PC (*(pREG32 (0x40018010))) // Prescale counter register
3151 #define TMR_TMR32B1MCR (*(pREG32 (0x40018014))) // Match control register
3152 #define TMR_TMR32B1MR0 (*(pREG32 (0x40018018))) // Match register 0
3153 #define TMR_TMR32B1MR1 (*(pREG32 (0x4001801C))) // Match register 1
3154 #define TMR_TMR32B1MR2 (*(pREG32 (0x40018020))) // Match register 2
3155 #define TMR_TMR32B1MR3 (*(pREG32 (0x40018024))) // Match register 3
3156 #define TMR_TMR32B1CCR (*(pREG32 (0x40018028))) // Capture control register
3157 #define TMR_TMR32B1CR0 (*(pREG32 (0x4001802C))) // Capture register
3158 #define TMR_TMR32B1EMR (*(pREG32 (0x4001803C))) // External match register
3159 #define TMR_TMR32B1CTCR (*(pREG32 (0x40018070))) // Count control register
3160 #define TMR_TMR32B1PWMC (*(pREG32 (0x40018074))) // PWM control register
3161
3162 #define TMR_TMR32B1IR_MR0_MASK ((unsigned int) 0x00000001) // Interrupt flag for match channel 0
3163 #define TMR_TMR32B1IR_MR0 ((unsigned int) 0x00000001)
3164 #define TMR_TMR32B1IR_MR1_MASK ((unsigned int) 0x00000002) // Interrupt flag for match channel 1
3165 #define TMR_TMR32B1IR_MR1 ((unsigned int) 0x00000002)
3166 #define TMR_TMR32B1IR_MR2_MASK ((unsigned int) 0x00000004) // Interrupt flag for match channel 2
3167 #define TMR_TMR32B1IR_MR2 ((unsigned int) 0x00000004)
3168 #define TMR_TMR32B1IR_MR3_MASK ((unsigned int) 0x00000008) // Interrupt flag for match channel 3
3169 #define TMR_TMR32B1IR_MR3 ((unsigned int) 0x00000008)
3170 #define TMR_TMR32B1IR_CR0_MASK ((unsigned int) 0x00000010) // Interrupt flag for capture channel 0 event
3171 #define TMR_TMR32B1IR_CR0 ((unsigned int) 0x00000010)
3172 #define TMR_TMR32B1IR_MASK_ALL ((unsigned int) 0x0000001F)
3173
3174 #define TMR_TMR32B1TCR_COUNTERENABLE_MASK ((unsigned int) 0x00000001) // Counter enable
3175 #define TMR_TMR32B1TCR_COUNTERENABLE_ENABLED ((unsigned int) 0x00000001)
3176 #define TMR_TMR32B1TCR_COUNTERENABLE_DISABLED ((unsigned int) 0x00000000)
3177 #define TMR_TMR32B1TCR_COUNTERRESET_MASK ((unsigned int) 0x00000002)
3178 #define TMR_TMR32B1TCR_COUNTERRESET_ENABLED ((unsigned int) 0x00000002)
3179 #define TMR_TMR32B1TCR_COUNTERRESET_DISABLED ((unsigned int) 0x00000000)
3180
3181 #define TMR_TMR32B1MCR_MR0_INT_MASK ((unsigned int) 0x00000001) // Interrupt on MRO
3182 #define TMR_TMR32B1MCR_MR0_INT_ENABLED ((unsigned int) 0x00000001)
3183 #define TMR_TMR32B1MCR_MR0_INT_DISABLED ((unsigned int) 0x00000000)
3184 #define TMR_TMR32B1MCR_MR0_RESET_MASK ((unsigned int) 0x00000002) // Reset on MR0
3185 #define TMR_TMR32B1MCR_MR0_RESET_ENABLED ((unsigned int) 0x00000002)
3186 #define TMR_TMR32B1MCR_MR0_RESET_DISABLED ((unsigned int) 0x00000000)
3187 #define TMR_TMR32B1MCR_MR0_STOP_MASK ((unsigned int) 0x00000004) // Stop on MR0
3188 #define TMR_TMR32B1MCR_MR0_STOP_ENABLED ((unsigned int) 0x00000004)
3189 #define TMR_TMR32B1MCR_MR0_STOP_DISABLED ((unsigned int) 0x00000000)
3190 #define TMR_TMR32B1MCR_MR1_INT_MASK ((unsigned int) 0x00000008) // Interrupt on MR1
3191 #define TMR_TMR32B1MCR_MR1_INT_ENABLED ((unsigned int) 0x00000008)
3192 #define TMR_TMR32B1MCR_MR1_INT_DISABLED ((unsigned int) 0x00000000)
3193 #define TMR_TMR32B1MCR_MR1_RESET_MASK ((unsigned int) 0x00000010) // Reset on MR1
3194 #define TMR_TMR32B1MCR_MR1_RESET_ENABLED ((unsigned int) 0x00000010)
3195 #define TMR_TMR32B1MCR_MR1_RESET_DISABLED ((unsigned int) 0x00000000)
3196 #define TMR_TMR32B1MCR_MR1_STOP_MASK ((unsigned int) 0x00000020) // Stop on MR1
3197 #define TMR_TMR32B1MCR_MR1_STOP_ENABLED ((unsigned int) 0x00000020)
3198 #define TMR_TMR32B1MCR_MR1_STOP_DISABLED ((unsigned int) 0x00000000)
3199 #define TMR_TMR32B1MCR_MR2_INT_MASK ((unsigned int) 0x00000040) // Interrupt on MR2
3200 #define TMR_TMR32B1MCR_MR2_INT_ENABLED ((unsigned int) 0x00000040)
3201 #define TMR_TMR32B1MCR_MR2_INT_DISABLED ((unsigned int) 0x00000000)
3202 #define TMR_TMR32B1MCR_MR2_RESET_MASK ((unsigned int) 0x00000080) // Reset on MR2
3203 #define TMR_TMR32B1MCR_MR2_RESET_ENABLED ((unsigned int) 0x00000080)
3204 #define TMR_TMR32B1MCR_MR2_RESET_DISABLED ((unsigned int) 0x00000000)
3205 #define TMR_TMR32B1MCR_MR2_STOP_MASK ((unsigned int) 0x00000100) // Stop on MR2
3206 #define TMR_TMR32B1MCR_MR2_STOP_ENABLED ((unsigned int) 0x00000100)
3207 #define TMR_TMR32B1MCR_MR2_STOP_DISABLED ((unsigned int) 0x00000000)
3208 #define TMR_TMR32B1MCR_MR3_INT_MASK ((unsigned int) 0x00000200) // Interrupt on MR3
3209 #define TMR_TMR32B1MCR_MR3_INT_ENABLED ((unsigned int) 0x00000200)
3210 #define TMR_TMR32B1MCR_MR3_INT_DISABLED ((unsigned int) 0x00000000)
3211 #define TMR_TMR32B1MCR_MR3_RESET_MASK ((unsigned int) 0x00000400) // Reset on MR3
3212 #define TMR_TMR32B1MCR_MR3_RESET_ENABLED ((unsigned int) 0x00000400)
3213 #define TMR_TMR32B1MCR_MR3_RESET_DISABLED ((unsigned int) 0x00000000)
3214 #define TMR_TMR32B1MCR_MR3_STOP_MASK ((unsigned int) 0x00000800) // Stop on MR3
3215 #define TMR_TMR32B1MCR_MR3_STOP_ENABLED ((unsigned int) 0x00000800)
3216 #define TMR_TMR32B1MCR_MR3_STOP_DISABLED ((unsigned int) 0x00000000)
3217
3218 #define TMR_TMR32B1CCR_CAP0RE_MASK ((unsigned int) 0x00000001) // Capture on rising edge
3219 #define TMR_TMR32B1CCR_CAP0RE_ENABLED ((unsigned int) 0x00000001)
3220 #define TMR_TMR32B1CCR_CAP0RE_DISABLED ((unsigned int) 0x00000000)
3221 #define TMR_TMR32B1CCR_CAP0FE_MASK ((unsigned int) 0x00000002) // Capture on falling edge
3222 #define TMR_TMR32B1CCR_CAP0FE_ENABLED ((unsigned int) 0x00000002)
3223 #define TMR_TMR32B1CCR_CAP0FE_DISABLED ((unsigned int) 0x00000000)
3224 #define TMR_TMR32B1CCR_CAP0I_MASK ((unsigned int) 0x00000004) // Interrupt on CAP0 event
3225 #define TMR_TMR32B1CCR_CAP0I_ENABLED ((unsigned int) 0x00000004)
3226 #define TMR_TMR32B1CCR_CAP0I_DISABLED ((unsigned int) 0x00000000)
3227
3228 #define TMR_TMR32B1EMR_EM0_MASK ((unsigned int) 0x00000001) // External match 0
3229 #define TMR_TMR32B1EMR_EM0 ((unsigned int) 0x00000001)
3230 #define TMR_TMR32B1EMR_EMC0_MASK ((unsigned int) 0x00000030)
3231 #define TMR_TMR32B1EMR_EMC0_DONOTHING ((unsigned int) 0x00000000)
3232 #define TMR_TMR32B1EMR_EMC0_LOW ((unsigned int) 0x00000010)
3233 #define TMR_TMR32B1EMR_EMC0_HIGH ((unsigned int) 0x00000020)
3234 #define TMR_TMR32B1EMR_EMC0_TOGGLE ((unsigned int) 0x00000030)
3235 #define TMR_TMR32B1EMR_EM1_MASK ((unsigned int) 0x00000002) // External match 1
3236 #define TMR_TMR32B1EMR_EM1 ((unsigned int) 0x00000002)
3237 #define TMR_TMR32B1EMR_EMC1_MASK ((unsigned int) 0x000000C0)
3238 #define TMR_TMR32B1EMR_EMC1_DONOTHING ((unsigned int) 0x00000000)
3239 #define TMR_TMR32B1EMR_EMC1_LOW ((unsigned int) 0x00000040)
3240 #define TMR_TMR32B1EMR_EMC1_HIGH ((unsigned int) 0x00000080)
3241 #define TMR_TMR32B1EMR_EMC1_TOGGLE ((unsigned int) 0x000000C0)
3242 #define TMR_TMR32B1EMR_EM2_MASK ((unsigned int) 0x00000004) // External match 2
3243 #define TMR_TMR32B1EMR_EM2 ((unsigned int) 0x00000004)
3244 #define TMR_TMR32B1EMR_EMC2_MASK ((unsigned int) 0x00000300)
3245 #define TMR_TMR32B1EMR_EMC2_DONOTHING ((unsigned int) 0x00000000)
3246 #define TMR_TMR32B1EMR_EMC2_LOW ((unsigned int) 0x00000100)
3247 #define TMR_TMR32B1EMR_EMC2_HIGH ((unsigned int) 0x00000200)
3248 #define TMR_TMR32B1EMR_EMC2_TOGGLE ((unsigned int) 0x00000300)
3249 #define TMR_TMR32B1EMR_EM3_MASK ((unsigned int) 0x00000008) // External match 3
3250 #define TMR_TMR32B1EMR_EM3 ((unsigned int) 0x00000008)
3251 #define TMR_TMR32B1EMR_EMC3_MASK ((unsigned int) 0x00000C00)
3252 #define TMR_TMR32B1EMR_EMC3_DONOTHING ((unsigned int) 0x00000000)
3253 #define TMR_TMR32B1EMR_EMC3_LOW ((unsigned int) 0x00000400)
3254 #define TMR_TMR32B1EMR_EMC3_HIGH ((unsigned int) 0x00000800)
3255 #define TMR_TMR32B1EMR_EMC3_TOGGLE ((unsigned int) 0x00000C00)
3256
3257 #define TMR_TMR32B1CTCR_CTMODE_MASK ((unsigned int) 0x00000003) // Counter/Timer mode
3258 #define TMR_TMR32B1CTCR_CTMODE_TIMER ((unsigned int) 0x00000000) // Timer Mode: Every rising PCLK edge
3259 #define TMR_TMR32B1CTCR_CTMODE_COUNTERRISING ((unsigned int) 0x00000001) // Counter: TC increments on rising edge of input
3260 #define TMR_TMR32B1CTCR_CTMODE_COUNTERFALLING ((unsigned int) 0x00000002) // Counter: TC increments on falling edge of input
3261 #define TMR_TMR32B1CTCR_CTMODE_COUNTERBOTH ((unsigned int) 0x00000003) // Counter: TC increments on both edges of input
3262 #define TMR_TMR32B1CTCR_CINPUTSELECT_MASK ((unsigned int) 0x0000000C)
3263 #define TMR_TMR32B1CTCR_CINPUTSELECT ((unsigned int) 0x00000000) // CINPUTSELECT must be set to 00
3264
3265 #define TMR_TMR32B1PWMC_PWM0_MASK ((unsigned int) 0x00000001)
3266 #define TMR_TMR32B1PWMC_PWM0_ENABLED ((unsigned int) 0x00000001) // PWM mode is enabled for CT32Bn_MAT0
3267 #define TMR_TMR32B1PWMC_PWM0_DISABLED ((unsigned int) 0x00000000)
3268 #define TMR_TMR32B1PWMC_PWM1_MASK ((unsigned int) 0x00000002)
3269 #define TMR_TMR32B1PWMC_PWM1_ENABLED ((unsigned int) 0x00000002) // PWM mode is enabled for CT32Bn_MAT1
3270 #define TMR_TMR32B1PWMC_PWM1_DISABLED ((unsigned int) 0x00000000)
3271 #define TMR_TMR32B1PWMC_PWM2_MASK ((unsigned int) 0x00000004)
3272 #define TMR_TMR32B1PWMC_PWM2_ENABLED ((unsigned int) 0x00000004) // PWM mode is enabled for CT32Bn_MAT2
3273 #define TMR_TMR32B1PWMC_PWM2_DISABLED ((unsigned int) 0x00000000)
3274 #define TMR_TMR32B1PWMC_PWM3_MASK ((unsigned int) 0x00000008)
3275 #define TMR_TMR32B1PWMC_PWM3_ENABLED ((unsigned int) 0x00000008) // PWM mode is enabled for CT32Bn_MAT3
3276 #define TMR_TMR32B1PWMC_PWM3_DISABLED ((unsigned int) 0x00000000)
3277
3278 /*##############################################################################
3279 ## System Tick Timer
3280 ##############################################################################*/
3281
3282 #define SYSTICK_BASE_ADDRESS (0xE000E000)
3283
3284 #define SYSTICK_STCTRL (*(pREG32 (0xE000E010))) // System tick control
3285 #define SYSTICK_STRELOAD (*(pREG32 (0xE000E014))) // System timer reload
3286 #define SYSTICK_STCURR (*(pREG32 (0xE000E018))) // System timer current
3287 #define SYSTICK_STCALIB (*(pREG32 (0xE000E01C))) // System timer calibration
3288
3289 /* STCTRL (System Timer Control and status register)
3290 The STCTRL register contains control information for the System Tick Timer, and provides
3291 a status flag. */
3292
3293 #define SYSTICK_STCTRL_ENABLE (0x00000001) // System tick counter enable
3294 #define SYSTICK_STCTRL_TICKINT (0x00000002) // System tick interrupt enable
3295 #define SYSTICK_STCTRL_CLKSOURCE (0x00000004) // NOTE: This isn't documented but is based on NXP examples
3296 #define SYSTICK_STCTRL_COUNTFLAG (0x00010000) // System tick counter flag
3297
3298 /* STRELOAD (System Timer Reload value register)
3299 The STRELOAD register is set to the value that will be loaded into the System Tick Timer
3300 whenever it counts down to zero. This register is loaded by software as part of timer
3301 initialization. The STCALIB register may be read and used as the value for STRELOAD if
3302 the CPU or external clock is running at the frequency intended for use with the STCALIB
3303 value. */
3304
3305 #define SYSTICK_STRELOAD_MASK (0x00FFFFFF)
3306
3307 /* STCURR (System Timer Current value register)
3308 The STCURR register returns the current count from the System Tick counter when it is
3309 read by software. */
3310
3311 #define SYSTICK_STCURR_MASK (0x00FFFFFF)
3312
3313 /* STCALIB (System Timer Calibration value register) */
3314
3315 #define SYSTICK_STCALIB_TENMS_MASK (0x00FFFFFF)
3316 #define SYSTICK_STCALIB_SKEW_MASK (0x40000000)
3317 #define SYSTICK_STCALIB_NOREF_MASK (0x80000000)
3318
3319 /*##############################################################################
3320 ## ADC
3321 ##############################################################################*/
3322
3323 #define ADC_AD0_BASE_ADDRESS (0x4001C000)
3324
3325 #define ADC_AD0CR (*(pREG32 (0x4001C000))) // ADC Control Register
3326 #define ADC_AD0GDR ((unsigned int) 0x4001C004) // ADC Global Data Register
3327 #define ADC_AD0INTEN ((unsigned int) 0x4001C00C) // ADC Interrupt Enable Register
3328 #define ADC_AD0DR0 ((unsigned int) 0x4001C010) // ADC Data Register 0
3329 #define ADC_AD0DR1 ((unsigned int) 0x4001C014) // ADC Data Register 1
3330 #define ADC_AD0DR2 ((unsigned int) 0x4001C018) // ADC Data Register 2
3331 #define ADC_AD0DR3 ((unsigned int) 0x4001C01C) // ADC Data Register 3
3332 #define ADC_AD0DR4 ((unsigned int) 0x4001C020) // ADC Data Register 4
3333 #define ADC_AD0DR5 ((unsigned int) 0x4001C024) // ADC Data Register 5
3334 #define ADC_AD0DR6 ((unsigned int) 0x4001C028) // ADC Data Register 6
3335 #define ADC_AD0DR7 ((unsigned int) 0x4001C02C) // ADC Data Register 7
3336 #define ADC_AD0STAT ((unsigned int) 0x4001C030) // ADC Status Register
3337
3338 #define ADC_AD0CR_SEL_MASK (0x000000FF)
3339 #define ADC_AD0CR_SEL_AD0 (0x00000001)
3340 #define ADC_AD0CR_SEL_AD1 (0x00000002)
3341 #define ADC_AD0CR_SEL_AD2 (0x00000004)
3342 #define ADC_AD0CR_SEL_AD3 (0x00000008)
3343 #define ADC_AD0CR_SEL_AD4 (0x00000010)
3344 #define ADC_AD0CR_SEL_AD5 (0x00000020)
3345 #define ADC_AD0CR_SEL_AD6 (0x00000040)
3346 #define ADC_AD0CR_SEL_AD7 (0x00000080)
3347 #define ADC_AD0CR_CLKDIV_MASK (0x0000FF00)
3348 #define ADC_AD0CR_BURST_MASK (0x00010000)
3349 #define ADC_AD0CR_BURST_SWMODE (0x00000000)
3350 #define ADC_AD0CR_BURST_HWSCANMODE (0x00010000)
3351 #define ADC_AD0CR_CLKS_MASK (0x000E0000)
3352 #define ADC_AD0CR_CLKS_10BITS (0x00000000)
3353 #define ADC_AD0CR_CLKS_9BITS (0x00020000)
3354 #define ADC_AD0CR_CLKS_8BITS (0x00040000)
3355 #define ADC_AD0CR_CLKS_7BITS (0x00060000)
3356 #define ADC_AD0CR_CLKS_6BITS (0x00080000)
3357 #define ADC_AD0CR_CLKS_5BITS (0x000A0000)
3358 #define ADC_AD0CR_CLKS_4BITS (0x000C0000)
3359 #define ADC_AD0CR_CLKS_3BITS (0x000E0000)
3360 #define ADC_AD0CR_START_MASK (0x07000000)
3361 #define ADC_AD0CR_START_NOSTART (0x00000000)
3362 #define ADC_AD0CR_START_STARTNOW (0x01000000)
3363 #define ADC_AD0CR_EDGE_MASK (0x08000000)
3364 #define ADC_AD0CR_EDGE_FALLING (0x08000000)
3365 #define ADC_AD0CR_EDGE_RISING (0x00000000)
3366
3367 /* AD9GDR (A/D Global Data Register)
3368 The A/D Global Data Register contains the result of the most recent A/D conversion. This
3369 includes the data, DONE, and Overrun flags, and the number of the A/D channel to which
3370 the data relates. */
3371
3372 #define ADC_AD0GDR_RESULT_MASK (0x0000FFC0)
3373 #define ADC_AD0GDR_CHN_MASK (0x07000000) // Channel from which the results were converted
3374 #define ADC_AD0GDR_OVERUN_MASK (0x40000000)
3375 #define ADC_AD0GDR_OVERUN (0x40000000)
3376 #define ADC_AD0GDR_DONE_MASK (0x80000000)
3377 #define ADC_AD0GDR_DONE (0x80000000)
3378
3379 /* AD0STAT (A/D Status Register)
3380 The A/D Status register allows checking the status of all A/D channels simultaneously.
3381 The DONE and OVERRUN flags appearing in the ADDRn register for each A/D channel
3382 are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is also found
3383 in ADSTAT. */
3384
3385 #define ADC_AD0STAT_DONE0_MASK (0x00000001)
3386 #define ADC_AD0STAT_DONE0 (0x00000001)
3387 #define ADC_AD0STAT_DONE1_MASK (0x00000002)
3388 #define ADC_AD0STAT_DONE1 (0x00000002)
3389 #define ADC_AD0STAT_DONE2_MASK (0x00000004)
3390 #define ADC_AD0STAT_DONE2 (0x00000004)
3391 #define ADC_AD0STAT_DONE3_MASK (0x00000008)
3392 #define ADC_AD0STAT_DONE3 (0x00000008)
3393 #define ADC_AD0STAT_DONE4_MASK (0x00000010)
3394 #define ADC_AD0STAT_DONE4 (0x00000010)
3395 #define ADC_AD0STAT_DONE5_MASK (0x00000020)
3396 #define ADC_AD0STAT_DONE5 (0x00000020)
3397 #define ADC_AD0STAT_DONE6_MASK (0x00000040)
3398 #define ADC_AD0STAT_DONE6 (0x00000040)
3399 #define ADC_AD0STAT_DONE7_MASK (0x00000080)
3400 #define ADC_AD0STAT_DONE7 (0x00000080)
3401 #define ADC_AD0STAT_OVERRUN0_MASK (0x00000100)
3402 #define ADC_AD0STAT_OVERRUN0 (0x00000100)
3403 #define ADC_AD0STAT_OVERRUN1_MASK (0x00000200)
3404 #define ADC_AD0STAT_OVERRUN1 (0x00000200)
3405 #define ADC_AD0STAT_OVERRUN2_MASK (0x00000400)
3406 #define ADC_AD0STAT_OVERRUN2 (0x00000400)
3407 #define ADC_AD0STAT_OVERRUN3_MASK (0x00000800)
3408 #define ADC_AD0STAT_OVERRUN3 (0x00000800)
3409 #define ADC_AD0STAT_OVERRUN4_MASK (0x00001000)
3410 #define ADC_AD0STAT_OVERRUN4 (0x00001000)
3411 #define ADC_AD0STAT_OVERRUN5_MASK (0x00002000)
3412 #define ADC_AD0STAT_OVERRUN5 (0x00002000)
3413 #define ADC_AD0STAT_OVERRUN6_MASK (0x00004000)
3414 #define ADC_AD0STAT_OVERRUN6 (0x00004000)
3415 #define ADC_AD0STAT_OVERRUN7_MASK (0x00008000)
3416 #define ADC_AD0STAT_OVERRUN7 (0x00008000)
3417 #define ADC_AD0STAT_ADINT_MASK (0x00010000)
3418 #define ADC_AD0STAT_ADINT (0x00010000)
3419
3420 /* ADINTEN0 (A/D Interrupt Enable Register)
3421 This register allows control over which A/D channels generate an interrupt when a
3422 conversion is complete. For example, it may be desirable to use some A/D channels to
3423 monitor sensors by continuously performing conversions on them. The most recent
3424 results are read by the application program whenever they are needed. In this case, an
3425 interrupt is not desirable at the end of each conversion for some A/D channels. */
3426
3427 #define ADC_AD0INTEN_ADINTEN0_MASK (0x00000001)
3428 #define ADC_AD0INTEN_ADINTEN0 (0x00000001)
3429 #define ADC_AD0INTEN_ADINTEN1_MASK (0x00000002)
3430 #define ADC_AD0INTEN_ADINTEN1 (0x00000002)
3431 #define ADC_AD0INTEN_ADINTEN2_MASK (0x00000004)
3432 #define ADC_AD0INTEN_ADINTEN2 (0x00000004)
3433 #define ADC_AD0INTEN_ADINTEN3_MASK (0x00000008)
3434 #define ADC_AD0INTEN_ADINTEN3 (0x00000008)
3435 #define ADC_AD0INTEN_ADINTEN4_MASK (0x00000010)
3436 #define ADC_AD0INTEN_ADINTEN4 (0x00000010)
3437 #define ADC_AD0INTEN_ADINTEN5_MASK (0x00000020)
3438 #define ADC_AD0INTEN_ADINTEN5 (0x00000020)
3439 #define ADC_AD0INTEN_ADINTEN6_MASK (0x00000040)
3440 #define ADC_AD0INTEN_ADINTEN6 (0x00000040)
3441 #define ADC_AD0INTEN_ADINTEN7_MASK (0x00000080)
3442 #define ADC_AD0INTEN_ADINTEN7 (0x00000080)
3443 #define ADC_AD0INTEN_ADGINTEN_MASK (0x00000100)
3444 #define ADC_AD0INTEN_ADGINTEN_ENABLE (0x00000100)
3445 #define ADC_AD0INTEN_ADGINTEN_DISABLE (0x00000000)
3446
3447 /* AD0DR0..7 (A/D Data Registers)
3448 The A/D Data Register hold the result when an A/D conversion is complete, and also
3449 include the flags that indicate when a conversion has been completed and when a
3450 conversion overrun has occurred. */
3451
3452 #define ADC_DR_V_MASK (0x0000FFC0)
3453 #define ADC_DR_OVERRUN_MASK (0x40000000)
3454 #define ADC_DR_OVERRUN (0x40000000)
3455 #define ADC_DR_DONE_MASK (0x80000000)
3456 #define ADC_DR_DONE (0x80000000)
3457
3458 /*##############################################################################
3459 ## WDT - Watchdog Timer
3460 ##############################################################################*/
3461
3462 #define WDT_BASE_ADDRESS (0x40004000)
3463
3464 #define WDT_WDMOD (*(pREG32 (0x40004000))) // Watchdog mode register
3465 #define WDT_WDTC (*(pREG32 (0x40004004))) // Watchdog timer constant register
3466 #define WDT_WDFEED (*(pREG32 (0x40004008))) // Watchdog feed sequence register
3467 #define WDT_WDTV (*(pREG32 (0x4000400C))) // Watchdog timer value register
3468
3469 /* WDMOD (Watchdog Mode register)
3470 The WDMOD register controls the operation of the Watchdog through the combination of
3471 WDEN and RESET bits. Note that a watchdog feed must be performed before any
3472 changes to the WDMOD register take effect. */
3473
3474 #define WDT_WDMOD_WDEN_DISABLED (0x00000000) // Watchdog enable bit
3475 #define WDT_WDMOD_WDEN_ENABLED (0x00000001)
3476 #define WDT_WDMOD_WDEN_MASK (0x00000001)
3477 #define WDT_WDMOD_WDRESET_DISABLED (0x00000000) // Watchdog reset enable bit
3478 #define WDT_WDMOD_WDRESET_ENABLED (0x00000002)
3479 #define WDT_WDMOD_WDRESET_MASK (0x00000002)
3480 #define WDT_WDMOD_WDTOF (0x00000004) // Watchdog time-out interrupt flag
3481 #define WDT_WDMOD_WDTOF_MASK (0x00000004) // Set when the watchdog times out
3482 #define WDT_WDMOD_WDINT (0x00000008) // Watchdog timer interrupt flag
3483 #define WDT_WDMOD_WDINT_MASK (0x00000008)
3484
3485 /* WDFEED (Watchdog Feed register)
3486 Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the
3487 WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD
3488 register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the
3489 Watchdog. A valid feed sequence must be completed after setting WDEN before the
3490 Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed
3491 errors. After writing 0xAA to WDFEED, access to any Watchdog register other than writing
3492 0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled.
3493 The reset will be generated during the second PCLK following an incorrect access to a
3494 Watchdog register during a feed sequence.
3495 Interrupts should be disabled during the feed sequence. An abort condition will occur if an
3496 interrupt happens during the feed sequence. */
3497
3498 #define WDT_WDFEED_FEED1 (0x000000AA)
3499 #define WDT_WDFEED_FEED2 (0x00000055)
3500
3501 /*##############################################################################
3502 ## Misc. Inline Functions
3503 ##############################################################################*/
3504
3505 /**************************************************************************/
3506 /*!
3507 @brief Reverses the bit order of a 32-bit value
3508
3509 Allows single-cycle reversing of 32-bit values (ASM RBIT)
3510
3511 @param[in] value
3512 The 32-bit value to reverse
3513 @returns The reversed value
3514 */
3515 /**************************************************************************/
3516 static inline uint32_t RBIT(uint32_t value) { uint32_t result=0; __asm volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); return(result); }
3517
3518 /**************************************************************************/
3519 /*!
3520 @brief Causes a system reset and enters the USB Bootloader
3521
3522 Resets the system using the AIRCR register, and waits in a loop until
3523 reset occurs. The resistor/divider on the LPC1343 Reference Design
3524 Base Board [1] causes the AIRCR reset to enter the bootloader rather
3525 than executing the existing firmware. If you wish to reset and execute
3526 the existing firmware, you need to use the watchdog timer to reset
3527 (see "wdt/wdt.c").
3528
3529 [1] http://www.microbuilder.eu/Projects/LPC1343ReferenceDesign.aspx
3530 */
3531 /**************************************************************************/
3532 static inline void __resetBootloader() { __disable_irq(); SCB_AIRCR = SCB_AIRCR_VECTKEY_VALUE | SCB_AIRCR_SYSRESETREQ; while(1); }
3533
3534 #endif
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