target/linux/ifxmips/image/u-boot/files/include/asm-mips/romconfig.h

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * This file contains the configuration parameters for the DANUBE board.
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31
  32 #define EXCEPTION_BASE  0x200
  33
  34 /*****************************************************************************
  35  * DANUBE
  36  *****************************************************************************/
  37 /* lock cache for C program stack */
  38 /* points to ROM */
  39 /* stack size is 16K */
  40 #define LOCK_DCACHE_ADDR        0x9FC00000
  41 #define LOCK_DCACHE_SIZE        0x1000
  42 #define CFG_EBU_BOOTWORD              0x688c688c
  43
  44 #define CFG_HZ       (danube_get_cpuclk() / 2)
  45
  46
  47 /*
  48  * Memory layout
  49  */
  50 //#define CFG_SDRAM_BASE       0x80080000
  51 #define CFG_CACHE_LOCK_SIZE  LOCK_DCACHE_SIZE
  52 #define CFG_INIT_SP_OFFSET   CFG_CACHE_LOCK_SIZE
  53
  54 /*
  55  * Cache settings
  56  */
  57 #define CFG_CACHE_SIZE   16384
  58 #define CFG_CACHE_LINES  32
  59 #define CFG_CACHE_WAYS   4
  60 #define CFG_CACHE_SETS   128
  61
  62 #define CFG_ICACHE_SIZE   CFG_CACHE_SIZE
  63 #define CFG_DCACHE_SIZE   CFG_CACHE_SIZE
  64 #define CFG_CACHELINE_SIZE  CFG_CACHE_LINES
  65
  66 #endif  /* __CONFIG_H */