include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/image.mk
+define Build/Clean
+ $(MAKE) -C u-boot clean
+endef
+
+define Build/Compile
+ $(MAKE) -C u-boot compile
+endef
+
define Image/BuildKernel
$(STAGING_DIR_HOST)/bin/lzma e $(KDIR)/vmlinux $(KDIR)/vmlinux.lzma
mkimage -A mips -O linux -T kernel -a 0x80002000 -C lzma -e \
--- /dev/null
+#
+# Copyright (C) 2008 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=u-boot
+PKG_VERSION:=1.1.5
+PKG_RELEASE:=1
+
+PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
+PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot
+PKG_MD5SUM:=579707c8ecbf1ab4127285d2aac2a9ee
+PKG_CAT:=bzcat
+
+include $(INCLUDE_DIR)/package.mk
+
+define Build/Compile
+ cp -r ./files/* $(PKG_BUILD_DIR)
+ cd $(PKG_BUILD_DIR);chmod a+x build_danube.sh;./build_danube.sh
+endef
+
+define Build/InstallDev
+ dd if=$(PKG_BUILD_DIR)/u-boot.ifx of=$(BIN_DIR)/u-boot.ifx bs=64k conv=sync
+endef
+
+$(eval $(call Build/DefaultTargets))
--- /dev/null
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+SOBJS = lowlevel_init.o pmuenable.o
+
+$(LIB): .depend $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+/*
+** Copyright (C) 2005 Wu Qi Ming <Qi-Ming.Wu@infineon.com>
+**
+** This program is free software; you can redistribute it and/or modify
+** it under the terms of the GNU General Public License as published by
+** the Free Software Foundation; either version 2 of the License, or
+** (at your option) any later version.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+** GNU General Public License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with this program; if not, write to the Free Software
+** Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+*/
+
+To build a u-boot for danube board, user need to do the following things:
+To configure u-boot for a proper board, user need to modify two files accordingly.
+
+To configure u-boot for evaluation board, in danube-uboot/include/configs/danube.h, set
+#define USE_EVALUATION_BOARD
+#undef USE_REFERENCE_BOARD
+and vice-versa.
+
+To let u-boot boot from ebu(flash,e.g), in danube-uboot/include/configus/danube.h, set
+#define DANUBE_BOOT_FROM_EBU
+Otherwise u-boot will be compiled for booting from RAM.
+
+To use DDR RAM running at 111M, in danube-uboot/include/configus/danube.
+h, set
+#define DANUBE_DDR_RAM_111M
+#undef DANUBE_DDR_RAM_166M
+and vice-versa.
+
+To define RAM size of RAM, in danube-uboot/include/configus/danube.
+h, set
+#define RAM_SIZE 0x2000000 /*32M ram*/
+This is an example for a 32M RAM.
+
+
+Besides above settings, user need to change danube-uboot/board/danube/config.mk to set the loading address of u-boot.
+If U-Boot is to boot from EBU(flash), user needs to set
+TEXT_BASE=0xB0000000
+If u-boot is to boot from RAM, user needs to set
+TEXT_BASE=0xa0400000
+
+Use the script gct to build a uart downloadable u-boot image:
+./gct danube_ref_ddr166.conf u-boot.srec u-boot.asc
+
+
+
+
+
--- /dev/null
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Danube board with MIPS 24Kec CPU core
+#boot from ebu
+TEXT_BASE = 0xB0000000
+BOOTSTRAP_TEXT_BASE = 0xB0000000
+
+#boot from ram
+#TEXT_BASE = 0xa0400000
+#TEXT_BASE = 0x807c0000
+
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/addrspace.h>
+#include <asm/danube.h>
+
+#ifdef DANUBE_USE_DDR_RAM
+long int initdram(int board_type)
+{
+ return (1024*1024*DANUBE_DDR_RAM_SIZE);
+}
+#else
+extern uint danube_get_cpuclk(void);
+
+static ulong max_sdram_size(void) /* per Chip Select */
+{
+ /* The only supported SDRAM data width is 16bit.
+ */
+#define CFG_DW 4
+
+ /* The only supported number of SDRAM banks is 4.
+ */
+#define CFG_NB 4
+
+ ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
+ int cols = cfgpb0 & 0xF;
+ int rows = (cfgpb0 & 0xF0) >> 4;
+ ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
+
+ return size;
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'.
+ */
+
+static long int dram_size(long int *base, long int maxsize)
+{
+ volatile long int *addr;
+ ulong cnt, val;
+ ulong save[32]; /* to make test non-destructive */
+ unsigned char i = 0;
+
+ for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ save[i++] = *addr;
+ *addr = ~cnt;
+ }
+
+ /* write 0 to base address */
+ addr = base;
+ save[i] = *addr;
+ *addr = 0;
+
+ /* check at base address */
+ if ((val = *addr) != 0) {
+ *addr = save[i];
+ return (0);
+ }
+
+ for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ val = *addr;
+ *addr = save[--i];
+
+ if (val != (~cnt)) {
+ return (cnt * sizeof (long));
+ }
+ }
+ return (maxsize);
+}
+
+long int initdram(int board_type)
+{
+ int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
+ ulong size, max_size = 0;
+ ulong our_address;
+
+ /* load t9 into our_address */
+ asm volatile ("move %0, $25" : "=r" (our_address) :);
+
+ /* Can't probe for RAM size unless we are running from Flash.
+ * find out whether running from DRAM or Flash.
+ */
+ if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1))
+ {
+ return max_sdram_size();
+ }
+
+ for (cols = 0x8; cols <= 0xC; cols++)
+ {
+ for (rows = 0xB; rows <= 0xD; rows++)
+ {
+ *DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
+ (rows << 4) | cols;
+ size = dram_size((ulong *)CFG_SDRAM_BASE,
+ max_sdram_size());
+
+ if (size > max_size)
+ {
+ best_val = *DANUBE_SDRAM_MC_CFGPB0;
+ max_size = size;
+ }
+ }
+ }
+
+ *DANUBE_SDRAM_MC_CFGPB0 = best_val;
+ return max_size;
+}
+#endif
+
+int checkboard (void)
+{
+ /* No such register in Amazon */
+#if 0
+ unsigned long chipid = *AMAZON_MCD_CHIPID;
+ int part_num;
+
+ puts ("Board: AMAZON ");
+ part_num = AMAZON_MCD_CHIPID_PART_NUMBER_GET(chipid);
+ switch (part_num) {
+ case AMAZON_CHIPID_STANDARD:
+ printf ("Standard Version, ");
+ break;
+ case AMAZON_CHIPID_YANGTSE:
+ printf ("Yangtse Version, ");
+ break;
+ default:
+ printf ("Unknown Part Number 0x%x ", part_num);
+ break;
+ }
+
+ printf ("Chip V1.%ld, ", AMAZON_MCD_CHIPID_VERSION_GET(chipid));
+
+
+ printf("CPU Speed %d MHz\n", danube_get_cpuclk()/1000000);
+
+#endif
+ return 0;
+}
+
+
+/*
+ * Disk On Chip (NAND) Millenium initialization.
+ * The NAND lives in the CS2* space
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+extern void
+nand_probe(ulong physadr);
+
+#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */
+void
+nand_init(void)
+{
+ int devtype;
+ /* Configure EBU */
+//TODO: should we keep this?
+ //Set GPIO23 to be Flash CS1;
+ *DANUBE_GPIO_P1_ALTSEL0 = *DANUBE_GPIO_P1_ALTSEL0 | (1<<7);
+ *DANUBE_GPIO_P1_ALTSEL1 = *DANUBE_GPIO_P1_ALTSEL1 & ~(1<<7);
+ *DANUBE_GPIO_P1_DIR = *DANUBE_GPIO_P1_DIR | (1<<7) ;
+ *DANUBE_GPIO_P1_OD = *DANUBE_GPIO_P1_OD | (1<<7) ;
+
+ *EBU_ADDR_SEL_1 = (NAND_BASE_ADDRESS&0x1fffff00)|0x31;
+ /* byte swap;minimum delay*/
+ *EBU_CON_1 = 0x40C155;
+ *EBU_NAND_CON = 0x000005F3;
+
+ /* Set bus signals to inactive */
+ NAND_READY_CLEAR;
+
+ NAND_CE_CLEAR;
+ nand_probe(NAND_BASE_ADDRESS);
+
+
+
+ //nand_probe(AT91_SMARTMEDIA_BASE);
+}
+#endif
+
+
+
--- /dev/null
+/* Settings for Denali DDR SDRAM controller */\r
+/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */\r
+#define MC_DC0_VALUE 0x1B1B\r
+#define MC_DC1_VALUE 0x0\r
+#define MC_DC2_VALUE 0x0\r
+#define MC_DC3_VALUE 0x0\r
+#define MC_DC4_VALUE 0x0\r
+#define MC_DC5_VALUE 0x200\r
+#define MC_DC6_VALUE 0x605\r
+#define MC_DC7_VALUE 0x303\r
+#define MC_DC8_VALUE 0x102\r
+#define MC_DC9_VALUE 0x70a\r
+#define MC_DC10_VALUE 0x203\r
+#define MC_DC11_VALUE 0xc02\r
+#define MC_DC12_VALUE 0x1C8\r
+#define MC_DC13_VALUE 0x1\r
+#define MC_DC14_VALUE 0x0\r
+#define MC_DC15_VALUE 0xf3c\r
+#define MC_DC16_VALUE 0xC800\r
+#define MC_DC17_VALUE 0xd\r
+#define MC_DC18_VALUE 0x300\r
+#define MC_DC19_VALUE 0x200\r
+#define MC_DC20_VALUE 0xA03\r
+#define MC_DC21_VALUE 0x1d00\r
+#define MC_DC22_VALUE 0x1d1d\r
+#define MC_DC23_VALUE 0x0\r
+#define MC_DC24_VALUE 0x5e /* was 0x7f */\r
+#define MC_DC25_VALUE 0x0\r
+#define MC_DC26_VALUE 0x0\r
+#define MC_DC27_VALUE 0x0\r
+#define MC_DC28_VALUE 0x510\r
+#define MC_DC29_VALUE 0x2d89\r
+#define MC_DC30_VALUE 0x8300\r
+#define MC_DC31_VALUE 0x0\r
+#define MC_DC32_VALUE 0x0\r
+#define MC_DC33_VALUE 0x0\r
+#define MC_DC34_VALUE 0x0\r
+#define MC_DC35_VALUE 0x0\r
+#define MC_DC36_VALUE 0x0\r
+#define MC_DC37_VALUE 0x0\r
+#define MC_DC38_VALUE 0x0\r
+#define MC_DC39_VALUE 0x0\r
+#define MC_DC40_VALUE 0x0\r
+#define MC_DC41_VALUE 0x0\r
+#define MC_DC42_VALUE 0x0\r
+#define MC_DC43_VALUE 0x0\r
+#define MC_DC44_VALUE 0x0\r
+#define MC_DC45_VALUE 0x500\r
+//#define MC_DC45_VALUE 0x400\r
+#define MC_DC46_VALUE 0x0\r
--- /dev/null
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
+#define MC_DC0_VALUE 0x1B1B
+#define MC_DC1_VALUE 0x0
+#define MC_DC2_VALUE 0x0
+#define MC_DC3_VALUE 0x0
+#define MC_DC4_VALUE 0x0
+#define MC_DC5_VALUE 0x200
+#define MC_DC6_VALUE 0x605
+#define MC_DC7_VALUE 0x303
+#define MC_DC8_VALUE 0x102
+#define MC_DC9_VALUE 0x70a
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xc02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xd
+#define MC_DC18_VALUE 0x300
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE 0x1800
+#define MC_DC22_VALUE 0x1818
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x2d89
+#define MC_DC30_VALUE 0x8300
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+//#define MC_DC45_VALUE 0x400
+#define MC_DC46_VALUE 0x0
--- /dev/null
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
+#define MC_DC0_VALUE 0x1B1B
+#define MC_DC1_VALUE 0x0
+#define MC_DC2_VALUE 0x0
+#define MC_DC3_VALUE 0x0
+#define MC_DC4_VALUE 0x0
+#define MC_DC5_VALUE 0x200
+#define MC_DC6_VALUE 0x605
+#define MC_DC7_VALUE 0x303
+#define MC_DC8_VALUE 0x102
+#define MC_DC9_VALUE 0x70a
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xc02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xd
+#define MC_DC18_VALUE 0x300
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE 0x1800
+#define MC_DC22_VALUE 0x1818
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x2d89
+#define MC_DC30_VALUE 0x8300
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+//#define MC_DC45_VALUE 0x400
+#define MC_DC46_VALUE 0x0
--- /dev/null
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
+#define MC_DC0_VALUE 0x1B1B
+#define MC_DC1_VALUE 0x0
+#define MC_DC2_VALUE 0x0
+#define MC_DC3_VALUE 0x0
+#define MC_DC4_VALUE 0x0
+#define MC_DC5_VALUE 0x200
+#define MC_DC6_VALUE 0x605
+#define MC_DC7_VALUE 0x303
+#define MC_DC8_VALUE 0x102
+#define MC_DC9_VALUE 0x70a
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xa02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x0
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xd
+#define MC_DC18_VALUE 0x300
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE 0x1200
+#define MC_DC22_VALUE 0x1212
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x4e20
+#define MC_DC30_VALUE 0x8300
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+//#define MC_DC45_VALUE 0x400
+#define MC_DC46_VALUE 0x0
--- /dev/null
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
+
+#define MC_DC0_VALUE 0x1B1B
+#define MC_DC1_VALUE 0x0
+#define MC_DC2_VALUE 0x0
+#define MC_DC3_VALUE 0x0
+#define MC_DC4_VALUE 0x0
+#define MC_DC5_VALUE 0x200
+#define MC_DC6_VALUE 0x605
+#define MC_DC7_VALUE 0x303
+#define MC_DC8_VALUE 0x102
+#define MC_DC9_VALUE 0x70a
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xc02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xd
+#define MC_DC18_VALUE 0x301
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE 0x1400
+#define MC_DC22_VALUE 0x1414
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x4e /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x2d93
+#define MC_DC30_VALUE 0x8235
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+//#define MC_DC45_VALUE 0x400
+#define MC_DC46_VALUE 0x0
--- /dev/null
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
+#define MC_DC0_VALUE 0x1B1B
+#define MC_DC1_VALUE 0x0
+#define MC_DC2_VALUE 0x0
+#define MC_DC3_VALUE 0x0
+#define MC_DC4_VALUE 0x0
+#define MC_DC5_VALUE 0x200
+#define MC_DC6_VALUE 0x605
+#define MC_DC7_VALUE 0x303
+#define MC_DC8_VALUE 0x102
+#define MC_DC9_VALUE 0x70a
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xc02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xd
+#define MC_DC18_VALUE 0x300
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE 0x1800
+#define MC_DC22_VALUE 0x1818
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x2d89
+#define MC_DC30_VALUE 0x8300
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+//#define MC_DC45_VALUE 0x400
+#define MC_DC46_VALUE 0x0
--- /dev/null
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */
+#define MC_DC0_VALUE 0x1B1B
+#define MC_DC1_VALUE 0x0
+#define MC_DC2_VALUE 0x0
+#define MC_DC3_VALUE 0x0
+#define MC_DC4_VALUE 0x0
+#define MC_DC5_VALUE 0x200
+#define MC_DC6_VALUE 0x605
+#define MC_DC7_VALUE 0x303
+#define MC_DC8_VALUE 0x102
+#define MC_DC9_VALUE 0x70a
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xc02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xd
+#define MC_DC18_VALUE 0x300
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE 0x1800
+#define MC_DC22_VALUE 0x1818
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x2d89
+#define MC_DC30_VALUE 0x8300
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+//#define MC_DC45_VALUE 0x400
+#define MC_DC46_VALUE 0x0
--- /dev/null
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for PSC DDR A2S56D40CTP for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */
+
+#define MC_DC0_VALUE 0x1B1B
+#define MC_DC1_VALUE 0x0
+#define MC_DC2_VALUE 0x0
+#define MC_DC3_VALUE 0x0
+#define MC_DC4_VALUE 0x0
+#define MC_DC5_VALUE 0x200
+#define MC_DC6_VALUE 0x605
+#define MC_DC7_VALUE 0x303
+#define MC_DC8_VALUE 0x102
+#define MC_DC9_VALUE 0x70a
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xc02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xd
+#define MC_DC18_VALUE 0x301
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE 0x1700
+#define MC_DC22_VALUE 0x1717
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x52 /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x4e20
+#define MC_DC30_VALUE 0x8235
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+//#define MC_DC45_VALUE 0x400
+#define MC_DC46_VALUE 0x0
--- /dev/null
+/* Settings for Denali DDR SDRAM controller */\r
+/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */\r
+#define MC_DC0_VALUE 0x1B1B\r
+#define MC_DC1_VALUE 0x0\r
+#define MC_DC2_VALUE 0x0\r
+#define MC_DC3_VALUE 0x0\r
+#define MC_DC4_VALUE 0x0\r
+#define MC_DC5_VALUE 0x200\r
+#define MC_DC6_VALUE 0x605\r
+#define MC_DC7_VALUE 0x303\r
+#define MC_DC8_VALUE 0x102\r
+#define MC_DC9_VALUE 0x70a\r
+#define MC_DC10_VALUE 0x203\r
+#define MC_DC11_VALUE 0xc02\r
+#define MC_DC12_VALUE 0x1C8\r
+#define MC_DC13_VALUE 0x1\r
+#define MC_DC14_VALUE 0x0\r
+#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/\r
+#define MC_DC16_VALUE 0xC800\r
+#define MC_DC17_VALUE 0xd\r
+#define MC_DC18_VALUE 0x300\r
+#define MC_DC19_VALUE 0x200\r
+#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */\r
+#define MC_DC21_VALUE 0x1200\r
+#define MC_DC22_VALUE 0x1212\r
+#define MC_DC23_VALUE 0x0\r
+#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */\r
+#define MC_DC25_VALUE 0x0\r
+#define MC_DC26_VALUE 0x0\r
+#define MC_DC27_VALUE 0x0\r
+#define MC_DC28_VALUE 0x510\r
+#define MC_DC29_VALUE 0x2d89\r
+#define MC_DC30_VALUE 0x8300\r
+#define MC_DC31_VALUE 0x0\r
+#define MC_DC32_VALUE 0x0\r
+#define MC_DC33_VALUE 0x0\r
+#define MC_DC34_VALUE 0x0\r
+#define MC_DC35_VALUE 0x0\r
+#define MC_DC36_VALUE 0x0\r
+#define MC_DC37_VALUE 0x0\r
+#define MC_DC38_VALUE 0x0\r
+#define MC_DC39_VALUE 0x0\r
+#define MC_DC40_VALUE 0x0\r
+#define MC_DC41_VALUE 0x0\r
+#define MC_DC42_VALUE 0x0\r
+#define MC_DC43_VALUE 0x0\r
+#define MC_DC44_VALUE 0x0\r
+#define MC_DC45_VALUE 0x500\r
+//#define MC_DC45_VALUE 0x400\r
+#define MC_DC46_VALUE 0x0\r
--- /dev/null
+/* Settings for Denali DDR SDRAM controller */
+/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */
+#define MC_DC0_VALUE 0x1B1B
+#define MC_DC1_VALUE 0x0
+#define MC_DC2_VALUE 0x0
+#define MC_DC3_VALUE 0x0
+#define MC_DC4_VALUE 0x0
+#define MC_DC5_VALUE 0x200
+#define MC_DC6_VALUE 0x605
+#define MC_DC7_VALUE 0x303
+#define MC_DC8_VALUE 0x102
+#define MC_DC9_VALUE 0x70a
+#define MC_DC10_VALUE 0x203
+#define MC_DC11_VALUE 0xc02
+#define MC_DC12_VALUE 0x1C8
+#define MC_DC13_VALUE 0x1
+#define MC_DC14_VALUE 0x0
+#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/
+#define MC_DC16_VALUE 0xC800
+#define MC_DC17_VALUE 0xd
+#define MC_DC18_VALUE 0x300
+#define MC_DC19_VALUE 0x200
+#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
+#define MC_DC21_VALUE 0xd00
+#define MC_DC22_VALUE 0xd0d
+#define MC_DC23_VALUE 0x0
+#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */
+#define MC_DC25_VALUE 0x0
+#define MC_DC26_VALUE 0x0
+#define MC_DC27_VALUE 0x0
+#define MC_DC28_VALUE 0x510
+#define MC_DC29_VALUE 0x2d89
+#define MC_DC30_VALUE 0x8300
+#define MC_DC31_VALUE 0x0
+#define MC_DC32_VALUE 0x0
+#define MC_DC33_VALUE 0x0
+#define MC_DC34_VALUE 0x0
+#define MC_DC35_VALUE 0x0
+#define MC_DC36_VALUE 0x0
+#define MC_DC37_VALUE 0x0
+#define MC_DC38_VALUE 0x0
+#define MC_DC39_VALUE 0x0
+#define MC_DC40_VALUE 0x0
+#define MC_DC41_VALUE 0x0
+#define MC_DC42_VALUE 0x0
+#define MC_DC43_VALUE 0x0
+#define MC_DC44_VALUE 0x0
+#define MC_DC45_VALUE 0x500
+//#define MC_DC45_VALUE 0x400
+#define MC_DC46_VALUE 0x0
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+//joelin 10/07/2004 for MXIC MX29LV320ABTC-90
+#include <common.h>
+#include <asm/danube.h>
+
+/*
+#ifdef CONFIG_AMAZON
+ #define FLASH_DELAY {int i; \
+ for(i=0;i<800;i++) \
+ *((volatile u32 *)CFG_SDRAM_BASE_UNCACHE); \
+ }
+#else
+ #define FLASH_DELAY
+#endif
+*/
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ * has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+#define FLASH_ID_MASK 0xFFFF
+#else
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+#define FLASH_ID_MASK 0xFFFFFFFF
+#endif
+
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK) // 0xffff8000
+
+#if 0
+#define FLASH_CYCLE1 0x0555
+#define FLASH_CYCLE2 0x02aa
+#else
+#define FLASH_CYCLE1 0x0554 //joelin for MX29LV320AT/B 0x0555
+#define FLASH_CYCLE2 0x02ab //joelin for MX29LV320AT/B 0x02aa
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+ unsigned long size = 0;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { // 1 bank
+ ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; // 0xb0000000, 0xb4000000
+
+ volatile ulong * buscon = (ulong *)
+ ((i == 0) ? DANUBE_EBU_BUSCON0 : DANUBE_EBU_BUSCON1);
+
+ /* Disable write protection */
+// *buscon &= ~AMAZON_EBU_BUSCON0_WRDIS;
+ /* Enable write protection */
+ *buscon |= DANUBE_EBU_BUSCON0_WRDIS;
+
+#if 1
+ memset(&flash_info[i], 0, sizeof(flash_info_t));
+#endif
+
+ flash_info[i].size =
+ flash_get_size((FPW *)flashbase, &flash_info[i]);
+
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
+ i, flash_info[i].size);
+ }
+
+ size += flash_info[i].size;
+ }
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE // TEXT_BASE >= 0xB3000000
+ /* monitor protection ON by default */ /* only use software protection, info->protect[i]=0/1 */
+/* flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+ flash_get_info(CFG_MONITOR_BASE));
+*/
+ flash_protect(FLAG_PROTECT_CLEAR, // clear protect
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+ flash_get_info(CFG_MONITOR_BASE));
+
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH /* 1 */
+ /* ENV protection ON by default */
+/* flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+ flash_get_info(CFG_ENV_ADDR));
+*/
+ flash_protect(FLAG_PROTECT_CLEAR,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+ flash_get_info(CFG_ENV_ADDR));
+
+#endif
+
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+ FPWV *base = (FPWV *)(info->start[0]);
+
+ (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing
+ (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing
+ (*EBU_NAND_CON)=0;
+ /* Put FLASH back in read mode */
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){
+ *base = (FPW)0x00FF00FF; /* Intel Read Mode */
+ asm("SYNC");
+ }
+ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD){
+ *base = (FPW)0x00F000F0; /* AMD Read Mode */
+ asm("SYNC"); //joelin
+ }
+ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX){
+ *base = (FPW)0x00F000F0; /* MXIC Read Mode */
+ asm("SYNC"); //joelin
+ }
+
+ (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing
+ (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ /* set up sector start address table */
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+ && (info->flash_id & FLASH_BTYPE)) {
+ int bootsect_size; /* number of bytes/boot sector */
+ int sect_size; /* number of bytes/regular sector */
+
+ bootsect_size = 0x00002000 * (sizeof(FPW)/2);
+ sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+ /* set sector offsets for bottom boot block type */
+ for (i = 0; i < 8; ++i) {
+ info->start[i] = base + (i * bootsect_size);
+ }
+ for (i = 8; i < info->sector_count; i++) {
+ info->start[i] = base + ((i - 7) * sect_size);
+ }
+ }
+ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+ && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+ int sect_size; /* number of bytes/sector */
+
+ sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+ /* set up sector start address table (uniform sector type) */
+ for( i = 0; i < info->sector_count; i++ )
+ info->start[i] = base + (i * sect_size);
+ }
+ else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+ && ((info->flash_id & FLASH_TYPEMASK)==FLASH_28F128J3A)){
+ int sect_size;
+ sect_size = 0x20000;
+ for(i=0;i < info->sector_count; i++)
+ info->start[i]= base + (i*sect_size);
+ }
+ else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+ && ((info->flash_id & FLASH_TYPEMASK)==FLASH_28F320J3A)){
+ int sect_size;
+ sect_size = 0x20000;
+ for(i=0;i < info->sector_count; i++)
+ info->start[i]= base + (i*sect_size);
+ }
+//joelin add for MX29LV320AB-- SA0~SA7:sector size=8K bytes ,SA9~SA70 :sector size=64k bytes
+ else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX)
+ && ((info->flash_id & FLASH_TYPEMASK)==FLASH_29LV320AB)){
+ int bootsect_size; /* number of bytes/boot sector */
+ int sect_size; /* number of bytes/regular sector */
+
+ bootsect_size = 0x00002000 * (sizeof(FPW)/2);
+ sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+ /* set sector offsets for bottom boot block type */
+ for (i = 0; i < 8; ++i) {
+ info->start[i] = base + (i * bootsect_size);
+ }
+ for (i = 8; i < info->sector_count; i++) {
+ info->start[i] = base + ((i - 7) * sect_size);
+ }
+ }
+//joelin add for MX29LV160BB-- SA0=16K,SA1,SA2=8K,SA3=32K bytes ,SA4~SA34 :sector size=64k bytes
+ else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX)
+ && ((info->flash_id & FLASH_TYPEMASK)==FLASH_29LV160BB)){
+ int bootsect_size; /* number of bytes/boot sector */
+ int sect_size; /* number of bytes/regular sector */
+
+ bootsect_size = 0x00002000 * (sizeof(FPW)/2);
+ sect_size = 0x00010000 * (sizeof(FPW)/2);
+/* set sector offsets for bottom boot block type */
+//MX29LV160BB
+ info->start[0] = base ; //SA0=16K bytes
+ info->start[1] = info->start[0] + (1 * 0x00004000 * (sizeof(FPW)/2)); //SA1=8K bytes
+ info->start[2] = info->start[1] + (1 * 0x00002000 * (sizeof(FPW)/2)); //SA2=8K bytes
+ info->start[3] = info->start[2] + (1 * 0x00002000 * (sizeof(FPW)/2)); //SA3=32K bytes
+
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + ((i - 3) * sect_size);
+ }
+ }
+//liupeng add for MX29LV640BB-- SA0~SA7:sector size=8k bytes ,SA8~SA134 :sector size=64k bytes
+ else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX)
+ && ((info->flash_id & FLASH_TYPEMASK)==FLASH_29LV640BB)){
+ int bootsect_size; /* number of bytes/boot sector */
+ int sect_size; /* number of bytes/regular sector */
+
+ bootsect_size = 0x00002000 * (sizeof(FPW)/2);
+ sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+ /* set sector offsets for bottom boot block type */
+ for (i = 0; i < 8; ++i) {
+ info->start[i] = base + (i * bootsect_size);
+ }
+ for (i = 8; i < info->sector_count; i++) {
+ info->start[i] = base + ((i - 7) * sect_size);
+ }
+ }
+ else{
+ printf("flash get offsets fail\n");
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+ int i;
+ flash_info_t * info;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+ info = & flash_info[i];
+ if (info->start[0] <= base && base < info->start[0] + info->size)
+ break;
+ }
+
+ return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+ uchar *boottype;
+ uchar *bootletter;
+ uchar *fmt;
+ uchar botbootletter[] = "B";
+ uchar topbootletter[] = "T";
+ uchar botboottype[] = "bottom boot sector";
+ uchar topboottype[] = "top boot sector";
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
+ case FLASH_MAN_SST: printf ("SST "); break;
+ case FLASH_MAN_STM: printf ("STM "); break;
+ case FLASH_MAN_INTEL: printf ("INTEL "); break;
+ case FLASH_MAN_MX: printf ("MXIC "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ /* check for top or bottom boot, if it applies */
+ if (info->flash_id & FLASH_BTYPE) {
+ boottype = botboottype;
+ bootletter = botbootletter;
+ }
+ else {
+ boottype = topboottype;
+ bootletter = topbootletter;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM640U:
+ fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+ break;
+ case FLASH_28F800C3B:
+ case FLASH_28F800C3T:
+ fmt = "28F800C3%s (8 Mbit, %s)\n";
+ break;
+ case FLASH_INTEL800B:
+ case FLASH_INTEL800T:
+ fmt = "28F800B3%s (8 Mbit, %s)\n";
+ break;
+ case FLASH_28F160C3B:
+ case FLASH_28F160C3T:
+ fmt = "28F160C3%s (16 Mbit, %s)\n";
+ break;
+ case FLASH_INTEL160B:
+ case FLASH_INTEL160T:
+ fmt = "28F160B3%s (16 Mbit, %s)\n";
+ break;
+ case FLASH_28F320C3B:
+ case FLASH_28F320C3T:
+ fmt = "28F320C3%s (32 Mbit, %s)\n";
+ break;
+ case FLASH_INTEL320B:
+ case FLASH_INTEL320T:
+ fmt = "28F320B3%s (32 Mbit, %s)\n";
+ break;
+ case FLASH_28F640C3B:
+ case FLASH_28F640C3T:
+ fmt = "28F640C3%s (64 Mbit, %s)\n";
+ break;
+ case FLASH_INTEL640B:
+ case FLASH_INTEL640T:
+ fmt = "28F640B3%s (64 Mbit, %s)\n";
+ break;
+ case FLASH_28F128J3A:
+ fmt = "28F128J3A (128 Mbit, 128 uniform sectors)\n";
+ break;
+ case FLASH_28F320J3A:
+ fmt = "28F320J3A (32 Mbit, 32 uniform sectors)\n";
+ break;
+ case FLASH_29LV640BB: //liupeng for MXIC FLASH_29LV640BB
+ fmt = "29LV640BB (64 Mbit, boot sector SA0~SA126 size 64k bytes,other sectors SA127~SA135 size 8k bytes)\n";
+ break;
+ case FLASH_29LV320AB: //joelin for MXIC FLASH_29LV320AB
+ fmt = "29LV320AB (32 Mbit, boot sector SA0~SA7 size 8K bytes,other sectors SA8~SA70 size 64K bytes)\n";
+ break;
+ case FLASH_29LV160BB: //joelin for MXIC FLASH_29LV160BB
+ fmt = "29LV160BB (16 Mbit, boot sector SA0 size 16K bytes,SA1,SA2 size 8K bytes,SA3 size 32k bytes,other sectors SA4~SA34 size 64K bytes)\n";
+ break;
+ default:
+ fmt = "Unknown Chip Type\n";
+ break;
+ }
+
+ printf (fmt, bootletter, boottype);
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20,
+ info->sector_count);
+
+ printf (" Sector Start Addresses:");
+
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0) {
+ printf ("\n ");
+ }
+
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+ (*DANUBE_EBU_BUSCON0)=0x1d7ff; //value from Aikann, should be used on the real chip
+ (*EBU_ADDR_SEL_0) = 0x10000031; //starting address from 0xb0000000
+ (*EBU_NAND_CON)=0;
+ (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing
+ (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing
+ /* Write auto select command: read Manufacturer ID */
+
+ /* Write auto select command sequence and test FLASH answer */
+ addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
+ asm("SYNC");
+ addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
+ asm("SYNC");
+ addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
+ asm("SYNC");
+
+ /* The manufacturer codes are only 1 byte, so just use 1 byte.
+ * This works for any bus width and any FLASH device width.
+ */
+
+// printf("\n type is %08lx", addr[1] & 0xff); //joelin 10/06/2004 flash type
+// printf("\n type is %08lx", addr[0] & 0xff); //joelin 10/06/2004 flash type
+// asm("SYNC");
+ switch (addr[1] & 0xff) {
+ case (uchar)AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+
+ case (uchar)INTEL_MANUFACT: // 0x0089
+ info->flash_id = FLASH_MAN_INTEL; //0x00300000
+ break;
+
+//joelin for MXIC
+ case (uchar)MX_MANUFACT: // 0x00c2
+ info->flash_id = FLASH_MAN_MX ;//0x00030000
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ break;
+/* default:
+ info->flash_id = FLASH_MAN_INTEL; //0x00300000
+ break;*/
+ }
+
+ /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+ if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) {
+ case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
+ info->flash_id += FLASH_AM640U;
+ info->sector_count = 128;
+ info->size = 0x00800000 * (sizeof(FPW)/2);
+ break; /* => 8 or 16 MB */
+
+ case (FPW)INTEL_ID_28F800C3B:
+ info->flash_id += FLASH_28F800C3B;
+ info->sector_count = 23;
+ info->size = 0x00100000 * (sizeof(FPW)/2);
+ break; /* => 1 or 2 MB */
+
+ case (FPW)INTEL_ID_28F800B3B:
+ info->flash_id += FLASH_INTEL800B;
+ info->sector_count = 23;
+ info->size = 0x00100000 * (sizeof(FPW)/2);
+ break; /* => 1 or 2 MB */
+
+ case (FPW)INTEL_ID_28F160C3B:
+ info->flash_id += FLASH_28F160C3B;
+ info->sector_count = 39;
+ info->size = 0x00200000 * (sizeof(FPW)/2);
+ break; /* => 2 or 4 MB */
+
+ case (FPW)INTEL_ID_28F160B3B:
+ info->flash_id += FLASH_INTEL160B;
+ info->sector_count = 39;
+ info->size = 0x00200000 * (sizeof(FPW)/2);
+ break; /* => 2 or 4 MB */
+
+ case (FPW)INTEL_ID_28F320C3B:
+ info->flash_id += FLASH_28F320C3B;
+ info->sector_count = 71;
+ info->size = 0x00400000 * (sizeof(FPW)/2);
+ break; /* => 4 or 8 MB */
+
+ case (FPW)INTEL_ID_28F320B3B:
+ info->flash_id += FLASH_INTEL320B;
+ info->sector_count = 71;
+ info->size = 0x00400000 * (sizeof(FPW)/2);
+ break; /* => 4 or 8 MB */
+
+ case (FPW)INTEL_ID_28F640C3B:
+ info->flash_id += FLASH_28F640C3B;
+ info->sector_count = 135;
+ info->size = 0x00800000 * (sizeof(FPW)/2);
+ break; /* => 8 or 16 MB */
+
+ case (FPW)INTEL_ID_28F640B3B:
+ info->flash_id += FLASH_INTEL640B;
+ info->sector_count = 135;
+ info->size = 0x00800000 * (sizeof(FPW)/2);
+ break; /* => 8 or 16 MB */
+
+ case (FPW)INTEL_ID_28F128J3A:
+ info->flash_id +=FLASH_28F128J3A;
+ info->sector_count = 128;
+ info->size = 0x01000000 * (sizeof(FPW)/2);
+ break; /* => 16 MB */
+ case (FPW)INTEL_ID_28F320J3A:
+ info->flash_id += FLASH_28F320J3A;
+ info->sector_count = 32;
+ info->size = 0x00400000 * (sizeof(FPW)/2);
+ break;
+//joelin for MXIC
+ case (FPW)MX_ID_29LV320AB:
+ info->flash_id += FLASH_29LV320AB;
+ info->sector_count = 71;
+ info->size = 0x00400000 * (sizeof(FPW)/2);
+ break; /* => 4 MB */
+ /* => 4 MB */
+//joelin for MXIC
+ case (FPW)MX_ID_29LV160BB:
+ info->flash_id += FLASH_29LV160BB;
+ info->sector_count = 35;
+ info->size = 0x00200000 * (sizeof(FPW)/2);
+ break; /* => 2 MB */
+ /* => 2 MB */
+ /* liupeng*/
+ case (FPW)MX_ID_29LV640BB:
+ info->flash_id += FLASH_29LV640BB;
+ info->sector_count = 135;
+ info->size = 0x00800000 * (sizeof(FPW)/2);
+ break; /* => 2 MB */
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* => no or unknown flash */
+/* default:
+ info->flash_id += FLASH_28F320J3A;
+ info->sector_count = 32;
+ info->size = 0x00400000 * (sizeof(FPW)/2);
+ break;*/
+ }
+
+
+ (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing
+ (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing
+
+ flash_get_offsets((ulong)addr, info);
+
+ /* Put FLASH back in read mode */
+ flash_reset(info);
+
+ return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ FPWV *addr;
+ int flag, prot, sect;
+ int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+ ulong start, now, last;
+ int rcode = 0;
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_INTEL800B:
+ case FLASH_INTEL160B:
+ case FLASH_INTEL320B:
+ case FLASH_INTEL640B:
+ case FLASH_28F800C3B:
+ case FLASH_28F160C3B:
+ case FLASH_28F320C3B:
+ case FLASH_28F640C3B:
+ case FLASH_28F128J3A:
+ case FLASH_28F320J3A:
+ case FLASH_AM640U:
+ case FLASH_29LV640BB: //liupeng for MXIC MX29LV640BB
+ case FLASH_29LV320AB: //joelin for MXIC MX29LV320AB
+ case FLASH_29LV160BB: //joelin for MXIC MX29LV160BB
+ break;
+ case FLASH_UNKNOWN:
+ default:
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ last = get_timer(0);
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+ if (info->protect[sect] != 0) /* protected, skip it */
+ continue;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing
+ (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing
+ (*EBU_NAND_CON)=0;
+ addr = (FPWV *)(info->start[sect]);
+ if (intel) {
+ *addr = (FPW)0x00500050; /* clear status register */
+ *addr = (FPW)0x00200020; /* erase setup */
+ *addr = (FPW)0x00D000D0; /* erase confirm */
+ asm("SYNC");
+ }
+ else {
+ /* must be AMD style if not Intel */
+ FPWV *base; /* first address in bank */
+
+ base = (FPWV *)(info->start[0]);
+ base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
+ base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
+ base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
+ *addr = (FPW)0x00300030; /* erase sector */
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer(0);
+
+ /* wait at least 50us for AMD, 80us for Intel.
+ * Let's wait 1 ms.
+ */
+ udelay (1000);
+
+ while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Erase Timeout\n");
+
+ if (intel) {
+ /* suspend erase */
+ *addr = (FPW)0x00B000B0;
+ }
+
+ flash_reset(info); /* reset to read mode */
+ rcode = 1; /* failed */
+ break;
+ }
+
+ /* show that we're waiting */
+ if ((get_timer(last)) > CFG_HZ) {/* every second */
+ putc ('.');
+ last = get_timer(0);
+ }
+ }
+
+
+//joelin for MXIC
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_MX: //joelin for MXIC
+ break;
+ default:
+ if((*addr & (FPW)0x00200020) != (FPW)0x0)
+ printf("Erase Error\n");
+ break;
+ }
+
+
+
+ /* show that we're waiting */
+ if ((get_timer(last)) > CFG_HZ) { /* every second */
+ putc ('.');
+ last = get_timer(0);
+ }
+
+ //flash_reset(info); /* reset to read mode */
+ }
+
+ (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing
+ (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing
+
+ printf (" done\n");
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+ int bytes; /* number of bytes to program in current word */
+ int left; /* number of bytes left to program */
+ int i, res;
+
+ for (left = cnt, res = 0;
+ left > 0 && res == 0;
+ addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+ bytes = addr & (sizeof(data) - 1);
+ addr &= ~(sizeof(data) - 1);
+
+ /* combine source and destination data so can program
+ * an entire word of 16 or 32 bits
+ */
+ for (i = 0; i < sizeof(data); i++) {
+ data <<= 8;
+ if (i < bytes || i - bytes >= left )
+ data += *((uchar *)addr + i);
+ else
+ data += *src++;
+ }
+
+ /* write one word to the flash */
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ case FLASH_MAN_MX: //joelin for MXIC
+ res = write_word_amd(info, (FPWV *)addr, data);
+ break;
+ case FLASH_MAN_INTEL:
+ res = write_word_intel(info, (FPWV *)addr, data);
+ break;
+ default:
+ /* unknown flash type, error! */
+ printf ("missing or unknown FLASH type\n");
+ res = 1; /* not really a timeout, but gives error */
+ break;
+ }
+ }
+
+ return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+ ulong start;
+ int flag;
+ int res = 0; /* result, assume success */
+ FPWV *base; /* first address in flash bank */
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*dest & data) != data) {
+ return (2);
+ }
+
+ base = (FPWV *)(info->start[0]);
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing
+ (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing
+ (*EBU_NAND_CON)=0;
+
+ base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
+ base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
+
+ *dest = data; /* start programming the data */
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer (0);
+
+ /* data polling for D7 */
+ while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ *dest = (FPW)0x00F000F0; /* reset bank */
+ res = 1;
+ }
+ }
+
+ (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing
+ (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing
+
+ return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
+{
+ ulong start;
+ int flag;
+ int res = 0; /* result, assume success */
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*dest & data) != data) {
+ return (2);
+ }
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing
+ (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing
+ (*EBU_NAND_CON)=0;
+ *dest = (FPW)0x00500050; /* clear status register */
+ *dest = (FPW)0x00FF00FF; /* make sure in read mode */
+ *dest = (FPW)0x00400040; /* program setup */
+ *dest = data; /* start programming the data */
+ asm("SYNC");
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer (0);
+
+ while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ *dest = (FPW)0x00B000B0; /* Suspend program */
+ res = 1;
+ }
+ }
+
+ if (res == 0 && (*dest & (FPW)0x00100010))
+ res = 1; /* write failed, time out error is close enough */
+
+ *dest = (FPW)0x00500050; /* clear status register */
+ flash_reset(info);
+
+ (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing
+ (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing
+
+ return (res);
+}
--- /dev/null
+
+/*
+ * Memory sub-system initialization code for INCA-IP2 development board.
+ * Andre Messerschmidt
+ * Copyright (c) 2005 Infineon Technologies AG
+ *
+ * Based on Inca-IP code
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* History:
+ peng liu May 25, 2006, for PLL setting after reset, 05252006
+ */
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <configs/danube.h>
+
+
+#ifdef USE_REFERENCE_BOARD
+#ifdef DANUBE_DDR_RAM_111M
+#include "ddr_settings_r111.h"
+#elif defined(PROMOSDDR400)
+#include "ddr_settings_PROMOSDDR400.h"
+#elif defined(DDR_SAMSUNG_166M)
+#include "ddr_settings_Samsung_166.h"
+#elif defined(DDR_PSC_166M)
+#include "ddr_settings_psc_166.h"
+#else
+#include "ddr_settings_r166.h"
+#endif
+#endif
+
+#ifdef USE_EVALUATION_BOARD
+#ifdef DANUBE_DDR_RAM_111M
+#include "ddr_settings_e111.h"
+#else
+#include "ddr_settings_e166.h"
+#endif
+#endif
+
+
+
+/*TODO: liupeng check !!! */
+#define EBU_MODUL_BASE 0xB4102000
+#define EBU_CLC(value) 0x0000(value)
+#define EBU_CON(value) 0x0010(value)
+#define EBU_ADDSEL0(value) 0x0020(value)
+#define EBU_ADDSEL1(value) 0x0024(value)
+#define EBU_ADDSEL2(value) 0x0028(value)
+#define EBU_ADDSEL3(value) 0x002C(value)
+#define EBU_BUSCON0(value) 0x0060(value)
+#define EBU_BUSCON1(value) 0x0064(value)
+#define EBU_BUSCON2(value) 0x0068(value)
+#define EBU_BUSCON3(value) 0x006C(value)
+
+#define MC_MODUL_BASE 0xBF800000
+#define MC_ERRCAUSE(value) 0x0010(value)
+#define MC_ERRADDR(value) 0x0020(value)
+#define MC_CON(value) 0x0060(value)
+
+#define MC_SRAM_ENABLE 0x00000004
+#define MC_SDRAM_ENABLE 0x00000002
+#define MC_DDRRAM_ENABLE 0x00000001
+
+#define MC_SDR_MODUL_BASE 0xBF800200
+#define MC_IOGP(value) 0x0000(value)
+#define MC_CTRLENA(value) 0x0010(value)
+#define MC_MRSCODE(value) 0x0020(value)
+#define MC_CFGDW(value) 0x0030(value)
+#define MC_CFGPB0(value) 0x0040(value)
+#define MC_LATENCY(value) 0x0080(value)
+#define MC_TREFRESH(value) 0x0090(value)
+#define MC_SELFRFSH(value) 0x00A0(value)
+
+#define MC_DDR_MODUL_BASE 0xBF801000
+#define MC_DC00(value) 0x0000(value)
+#define MC_DC01(value) 0x0010(value)
+#define MC_DC02(value) 0x0020(value)
+#define MC_DC03(value) 0x0030(value)
+#define MC_DC04(value) 0x0040(value)
+#define MC_DC05(value) 0x0050(value)
+#define MC_DC06(value) 0x0060(value)
+#define MC_DC07(value) 0x0070(value)
+#define MC_DC08(value) 0x0080(value)
+#define MC_DC09(value) 0x0090(value)
+#define MC_DC10(value) 0x00A0(value)
+#define MC_DC11(value) 0x00B0(value)
+#define MC_DC12(value) 0x00C0(value)
+#define MC_DC13(value) 0x00D0(value)
+#define MC_DC14(value) 0x00E0(value)
+#define MC_DC15(value) 0x00F0(value)
+#define MC_DC16(value) 0x0100(value)
+#define MC_DC17(value) 0x0110(value)
+#define MC_DC18(value) 0x0120(value)
+#define MC_DC19(value) 0x0130(value)
+#define MC_DC20(value) 0x0140(value)
+#define MC_DC21(value) 0x0150(value)
+#define MC_DC22(value) 0x0160(value)
+#define MC_DC23(value) 0x0170(value)
+#define MC_DC24(value) 0x0180(value)
+#define MC_DC25(value) 0x0190(value)
+#define MC_DC26(value) 0x01A0(value)
+#define MC_DC27(value) 0x01B0(value)
+#define MC_DC28(value) 0x01C0(value)
+#define MC_DC29(value) 0x01D0(value)
+#define MC_DC30(value) 0x01E0(value)
+#define MC_DC31(value) 0x01F0(value)
+#define MC_DC32(value) 0x0200(value)
+#define MC_DC33(value) 0x0210(value)
+#define MC_DC34(value) 0x0220(value)
+#define MC_DC35(value) 0x0230(value)
+#define MC_DC36(value) 0x0240(value)
+#define MC_DC37(value) 0x0250(value)
+#define MC_DC38(value) 0x0260(value)
+#define MC_DC39(value) 0x0270(value)
+#define MC_DC40(value) 0x0280(value)
+#define MC_DC41(value) 0x0290(value)
+#define MC_DC42(value) 0x02A0(value)
+#define MC_DC43(value) 0x02B0(value)
+#define MC_DC44(value) 0x02C0(value)
+#define MC_DC45(value) 0x02D0(value)
+#define MC_DC46(value) 0x02E0(value)
+
+#define RCU_OFFSET 0xBF203000
+#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
+#define RCU_STS (RCU_OFFSET + 0x0014)
+
+#define CGU_OFFSET 0xBF103000
+#define PLL0_CFG (CGU_OFFSET + 0x0004)
+#define PLL1_CFG (CGU_OFFSET + 0x0008)
+#define PLL2_CFG (CGU_OFFSET + 0x000C)
+#define CGU_SYS (CGU_OFFSET + 0x0010)
+#define CGU_UPDATE (CGU_OFFSET + 0x0014)
+#define IF_CLK (CGU_OFFSET + 0x0018)
+#define CGU_SMD (CGU_OFFSET + 0x0020)
+#define CGU_CT1SR (CGU_OFFSET + 0x0028)
+#define CGU_CT2SR (CGU_OFFSET + 0x002C)
+#define CGU_PCMCR (CGU_OFFSET + 0x0030)
+#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
+#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
+#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
+#define CLK_MEASURE (CGU_OFFSET + 0x003C)
+
+//05252006
+#define pll0_35MHz_CONFIG 0x9D861059
+#define pll1_35MHz_CONFIG 0x1A260CD9
+#define pll2_35MHz_CONFIG 0x8000f1e5
+#define pll0_36MHz_CONFIG 0x1000125D
+#define pll1_36MHz_CONFIG 0x1B1E0C99
+#define pll2_36MHz_CONFIG 0x8002f2a1
+//05252006
+
+//06063001-joelin disable the PCI CFRAME mask -start
+/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
+But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
+
+The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
+The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
+*/
+#define PCI_CR_PR_OFFSET 0xBE105400
+#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
+#define PCI_CONFIG_SPACE 0xB7000000
+#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
+//06063001-joelin disable the PCI CFRAME mask -end
+ .set noreorder
+
+
+/*
+ * void ebu_init(long)
+ *
+ * a0 has the clock value we are going to run at
+ */
+ .globl ebu_init
+ .ent ebu_init
+ebu_init:
+/*TODO:liupeng */
+ j ra
+ nop
+
+ .end ebu_init
+
+
+/*
+ * void cgu_init(long)
+ *
+ * a0 has the clock value
+ */
+ .globl cgu_init
+ .ent cgu_init
+cgu_init:
+ li t2, CGU_SYS
+ lw t2,0(t2)
+ beq t2,a0,freq_up2date
+ nop
+
+ li t2, RCU_STS
+ lw t2, 0(t2)
+ and t2,0x00020000
+ beq t2,0x00020000,boot_36MHZ
+ nop
+//05252006
+ li t1, PLL0_CFG
+ li t2, pll0_35MHz_CONFIG
+ sw t2,0(t1)
+ li t1, PLL1_CFG
+ li t2, pll1_35MHz_CONFIG
+ sw t2,0(t1)
+ li t1, PLL2_CFG
+ li t2, pll2_35MHz_CONFIG
+ sw t2,0(t1)
+ li t1, CGU_SYS
+ sw a0,0(t1)
+ li t1, RCU_RST_REQ
+ li t2, 0x40000008
+ sw t2,0(t1)
+ b wait_reset
+ nop
+boot_36MHZ:
+ li t1, PLL0_CFG
+ li t2, pll0_36MHz_CONFIG
+ sw t2,0(t1)
+ li t1, PLL1_CFG
+ li t2, pll1_36MHz_CONFIG
+ sw t2,0(t1)
+ li t1, PLL2_CFG
+ li t2, pll2_36MHz_CONFIG
+ sw t2,0(t1)
+ li t1, CGU_SYS
+ sw a0,0(t1)
+ li t1, RCU_RST_REQ
+ li t2, 0x40000008
+ sw t2,0(t1)
+//05252006
+
+wait_reset:
+ b wait_reset
+ nop
+freq_up2date:
+ j ra
+ nop
+ .end cgu_init
+
+
+/*
+ * void sdram_init(long)
+ *
+ * a0 has the clock value
+ */
+ .globl sdram_init
+ .ent sdram_init
+sdram_init:
+
+ /* SDRAM Initialization
+ */
+ li t1, MC_MODUL_BASE
+
+ /* Clear Error log registers */
+ sw zero, MC_ERRCAUSE(t1)
+ sw zero, MC_ERRADDR(t1)
+
+ /* Enable SDRAM module in memory controller */
+ li t3, MC_SDRAM_ENABLE
+ lw t2, MC_CON(t1)
+ or t3, t2, t3
+ sw t3, MC_CON(t1)
+
+ li t1, MC_SDR_MODUL_BASE
+
+ /* disable the controller */
+ li t2, 0
+ sw t2, MC_CTRLENA(t1)
+
+ li t2, 0x822
+ sw t2, MC_IOGP(t1)
+
+ li t2, 0x2
+ sw t2, MC_CFGDW(t1)
+
+ /* Set CAS Latency */
+ li t2, 0x00000020
+ sw t2, MC_MRSCODE(t1)
+
+ /* Set CS0 to SDRAM parameters */
+ li t2, 0x000014d8
+ sw t2, MC_CFGPB0(t1)
+
+ /* Set SDRAM latency parameters */
+ li t2, 0x00036325; /* BC PC100 */
+ sw t2, MC_LATENCY(t1)
+
+ /* Set SDRAM refresh rate */
+ li t2, 0x00000C30
+ sw t2, MC_TREFRESH(t1)
+
+ /* Clear Power-down registers */
+ sw zero, MC_SELFRFSH(t1)
+
+ /* Finally enable the controller */
+ li t2, 1
+ sw t2, MC_CTRLENA(t1)
+
+
+ j ra
+ nop
+
+
+ .end sdram_init
+
+/*
+ * void ddrram_init(long)
+ *
+ * a0 has the clock value
+ */
+ .globl ddrram_init
+ .ent ddrram_init
+ddrram_init:
+
+ /* DDR-DRAM Initialization
+ */
+ li t1, MC_MODUL_BASE
+
+ /* Clear Error log registers */
+ sw zero, MC_ERRCAUSE(t1)
+ sw zero, MC_ERRADDR(t1)
+
+ /* Enable DDR module in memory controller */
+ li t3, MC_DDRRAM_ENABLE
+ lw t2, MC_CON(t1)
+ or t3, t2, t3
+ sw t3, MC_CON(t1)
+
+ li t1, MC_DDR_MODUL_BASE
+
+ /* Write configuration to DDR controller registers */
+ li t2, MC_DC0_VALUE
+ sw t2, MC_DC00(t1)
+
+ li t2, MC_DC1_VALUE
+ sw t2, MC_DC01(t1)
+
+ li t2, MC_DC2_VALUE
+ sw t2, MC_DC02(t1)
+
+ li t2, MC_DC3_VALUE
+ sw t2, MC_DC03(t1)
+
+ li t2, MC_DC4_VALUE
+ sw t2, MC_DC04(t1)
+
+ li t2, MC_DC5_VALUE
+ sw t2, MC_DC05(t1)
+
+ li t2, MC_DC6_VALUE
+ sw t2, MC_DC06(t1)
+
+ li t2, MC_DC7_VALUE
+ sw t2, MC_DC07(t1)
+
+ li t2, MC_DC8_VALUE
+ sw t2, MC_DC08(t1)
+
+ li t2, MC_DC9_VALUE
+ sw t2, MC_DC09(t1)
+
+ li t2, MC_DC10_VALUE
+ sw t2, MC_DC10(t1)
+
+ li t2, MC_DC11_VALUE
+ sw t2, MC_DC11(t1)
+
+ li t2, MC_DC12_VALUE
+ sw t2, MC_DC12(t1)
+
+ li t2, MC_DC13_VALUE
+ sw t2, MC_DC13(t1)
+
+ li t2, MC_DC14_VALUE
+ sw t2, MC_DC14(t1)
+
+ li t2, MC_DC15_VALUE
+ sw t2, MC_DC15(t1)
+
+ li t2, MC_DC16_VALUE
+ sw t2, MC_DC16(t1)
+
+ li t2, MC_DC17_VALUE
+ sw t2, MC_DC17(t1)
+
+ li t2, MC_DC18_VALUE
+ sw t2, MC_DC18(t1)
+
+ li t2, MC_DC19_VALUE
+ sw t2, MC_DC19(t1)
+
+ li t2, MC_DC20_VALUE
+ sw t2, MC_DC20(t1)
+
+ li t2, MC_DC21_VALUE
+ sw t2, MC_DC21(t1)
+
+ li t2, MC_DC22_VALUE
+ sw t2, MC_DC22(t1)
+
+ li t2, MC_DC23_VALUE
+ sw t2, MC_DC23(t1)
+
+ li t2, MC_DC24_VALUE
+ sw t2, MC_DC24(t1)
+
+ li t2, MC_DC25_VALUE
+ sw t2, MC_DC25(t1)
+
+ li t2, MC_DC26_VALUE
+ sw t2, MC_DC26(t1)
+
+ li t2, MC_DC27_VALUE
+ sw t2, MC_DC27(t1)
+
+ li t2, MC_DC28_VALUE
+ sw t2, MC_DC28(t1)
+
+ li t2, MC_DC29_VALUE
+ sw t2, MC_DC29(t1)
+
+ li t2, MC_DC30_VALUE
+ sw t2, MC_DC30(t1)
+
+ li t2, MC_DC31_VALUE
+ sw t2, MC_DC31(t1)
+
+ li t2, MC_DC32_VALUE
+ sw t2, MC_DC32(t1)
+
+ li t2, MC_DC33_VALUE
+ sw t2, MC_DC33(t1)
+
+ li t2, MC_DC34_VALUE
+ sw t2, MC_DC34(t1)
+
+ li t2, MC_DC35_VALUE
+ sw t2, MC_DC35(t1)
+
+ li t2, MC_DC36_VALUE
+ sw t2, MC_DC36(t1)
+
+ li t2, MC_DC37_VALUE
+ sw t2, MC_DC37(t1)
+
+ li t2, MC_DC38_VALUE
+ sw t2, MC_DC38(t1)
+
+ li t2, MC_DC39_VALUE
+ sw t2, MC_DC39(t1)
+
+ li t2, MC_DC40_VALUE
+ sw t2, MC_DC40(t1)
+
+ li t2, MC_DC41_VALUE
+ sw t2, MC_DC41(t1)
+
+ li t2, MC_DC42_VALUE
+ sw t2, MC_DC42(t1)
+
+ li t2, MC_DC43_VALUE
+ sw t2, MC_DC43(t1)
+
+ li t2, MC_DC44_VALUE
+ sw t2, MC_DC44(t1)
+
+ li t2, MC_DC45_VALUE
+ sw t2, MC_DC45(t1)
+
+ li t2, MC_DC46_VALUE
+ sw t2, MC_DC46(t1)
+
+ li t2, 0x00000100
+ sw t2, MC_DC03(t1)
+
+ j ra
+ nop
+
+
+ .end ddrram_init
+
+ .globl lowlevel_init
+ .ent lowlevel_init
+lowlevel_init:
+ /* EBU, CGU and SDRAM/DDR-RAM Initialization.
+ */
+ move t0, ra
+ /* We rely on the fact that neither cgu_init() nor sdram_init()
+ * modify t0
+ */
+#ifdef DANUBE_BOOT_FROM_EBU
+#ifdef DANUBE_DDR_RAM_166M
+//05252006
+ /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
+ li a0,0xe8
+ bal cgu_init
+ nop
+#endif
+#ifdef PROMOSDDR400
+ li a0,0xe8
+ bal cgu_init
+ nop
+#endif
+#ifdef DDR_SAMSUNG_166M
+ li a0,0xe8
+ bal cgu_init
+ nop
+#endif
+#ifdef DDR_PSC_166M
+ li a0,0xe8
+ bal cgu_init
+ nop
+#endif
+#ifdef DANUBE_DDR_RAM_133M
+ li a0,0xe9
+//05252006
+ bal cgu_init
+ nop
+#endif
+#endif
+/*TODO:liupeng add this define !!!! */
+/*
+ #define DANUBE_BOOT_FROM_EBU
+ #define DANUBE_USE_DDR_RAM
+*/
+
+//06063001-joelin disable the PCI CFRAME mask-start
+#ifdef DISABLE_CFRAME
+ li t1, PCI_CR_PCI //mw bf103034 80000000
+ li t2, 0x80000000
+ sw t2,0(t1)
+
+ li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
+ li t2, 0x103
+ sw t2,0(t1)
+
+ li t1, CS_CFM //mw b700006c 0
+ li t2, 0x00
+ sw t2, 0(t1)
+
+ li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
+ li t2, 0x1000103
+ sw t2, 0(t1)
+#endif
+//06063001-joelin disable the PCI CFRAME mask-end
+
+#ifdef DANUBE_BOOT_FROM_EBU
+#ifdef DANUBE_USE_DDR_RAM
+ bal ddrram_init
+ nop
+#else
+ bal sdram_init
+ nop
+#endif
+#endif
+
+ move ra, t0
+ j ra
+ nop
+
+ .end lowlevel_init
--- /dev/null
+/*
+ * Power Management unit initialization code for AMAZON development board.
+ *
+ * Copyright (c) 2003 Ou Ke, Infineon.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+
+#define PMU_PWDCR 0xBF10201C
+#define PMU_SR 0xBF102020
+
+ .globl pmuenable
+
+pmuenable:
+ li t0, PMU_PWDCR
+ li t1, 0x2 /* enable everything */
+ sw t1, 0(t0)
+#if 0
+1:
+ li t0, PMU_SR
+ lw t2, 0(t0)
+ bne t1, t2, 1b
+ nop
+#endif
+ j ra
+ nop
+
+
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_ARCH(mips)
+ENTRY(_start_bootstrap)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .sdata : { *(.sdata) }
+
+ _gp = ALIGN(16);
+
+ __got_start_bootstrap = .;
+ .got : { *(.got) }
+ __got_end_bootstrap = .;
+
+ .sdata : { *(.sdata) }
+
+ . = .;
+ __u_boot_cmd_start_bootstrap = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end_bootstrap = .;
+
+ uboot_end_data_bootstrap = .;
+ num_got_entries = (__got_end_bootstrap - __got_start_bootstrap) >> 2;
+
+ . = ALIGN(4);
+ .sbss : { *(.sbss) }
+ .bss : { *(.bss) }
+ uboot_end_bootstrap = .;
+}
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .sdata : { *(.sdata) }
+
+ _gp = ALIGN(16);
+
+ __got_start = .;
+ .got : { *(.got) }
+ __got_end = .;
+
+ .sdata : { *(.sdata) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ uboot_end_data = .;
+ num_got_entries = (__got_end - __got_start) >> 2;
+
+ . = ALIGN(4);
+ .sbss : { *(.sbss) }
+ .bss : { *(.bss) }
+ uboot_end = .;
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <flash.h>
+
+#if !defined(CFG_NO_FLASH)
+
+extern flash_info_t flash_info[]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+/*-----------------------------------------------------------------------
+ * Set protection status for monitor sectors
+ *
+ * The monitor is always located in the _first_ Flash bank.
+ * If necessary you have to map the second bank at lower addresses.
+ */
+void
+flash_protect (int flag, ulong from, ulong to, flash_info_t *info)
+{
+ ulong b_end = info->start[0] + info->size - 1; /* bank end address */
+ short s_end = info->sector_count - 1; /* index of last sector */
+ int i;
+
+ debug ("flash_protect %s: from 0x%08lX to 0x%08lX\n",
+ (flag & FLAG_PROTECT_SET) ? "ON" :
+ (flag & FLAG_PROTECT_CLEAR) ? "OFF" : "???",
+ from, to);
+
+ /* Do nothing if input data is bad. */
+ if (info->sector_count == 0 || info->size == 0 || to < from) {
+ return;
+ }
+
+ /* There is nothing to do if we have no data about the flash
+ * or the protect range and flash range don't overlap.
+ */
+ if (info->flash_id == FLASH_UNKNOWN ||
+ to < info->start[0] || from > b_end) {
+ return;
+ }
+
+ for (i=0; i<info->sector_count; ++i) {
+ ulong end; /* last address in current sect */
+
+ end = (i == s_end) ? b_end : info->start[i + 1] - 1;
+
+ /* Update protection if any part of the sector
+ * is in the specified range.
+ */
+ if (from <= end && to >= info->start[i]) {
+ if (flag & FLAG_PROTECT_CLEAR) {
+#if defined(CFG_FLASH_PROTECTION)
+ flash_real_protect(info, i, 0);
+#else
+ info->protect[i] = 0;
+#endif /* CFG_FLASH_PROTECTION */
+ debug ("protect off %d\n", i);
+ }
+ else if (flag & FLAG_PROTECT_SET) {
+#if defined(CFG_FLASH_PROTECTION)
+ flash_real_protect(info, i, 1);
+#else
+ info->protect[i] = 1;
+#endif /* CFG_FLASH_PROTECTION */
+ debug ("protect on %d\n", i);
+ }
+ }
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+flash_info_t *
+addr2info (ulong addr)
+{
+#ifndef CONFIG_SPD823TS
+ flash_info_t *info;
+ int i;
+
+ for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
+ if (info->flash_id != FLASH_UNKNOWN &&
+ addr >= info->start[0] &&
+ /* WARNING - The '- 1' is needed if the flash
+ * is at the end of the address space, since
+ * info->start[0] + info->size wraps back to 0.
+ * Please don't change this unless you understand this.
+ */
+ addr <= info->start[0] + info->size - 1) {
+ return (info);
+ }
+ }
+#endif /* CONFIG_SPD823TS */
+
+ return (NULL);
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ * Make sure all target addresses are within Flash bounds,
+ * and no protected sectors are hit.
+ * Returns:
+ * ERR_OK 0 - OK
+ * ERR_TIMOUT 1 - write timeout
+ * ERR_NOT_ERASED 2 - Flash not erased
+ * ERR_PROTECTED 4 - target range includes protected sectors
+ * ERR_INVAL 8 - target address not in Flash memory
+ * ERR_ALIGN 16 - target address not aligned on boundary
+ * (only some targets require alignment)
+ */
+int
+flash_write (char *src, ulong addr, ulong cnt)
+{
+#ifdef CONFIG_SPD823TS
+ return (ERR_TIMOUT); /* any other error codes are possible as well */
+#else
+ int i;
+ ulong end = addr + cnt - 1;
+ flash_info_t *info_first = addr2info (addr);
+ flash_info_t *info_last = addr2info (end );
+ flash_info_t *info;
+
+ if (cnt == 0) {
+ return (ERR_OK);
+ }
+
+ if (!info_first || !info_last) {
+ return (ERR_INVAL);
+ }
+
+ for (info = info_first; info <= info_last; ++info) {
+ ulong b_end = info->start[0] + info->size; /* bank end addr */
+ short s_end = info->sector_count - 1;
+ for (i=0; i<info->sector_count; ++i) {
+ ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
+
+ if ((end >= info->start[i]) && (addr < e_addr) &&
+ (info->protect[i] != 0) ) {
+ return (ERR_PROTECTED);
+ }
+ }
+ }
+
+ /* finally write data to flash */
+ for (info = info_first; info <= info_last && cnt>0; ++info) {
+ ulong len;
+
+ len = info->start[0] + info->size - addr;
+ if (len > cnt)
+ len = cnt;
+ if ((i = write_buff(info, (uchar *)src, addr, len)) != 0) {
+ return (i);
+ }
+ cnt -= len;
+ addr += len;
+ src += len;
+ }
+ return (ERR_OK);
+#endif /* CONFIG_SPD823TS */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_perror (int err)
+{
+ switch (err) {
+ case ERR_OK:
+ break;
+ case ERR_TIMOUT:
+ puts ("Timeout writing to Flash\n");
+ break;
+ case ERR_NOT_ERASED:
+ puts ("Flash not Erased\n");
+ break;
+ case ERR_PROTECTED:
+ puts ("Can't write to protected Flash sectors\n");
+ break;
+ case ERR_INVAL:
+ puts ("Outside available Flash\n");
+ break;
+ case ERR_ALIGN:
+ puts ("Start and/or end address not on sector boundary\n");
+ break;
+ case ERR_UNKNOWN_FLASH_VENDOR:
+ puts ("Unknown Vendor of Flash\n");
+ break;
+ case ERR_UNKNOWN_FLASH_TYPE:
+ puts ("Unknown Type of Flash\n");
+ break;
+ case ERR_PROG_ERROR:
+ puts ("General Flash Programming Error\n");
+ break;
+ default:
+ printf ("%s[%d] FIXME: rc=%d\n", __FILE__, __LINE__, err);
+ break;
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+#endif /* !CFG_NO_FLASH */
--- /dev/null
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).a
+
+START = start.o
+COBJS = asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \
+ cpu.o interrupts.o incaip_clock.o ifx_asc.o ifx_clock.o
+SOBJS = incaip_wdt.o cache.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (INCA) ASC UART support
+ */
+
+#include <config.h>
+
+#if defined(CONFIG_PURPLE) || defined(CONFIG_INCA_IP)
+
+#ifdef CONFIG_PURPLE
+#define serial_init asc_serial_init
+#define serial_putc asc_serial_putc
+#define serial_puts asc_serial_puts
+#define serial_getc asc_serial_getc
+#define serial_tstc asc_serial_tstc
+#define serial_setbrg asc_serial_setbrg
+#endif
+
+#include <common.h>
+#include <asm/inca-ip.h>
+#include "asc_serial.h"
+
+#ifdef CONFIG_PURPLE
+
+#undef ASC_FIFO_PRESENT
+#define TOUT_LOOP 100000
+
+/* Set base address for second FPI interrupt control register bank */
+#define SFPI_INTCON_BASEADDR 0xBF0F0000
+
+/* Register offset from base address */
+#define FBS_ISR 0x00000000 /* Interrupt status register */
+#define FBS_IMR 0x00000008 /* Interrupt mask register */
+#define FBS_IDIS 0x00000010 /* Interrupt disable register */
+
+/* Interrupt status register bits */
+#define FBS_ISR_AT 0x00000040 /* ASC transmit interrupt */
+#define FBS_ISR_AR 0x00000020 /* ASC receive interrupt */
+#define FBS_ISR_AE 0x00000010 /* ASC error interrupt */
+#define FBS_ISR_AB 0x00000008 /* ASC transmit buffer interrupt */
+#define FBS_ISR_AS 0x00000004 /* ASC start of autobaud detection interrupt */
+#define FBS_ISR_AF 0x00000002 /* ASC end of autobaud detection interrupt */
+
+#else
+
+#define ASC_FIFO_PRESENT
+
+#endif
+
+
+#define SET_BIT(reg, mask) reg |= (mask)
+#define CLEAR_BIT(reg, mask) reg &= (~mask)
+#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
+#define SET_BITS(reg, mask) SET_BIT(reg, mask)
+#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
+
+extern uint incaip_get_fpiclk(void);
+
+static int serial_setopt (void);
+
+/* pointer to ASC register base address */
+static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC;
+
+/******************************************************************************
+*
+* serial_init - initialize a INCAASC channel
+*
+* This routine initializes the number of data bits, parity
+* and set the selected baud rate. Interrupts are disabled.
+* Set the modem control signals if the option is selected.
+*
+* RETURNS: N/A
+*/
+
+int serial_init (void)
+{
+#ifdef CONFIG_INCA_IP
+ /* we have to set PMU.EN13 bit to enable an ASC device*/
+ INCAASC_PMU_ENABLE(13);
+#endif
+
+ /* and we have to set CLC register*/
+ CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
+ SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
+
+ /* initialy we are in async mode */
+ pAsc->asc_con = ASCCON_M_8ASYNC;
+
+ /* select input port */
+ pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
+
+#ifdef ASC_FIFO_PRESENT
+ /* TXFIFO's filling level */
+ SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
+ ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL);
+ /* enable TXFIFO */
+ SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
+
+ /* RXFIFO's filling level */
+ SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
+ ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL);
+ /* enable RXFIFO */
+ SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
+#endif
+
+ /* enable error signals */
+ SET_BIT(pAsc->asc_con, ASCCON_FEN);
+ SET_BIT(pAsc->asc_con, ASCCON_OEN);
+
+#ifdef CONFIG_INCA_IP
+ /* acknowledge ASC interrupts */
+ ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL);
+
+ /* disable ASC interrupts */
+ ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL);
+#endif
+
+#ifdef ASC_FIFO_PRESENT
+ /* set FIFOs into the transparent mode */
+ SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN);
+ SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN);
+#endif
+
+ /* set baud rate */
+ serial_setbrg();
+
+ /* set the options */
+ serial_setopt();
+
+ return 0;
+}
+
+void serial_setbrg (void)
+{
+ ulong uiReloadValue, fdv;
+ ulong f_ASC;
+
+#ifdef CONFIG_INCA_IP
+ f_ASC = incaip_get_fpiclk();
+#else
+ f_ASC = ASC_CLOCK_RATE;
+#endif
+
+#ifndef INCAASC_USE_FDV
+ fdv = 2;
+ uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
+#else
+ fdv = INCAASC_FDV_HIGH_BAUDRATE;
+ uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
+#endif /* INCAASC_USE_FDV */
+
+ if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
+ {
+#ifndef INCAASC_USE_FDV
+ fdv = 3;
+ uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
+#else
+ fdv = INCAASC_FDV_LOW_BAUDRATE;
+ uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
+#endif /* INCAASC_USE_FDV */
+
+ if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
+ {
+ return; /* can't impossibly generate that baud rate */
+ }
+ }
+
+ /* Disable Baud Rate Generator; BG should only be written when R=0 */
+ CLEAR_BIT(pAsc->asc_con, ASCCON_R);
+
+#ifndef INCAASC_USE_FDV
+ /*
+ * Disable Fractional Divider (FDE)
+ * Divide clock by reload-value + constant (BRS)
+ */
+ /* FDE = 0 */
+ CLEAR_BIT(pAsc->asc_con, ASCCON_FDE);
+
+ if ( fdv == 2 )
+ CLEAR_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 0 */
+ else
+ SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */
+
+#else /* INCAASC_USE_FDV */
+
+ /* Enable Fractional Divider */
+ SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */
+
+ /* Set fractional divider value */
+ pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK;
+
+#endif /* INCAASC_USE_FDV */
+
+ /* Set reload value in BG */
+ pAsc->asc_bg = uiReloadValue;
+
+ /* Enable Baud Rate Generator */
+ SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */
+}
+
+/*******************************************************************************
+*
+* serial_setopt - set the serial options
+*
+* Set the channel operating mode to that specified. Following options
+* are supported: CREAD, CSIZE, PARENB, and PARODD.
+*
+* Note, this routine disables the transmitter. The calling routine
+* may have to re-enable it.
+*
+* RETURNS:
+* Returns 0 to indicate success, otherwise -1 is returned
+*/
+
+static int serial_setopt (void)
+{
+ ulong con;
+
+ switch ( ASC_OPTIONS & ASCOPT_CSIZE )
+ {
+ /* 7-bit-data */
+ case ASCOPT_CS7:
+ con = ASCCON_M_7ASYNCPAR; /* 7-bit-data and parity bit */
+ break;
+
+ /* 8-bit-data */
+ case ASCOPT_CS8:
+ if ( ASC_OPTIONS & ASCOPT_PARENB )
+ con = ASCCON_M_8ASYNCPAR; /* 8-bit-data and parity bit */
+ else
+ con = ASCCON_M_8ASYNC; /* 8-bit-data no parity */
+ break;
+
+ /*
+ * only 7 and 8-bit frames are supported
+ * if we don't use IOCTL extensions
+ */
+ default:
+ return -1;
+ }
+
+ if ( ASC_OPTIONS & ASCOPT_STOPB )
+ SET_BIT(con, ASCCON_STP); /* 2 stop bits */
+ else
+ CLEAR_BIT(con, ASCCON_STP); /* 1 stop bit */
+
+ if ( ASC_OPTIONS & ASCOPT_PARENB )
+ SET_BIT(con, ASCCON_PEN); /* enable parity checking */
+ else
+ CLEAR_BIT(con, ASCCON_PEN); /* disable parity checking */
+
+ if ( ASC_OPTIONS & ASCOPT_PARODD )
+ SET_BIT(con, ASCCON_ODD); /* odd parity */
+ else
+ CLEAR_BIT(con, ASCCON_ODD); /* even parity */
+
+ if ( ASC_OPTIONS & ASCOPT_CREAD )
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */
+
+ pAsc->asc_con |= con;
+
+ return 0;
+}
+
+void serial_putc (const char c)
+{
+#ifdef ASC_FIFO_PRESENT
+ uint txFl = 0;
+#else
+ uint timeout = 0;
+#endif
+
+ if (c == '\n') serial_putc ('\r');
+
+#ifdef ASC_FIFO_PRESENT
+ /* check do we have a free space in the TX FIFO */
+ /* get current filling level */
+ do
+ {
+ txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
+ }
+ while ( txFl == INCAASC_TXFIFO_FULL );
+#else
+
+ while(!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
+ FBS_ISR_AB))
+ {
+ if (timeout++ > TOUT_LOOP)
+ {
+ break;
+ }
+ }
+#endif
+
+ pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
+
+#ifndef ASC_FIFO_PRESENT
+ *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AB |
+ FBS_ISR_AT;
+#endif
+
+ /* check for errors */
+ if ( pAsc->asc_con & ASCCON_OE )
+ {
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
+ return;
+ }
+}
+
+void serial_puts (const char *s)
+{
+ while (*s)
+ {
+ serial_putc (*s++);
+ }
+}
+
+int serial_getc (void)
+{
+ ulong symbol_mask;
+ char c;
+
+ while (!serial_tstc());
+
+ symbol_mask =
+ ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
+
+ c = (char)(pAsc->asc_rbuf & symbol_mask);
+
+#ifndef ASC_FIFO_PRESENT
+ *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AR;
+#endif
+
+ return c;
+}
+
+int serial_tstc (void)
+{
+ int res = 1;
+
+#ifdef ASC_FIFO_PRESENT
+ if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
+ {
+ res = 0;
+ }
+#else
+ if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
+ FBS_ISR_AR))
+
+ {
+ res = 0;
+ }
+#endif
+ else if ( pAsc->asc_con & ASCCON_FE )
+ {
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
+ res = 0;
+ }
+ else if ( pAsc->asc_con & ASCCON_PE )
+ {
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
+ res = 0;
+ }
+ else if ( pAsc->asc_con & ASCCON_OE )
+ {
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
+ res = 0;
+ }
+
+ return res;
+}
+#endif /* CONFIG_PURPLE || CONFIG_INCA_IP */
--- /dev/null
+/* incaAscSio.h - (INCA) ASC UART tty driver header */
+
+#ifndef __INCincaAscSioh
+#define __INCincaAscSioh
+
+#include <asm/inca-ip.h>
+
+/* channel operating modes */
+#define ASCOPT_CSIZE 0x00000003
+#define ASCOPT_CS7 0x00000001
+#define ASCOPT_CS8 0x00000002
+#define ASCOPT_PARENB 0x00000004
+#define ASCOPT_STOPB 0x00000008
+#define ASCOPT_PARODD 0x00000010
+#define ASCOPT_CREAD 0x00000020
+
+#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
+
+/* ASC input select (0 or 1) */
+#define CONSOLE_TTY 0
+
+/* use fractional divider for baudrate settings */
+#define INCAASC_USE_FDV
+
+#ifdef INCAASC_USE_FDV
+ #define INCAASC_FDV_LOW_BAUDRATE 71
+ #define INCAASC_FDV_HIGH_BAUDRATE 453
+#endif /*INCAASC_USE_FDV*/
+
+
+#define INCAASC_TXFIFO_FL 1
+#define INCAASC_RXFIFO_FL 1
+#define INCAASC_TXFIFO_FULL 16
+
+/* interrupt lines masks for the ASC device interrupts*/
+/* change these macroses if it's necessary */
+#define INCAASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */
+
+#define INCAASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */
+#define INCAASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */
+#define INCAASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */
+#define INCAASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/
+
+/* interrupt controller access macros */
+#define ASC_INTERRUPTS_ENABLE(X) \
+ *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X;
+#define ASC_INTERRUPTS_DISABLE(X) \
+ *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X;
+#define ASC_INTERRUPTS_CLEAR(X) \
+ *((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X;
+
+/* CLC register's bits and bitfields */
+#define ASCCLC_DISR 0x00000001
+#define ASCCLC_DISS 0x00000002
+#define ASCCLC_RMCMASK 0x0000FF00
+#define ASCCLC_RMCOFFSET 8
+
+/* CON register's bits and bitfields */
+#define ASCCON_MODEMASK 0x0007
+ #define ASCCON_M_8SYNC 0x0
+ #define ASCCON_M_8ASYNC 0x1
+ #define ASCCON_M_8IRDAASYNC 0x2
+ #define ASCCON_M_7ASYNCPAR 0x3
+ #define ASCCON_M_9ASYNC 0x4
+ #define ASCCON_M_8WAKEUPASYNC 0x5
+ #define ASCCON_M_8ASYNCPAR 0x7
+#define ASCCON_STP 0x0008
+#define ASCCON_REN 0x0010
+#define ASCCON_PEN 0x0020
+#define ASCCON_FEN 0x0040
+#define ASCCON_OEN 0x0080
+#define ASCCON_PE 0x0100
+#define ASCCON_FE 0x0200
+#define ASCCON_OE 0x0400
+#define ASCCON_FDE 0x0800
+#define ASCCON_ODD 0x1000
+#define ASCCON_BRS 0x2000
+#define ASCCON_LB 0x4000
+#define ASCCON_R 0x8000
+
+/* WHBCON register's bits and bitfields */
+#define ASCWHBCON_CLRREN 0x0010
+#define ASCWHBCON_SETREN 0x0020
+#define ASCWHBCON_CLRPE 0x0100
+#define ASCWHBCON_CLRFE 0x0200
+#define ASCWHBCON_CLROE 0x0400
+#define ASCWHBCON_SETPE 0x0800
+#define ASCWHBCON_SETFE 0x1000
+#define ASCWHBCON_SETOE 0x2000
+
+/* ABCON register's bits and bitfields */
+#define ASCABCON_ABEN 0x0001
+#define ASCABCON_AUREN 0x0002
+#define ASCABCON_ABSTEN 0x0004
+#define ASCABCON_ABDETEN 0x0008
+#define ASCABCON_FCDETEN 0x0010
+#define ASCABCON_EMMASK 0x0300
+ #define ASCABCON_EMOFF 8
+ #define ASCABCON_EM_DISAB 0x0
+ #define ASCABCON_EM_DURAB 0x1
+ #define ASCABCON_EM_ALWAYS 0x2
+#define ASCABCON_TXINV 0x0400
+#define ASCABCON_RXINV 0x0800
+
+/* FDV register mask, offset and bitfields*/
+#define ASCFDV_VALUE_MASK 0x000001FF
+
+/* WHBABCON register's bits and bitfields */
+#define ASCWHBABCON_SETABEN 0x0001
+#define ASCWHBABCON_CLRABEN 0x0002
+
+/* ABSTAT register's bits and bitfields */
+#define ASCABSTAT_FCSDET 0x0001
+#define ASCABSTAT_FCCDET 0x0002
+#define ASCABSTAT_SCSDET 0x0004
+#define ASCABSTAT_SCCDET 0x0008
+#define ASCABSTAT_DETWAIT 0x0010
+
+/* WHBABSTAT register's bits and bitfields */
+#define ASCWHBABSTAT_CLRFCSDET 0x0001
+#define ASCWHBABSTAT_SETFCSDET 0x0002
+#define ASCWHBABSTAT_CLRFCCDET 0x0004
+#define ASCWHBABSTAT_SETFCCDET 0x0008
+#define ASCWHBABSTAT_CLRSCSDET 0x0010
+#define ASCWHBABSTAT_SETSCSDET 0x0020
+#define ASCWHBABSTAT_SETSCCDET 0x0040
+#define ASCWHBABSTAT_CLRSCCDET 0x0080
+#define ASCWHBABSTAT_CLRDETWAIT 0x0100
+#define ASCWHBABSTAT_SETDETWAIT 0x0200
+
+/* TXFCON register's bits and bitfields */
+#define ASCTXFCON_TXFEN 0x0001
+#define ASCTXFCON_TXFFLU 0x0002
+#define ASCTXFCON_TXTMEN 0x0004
+#define ASCTXFCON_TXFITLMASK 0x3F00
+#define ASCTXFCON_TXFITLOFF 8
+
+/* RXFCON register's bits and bitfields */
+#define ASCRXFCON_RXFEN 0x0001
+#define ASCRXFCON_RXFFLU 0x0002
+#define ASCRXFCON_RXTMEN 0x0004
+#define ASCRXFCON_RXFITLMASK 0x3F00
+#define ASCRXFCON_RXFITLOFF 8
+
+/* FSTAT register's bits and bitfields */
+#define ASCFSTAT_RXFFLMASK 0x003F
+#define ASCFSTAT_TXFFLMASK 0x3F00
+#define ASCFSTAT_TXFFLOFF 8
+
+#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT);
+
+typedef struct /* incaAsc_t */
+{
+ volatile unsigned long asc_clc; /*0x0000*/
+ volatile unsigned long asc_pisel; /*0x0004*/
+ volatile unsigned long asc_rsvd1[2]; /* for mapping */ /*0x0008*/
+ volatile unsigned long asc_con; /*0x0010*/
+ volatile unsigned long asc_bg; /*0x0014*/
+ volatile unsigned long asc_fdv; /*0x0018*/
+ volatile unsigned long asc_pmw; /* not used */ /*0x001C*/
+ volatile unsigned long asc_tbuf; /*0x0020*/
+ volatile unsigned long asc_rbuf; /*0x0024*/
+ volatile unsigned long asc_rsvd2[2]; /* for mapping */ /*0x0028*/
+ volatile unsigned long asc_abcon; /*0x0030*/
+ volatile unsigned long asc_abstat; /* not used */ /*0x0034*/
+ volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0038*/
+ volatile unsigned long asc_rxfcon; /*0x0040*/
+ volatile unsigned long asc_txfcon; /*0x0044*/
+ volatile unsigned long asc_fstat; /*0x0048*/
+ volatile unsigned long asc_rsvd4; /* for mapping */ /*0x004C*/
+ volatile unsigned long asc_whbcon; /*0x0050*/
+ volatile unsigned long asc_whbabcon; /*0x0054*/
+ volatile unsigned long asc_whbabstat; /* not used */ /*0x0058*/
+
+} incaAsc_t;
+
+#endif /* __INCincaAscSioh */
--- /dev/null
+/* Only eth0 supported for now
+ *
+ * (C) Copyright 2003
+ * Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+
+#ifdef CONFIG_AU1X00
+
+#if defined(CFG_DISCOVER_PHY)
+#error "PHY not supported yet"
+/* We just assume that we are running 100FD for now */
+/* We all use switches, right? ;-) */
+#endif
+
+/* I assume ethernet behaves like au1000 */
+
+#ifdef CONFIG_AU1000
+/* Base address differ between cpu:s */
+#define ETH0_BASE AU1000_ETH0_BASE
+#define MAC0_ENABLE AU1000_MAC0_ENABLE
+#else
+#ifdef CONFIG_AU1100
+#define ETH0_BASE AU1100_ETH0_BASE
+#define MAC0_ENABLE AU1100_MAC0_ENABLE
+#else
+#ifdef CONFIG_AU1500
+#define ETH0_BASE AU1500_ETH0_BASE
+#define MAC0_ENABLE AU1500_MAC0_ENABLE
+#else
+#ifdef CONFIG_AU1550
+#define ETH0_BASE AU1550_ETH0_BASE
+#define MAC0_ENABLE AU1550_MAC0_ENABLE
+#else
+#error "No valid cpu set"
+#endif
+#endif
+#endif
+#endif
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/au1x00.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+#include <miiphy.h>
+#endif
+
+/* Ethernet Transmit and Receive Buffers */
+#define DBUF_LENGTH 1520
+#define PKT_MAXBUF_SIZE 1518
+
+static char txbuf[DBUF_LENGTH];
+
+static int next_tx;
+static int next_rx;
+
+/* 4 rx and 4 tx fifos */
+#define NO_OF_FIFOS 4
+
+typedef struct{
+ u32 status;
+ u32 addr;
+ u32 len; /* Only used for tx */
+ u32 not_used;
+} mac_fifo_t;
+
+mac_fifo_t mac_fifo[NO_OF_FIFOS];
+
+#define MAX_WAIT 1000
+
+static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
+ volatile mac_fifo_t *fifo_tx =
+ (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
+ int i;
+ int res;
+
+ /* tx fifo should always be idle */
+ fifo_tx[next_tx].len = length;
+ fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
+ au_sync();
+
+ udelay(1);
+ i=0;
+ while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
+ if(i>MAX_WAIT){
+ printf("TX timeout\n");
+ break;
+ }
+ udelay(1);
+ i++;
+ }
+
+ /* Clear done bit */
+ fifo_tx[next_tx].addr = 0;
+ fifo_tx[next_tx].len = 0;
+ au_sync();
+
+ res = fifo_tx[next_tx].status;
+
+ next_tx++;
+ if(next_tx>=NO_OF_FIFOS){
+ next_tx=0;
+ }
+ return(res);
+}
+
+static int au1x00_recv(struct eth_device* dev){
+ volatile mac_fifo_t *fifo_rx =
+ (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
+
+ int length;
+ u32 status;
+
+ for(;;){
+ if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
+ /* Nothing has been received */
+ return(-1);
+ }
+
+ status = fifo_rx[next_rx].status;
+
+ length = status&0x3FFF;
+
+ if(status&RX_ERROR){
+ printf("Rx error 0x%x\n", status);
+ }
+ else{
+ /* Pass the packet up to the protocol layers. */
+ NetReceive(NetRxPackets[next_rx], length - 4);
+ }
+
+ fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;
+
+ next_rx++;
+ if(next_rx>=NO_OF_FIFOS){
+ next_rx=0;
+ }
+ } /* for */
+
+ return(0); /* Does anyone use this? */
+}
+
+static int au1x00_init(struct eth_device* dev, bd_t * bd){
+
+ volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
+ volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
+ volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
+ volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
+ volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
+ volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
+ volatile mac_fifo_t *fifo_tx =
+ (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
+ volatile mac_fifo_t *fifo_rx =
+ (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
+ int i;
+
+ next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
+ next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
+
+ /* We have to enable clocks before releasing reset */
+ *macen = MAC_EN_CLOCK_ENABLE;
+ udelay(10);
+
+ /* Enable MAC0 */
+ /* We have to release reset before accessing registers */
+ *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
+ MAC_EN_RESET1|MAC_EN_RESET2;
+ udelay(10);
+
+ for(i=0;i<NO_OF_FIFOS;i++){
+ fifo_tx[i].len = 0;
+ fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
+ fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
+ }
+
+ /* Put mac addr in little endian */
+#define ea eth_get_dev()->enetaddr
+ *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
+ *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
+ (ea[1] << 8) | (ea[0] ) ;
+#undef ea
+ *mac_mcast_low = 0;
+ *mac_mcast_high = 0;
+
+ /* Make sure the MAC buffer is in the correct endian mode */
+#ifdef __LITTLE_ENDIAN
+ *mac_ctrl = MAC_FULL_DUPLEX;
+ udelay(1);
+ *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
+#else
+ *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
+ udelay(1);
+ *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
+#endif
+
+ return(1);
+}
+
+static void au1x00_halt(struct eth_device* dev){
+}
+
+int au1x00_enet_initialize(bd_t *bis){
+ struct eth_device* dev;
+
+ if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
+ puts ("malloc failed\n");
+ return 0;
+ }
+
+ memset(dev, 0, sizeof *dev);
+
+ sprintf(dev->name, "Au1X00 ethernet");
+ dev->iobase = 0;
+ dev->priv = 0;
+ dev->init = au1x00_init;
+ dev->halt = au1x00_halt;
+ dev->send = au1x00_send;
+ dev->recv = au1x00_recv;
+
+ eth_register(dev);
+
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+ miiphy_register(dev->name,
+ au1x00_miiphy_read, au1x00_miiphy_write);
+#endif
+
+ return 1;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+int au1x00_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short * value)
+{
+ volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
+ volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
+ u32 mii_control;
+ unsigned int timedout = 20;
+
+ while (*mii_control_reg & MAC_MII_BUSY) {
+ udelay(1000);
+ if (--timedout == 0) {
+ printf("au1x00_eth: miiphy_read busy timeout!!\n");
+ return -1;
+ }
+ }
+
+ mii_control = MAC_SET_MII_SELECT_REG(reg) |
+ MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
+
+ *mii_control_reg = mii_control;
+
+ timedout = 20;
+ while (*mii_control_reg & MAC_MII_BUSY) {
+ udelay(1000);
+ if (--timedout == 0) {
+ printf("au1x00_eth: miiphy_read busy timeout!!\n");
+ return -1;
+ }
+ }
+ *value = *mii_data_reg;
+ return 0;
+}
+
+int au1x00_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
+{
+ volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
+ volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
+ u32 mii_control;
+ unsigned int timedout = 20;
+
+ while (*mii_control_reg & MAC_MII_BUSY) {
+ udelay(1000);
+ if (--timedout == 0) {
+ printf("au1x00_eth: miiphy_write busy timeout!!\n");
+ return;
+ }
+ }
+
+ mii_control = MAC_SET_MII_SELECT_REG(reg) |
+ MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
+
+ *mii_data_reg = value;
+ *mii_control_reg = mii_control;
+ return 0;
+}
+#endif /* CONFIG_COMMANDS & CFG_CMD_MII */
+
+#endif /* CONFIG_AU1X00 */
--- /dev/null
+/*
+ * AU1X00 UART support
+ *
+ * Hardcoded to UART 0 for now
+ * Speed and options also hardcoded to 115200 8N1
+ *
+ * Copyright (c) 2003 Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_AU1X00
+
+#include <common.h>
+#include <asm/au1x00.h>
+
+/******************************************************************************
+*
+* serial_init - initialize a channel
+*
+* This routine initializes the number of data bits, parity
+* and set the selected baud rate. Interrupts are disabled.
+* Set the modem control signals if the option is selected.
+*
+* RETURNS: N/A
+*/
+
+int serial_init (void)
+{
+ volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR);
+ volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE);
+
+ /* Enable clocks first */
+ *uart_enable = UART_EN_CE;
+
+ /* Then release reset */
+ /* Must release reset before setting other regs */
+ *uart_enable = UART_EN_CE|UART_EN_E;
+
+ /* Activate fifos, reset tx and rx */
+ /* Set tx trigger level to 12 */
+ *uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|
+ UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12;
+
+ serial_setbrg();
+
+ return 0;
+}
+
+
+void serial_setbrg (void)
+{
+ volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
+ volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
+ volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL;
+ int sd;
+ int divisorx2;
+
+ /* sd is system clock divisor */
+ /* see section 10.4.5 in au1550 datasheet */
+ sd = (*sys_powerctrl & 0x03) + 2;
+
+ /* calulate 2x baudrate and round */
+ divisorx2 = ((CFG_HZ/(sd * 16 * CONFIG_BAUDRATE)));
+
+ if (divisorx2 & 0x01)
+ divisorx2 = divisorx2 + 1;
+
+ *uart_clk = divisorx2 / 2;
+
+ /* Set parity, stop bits and word length to 8N1 */
+ *uart_lcr = UART_LCR_WLEN8;
+}
+
+void serial_putc (const char c)
+{
+ volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
+ volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX);
+
+ if (c == '\n') serial_putc ('\r');
+
+ /* Wait for fifo to shift out some bytes */
+ while((*uart_lsr&UART_LSR_THRE)==0);
+
+ *uart_tx = (u32)c;
+}
+
+void serial_puts (const char *s)
+{
+ while (*s)
+ {
+ serial_putc (*s++);
+ }
+}
+
+int serial_getc (void)
+{
+ volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
+ char c;
+
+ while (!serial_tstc());
+
+ c = (*uart_rx&0xFF);
+ return c;
+}
+
+int serial_tstc (void)
+{
+ volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
+
+ if(*uart_lsr&UART_LSR_DR){
+ /* Data in rfifo */
+ return(1);
+ }
+ return 0;
+}
+#endif /* CONFIG_SERIAL_AU1X00 */
--- /dev/null
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
+ *
+ * (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+/*
+ * IMPORTANT NOTES
+ * 1 - you MUST define LITTLEENDIAN in the configuration file for the
+ * board or this driver will NOT work!
+ * 2 - this driver is intended for use with USB Mass Storage Devices
+ * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
+ */
+
+#include <config.h>
+
+#if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI)
+
+/* #include <pci.h> no PCI on the AU1x00 */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/au1x00.h>
+#include <usb.h>
+#include "au1x00_usb_ohci.h"
+
+#define OHCI_USE_NPS /* force NoPowerSwitching mode */
+#define OHCI_VERBOSE_DEBUG /* not always helpful */
+#define OHCI_FILL_TRACE
+
+#define USBH_ENABLE_BE (1<<0)
+#define USBH_ENABLE_C (1<<1)
+#define USBH_ENABLE_E (1<<2)
+#define USBH_ENABLE_CE (1<<3)
+#define USBH_ENABLE_RD (1<<4)
+
+#ifdef LITTLEENDIAN
+#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C)
+#else
+#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE)
+#endif
+
+
+/* For initializing controller (mask in an HCFS mode too) */
+#define OHCI_CONTROL_INIT \
+ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
+
+#undef readl
+#undef writel
+
+#define readl(a) au_readl((long)(a))
+#define writel(v,a) au_writel((v),(int)(a))
+
+#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
+
+#define DEBUG
+#ifdef DEBUG
+#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
+#else
+#define dbg(format, arg...) do {} while(0)
+#endif /* DEBUG */
+#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
+#define SHOW_INFO
+#ifdef SHOW_INFO
+#define info(format, arg...) printf("INFO: " format "\n", ## arg)
+#else
+#define info(format, arg...) do {} while(0)
+#endif
+
+#define m16_swap(x) swap_16(x)
+#define m32_swap(x) swap_32(x)
+
+/* global ohci_t */
+static ohci_t gohci;
+/* this must be aligned to a 256 byte boundary */
+struct ohci_hcca ghcca[1];
+/* a pointer to the aligned storage */
+struct ohci_hcca *phcca;
+/* this allocates EDs for all possible endpoints */
+struct ohci_device ohci_dev;
+/* urb_priv */
+urb_priv_t urb_priv;
+/* RHSC flag */
+int got_rhsc;
+/* device which was disconnected */
+struct usb_device *devgone;
+
+/*-------------------------------------------------------------------------*/
+
+/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
+ * The erratum (#4) description is incorrect. AMD's workaround waits
+ * till some bits (mostly reserved) are clear; ok for all revs.
+ */
+#define OHCI_QUIRK_AMD756 0xabcd
+#define read_roothub(hc, register, mask) ({ \
+ u32 temp = readl (&hc->regs->roothub.register); \
+ if (hc->flags & OHCI_QUIRK_AMD756) \
+ while (temp & mask) \
+ temp = readl (&hc->regs->roothub.register); \
+ temp; })
+
+static u32 roothub_a (struct ohci *hc)
+ { return read_roothub (hc, a, 0xfc0fe000); }
+static inline u32 roothub_b (struct ohci *hc)
+ { return readl (&hc->regs->roothub.b); }
+static inline u32 roothub_status (struct ohci *hc)
+ { return readl (&hc->regs->roothub.status); }
+static u32 roothub_portstatus (struct ohci *hc, int i)
+ { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
+
+
+/* forward declaration */
+static int hc_interrupt (void);
+static void
+td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
+ int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
+
+/*-------------------------------------------------------------------------*
+ * URB support functions
+ *-------------------------------------------------------------------------*/
+
+/* free HCD-private data associated with this URB */
+
+static void urb_free_priv (urb_priv_t * urb)
+{
+ int i;
+ int last;
+ struct td * td;
+
+ last = urb->length - 1;
+ if (last >= 0) {
+ for (i = 0; i <= last; i++) {
+ td = urb->td[i];
+ if (td) {
+ td->usb_dev = NULL;
+ urb->td[i] = NULL;
+ }
+ }
+ }
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+static int sohci_get_current_frame_number (struct usb_device * dev);
+
+/* debug| print the main components of an URB
+ * small: 0) header + data packets 1) just header */
+
+static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
+ int transfer_len, struct devrequest * setup, char * str, int small)
+{
+ urb_priv_t * purb = &urb_priv;
+
+ dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
+ str,
+ sohci_get_current_frame_number (dev),
+ usb_pipedevice (pipe),
+ usb_pipeendpoint (pipe),
+ usb_pipeout (pipe)? 'O': 'I',
+ usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
+ (usb_pipecontrol (pipe)? "CTRL": "BULK"),
+ purb->actual_length,
+ transfer_len, dev->status);
+#ifdef OHCI_VERBOSE_DEBUG
+ if (!small) {
+ int i, len;
+
+ if (usb_pipecontrol (pipe)) {
+ printf (__FILE__ ": cmd(8):");
+ for (i = 0; i < 8 ; i++)
+ printf (" %02x", ((__u8 *) setup) [i]);
+ printf ("\n");
+ }
+ if (transfer_len > 0 && buffer) {
+ printf (__FILE__ ": data(%d/%d):",
+ purb->actual_length,
+ transfer_len);
+ len = usb_pipeout (pipe)?
+ transfer_len: purb->actual_length;
+ for (i = 0; i < 16 && i < len; i++)
+ printf (" %02x", ((__u8 *) buffer) [i]);
+ printf ("%s\n", i < len? "...": "");
+ }
+ }
+#endif
+}
+
+/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
+void ep_print_int_eds (ohci_t *ohci, char * str) {
+ int i, j;
+ __u32 * ed_p;
+ for (i= 0; i < 32; i++) {
+ j = 5;
+ ed_p = &(ohci->hcca->int_table [i]);
+ if (*ed_p == 0)
+ continue;
+ printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
+ while (*ed_p != 0 && j--) {
+ ed_t *ed = (ed_t *)m32_swap(ed_p);
+ printf (" ed: %4x;", ed->hwINFO);
+ ed_p = &ed->hwNextED;
+ }
+ printf ("\n");
+ }
+}
+
+static void ohci_dump_intr_mask (char *label, __u32 mask)
+{
+ dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
+ label,
+ mask,
+ (mask & OHCI_INTR_MIE) ? " MIE" : "",
+ (mask & OHCI_INTR_OC) ? " OC" : "",
+ (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
+ (mask & OHCI_INTR_FNO) ? " FNO" : "",
+ (mask & OHCI_INTR_UE) ? " UE" : "",
+ (mask & OHCI_INTR_RD) ? " RD" : "",
+ (mask & OHCI_INTR_SF) ? " SF" : "",
+ (mask & OHCI_INTR_WDH) ? " WDH" : "",
+ (mask & OHCI_INTR_SO) ? " SO" : ""
+ );
+}
+
+static void maybe_print_eds (char *label, __u32 value)
+{
+ ed_t *edp = (ed_t *)value;
+
+ if (value) {
+ dbg ("%s %08x", label, value);
+ dbg ("%08x", edp->hwINFO);
+ dbg ("%08x", edp->hwTailP);
+ dbg ("%08x", edp->hwHeadP);
+ dbg ("%08x", edp->hwNextED);
+ }
+}
+
+static char * hcfs2string (int state)
+{
+ switch (state) {
+ case OHCI_USB_RESET: return "reset";
+ case OHCI_USB_RESUME: return "resume";
+ case OHCI_USB_OPER: return "operational";
+ case OHCI_USB_SUSPEND: return "suspend";
+ }
+ return "?";
+}
+
+/* dump control and status registers */
+static void ohci_dump_status (ohci_t *controller)
+{
+ struct ohci_regs *regs = controller->regs;
+ __u32 temp;
+
+ temp = readl (®s->revision) & 0xff;
+ if (temp != 0x10)
+ dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
+
+ temp = readl (®s->control);
+ dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
+ (temp & OHCI_CTRL_RWE) ? " RWE" : "",
+ (temp & OHCI_CTRL_RWC) ? " RWC" : "",
+ (temp & OHCI_CTRL_IR) ? " IR" : "",
+ hcfs2string (temp & OHCI_CTRL_HCFS),
+ (temp & OHCI_CTRL_BLE) ? " BLE" : "",
+ (temp & OHCI_CTRL_CLE) ? " CLE" : "",
+ (temp & OHCI_CTRL_IE) ? " IE" : "",
+ (temp & OHCI_CTRL_PLE) ? " PLE" : "",
+ temp & OHCI_CTRL_CBSR
+ );
+
+ temp = readl (®s->cmdstatus);
+ dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
+ (temp & OHCI_SOC) >> 16,
+ (temp & OHCI_OCR) ? " OCR" : "",
+ (temp & OHCI_BLF) ? " BLF" : "",
+ (temp & OHCI_CLF) ? " CLF" : "",
+ (temp & OHCI_HCR) ? " HCR" : ""
+ );
+
+ ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus));
+ ohci_dump_intr_mask ("intrenable", readl (®s->intrenable));
+
+ maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent));
+
+ maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead));
+ maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent));
+
+ maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead));
+ maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent));
+
+ maybe_print_eds ("donehead", readl (®s->donehead));
+}
+
+static void ohci_dump_roothub (ohci_t *controller, int verbose)
+{
+ __u32 temp, ndp, i;
+
+ temp = roothub_a (controller);
+ ndp = (temp & RH_A_NDP);
+
+ if (verbose) {
+ dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
+ ((temp & RH_A_POTPGT) >> 24) & 0xff,
+ (temp & RH_A_NOCP) ? " NOCP" : "",
+ (temp & RH_A_OCPM) ? " OCPM" : "",
+ (temp & RH_A_DT) ? " DT" : "",
+ (temp & RH_A_NPS) ? " NPS" : "",
+ (temp & RH_A_PSM) ? " PSM" : "",
+ ndp
+ );
+ temp = roothub_b (controller);
+ dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
+ temp,
+ (temp & RH_B_PPCM) >> 16,
+ (temp & RH_B_DR)
+ );
+ temp = roothub_status (controller);
+ dbg ("roothub.status: %08x%s%s%s%s%s%s",
+ temp,
+ (temp & RH_HS_CRWE) ? " CRWE" : "",
+ (temp & RH_HS_OCIC) ? " OCIC" : "",
+ (temp & RH_HS_LPSC) ? " LPSC" : "",
+ (temp & RH_HS_DRWE) ? " DRWE" : "",
+ (temp & RH_HS_OCI) ? " OCI" : "",
+ (temp & RH_HS_LPS) ? " LPS" : ""
+ );
+ }
+
+ for (i = 0; i < ndp; i++) {
+ temp = roothub_portstatus (controller, i);
+ dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
+ i,
+ temp,
+ (temp & RH_PS_PRSC) ? " PRSC" : "",
+ (temp & RH_PS_OCIC) ? " OCIC" : "",
+ (temp & RH_PS_PSSC) ? " PSSC" : "",
+ (temp & RH_PS_PESC) ? " PESC" : "",
+ (temp & RH_PS_CSC) ? " CSC" : "",
+
+ (temp & RH_PS_LSDA) ? " LSDA" : "",
+ (temp & RH_PS_PPS) ? " PPS" : "",
+ (temp & RH_PS_PRS) ? " PRS" : "",
+ (temp & RH_PS_POCI) ? " POCI" : "",
+ (temp & RH_PS_PSS) ? " PSS" : "",
+
+ (temp & RH_PS_PES) ? " PES" : "",
+ (temp & RH_PS_CCS) ? " CCS" : ""
+ );
+ }
+}
+
+static void ohci_dump (ohci_t *controller, int verbose)
+{
+ dbg ("OHCI controller usb-%s state", controller->slot_name);
+
+ /* dumps some of the state we know about */
+ ohci_dump_status (controller);
+ if (verbose)
+ ep_print_int_eds (controller, "hcca");
+ dbg ("hcca frame #%04x", controller->hcca->frame_no);
+ ohci_dump_roothub (controller, 1);
+}
+
+
+#endif /* DEBUG */
+
+/*-------------------------------------------------------------------------*
+ * Interface functions (URB)
+ *-------------------------------------------------------------------------*/
+
+/* get a transfer request */
+
+int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, int interval)
+{
+ ohci_t *ohci;
+ ed_t * ed;
+ urb_priv_t *purb_priv;
+ int i, size = 0;
+
+ ohci = &gohci;
+
+ /* when controller's hung, permit only roothub cleanup attempts
+ * such as powering down ports */
+ if (ohci->disabled) {
+ err("sohci_submit_job: EPIPE");
+ return -1;
+ }
+
+ /* every endpoint has a ed, locate and fill it */
+ if (!(ed = ep_add_ed (dev, pipe))) {
+ err("sohci_submit_job: ENOMEM");
+ return -1;
+ }
+
+ /* for the private part of the URB we need the number of TDs (size) */
+ switch (usb_pipetype (pipe)) {
+ case PIPE_BULK: /* one TD for every 4096 Byte */
+ size = (transfer_len - 1) / 4096 + 1;
+ break;
+ case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
+ size = (transfer_len == 0)? 2:
+ (transfer_len - 1) / 4096 + 3;
+ break;
+ }
+
+ if (size >= (N_URB_TD - 1)) {
+ err("need %d TDs, only have %d", size, N_URB_TD);
+ return -1;
+ }
+ purb_priv = &urb_priv;
+ purb_priv->pipe = pipe;
+
+ /* fill the private part of the URB */
+ purb_priv->length = size;
+ purb_priv->ed = ed;
+ purb_priv->actual_length = 0;
+
+ /* allocate the TDs */
+ /* note that td[0] was allocated in ep_add_ed */
+ for (i = 0; i < size; i++) {
+ purb_priv->td[i] = td_alloc (dev);
+ if (!purb_priv->td[i]) {
+ purb_priv->length = i;
+ urb_free_priv (purb_priv);
+ err("sohci_submit_job: ENOMEM");
+ return -1;
+ }
+ }
+
+ if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
+ urb_free_priv (purb_priv);
+ err("sohci_submit_job: EINVAL");
+ return -1;
+ }
+
+ /* link the ed into a chain if is not already */
+ if (ed->state != ED_OPER)
+ ep_link (ohci, ed);
+
+ /* fill the TDs and link it to the ed */
+ td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+/* tell us the current USB frame number */
+
+static int sohci_get_current_frame_number (struct usb_device *usb_dev)
+{
+ ohci_t *ohci = &gohci;
+
+ return m16_swap (ohci->hcca->frame_no);
+}
+#endif
+
+/*-------------------------------------------------------------------------*
+ * ED handling functions
+ *-------------------------------------------------------------------------*/
+
+/* link an ed into one of the HC chains */
+
+static int ep_link (ohci_t *ohci, ed_t *edi)
+{
+ volatile ed_t *ed = edi;
+
+ ed->state = ED_OPER;
+
+ switch (ed->type) {
+ case PIPE_CONTROL:
+ ed->hwNextED = 0;
+ if (ohci->ed_controltail == NULL) {
+ writel ((long)ed, &ohci->regs->ed_controlhead);
+ } else {
+ ohci->ed_controltail->hwNextED = m32_swap (ed);
+ }
+ ed->ed_prev = ohci->ed_controltail;
+ if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
+ !ohci->ed_rm_list[1] && !ohci->sleeping) {
+ ohci->hc_control |= OHCI_CTRL_CLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ ohci->ed_controltail = edi;
+ break;
+
+ case PIPE_BULK:
+ ed->hwNextED = 0;
+ if (ohci->ed_bulktail == NULL) {
+ writel ((long)ed, &ohci->regs->ed_bulkhead);
+ } else {
+ ohci->ed_bulktail->hwNextED = m32_swap (ed);
+ }
+ ed->ed_prev = ohci->ed_bulktail;
+ if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
+ !ohci->ed_rm_list[1] && !ohci->sleeping) {
+ ohci->hc_control |= OHCI_CTRL_BLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ ohci->ed_bulktail = edi;
+ break;
+ }
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* unlink an ed from one of the HC chains.
+ * just the link to the ed is unlinked.
+ * the link from the ed still points to another operational ed or 0
+ * so the HC can eventually finish the processing of the unlinked ed */
+
+static int ep_unlink (ohci_t *ohci, ed_t *ed)
+{
+ ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
+
+ switch (ed->type) {
+ case PIPE_CONTROL:
+ if (ed->ed_prev == NULL) {
+ if (!ed->hwNextED) {
+ ohci->hc_control &= ~OHCI_CTRL_CLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
+ } else {
+ ed->ed_prev->hwNextED = ed->hwNextED;
+ }
+ if (ohci->ed_controltail == ed) {
+ ohci->ed_controltail = ed->ed_prev;
+ } else {
+ ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+ }
+ break;
+
+ case PIPE_BULK:
+ if (ed->ed_prev == NULL) {
+ if (!ed->hwNextED) {
+ ohci->hc_control &= ~OHCI_CTRL_BLE;
+ writel (ohci->hc_control, &ohci->regs->control);
+ }
+ writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
+ } else {
+ ed->ed_prev->hwNextED = ed->hwNextED;
+ }
+ if (ohci->ed_bulktail == ed) {
+ ohci->ed_bulktail = ed->ed_prev;
+ } else {
+ ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+ }
+ break;
+ }
+ ed->state = ED_UNLINK;
+ return 0;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
+ * but the USB stack is a little bit stateless so we do it at every transaction
+ * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
+ * in all other cases the state is left unchanged
+ * the ed info fields are setted anyway even though most of them should not change */
+
+static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
+{
+ td_t *td;
+ ed_t *ed_ret;
+ volatile ed_t *ed;
+
+ ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
+ (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
+
+ if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
+ err("ep_add_ed: pending delete");
+ /* pending delete request */
+ return NULL;
+ }
+
+ if (ed->state == ED_NEW) {
+ ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
+ /* dummy td; end of td list for ed */
+ td = td_alloc (usb_dev);
+ ed->hwTailP = m32_swap (td);
+ ed->hwHeadP = ed->hwTailP;
+ ed->state = ED_UNLINK;
+ ed->type = usb_pipetype (pipe);
+ ohci_dev.ed_cnt++;
+ }
+
+ ed->hwINFO = m32_swap (usb_pipedevice (pipe)
+ | usb_pipeendpoint (pipe) << 7
+ | (usb_pipeisoc (pipe)? 0x8000: 0)
+ | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
+ | usb_pipeslow (pipe) << 13
+ | usb_maxpacket (usb_dev, pipe) << 16);
+
+ return ed_ret;
+}
+
+/*-------------------------------------------------------------------------*
+ * TD handling functions
+ *-------------------------------------------------------------------------*/
+
+/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
+
+static void td_fill (ohci_t *ohci, unsigned int info,
+ void *data, int len,
+ struct usb_device *dev, int index, urb_priv_t *urb_priv)
+{
+ volatile td_t *td, *td_pt;
+#ifdef OHCI_FILL_TRACE
+ int i;
+#endif
+
+ if (index > urb_priv->length) {
+ err("index > length");
+ return;
+ }
+ /* use this td as the next dummy */
+ td_pt = urb_priv->td [index];
+ td_pt->hwNextTD = 0;
+
+ /* fill the old dummy TD */
+ td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
+
+ td->ed = urb_priv->ed;
+ td->next_dl_td = NULL;
+ td->index = index;
+ td->data = (__u32)data;
+#ifdef OHCI_FILL_TRACE
+ if (1 || ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe))) {
+ for (i = 0; i < len; i++)
+ printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]);
+ }
+#endif
+ if (!len)
+ data = 0;
+
+ td->hwINFO = m32_swap (info);
+ td->hwCBP = m32_swap (data);
+ if (data)
+ td->hwBE = m32_swap (data + len - 1);
+ else
+ td->hwBE = 0;
+ td->hwNextTD = m32_swap (td_pt);
+ td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
+
+ /* append to queue */
+ td->ed->hwTailP = td->hwNextTD;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* prepare all TDs of a transfer */
+
+#define kseg_to_phys(x) ((void *)((__u32)(x) - 0x80000000))
+
+static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
+{
+ ohci_t *ohci = &gohci;
+ int data_len = transfer_len;
+ void *data;
+ int cnt = 0;
+ __u32 info = 0;
+ unsigned int toggle = 0;
+
+ /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
+ if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
+ toggle = TD_T_TOGGLE;
+ } else {
+ toggle = TD_T_DATA0;
+ usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
+ }
+ urb->td_cnt = 0;
+ if (data_len)
+ data = kseg_to_phys(buffer);
+ else
+ data = 0;
+
+ switch (usb_pipetype (pipe)) {
+ case PIPE_BULK:
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
+ while(data_len > 4096) {
+ td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
+ data += 4096; data_len -= 4096; cnt++;
+ }
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
+ td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
+ cnt++;
+
+ if (!ohci->sleeping)
+ writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
+ break;
+
+ case PIPE_CONTROL:
+ info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
+ td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb);
+ if (data_len > 0) {
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
+ /* NOTE: mishandles transfers >8K, some >4K */
+ td_fill (ohci, info, data, data_len, dev, cnt++, urb);
+ }
+ info = usb_pipeout (pipe)?
+ TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
+ td_fill (ohci, info, data, 0, dev, cnt++, urb);
+ if (!ohci->sleeping)
+ writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
+ break;
+ }
+ if (urb->length != cnt)
+ dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
+}
+
+/*-------------------------------------------------------------------------*
+ * Done List handling functions
+ *-------------------------------------------------------------------------*/
+
+
+/* calculate the transfer length and update the urb */
+
+static void dl_transfer_length(td_t * td)
+{
+ __u32 tdINFO, tdBE, tdCBP;
+ urb_priv_t *lurb_priv = &urb_priv;
+
+ tdINFO = m32_swap (td->hwINFO);
+ tdBE = m32_swap (td->hwBE);
+ tdCBP = m32_swap (td->hwCBP);
+
+
+ if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
+ ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
+ if (tdBE != 0) {
+ if (td->hwCBP == 0)
+ lurb_priv->actual_length += tdBE - td->data + 1;
+ else
+ lurb_priv->actual_length += tdCBP - td->data;
+ }
+ }
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* replies to the request have to be on a FIFO basis so
+ * we reverse the reversed done-list */
+
+static td_t * dl_reverse_done_list (ohci_t *ohci)
+{
+ __u32 td_list_hc;
+ td_t *td_rev = NULL;
+ td_t *td_list = NULL;
+ urb_priv_t *lurb_priv = NULL;
+
+ td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
+ ohci->hcca->done_head = 0;
+
+ while (td_list_hc) {
+ td_list = (td_t *)td_list_hc;
+
+ if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
+ lurb_priv = &urb_priv;
+ dbg(" USB-error/status: %x : %p",
+ TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
+ if (td_list->ed->hwHeadP & m32_swap (0x1)) {
+ if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
+ td_list->ed->hwHeadP =
+ (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
+ (td_list->ed->hwHeadP & m32_swap (0x2));
+ lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
+ } else
+ td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
+ }
+ }
+
+ td_list->next_dl_td = td_rev;
+ td_rev = td_list;
+ td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
+ }
+ return td_list;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* td done list */
+static int dl_done_list (ohci_t *ohci, td_t *td_list)
+{
+ td_t *td_list_next = NULL;
+ ed_t *ed;
+ int cc = 0;
+ int stat = 0;
+ /* urb_t *urb; */
+ urb_priv_t *lurb_priv;
+ __u32 tdINFO, edHeadP, edTailP;
+
+ while (td_list) {
+ td_list_next = td_list->next_dl_td;
+
+ lurb_priv = &urb_priv;
+ tdINFO = m32_swap (td_list->hwINFO);
+
+ ed = td_list->ed;
+
+ dl_transfer_length(td_list);
+
+ /* error code of transfer */
+ cc = TD_CC_GET (tdINFO);
+ if (cc != 0) {
+ dbg("ConditionCode %#x", cc);
+ stat = cc_to_error[cc];
+ }
+
+ if (ed->state != ED_NEW) {
+ edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
+ edTailP = m32_swap (ed->hwTailP);
+
+ /* unlink eds if they are not busy */
+ if ((edHeadP == edTailP) && (ed->state == ED_OPER))
+ ep_unlink (ohci, ed);
+ }
+
+ td_list = td_list_next;
+ }
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*
+ * Virtual Root Hub
+ *-------------------------------------------------------------------------*/
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] =
+{
+ 0x12, /* __u8 bLength; */
+ 0x01, /* __u8 bDescriptorType; Device */
+ 0x10, /* __u16 bcdUSB; v1.1 */
+ 0x01,
+ 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 bDeviceSubClass; */
+ 0x00, /* __u8 bDeviceProtocol; */
+ 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
+ 0x00, /* __u16 idVendor; */
+ 0x00,
+ 0x00, /* __u16 idProduct; */
+ 0x00,
+ 0x00, /* __u16 bcdDevice; */
+ 0x00,
+ 0x00, /* __u8 iManufacturer; */
+ 0x01, /* __u8 iProduct; */
+ 0x00, /* __u8 iSerialNumber; */
+ 0x01 /* __u8 bNumConfigurations; */
+};
+
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] =
+{
+ 0x09, /* __u8 bLength; */
+ 0x02, /* __u8 bDescriptorType; Configuration */
+ 0x19, /* __u16 wTotalLength; */
+ 0x00,
+ 0x01, /* __u8 bNumInterfaces; */
+ 0x01, /* __u8 bConfigurationValue; */
+ 0x00, /* __u8 iConfiguration; */
+ 0x40, /* __u8 bmAttributes;
+ Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+ 0x00, /* __u8 MaxPower; */
+
+ /* interface */
+ 0x09, /* __u8 if_bLength; */
+ 0x04, /* __u8 if_bDescriptorType; Interface */
+ 0x00, /* __u8 if_bInterfaceNumber; */
+ 0x00, /* __u8 if_bAlternateSetting; */
+ 0x01, /* __u8 if_bNumEndpoints; */
+ 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 if_bInterfaceSubClass; */
+ 0x00, /* __u8 if_bInterfaceProtocol; */
+ 0x00, /* __u8 if_iInterface; */
+
+ /* endpoint */
+ 0x07, /* __u8 ep_bLength; */
+ 0x05, /* __u8 ep_bDescriptorType; Endpoint */
+ 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
+ 0x03, /* __u8 ep_bmAttributes; Interrupt */
+ 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+ 0x00,
+ 0xff /* __u8 ep_bInterval; 255 ms */
+};
+
+static unsigned char root_hub_str_index0[] =
+{
+ 0x04, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 0x09, /* __u8 lang ID */
+ 0x04, /* __u8 lang ID */
+};
+
+static unsigned char root_hub_str_index1[] =
+{
+ 28, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 'O', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'C', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'I', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'R', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 't', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'u', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'b', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+};
+
+/* Hub class-specific descriptor is constructed dynamically */
+
+
+/*-------------------------------------------------------------------------*/
+
+#define OK(x) len = (x); break
+#ifdef DEBUG
+#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
+#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
+#else
+#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
+#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
+#endif
+#define RD_RH_STAT roothub_status(&gohci)
+#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
+
+/* request to virtual root hub */
+
+int rh_check_port_status(ohci_t *controller)
+{
+ __u32 temp, ndp, i;
+ int res;
+
+ res = -1;
+ temp = roothub_a (controller);
+ ndp = (temp & RH_A_NDP);
+ for (i = 0; i < ndp; i++) {
+ temp = roothub_portstatus (controller, i);
+ /* check for a device disconnect */
+ if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
+ (RH_PS_PESC | RH_PS_CSC)) &&
+ ((temp & RH_PS_CCS) == 0)) {
+ res = i;
+ break;
+ }
+ }
+ return res;
+}
+
+static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len, struct devrequest *cmd)
+{
+ void * data = buffer;
+ int leni = transfer_len;
+ int len = 0;
+ int stat = 0;
+ __u32 datab[4];
+ __u8 *data_buf = (__u8 *)datab;
+ __u16 bmRType_bReq;
+ __u16 wValue;
+ __u16 wIndex;
+ __u16 wLength;
+
+#ifdef DEBUG
+urb_priv.actual_length = 0;
+pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
+#else
+ wait_ms(1);
+#endif
+ if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+ info("Root-Hub submit IRQ: NOT implemented");
+ return 0;
+ }
+
+ bmRType_bReq = cmd->requesttype | (cmd->request << 8);
+ wValue = m16_swap (cmd->value);
+ wIndex = m16_swap (cmd->index);
+ wLength = m16_swap (cmd->length);
+
+ info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
+ dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
+
+ switch (bmRType_bReq) {
+ /* Request Destination:
+ without flags: Device,
+ RH_INTERFACE: interface,
+ RH_ENDPOINT: endpoint,
+ RH_CLASS means HUB here,
+ RH_OTHER | RH_CLASS almost ever means HUB_PORT here
+ */
+
+ case RH_GET_STATUS:
+ *(__u16 *) data_buf = m16_swap (1); OK (2);
+ case RH_GET_STATUS | RH_INTERFACE:
+ *(__u16 *) data_buf = m16_swap (0); OK (2);
+ case RH_GET_STATUS | RH_ENDPOINT:
+ *(__u16 *) data_buf = m16_swap (0); OK (2);
+ case RH_GET_STATUS | RH_CLASS:
+ *(__u32 *) data_buf = m32_swap (
+ RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
+ OK (4);
+ case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+ *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
+
+ case RH_CLEAR_FEATURE | RH_ENDPOINT:
+ switch (wValue) {
+ case (RH_ENDPOINT_STALL): OK (0);
+ }
+ break;
+
+ case RH_CLEAR_FEATURE | RH_CLASS:
+ switch (wValue) {
+ case RH_C_HUB_LOCAL_POWER:
+ OK(0);
+ case (RH_C_HUB_OVER_CURRENT):
+ WR_RH_STAT(RH_HS_OCIC); OK (0);
+ }
+ break;
+
+ case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+ switch (wValue) {
+ case (RH_PORT_ENABLE):
+ WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
+ case (RH_PORT_SUSPEND):
+ WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
+ case (RH_PORT_POWER):
+ WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
+ case (RH_C_PORT_CONNECTION):
+ WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
+ case (RH_C_PORT_ENABLE):
+ WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
+ case (RH_C_PORT_SUSPEND):
+ WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
+ case (RH_C_PORT_OVER_CURRENT):
+ WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
+ case (RH_C_PORT_RESET):
+ WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
+ }
+ break;
+
+ case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+ switch (wValue) {
+ case (RH_PORT_SUSPEND):
+ WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
+ case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
+ if (RD_RH_PORTSTAT & RH_PS_CCS)
+ WR_RH_PORTSTAT (RH_PS_PRS);
+ OK (0);
+ case (RH_PORT_POWER):
+ WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
+ case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
+ if (RD_RH_PORTSTAT & RH_PS_CCS)
+ WR_RH_PORTSTAT (RH_PS_PES );
+ OK (0);
+ }
+ break;
+
+ case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
+
+ case RH_GET_DESCRIPTOR:
+ switch ((wValue & 0xff00) >> 8) {
+ case (0x01): /* device descriptor */
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_dev_des),
+ wLength));
+ data_buf = root_hub_dev_des; OK(len);
+ case (0x02): /* configuration descriptor */
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_config_des),
+ wLength));
+ data_buf = root_hub_config_des; OK(len);
+ case (0x03): /* string descriptors */
+ if(wValue==0x0300) {
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_str_index0),
+ wLength));
+ data_buf = root_hub_str_index0;
+ OK(len);
+ }
+ if(wValue==0x0301) {
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof (root_hub_str_index1),
+ wLength));
+ data_buf = root_hub_str_index1;
+ OK(len);
+ }
+ default:
+ stat = USB_ST_STALLED;
+ }
+ break;
+
+ case RH_GET_DESCRIPTOR | RH_CLASS:
+ {
+ __u32 temp = roothub_a (&gohci);
+
+ data_buf [0] = 9; /* min length; */
+ data_buf [1] = 0x29;
+ data_buf [2] = temp & RH_A_NDP;
+ data_buf [3] = 0;
+ if (temp & RH_A_PSM) /* per-port power switching? */
+ data_buf [3] |= 0x1;
+ if (temp & RH_A_NOCP) /* no overcurrent reporting? */
+ data_buf [3] |= 0x10;
+ else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
+ data_buf [3] |= 0x8;
+
+ /* corresponds to data_buf[4-7] */
+ datab [1] = 0;
+ data_buf [5] = (temp & RH_A_POTPGT) >> 24;
+ temp = roothub_b (&gohci);
+ data_buf [7] = temp & RH_B_DR;
+ if (data_buf [2] < 7) {
+ data_buf [8] = 0xff;
+ } else {
+ data_buf [0] += 2;
+ data_buf [8] = (temp & RH_B_DR) >> 8;
+ data_buf [10] = data_buf [9] = 0xff;
+ }
+
+ len = min_t(unsigned int, leni,
+ min_t(unsigned int, data_buf [0], wLength));
+ OK (len);
+ }
+
+ case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
+
+ case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
+
+ default:
+ dbg ("unsupported root hub command");
+ stat = USB_ST_STALLED;
+ }
+
+#ifdef DEBUG
+ ohci_dump_roothub (&gohci, 1);
+#else
+ wait_ms(1);
+#endif
+
+ len = min_t(int, len, leni);
+ if (data != data_buf)
+ memcpy (data, data_buf, len);
+ dev->act_len = len;
+ dev->status = stat;
+
+#ifdef DEBUG
+ if (transfer_len)
+ urb_priv.actual_length = transfer_len;
+ pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
+#else
+ wait_ms(1);
+#endif
+
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* common code for handling submit messages - used for all but root hub */
+/* accesses. */
+int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, int interval)
+{
+ int stat = 0;
+ int maxsize = usb_maxpacket(dev, pipe);
+ int timeout;
+
+ /* device pulled? Shortcut the action. */
+ if (devgone == dev) {
+ dev->status = USB_ST_CRC_ERR;
+ return 0;
+ }
+
+#ifdef DEBUG
+ urb_priv.actual_length = 0;
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#else
+ wait_ms(1);
+#endif
+ if (!maxsize) {
+ err("submit_common_message: pipesize for pipe %lx is zero",
+ pipe);
+ return -1;
+ }
+
+ if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
+ err("sohci_submit_job failed");
+ return -1;
+ }
+
+ wait_ms(10);
+ /* ohci_dump_status(&gohci); */
+
+ /* allow more time for a BULK device to react - some are slow */
+#define BULK_TO 5000 /* timeout in milliseconds */
+ if (usb_pipetype (pipe) == PIPE_BULK)
+ timeout = BULK_TO;
+ else
+ timeout = 100;
+
+ timeout *= 4;
+ /* wait for it to complete */
+ for (;;) {
+ /* check whether the controller is done */
+ stat = hc_interrupt();
+ if (stat < 0) {
+ stat = USB_ST_CRC_ERR;
+ break;
+ }
+ if (stat >= 0 && stat != 0xff) {
+ /* 0xff is returned for an SF-interrupt */
+ break;
+ }
+ if (--timeout) {
+ udelay(250); /* wait_ms(1); */
+ } else {
+ err("CTL:TIMEOUT ");
+ stat = USB_ST_CRC_ERR;
+ break;
+ }
+ }
+ /* we got an Root Hub Status Change interrupt */
+ if (got_rhsc) {
+#ifdef DEBUG
+ ohci_dump_roothub (&gohci, 1);
+#endif
+ got_rhsc = 0;
+ /* abuse timeout */
+ timeout = rh_check_port_status(&gohci);
+ if (timeout >= 0) {
+#if 0 /* this does nothing useful, but leave it here in case that changes */
+ /* the called routine adds 1 to the passed value */
+ usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
+#endif
+ /*
+ * XXX
+ * This is potentially dangerous because it assumes
+ * that only one device is ever plugged in!
+ */
+ devgone = dev;
+ }
+ }
+
+ dev->status = stat;
+ dev->act_len = transfer_len;
+
+#ifdef DEBUG
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
+#else
+ wait_ms(1);
+#endif
+
+ /* free TDs in urb_priv */
+ urb_free_priv (&urb_priv);
+ return 0;
+}
+
+/* submit routines called from usb.c */
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len)
+{
+ info("submit_bulk_msg");
+ return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup)
+{
+ int maxsize = usb_maxpacket(dev, pipe);
+
+ info("submit_control_msg");
+#ifdef DEBUG
+ urb_priv.actual_length = 0;
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#else
+ wait_ms(1);
+#endif
+ if (!maxsize) {
+ err("submit_control_message: pipesize for pipe %lx is zero",
+ pipe);
+ return -1;
+ }
+ if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
+ gohci.rh.dev = dev;
+ /* root hub - redirect */
+ return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
+ setup);
+ }
+
+ return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
+}
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, int interval)
+{
+ info("submit_int_msg");
+ return -1;
+}
+
+/*-------------------------------------------------------------------------*
+ * HC functions
+ *-------------------------------------------------------------------------*/
+
+/* reset the HC and BUS */
+
+static int hc_reset (ohci_t *ohci)
+{
+ int timeout = 30;
+ int smm_timeout = 50; /* 0,5 sec */
+
+ if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
+ writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
+ info("USB HC TakeOver from SMM");
+ while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
+ wait_ms (10);
+ if (--smm_timeout == 0) {
+ err("USB HC TakeOver failed!");
+ return -1;
+ }
+ }
+ }
+
+ /* Disable HC interrupts */
+ writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
+
+ dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
+ ohci->slot_name,
+ readl (&ohci->regs->control));
+
+ /* Reset USB (needed by some controllers) */
+ writel (0, &ohci->regs->control);
+
+ /* HC Reset requires max 10 us delay */
+ writel (OHCI_HCR, &ohci->regs->cmdstatus);
+ while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
+ if (--timeout == 0) {
+ err("USB HC reset timed out!");
+ return -1;
+ }
+ udelay (1);
+ }
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Start an OHCI controller, set the BUS operational
+ * enable interrupts
+ * connect the virtual root hub */
+
+static int hc_start (ohci_t * ohci)
+{
+ __u32 mask;
+ unsigned int fminterval;
+
+ ohci->disabled = 1;
+
+ /* Tell the controller where the control and bulk lists are
+ * The lists are empty now. */
+
+ writel (0, &ohci->regs->ed_controlhead);
+ writel (0, &ohci->regs->ed_bulkhead);
+
+ writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
+
+ fminterval = 0x2edf;
+ writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
+ fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
+ writel (fminterval, &ohci->regs->fminterval);
+ writel (0x628, &ohci->regs->lsthresh);
+
+ /* start controller operations */
+ ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
+ ohci->disabled = 0;
+ writel (ohci->hc_control, &ohci->regs->control);
+
+ /* disable all interrupts */
+ mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
+ OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
+ OHCI_INTR_OC | OHCI_INTR_MIE);
+ writel (mask, &ohci->regs->intrdisable);
+ /* clear all interrupts */
+ mask &= ~OHCI_INTR_MIE;
+ writel (mask, &ohci->regs->intrstatus);
+ /* Choose the interrupts we care about now - but w/o MIE */
+ mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
+ writel (mask, &ohci->regs->intrenable);
+
+#ifdef OHCI_USE_NPS
+ /* required for AMD-756 and some Mac platforms */
+ writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
+ &ohci->regs->roothub.a);
+ writel (RH_HS_LPSC, &ohci->regs->roothub.status);
+#endif /* OHCI_USE_NPS */
+
+#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
+ /* POTPGT delay is bits 24-31, in 2 ms units. */
+ mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
+
+ /* connect the virtual root hub */
+ ohci->rh.devnum = 0;
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* an interrupt happens */
+
+static int
+hc_interrupt (void)
+{
+ ohci_t *ohci = &gohci;
+ struct ohci_regs *regs = ohci->regs;
+ int ints;
+ int stat = -1;
+
+ if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
+ ints = OHCI_INTR_WDH;
+ } else {
+ ints = readl (®s->intrstatus);
+ }
+
+ /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
+
+ if (ints & OHCI_INTR_RHSC) {
+ got_rhsc = 1;
+ }
+
+ if (ints & OHCI_INTR_UE) {
+ ohci->disabled++;
+ err ("OHCI Unrecoverable Error, controller usb-%s disabled",
+ ohci->slot_name);
+ /* e.g. due to PCI Master/Target Abort */
+
+#ifdef DEBUG
+ ohci_dump (ohci, 1);
+#else
+ wait_ms(1);
+#endif
+ /* FIXME: be optimistic, hope that bug won't repeat often. */
+ /* Make some non-interrupt context restart the controller. */
+ /* Count and limit the retries though; either hardware or */
+ /* software errors can go forever... */
+ hc_reset (ohci);
+ return -1;
+ }
+
+ if (ints & OHCI_INTR_WDH) {
+ wait_ms(1);
+ writel (OHCI_INTR_WDH, ®s->intrdisable);
+ stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
+ writel (OHCI_INTR_WDH, ®s->intrenable);
+ }
+
+ if (ints & OHCI_INTR_SO) {
+ dbg("USB Schedule overrun\n");
+ writel (OHCI_INTR_SO, ®s->intrenable);
+ stat = -1;
+ }
+
+ /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
+ if (ints & OHCI_INTR_SF) {
+ unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
+ wait_ms(1);
+ writel (OHCI_INTR_SF, ®s->intrdisable);
+ if (ohci->ed_rm_list[frame] != NULL)
+ writel (OHCI_INTR_SF, ®s->intrenable);
+ stat = 0xff;
+ }
+
+ writel (ints, ®s->intrstatus);
+ return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------*/
+
+/* De-allocate all resources.. */
+
+static void hc_release_ohci (ohci_t *ohci)
+{
+ dbg ("USB HC release ohci usb-%s", ohci->slot_name);
+
+ if (!ohci->disabled)
+ hc_reset (ohci);
+}
+
+/*-------------------------------------------------------------------------*/
+
+#define __read_32bit_c0_register(source, sel) \
+({ int __res; \
+ if (sel == 0) \
+ __asm__ __volatile__( \
+ "mfc0\t%0, " #source "\n\t" \
+ : "=r" (__res)); \
+ else \
+ __asm__ __volatile__( \
+ ".set\tmips32\n\t" \
+ "mfc0\t%0, " #source ", " #sel "\n\t" \
+ ".set\tmips0\n\t" \
+ : "=r" (__res)); \
+ __res; \
+})
+
+#define read_c0_prid() __read_32bit_c0_register($15, 0)
+
+/*
+ * low level initalisation routine, called from usb.c
+ */
+static char ohci_inited = 0;
+
+int usb_lowlevel_init(void)
+{
+ u32 pin_func;
+ u32 sys_freqctrl, sys_clksrc;
+ u32 prid = read_c0_prid();
+
+ dbg("in usb_lowlevel_init\n");
+
+ /* zero and disable FREQ2 */
+ sys_freqctrl = au_readl(SYS_FREQCTRL0);
+ sys_freqctrl &= ~0xFFF00000;
+ au_writel(sys_freqctrl, SYS_FREQCTRL0);
+
+ /* zero and disable USBH/USBD clocks */
+ sys_clksrc = au_readl(SYS_CLKSRC);
+ sys_clksrc &= ~0x00007FE0;
+ au_writel(sys_clksrc, SYS_CLKSRC);
+
+ sys_freqctrl = au_readl(SYS_FREQCTRL0);
+ sys_freqctrl &= ~0xFFF00000;
+
+ sys_clksrc = au_readl(SYS_CLKSRC);
+ sys_clksrc &= ~0x00007FE0;
+
+ switch (prid & 0x000000FF) {
+ case 0x00: /* DA */
+ case 0x01: /* HA */
+ case 0x02: /* HB */
+ /* CPU core freq to 48MHz to slow it way down... */
+ au_writel(4, SYS_CPUPLL);
+
+ /*
+ * Setup 48MHz FREQ2 from CPUPLL for USB Host
+ */
+ /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
+ sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
+ au_writel(sys_freqctrl, SYS_FREQCTRL0);
+
+ /* CPU core freq to 384MHz */
+ au_writel(0x20, SYS_CPUPLL);
+
+ printf("Au1000: 48MHz OHCI workaround enabled\n");
+ break;
+
+ default: /* HC and newer */
+ /* FREQ2 = aux/2 = 48 MHz */
+ sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
+ au_writel(sys_freqctrl, SYS_FREQCTRL0);
+ break;
+ }
+
+ /*
+ * Route 48MHz FREQ2 into USB Host and/or Device
+ */
+ sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
+ au_writel(sys_clksrc, SYS_CLKSRC);
+
+ /* configure pins GPIO[14:9] as GPIO */
+ pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
+
+ au_writel(pin_func, SYS_PINFUNC);
+ au_writel(0x2800, SYS_TRIOUTCLR);
+ au_writel(0x0030, SYS_OUTPUTCLR);
+
+ dbg("OHCI board setup complete\n");
+
+ /* enable host controller */
+ au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG);
+ udelay(1000);
+ au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG);
+ udelay(1000);
+
+ /* wait for reset complete (read register twice; see au1500 errata) */
+ while (au_readl(USB_HOST_CONFIG),
+ !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD))
+ udelay(1000);
+
+ dbg("OHCI clock running\n");
+
+ memset (&gohci, 0, sizeof (ohci_t));
+ memset (&urb_priv, 0, sizeof (urb_priv_t));
+
+ /* align the storage */
+ if ((__u32)&ghcca[0] & 0xff) {
+ err("HCCA not aligned!!");
+ return -1;
+ }
+ phcca = &ghcca[0];
+ info("aligned ghcca %p", phcca);
+ memset(&ohci_dev, 0, sizeof(struct ohci_device));
+ if ((__u32)&ohci_dev.ed[0] & 0x7) {
+ err("EDs not aligned!!");
+ return -1;
+ }
+ memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
+ if ((__u32)gtd & 0x7) {
+ err("TDs not aligned!!");
+ return -1;
+ }
+ ptd = gtd;
+ gohci.hcca = phcca;
+ memset (phcca, 0, sizeof (struct ohci_hcca));
+
+ gohci.disabled = 1;
+ gohci.sleeping = 0;
+ gohci.irq = -1;
+ gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000);
+
+ gohci.flags = 0;
+ gohci.slot_name = "au1x00";
+
+ dbg("OHCI revision: 0x%08x\n"
+ " RH: a: 0x%08x b: 0x%08x\n",
+ readl(&gohci.regs->revision),
+ readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b));
+
+ if (hc_reset (&gohci) < 0)
+ goto errout;
+
+ /* FIXME this is a second HC reset; why?? */
+ writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
+ wait_ms (10);
+
+ if (hc_start (&gohci) < 0)
+ goto errout;
+
+#ifdef DEBUG
+ ohci_dump (&gohci, 1);
+#else
+ wait_ms(1);
+#endif
+ ohci_inited = 1;
+ return 0;
+
+ errout:
+ err("OHCI initialization error\n");
+ hc_release_ohci (&gohci);
+ /* Initialization failed */
+ au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
+ return -1;
+}
+
+int usb_lowlevel_stop(void)
+{
+ /* this gets called really early - before the controller has */
+ /* even been initialized! */
+ if (!ohci_inited)
+ return 0;
+ /* TODO release any interrupts, etc. */
+ /* call hc_release_ohci() here ? */
+ hc_reset (&gohci);
+ /* may not want to do this */
+ /* Disable clock */
+ au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
+ return 0;
+}
+
+#endif /* CONFIG_USB_OHCI */
--- /dev/null
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * usb-ohci.h
+ */
+
+
+static int cc_to_error[16] = {
+
+/* mapping of the OHCI CC status to error codes */
+ /* No Error */ 0,
+ /* CRC Error */ USB_ST_CRC_ERR,
+ /* Bit Stuff */ USB_ST_BIT_ERR,
+ /* Data Togg */ USB_ST_CRC_ERR,
+ /* Stall */ USB_ST_STALLED,
+ /* DevNotResp */ -1,
+ /* PIDCheck */ USB_ST_BIT_ERR,
+ /* UnExpPID */ USB_ST_BIT_ERR,
+ /* DataOver */ USB_ST_BUF_ERR,
+ /* DataUnder */ USB_ST_BUF_ERR,
+ /* reservd */ -1,
+ /* reservd */ -1,
+ /* BufferOver */ USB_ST_BUF_ERR,
+ /* BuffUnder */ USB_ST_BUF_ERR,
+ /* Not Access */ -1,
+ /* Not Access */ -1
+};
+
+/* ED States */
+
+#define ED_NEW 0x00
+#define ED_UNLINK 0x01
+#define ED_OPER 0x02
+#define ED_DEL 0x04
+#define ED_URB_DEL 0x08
+
+/* usb_ohci_ed */
+struct ed {
+ __u32 hwINFO;
+ __u32 hwTailP;
+ __u32 hwHeadP;
+ __u32 hwNextED;
+
+ struct ed *ed_prev;
+ __u8 int_period;
+ __u8 int_branch;
+ __u8 int_load;
+ __u8 int_interval;
+ __u8 state;
+ __u8 type;
+ __u16 last_iso;
+ struct ed *ed_rm_list;
+
+ struct usb_device *usb_dev;
+ __u32 unused[3];
+} __attribute((aligned(16)));
+typedef struct ed ed_t;
+
+
+/* TD info field */
+#define TD_CC 0xf0000000
+#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
+#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
+#define TD_EC 0x0C000000
+#define TD_T 0x03000000
+#define TD_T_DATA0 0x02000000
+#define TD_T_DATA1 0x03000000
+#define TD_T_TOGGLE 0x00000000
+#define TD_R 0x00040000
+#define TD_DI 0x00E00000
+#define TD_DI_SET(X) (((X) & 0x07)<< 21)
+#define TD_DP 0x00180000
+#define TD_DP_SETUP 0x00000000
+#define TD_DP_IN 0x00100000
+#define TD_DP_OUT 0x00080000
+
+#define TD_ISO 0x00010000
+#define TD_DEL 0x00020000
+
+/* CC Codes */
+#define TD_CC_NOERROR 0x00
+#define TD_CC_CRC 0x01
+#define TD_CC_BITSTUFFING 0x02
+#define TD_CC_DATATOGGLEM 0x03
+#define TD_CC_STALL 0x04
+#define TD_DEVNOTRESP 0x05
+#define TD_PIDCHECKFAIL 0x06
+#define TD_UNEXPECTEDPID 0x07
+#define TD_DATAOVERRUN 0x08
+#define TD_DATAUNDERRUN 0x09
+#define TD_BUFFEROVERRUN 0x0C
+#define TD_BUFFERUNDERRUN 0x0D
+#define TD_NOTACCESSED 0x0F
+
+
+#define MAXPSW 1
+
+struct td {
+ __u32 hwINFO;
+ __u32 hwCBP; /* Current Buffer Pointer */
+ __u32 hwNextTD; /* Next TD Pointer */
+ __u32 hwBE; /* Memory Buffer End Pointer */
+
+ __u16 hwPSW[MAXPSW];
+ __u8 unused;
+ __u8 index;
+ struct ed *ed;
+ struct td *next_dl_td;
+ struct usb_device *usb_dev;
+ int transfer_len;
+ __u32 data;
+
+ __u32 unused2[2];
+} __attribute((aligned(32)));
+typedef struct td td_t;
+
+#define OHCI_ED_SKIP (1 << 14)
+
+/*
+ * The HCCA (Host Controller Communications Area) is a 256 byte
+ * structure defined in the OHCI spec. that the host controller is
+ * told the base address of. It must be 256-byte aligned.
+ */
+
+#define NUM_INTS 32 /* part of the OHCI standard */
+struct ohci_hcca {
+ __u32 int_table[NUM_INTS]; /* Interrupt ED table */
+ __u16 frame_no; /* current frame number */
+ __u16 pad1; /* set to 0 on each frame_no change */
+ __u32 done_head; /* info returned for an interrupt */
+ u8 reserved_for_hc[116];
+} __attribute((aligned(256)));
+
+
+/*
+ * Maximum number of root hub ports.
+ */
+#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
+
+/*
+ * This is the structure of the OHCI controller's memory mapped I/O
+ * region. This is Memory Mapped I/O. You must use the readl() and
+ * writel() macros defined in asm/io.h to access these!!
+ */
+struct ohci_regs {
+ /* control and status registers */
+ __u32 revision;
+ __u32 control;
+ __u32 cmdstatus;
+ __u32 intrstatus;
+ __u32 intrenable;
+ __u32 intrdisable;
+ /* memory pointers */
+ __u32 hcca;
+ __u32 ed_periodcurrent;
+ __u32 ed_controlhead;
+ __u32 ed_controlcurrent;
+ __u32 ed_bulkhead;
+ __u32 ed_bulkcurrent;
+ __u32 donehead;
+ /* frame counters */
+ __u32 fminterval;
+ __u32 fmremaining;
+ __u32 fmnumber;
+ __u32 periodicstart;
+ __u32 lsthresh;
+ /* Root hub ports */
+ struct ohci_roothub_regs {
+ __u32 a;
+ __u32 b;
+ __u32 status;
+ __u32 portstatus[MAX_ROOT_PORTS];
+ } roothub;
+} __attribute((aligned(32)));
+
+
+/* OHCI CONTROL AND STATUS REGISTER MASKS */
+
+/*
+ * HcControl (control) register masks
+ */
+#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
+#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
+#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
+#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
+#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
+#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
+#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
+#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
+#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
+
+/* pre-shifted values for HCFS */
+# define OHCI_USB_RESET (0 << 6)
+# define OHCI_USB_RESUME (1 << 6)
+# define OHCI_USB_OPER (2 << 6)
+# define OHCI_USB_SUSPEND (3 << 6)
+
+/*
+ * HcCommandStatus (cmdstatus) register masks
+ */
+#define OHCI_HCR (1 << 0) /* host controller reset */
+#define OHCI_CLF (1 << 1) /* control list filled */
+#define OHCI_BLF (1 << 2) /* bulk list filled */
+#define OHCI_OCR (1 << 3) /* ownership change request */
+#define OHCI_SOC (3 << 16) /* scheduling overrun count */
+
+/*
+ * masks used with interrupt registers:
+ * HcInterruptStatus (intrstatus)
+ * HcInterruptEnable (intrenable)
+ * HcInterruptDisable (intrdisable)
+ */
+#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
+#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
+#define OHCI_INTR_SF (1 << 2) /* start frame */
+#define OHCI_INTR_RD (1 << 3) /* resume detect */
+#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
+#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
+#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
+#define OHCI_INTR_OC (1 << 30) /* ownership change */
+#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
+
+
+/* Virtual Root HUB */
+struct virt_root_hub {
+ int devnum; /* Address of Root Hub endpoint */
+ void *dev; /* was urb */
+ void *int_addr;
+ int send;
+ int interval;
+};
+
+/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
+
+/* destination of request */
+#define RH_INTERFACE 0x01
+#define RH_ENDPOINT 0x02
+#define RH_OTHER 0x03
+
+#define RH_CLASS 0x20
+#define RH_VENDOR 0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS 0x0080
+#define RH_CLEAR_FEATURE 0x0100
+#define RH_SET_FEATURE 0x0300
+#define RH_SET_ADDRESS 0x0500
+#define RH_GET_DESCRIPTOR 0x0680
+#define RH_SET_DESCRIPTOR 0x0700
+#define RH_GET_CONFIGURATION 0x0880
+#define RH_SET_CONFIGURATION 0x0900
+#define RH_GET_STATE 0x0280
+#define RH_GET_INTERFACE 0x0A80
+#define RH_SET_INTERFACE 0x0B00
+#define RH_SYNC_FRAME 0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP 0x2000
+
+
+/* Hub port features */
+#define RH_PORT_CONNECTION 0x00
+#define RH_PORT_ENABLE 0x01
+#define RH_PORT_SUSPEND 0x02
+#define RH_PORT_OVER_CURRENT 0x03
+#define RH_PORT_RESET 0x04
+#define RH_PORT_POWER 0x08
+#define RH_PORT_LOW_SPEED 0x09
+
+#define RH_C_PORT_CONNECTION 0x10
+#define RH_C_PORT_ENABLE 0x11
+#define RH_C_PORT_SUSPEND 0x12
+#define RH_C_PORT_OVER_CURRENT 0x13
+#define RH_C_PORT_RESET 0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER 0x00
+#define RH_C_HUB_OVER_CURRENT 0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP 0x00
+#define RH_ENDPOINT_STALL 0x01
+
+#define RH_ACK 0x01
+#define RH_REQ_ERR -1
+#define RH_NACK 0x00
+
+
+/* OHCI ROOT HUB REGISTER MASKS */
+
+/* roothub.portstatus [i] bits */
+#define RH_PS_CCS 0x00000001 /* current connect status */
+#define RH_PS_PES 0x00000002 /* port enable status*/
+#define RH_PS_PSS 0x00000004 /* port suspend status */
+#define RH_PS_POCI 0x00000008 /* port over current indicator */
+#define RH_PS_PRS 0x00000010 /* port reset status */
+#define RH_PS_PPS 0x00000100 /* port power status */
+#define RH_PS_LSDA 0x00000200 /* low speed device attached */
+#define RH_PS_CSC 0x00010000 /* connect status change */
+#define RH_PS_PESC 0x00020000 /* port enable status change */
+#define RH_PS_PSSC 0x00040000 /* port suspend status change */
+#define RH_PS_OCIC 0x00080000 /* over current indicator change */
+#define RH_PS_PRSC 0x00100000 /* port reset status change */
+
+/* roothub.status bits */
+#define RH_HS_LPS 0x00000001 /* local power status */
+#define RH_HS_OCI 0x00000002 /* over current indicator */
+#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
+#define RH_HS_LPSC 0x00010000 /* local power status change */
+#define RH_HS_OCIC 0x00020000 /* over current indicator change */
+#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
+
+/* roothub.b masks */
+#define RH_B_DR 0x0000ffff /* device removable flags */
+#define RH_B_PPCM 0xffff0000 /* port power control mask */
+
+/* roothub.a masks */
+#define RH_A_NDP (0xff << 0) /* number of downstream ports */
+#define RH_A_PSM (1 << 8) /* power switching mode */
+#define RH_A_NPS (1 << 9) /* no power switching */
+#define RH_A_DT (1 << 10) /* device type (mbz) */
+#define RH_A_OCPM (1 << 11) /* over current protection mode */
+#define RH_A_NOCP (1 << 12) /* no over current protection */
+#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
+
+/* urb */
+#define N_URB_TD 48
+typedef struct
+{
+ ed_t *ed;
+ __u16 length; /* number of tds associated with this request */
+ __u16 td_cnt; /* number of tds already serviced */
+ int state;
+ unsigned long pipe;
+ int actual_length;
+ td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
+} urb_priv_t;
+#define URB_DEL 1
+
+/*
+ * This is the full ohci controller description
+ *
+ * Note how the "proper" USB information is just
+ * a subset of what the full implementation needs. (Linus)
+ */
+
+
+typedef struct ohci {
+ struct ohci_hcca *hcca; /* hcca */
+ /*dma_addr_t hcca_dma;*/
+
+ int irq;
+ int disabled; /* e.g. got a UE, we're hung */
+ int sleeping;
+ unsigned long flags; /* for HC bugs */
+
+ struct ohci_regs *regs; /* OHCI controller's memory */
+
+ ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
+ ed_t *ed_bulktail; /* last endpoint of bulk list */
+ ed_t *ed_controltail; /* last endpoint of control list */
+ int intrstatus;
+ __u32 hc_control; /* copy of the hc control reg */
+ struct usb_device *dev[32];
+ struct virt_root_hub rh;
+
+ const char *slot_name;
+} ohci_t;
+
+#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
+
+struct ohci_device {
+ ed_t ed[NUM_EDS];
+ int ed_cnt;
+};
+
+/* hcd */
+/* endpoint */
+static int ep_link(ohci_t * ohci, ed_t * ed);
+static int ep_unlink(ohci_t * ohci, ed_t * ed);
+static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
+
+/*-------------------------------------------------------------------------*/
+
+/* we need more TDs than EDs */
+#define NUM_TD 64
+
+/* +1 so we can align the storage */
+td_t gtd[NUM_TD+1];
+/* pointers to aligned storage */
+td_t *ptd;
+
+/* TDs ... */
+static inline struct td *
+td_alloc (struct usb_device *usb_dev)
+{
+ int i;
+ struct td *td;
+
+ td = NULL;
+ for (i = 0; i < NUM_TD; i++) {
+ if (ptd[i].usb_dev == NULL) {
+ td = &ptd[i];
+ td->usb_dev = usb_dev;
+ break;
+ }
+ }
+ return td;
+}
+
+static inline void
+ed_free (struct ed *ed)
+{
+ ed->usb_dev = NULL;
+}
--- /dev/null
+/*
+ * Cache-handling routined for MIPS 4K CPUs
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+#if defined(CONFIG_IFX_MIPS)
+# include "ifx_cache.S"
+#endif
+
+ /* 16KB is the maximum size of instruction and data caches on
+ * MIPS 4K.
+ */
+#define MIPS_MAX_CACHE_SIZE 0x4000
+
+
+/*
+ * cacheop macro to automate cache operations
+ * first some helpers...
+ */
+#define _mincache(size, maxsize) \
+ bltu size,maxsize,9f ; \
+ move size,maxsize ; \
+9:
+
+#define _align(minaddr, maxaddr, linesize) \
+ .set noat ; \
+ subu AT,linesize,1 ; \
+ not AT ; \
+ and minaddr,AT ; \
+ addu maxaddr,-1 ; \
+ and maxaddr,AT ; \
+ .set at
+
+/* general operations */
+#define doop1(op1) \
+ cache op1,0(a0)
+#define doop2(op1, op2) \
+ cache op1,0(a0) ; \
+ nop ; \
+ cache op2,0(a0)
+
+/* specials for cache initialisation */
+#define doop1lw(op1) \
+ lw zero,0(a0)
+#define doop1lw1(op1) \
+ cache op1,0(a0) ; \
+ lw zero,0(a0) ; \
+ cache op1,0(a0)
+#define doop121(op1,op2) \
+ cache op1,0(a0) ; \
+ nop; \
+ cache op2,0(a0) ; \
+ nop; \
+ cache op1,0(a0)
+
+#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
+ .set noreorder ; \
+10: doop##tag##ops ; \
+ bne minaddr,maxaddr,10b ; \
+ add minaddr,linesize ; \
+ .set reorder
+
+/* finally the cache operation macros */
+#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
+ blez n,11f ; \
+ addu n,kva ; \
+ _align(kva, n, cacheLineSize) ; \
+ _oploopn(kva, n, cacheLineSize, tag, ops) ; \
+11:
+
+#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
+ _mincache(n, cacheSize); \
+ blez n,11f ; \
+ addu n,kva ; \
+ _align(kva, n, cacheLineSize) ; \
+ _oploopn(kva, n, cacheLineSize, tag, ops) ; \
+11:
+
+#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
+ vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
+
+#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
+ icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
+
+/*******************************************************************************
+*
+* mips_cache_reset - low level initialisation of the primary caches
+*
+* This routine initialises the primary caches to ensure that they
+* have good parity. It must be called by the ROM before any cached locations
+* are used to prevent the possibility of data with bad parity being written to
+* memory.
+* To initialise the instruction cache it is essential that a source of data
+* with good parity is available. This routine
+* will initialise an area of memory starting at location zero to be used as
+* a source of parity.
+*
+* RETURNS: N/A
+*
+*/
+ .globl mips_cache_reset
+ .ent mips_cache_reset
+mips_cache_reset:
+
+ li t2, CFG_ICACHE_SIZE
+ li t3, CFG_DCACHE_SIZE
+ li t4, CFG_CACHELINE_SIZE
+ move t5, t4
+
+
+ li v0, MIPS_MAX_CACHE_SIZE
+
+ /* Now clear that much memory starting from zero.
+ */
+
+ li a0, KSEG1
+ addu a1, a0, v0
+
+2: sw zero, 0(a0)
+ sw zero, 4(a0)
+ sw zero, 8(a0)
+ sw zero, 12(a0)
+ sw zero, 16(a0)
+ sw zero, 20(a0)
+ sw zero, 24(a0)
+ sw zero, 28(a0)
+ addu a0, 32
+ bltu a0, a1, 2b
+
+ /* Set invalid tag.
+ */
+
+ mtc0 zero, CP0_TAGLO
+#if defined(CONFIG_IFX_MIPS) && defined(IFX_CACHE_EXTRA_INVALID_TAG)
+ IFX_CACHE_EXTRA_INVALID_TAG
+#endif
+
+ /*
+ * The caches are probably in an indeterminate state,
+ * so we force good parity into them by doing an
+ * invalidate, load/fill, invalidate for each line.
+ */
+
+ /* Assume bottom of RAM will generate good parity for the cache.
+ */
+
+ li a0, K0BASE
+ move a2, t2 # icacheSize
+ move a3, t4 # icacheLineSize
+ move a1, a2
+ icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill))
+
+#if defined(CONFIG_IFX_MIPS) && defined(IFX_CACHE_EXTRA_OPERATION)
+ IFX_CACHE_EXTRA_OPERATION
+#else
+ /* To support Orion/R4600, we initialise the data cache in 3 passes.
+ */
+
+ /* 1: initialise dcache tags.
+ */
+
+ li a0, K0BASE
+ move a2, t3 # dcacheSize
+ move a3, t5 # dcacheLineSize
+ move a1, a2
+ icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
+
+ /* 2: fill dcache.
+ */
+
+ li a0, K0BASE
+ move a2, t3 # dcacheSize
+ move a3, t5 # dcacheLineSize
+ move a1, a2
+ icacheopn(a0,a1,a2,a3,1lw,(dummy))
+
+ /* 3: clear dcache tags.
+ */
+
+ li a0, K0BASE
+ move a2, t3 # dcacheSize
+ move a3, t5 # dcacheLineSize
+ move a1, a2
+ icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
+#endif
+
+ j ra
+ .end mips_cache_reset
+
+
+/*******************************************************************************
+*
+* dcache_status - get cache status
+*
+* RETURNS: 0 - cache disabled; 1 - cache enabled
+*
+*/
+ .globl dcache_status
+ .ent dcache_status
+dcache_status:
+
+ mfc0 v0, CP0_CONFIG
+ andi v0, v0, 1
+ j ra
+
+ .end dcache_status
+
+/*******************************************************************************
+*
+* dcache_disable - disable cache
+*
+* RETURNS: N/A
+*
+*/
+ .globl dcache_disable
+ .ent dcache_disable
+dcache_disable:
+
+ mfc0 t0, CP0_CONFIG
+ li t1, -8
+ and t0, t0, t1
+ ori t0, t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
+ j ra
+
+ .end dcache_disable
+
+
+/*******************************************************************************
+*
+* mips_cache_lock - lock RAM area pointed to by a0 in cache.
+*
+* RETURNS: N/A
+*
+*/
+#if defined(CONFIG_PURPLE)
+# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
+#else
+# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
+#endif
+ .globl mips_cache_lock
+ .ent mips_cache_lock
+mips_cache_lock:
+ li a1, K0BASE - CACHE_LOCK_SIZE
+ addu a0, a1
+ li a2, CACHE_LOCK_SIZE
+ li a3, CFG_CACHELINE_SIZE
+ move a1, a2
+ icacheop(a0,a1,a2,a3,0x1d)
+
+ j ra
+ .end mips_cache_lock
--- /dev/null
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+v=$(shell \
+$(CROSS_COMPILE)as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}')
+
+ifndef PLATFORM_CPU
+PLATFORM_CPU = mips32r2
+endif
+
+MIPSFLAGS=$(shell \
+if [ "$v" -lt "14" ]; then \
+ echo "-mcpu=$(PLATFORM_CPU)"; \
+else \
+ echo "-march=$(PLATFORM_CPU) -mtune=$(PLATFORM_CPU)"; \
+fi)
+
+ifeq ($(CROSS_COMPILE_UCLIBC),1)
+ifneq (,$(findstring mipsel,$(CROSS_COMIPLE)))
+ENDIANNESS = -el
+else
+ENDIANNESS = -eb
+endif
+else
+ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
+ENDIANNESS = -EL
+else
+ENDIANNESS = -EB
+endif
+endif
+
+MIPSFLAGS += $(ENDIANNESS) -mabicalls
+
+PLATFORM_CPPFLAGS += $(MIPSFLAGS)
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#if defined(CONFIG_INCA_IP)
+# include <asm/inca-ip.h>
+#elif defined(CONFIG_IFX_MIPS)
+# include <asm/danube.h>
+# include "ifx_cpu.c"
+#endif
+#include <asm/mipsregs.h>
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+#if defined(CONFIG_INCA_IP)
+ *INCA_IP_WDT_RST_REQ = 0x3f;
+#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229)
+ void (*f)(void) = (void *) 0xbfc00000;
+
+ f();
+#elif defined(CONFIG_IFX_MIPS)
+ IFX_CPU_RESET;
+#endif
+ fprintf(stderr, "*** reset failed ***\n");
+ return 0;
+}
+
+void flush_cache (ulong start_addr, ulong size)
+{
+
+}
+
+void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ){
+ write_32bit_cp0_register(CP0_ENTRYLO0, low0);
+ write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
+ write_32bit_cp0_register(CP0_ENTRYLO1, low1);
+ write_32bit_cp0_register(CP0_ENTRYHI, hi);
+ write_32bit_cp0_register(CP0_INDEX, index);
+ tlb_write_indexed();
+}
--- /dev/null
+/*****************************************************************************
+ * DANUBE BootROM
+ * Copyright (c) 2005, Infineon Technologies AG, All rights reserved
+ * IFAP DC COM SD
+ *****************************************************************************/
+
+#include <config.h>
+//#include <lib.h>
+#include <asm/danube.h>
+#include <asm/addrspace.h>
+#include <asm/ifx_asc.h>
+
+
+#define ASC_FIFO_PRESENT
+#define SET_BIT(reg, mask) reg |= (mask)
+#define CLEAR_BIT(reg, mask) reg &= (~mask)
+#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
+#define SET_BITS(reg, mask) SET_BIT(reg, mask)
+#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
+
+
+typedef unsigned char u8;
+typedef unsigned short u16;
+typedef unsigned long u32;
+typedef signed long s32;
+typedef unsigned int uint;
+typedef unsigned long ulong;
+typedef volatile unsigned short vuint;
+
+
+
+void serial_setbrg (void);
+
+/*TODO: undefine this !!!*/
+#undef DEBUG_ASC_RAW
+#ifdef DEBUG_ASC_RAW
+#define DEBUG_ASC_RAW_RX_BUF 0xA0800000
+#define DEBUG_ASC_RAW_TX_BUF 0xA0900000
+#endif
+
+static volatile DanubeAsc_t *pAsc = (DanubeAsc_t *)DANUBE_ASC1;
+
+typedef struct{
+ u16 fdv; /* 0~511 fractional divider value*/
+ u16 reload; /* 13 bit reload value*/
+} ifx_asc_baud_reg_t;
+
+#ifdef ON_VENUS
+/*9600 @1.25M rel 00.08*/
+//#define FDV 503
+//#define RELOAD 7
+/*9600 @0.625M rel final00.01 & rtl_freeze*/
+#define FDV 503
+#define RELOAD 3
+/* first index is DDR_SEL, second index is FPI_SEL */
+#endif
+static ifx_asc_baud_reg_t g_danube_asc_baud[4][2] =
+{
+#ifdef ON_VENUS
+ {{503,3},{503,3}}, /* 1152000 @ 166.67M and half*/
+ {{503,3},{503,3}}, /* 1152000 @ 133.3M and half*/
+ {{503,3},{503,3}}, /* 1152000 @ 111.11M and half*/
+ {{503.3},{503,3}} /* 1152000 @ 83.33M and half*/
+#else
+/* TAPEOUT table */
+ {{436,76},{419,36}}, /* 1152000 @ 166.67M and half*/
+ {{453,63},{453,31}}, /* 1152000 @ 133.3M and half*/
+ {{501,58},{510,29}}, /* 1152000 @ 111.11M and half*/
+ {{419.36},{453,19}} /* 1152000 @ 83.33M and half*/
+#endif
+};
+/******************************************************************************
+*
+* asc_init - initialize a Danube ASC channel
+*
+* This routine initializes the number of data bits, parity
+* and set the selected baud rate. Interrupts are disabled.
+* Set the modem control signals if the option is selected.
+*
+* RETURNS: N/A
+*/
+
+int serial_init (void)
+{
+
+ /* and we have to set CLC register*/
+ CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
+ SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
+
+ /* initialy we are in async mode */
+ pAsc->asc_con = ASCCON_M_8ASYNC;
+
+ /* select input port */
+ pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
+
+ /* TXFIFO's filling level */
+ SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
+ ASCTXFCON_TXFITLOFF, DANUBEASC_TXFIFO_FL);
+ /* enable TXFIFO */
+ SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
+
+ /* RXFIFO's filling level */
+ SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
+ ASCRXFCON_RXFITLOFF, DANUBEASC_RXFIFO_FL);
+ /* enable RXFIFO */
+ SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
+
+ /* set baud rate */
+ serial_setbrg();
+
+ /* enable error signals & Receiver enable */
+ SET_BIT(pAsc->asc_whbstate, ASCWHBSTATE_SETREN|ASCCON_FEN|ASCCON_TOEN|ASCCON_ROEN);
+
+ return 0;
+}
+
+void serial_setbrg (void)
+{
+ u32 uiReloadValue, fdv;
+
+#if defined(ON_IKOS)
+ /*1200 @77K */
+ fdv=472;
+ uiReloadValue=5;
+#else
+ /*venus & tapeout */
+ u32 ddr_sel,fpi_sel;
+ ddr_sel = (* DANUBE_CGU_SYS) & 0x3;
+ fpi_sel = ((* DANUBE_CGU_SYS) & 0x40)?1:0;
+ fdv= g_danube_asc_baud[ddr_sel][fpi_sel].fdv;
+ uiReloadValue=g_danube_asc_baud[ddr_sel][fpi_sel].reload;
+#endif //ON_IKOS
+ /* Disable Baud Rate Generator; BG should only be written when R=0 */
+ CLEAR_BIT(pAsc->asc_con, ASCCON_R);
+
+ /* Enable Fractional Divider */
+ SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */
+
+ /* Set fractional divider value */
+ pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK;
+
+ /* Set reload value in BG */
+ pAsc->asc_bg = uiReloadValue;
+
+ /* Enable Baud Rate Generator */
+ SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */
+}
+
+
+void serial_putc (const char c)
+{
+ u32 txFl = 0;
+#ifdef DEBUG_ASC_RAW
+ static u8 * debug = (u8 *) DEBUG_ASC_RAW_TX_BUF;
+ *debug++=c;
+#endif
+ if (c == '\n')
+ serial_putc ('\r');
+ /* check do we have a free space in the TX FIFO */
+ /* get current filling level */
+ do
+ {
+ txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
+ }
+ while ( txFl == DANUBEASC_TXFIFO_FULL );
+
+ pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
+
+ /* check for errors */
+ if ( pAsc->asc_state & ASCSTATE_TOE )
+ {
+ SET_BIT(pAsc->asc_whbstate, ASCWHBSTATE_CLRTOE);
+ return;
+ }
+}
+
+void serial_puts (const char *s)
+{
+ while (*s)
+ {
+ serial_putc (*s++);
+ }
+}
+
+int asc_inb(int timeout)
+{
+ u32 symbol_mask;
+ char c;
+ while ((pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) {
+ }
+ symbol_mask = ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
+ c = (char)(pAsc->asc_rbuf & symbol_mask);
+ return (c);
+}
+
+int serial_getc (void)
+{
+ char c;
+ while ((pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 );
+ c = (char)(pAsc->asc_rbuf & 0xff);
+
+#ifdef DEBUG_ASC_RAW
+ static u8* debug=(u8*)(DEBUG_ASC_RAW_RX_BUF);
+ *debug++=c;
+#endif
+ return c;
+}
+
+
+
+int serial_tstc (void)
+{
+ int res = 1;
+
+#ifdef ASC_FIFO_PRESENT
+ if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
+ {
+ res = 0;
+ }
+#else
+ if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
+ FBS_ISR_AR))
+
+ {
+ res = 0;
+ }
+#endif
+#if 0
+ else if ( pAsc->asc_con & ASCCON_FE )
+ {
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
+ res = 0;
+ }
+ else if ( pAsc->asc_con & ASCCON_PE )
+ {
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
+ res = 0;
+ }
+ else if ( pAsc->asc_con & ASCCON_OE )
+ {
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
+ res = 0;
+ }
+#endif
+ return res;
+}
+
+
+int serial_start(void)
+{
+ return 1;
+}
+
+int serial_stop(void)
+{
+ return 1;
+}
--- /dev/null
+
+#define IFX_CACHE_EXTRA_INVALID_TAG \
+ mtc0 zero, CP0_TAGLO, 1; \
+ mtc0 zero, CP0_TAGLO, 2; \
+ mtc0 zero, CP0_TAGLO, 3; \
+ mtc0 zero, CP0_TAGLO, 4;
+
+#define IFX_CACHE_EXTRA_OPERATION \
+ /* set WST bit */ \
+ mfc0 a0, CP0_ECC; \
+ li a1, ECCF_WST; \
+ or a0, a1; \
+ mtc0 a0, CP0_ECC; \
+ \
+ li a0, K0BASE; \
+ move a2, t2; /* icacheSize */ \
+ move a3, t4; /* icacheLineSize */ \
+ move a1, a2; \
+ icacheop(a0,a1,a2,a3,(Index_Store_Tag_I)); \
+ \
+ /* clear WST bit */ \
+ mfc0 a0, CP0_ECC; \
+ li a1, ~ECCF_WST; \
+ and a0, a1; \
+ mtc0 a0, CP0_ECC; \
+ \
+ /* 1: initialise dcache tags. */ \
+ \
+ /* cache line size */ \
+ li a2, CFG_CACHELINE_SIZE; \
+ /* kseg0 mem address */ \
+ li a1, 0; \
+ li a3, CFG_CACHE_SETS * CFG_CACHE_WAYS; \
+1: \
+ /* store tag (invalid, not locked) */ \
+ cache 0x8, 0(a1); \
+ cache 0x9, 0(a1); \
+ \
+ add a3, -1; \
+ bne a3, zero, 1b; \
+ add a1, a2; \
+ \
+ /* set WST bit */ \
+ mfc0 a0, CP0_ECC; \
+ li a1, ECCF_WST; \
+ or a0, a1; \
+ mtc0 a0, CP0_ECC; \
+ \
+ li a0, K0BASE; \
+ move a2, t3; /* dcacheSize */ \
+ move a3, t5; /* dcacheLineSize */ \
+ move a1, a2; \
+ icacheop(a0,a1,a2,a3,(Index_Store_Tag_D)); \
+ \
+ /* clear WST bit */ \
+ mfc0 a0, CP0_ECC; \
+ li a1, ~ECCF_WST; \
+ and a0, a1; \
+ mtc0 a0, CP0_ECC;
+
--- /dev/null
+/*\r
+ * ########################################################################\r
+ *\r
+ * This program is free software; you can distribute it and/or modify it\r
+ * under the terms of the GNU General Public License (Version 2) as\r
+ * published by the Free Software Foundation.\r
+ *\r
+ * This program is distributed in the hope it will be useful, but WITHOUT\r
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License along\r
+ * with this program; if not, write to the Free Software Foundation, Inc.,\r
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.\r
+ *\r
+ * ########################################################################\r
+ *\r
+ * danube_cgu.c\r
+ *\r
+ * Description:\r
+ * device driver of clock generation unit of Danube chip\r
+ * Author:\r
+ * Samuels Xu Liang\r
+ * Created:\r
+ * 19 Jul 2005\r
+ * History & Modification Tag:\r
+ * ___________________________________________________________________________\r
+ * | Tag | Comments | Modifier & Time |\r
+ * |--------+---------------------------------------------+------------------|\r
+ * | S0.0 | First version of this driver and the tag is | Samuels Xu Liang |\r
+ * | | implied. | 19 Jul 2005 |\r
+ * ---------------------------------------------------------------------------\r
+ *\r
+ */\r
+\r
+\r
+/*\r
+ * ####################################\r
+ * Head File\r
+ * ####################################\r
+ */\r
+\r
+/*\r
+ * Common Head File\r
+ */\r
+#include <linux/config.h>\r
+#include <linux/kernel.h>\r
+#include <linux/module.h>\r
+#include <linux/version.h>\r
+#include <linux/types.h>\r
+#include <linux/fs.h>\r
+#include <linux/miscdevice.h>\r
+#include <linux/init.h>\r
+#include <asm/uaccess.h>\r
+#include <asm/unistd.h>\r
+#include <asm/irq.h>\r
+#include <linux/errno.h>\r
+\r
+/*\r
+ * Chip Specific Head File\r
+ */\r
+#include "ifx_cgu.h"\r
+\r
+\r
+/*\r
+ * ####################################\r
+ * Definition\r
+ * ####################################\r
+ */\r
+\r
+#define DEBUG_ON_AMAZON 1\r
+#define DEBUG_PRINT_INFO 1\r
+\r
+/*\r
+ * Frequency of Clock Direct Feed from The Analog Line Driver Chip\r
+ */\r
+#define BASIC_INPUT_CLOCK_FREQUENCY 35328000\r
+\r
+/*\r
+ * Bits Operation\r
+ */\r
+#define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))\r
+#define SET_BITS(x, msb, lsb, value) (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))\r
+\r
+/*\r
+ * CGU Register Mapping\r
+ */\r
+#define DANUBE_CGU (KSEG1 + 0x1F103000)\r
+#define DANUBE_CGU_DIV ((volatile u32*)(DANUBE_CGU + 0x0000))\r
+#define DANUBE_CGU_PLL_NMK0 ((volatile u32*)(DANUBE_CGU + 0x0004))\r
+#define DANUBE_CGU_PLL_SR0 ((volatile u32*)(DANUBE_CGU + 0x0008))\r
+#define DANUBE_CGU_PLL_NMK1 ((volatile u32*)(DANUBE_CGU + 0x000C))\r
+#define DANUBE_CGU_PLL_SR1 ((volatile u32*)(DANUBE_CGU + 0x0010))\r
+#define DANUBE_CGU_PLL_SR2 ((volatile u32*)(DANUBE_CGU + 0x0014))\r
+#define DANUBE_CGU_IF_CLK ((volatile u32*)(DANUBE_CGU + 0x0018))\r
+#define DANUBE_CGU_OSC_CTRL ((volatile u32*)(DANUBE_CGU + 0x001C))\r
+#define DANUBE_CGU_SMD ((volatile u32*)(DANUBE_CGU + 0x0020))\r
+#define DANUBE_CGU_CRD ((volatile u32*)(DANUBE_CGU + 0x0024))\r
+#define DANUBE_CGU_CT1SR ((volatile u32*)(DANUBE_CGU + 0x0028))\r
+#define DANUBE_CGU_CT2SR ((volatile u32*)(DANUBE_CGU + 0x002C))\r
+#define DANUBE_CGU_PCMCR ((volatile u32*)(DANUBE_CGU + 0x0030))\r
+#define DANUBE_CGU_MUX ((volatile u32*)(DANUBE_CGU + 0x0034))\r
+\r
+/*\r
+ * CGU Divider Register\r
+ */\r
+#define CGU_DIV_SFTR (*DANUBE_CGU_DIV & (1 << 31))\r
+#define CGU_DIV_DIVE (*DANUBE_CGU_DIV & (1 << 16))\r
+#define CGU_DIV_IOR GET_BITS(*DANUBE_CGU_DIV, 5, 4)\r
+#define CGU_DIV_FKS GET_BITS(*DANUBE_CGU_DIV, 3, 2)\r
+#define CGU_DIV_FBS GET_BITS(*DANUBE_CGU_DIV, 1, 0)\r
+\r
+/*\r
+ * CGU PLL0 NMK Register\r
+ */\r
+#define CGU_PLL_NMK0_PLLN ((*DANUBE_CGU_PLL_NMK0 & (0xFFFFFFFF ^ ((1 << 24) - 1))) >> 24)\r
+#define CGU_PLL_NMK0_PLLM GET_BITS(*DANUBE_CGU_PLL_NMK0, 23, 20)\r
+#define CGU_PLL_NMK0_PLLK GET_BITS(*DANUBE_CGU_PLL_NMK0, 19, 0)\r
+\r
+/*\r
+ * CGU PLL0 Status Register\r
+ */\r
+#define CGU_PLL_SR0_PLLDIV ((*DANUBE_CGU_PLL_SR0 & (0xFFFFFFFF ^ ((1 << 28) - 1))) >> 28)\r
+#define CGU_PLL_SR0_PLLDEN (*DANUBE_CGU_PLL_SR0 & (1 << 26))\r
+#define CGU_PLL_SR0_PLLPSE GET_BITS(*DANUBE_CGU_PLL_SR0, 5, 4)\r
+#define CGU_PLL_SR0_PLLB (*DANUBE_CGU_PLL_SR0 & (1 << 2))\r
+#define CGU_PLL_SR0_PLLL (*DANUBE_CGU_PLL_SR0 & (1 << 1))\r
+#define CGU_PLL_SR0_PLLEN (*DANUBE_CGU_PLL_SR0 & (1 << 0))\r
+\r
+#define CGU_PLL_SR0_DSMSEL 1\r
+#define CGU_PLL_SR0_PHASE_DIV_EN 1\r
+\r
+/*\r
+ * CGU PLL1 NMK Register\r
+ */\r
+#define CGU_PLL_NMK1_PLLN ((*DANUBE_CGU_PLL_NMK1 & (0xFFFFFFFF ^ ((1 << 24) - 1))) >> 24)\r
+#define CGU_PLL_NMK1_PLLM GET_BITS(*DANUBE_CGU_PLL_NMK1, 23, 20)\r
+#define CGU_PLL_NMK1_PLLK GET_BITS(*DANUBE_CGU_PLL_NMK1, 19, 0)\r
+\r
+/*\r
+ * CGU PLL1 Status Register\r
+ */\r
+#define CGU_PLL_SR1_PLLDIV ((*DANUBE_CGU_PLL_SR1 & (0xFFFFFFFF ^ ((1 << 28) - 1))) >> 28)\r
+#define CGU_PLL_SR1_PLLDEN (*DANUBE_CGU_PLL_SR1 & (1 << 26))\r
+#define CGU_PLL_SR1_PLLPSE GET_BITS(*DANUBE_CGU_PLL_SR1, 5, 4)\r
+#define CGU_PLL_SR1_PLLB (*DANUBE_CGU_PLL_SR1 & (1 << 2))\r
+#define CGU_PLL_SR1_PLLL (*DANUBE_CGU_PLL_SR1 & (1 << 1))\r
+#define CGU_PLL_SR1_PLLEN (*DANUBE_CGU_PLL_SR1 & (1 << 0))\r
+\r
+#define CGU_PLL_SR1_DSMSEL 1\r
+#define CGU_PLL_SR1_PHASE_DIV_EN 1\r
+\r
+/*\r
+ * CGU PLL2 Status Register\r
+ */\r
+#define CGU_PLL_SR2_PLLDIV ((*DANUBE_CGU_PLL_SR2 & (0xFFFFFFFF ^ ((1 << 28) - 1))) >> 28)\r
+#define CGU_PLL_SR2_PLLDEN (*DANUBE_CGU_PLL_SR2 & (1 << 27))\r
+#define CGU_PLL_SR2_PLLN GET_BITS(*DANUBE_CGU_PLL_SR2, 25, 20)\r
+#define CGU_PLL_SR2_PLLM GET_BITS(*DANUBE_CGU_PLL_SR2, 19, 16)\r
+#define CGU_PLL_SR2_PLLPS (*DANUBE_CGU_PLL_SR2 & (1 << 5))\r
+#define CGU_PLL_SR2_PLLPE (*DANUBE_CGU_PLL_SR2 & (1 << 4))\r
+#define CGU_PLL_SR2_PLLB (*DANUBE_CGU_PLL_SR2 & (1 << 2))\r
+#define CGU_PLL_SR2_PLLL (*DANUBE_CGU_PLL_SR2 & (1 << 1))\r
+#define CGU_PLL_SR2_PLLEN (*DANUBE_CGU_PLL_SR2 & (1 << 0))\r
+\r
+/*\r
+ * CGU Interface Clock Register\r
+ */\r
+#define CGU_IF_CLK_CLKOD0 GET_BITS(*DANUBE_CGU_IF_CLK, 27, 26)\r
+#define CGU_IF_CLK_CLKOD1 GET_BITS(*DANUBE_CGU_IF_CLK, 25, 24)\r
+#define CGU_IF_CLK_CLKOD2 GET_BITS(*DANUBE_CGU_IF_CLK, 23, 22)\r
+#define CGU_IF_CLK_CLKOD3 GET_BITS(*DANUBE_CGU_IF_CLK, 21, 20)\r
+#define CGU_IF_CLK_PDA (*DANUBE_CGU_IF_CLK & (1 << 18))\r
+#define CGU_IF_CLK_PCI_B (*DANUBE_CGU_IF_CLK & (1 << 17))\r
+#define CGU_IF_CLK_PCIBM (*DANUBE_CGU_IF_CLK & (1 << 16))\r
+#define CGU_IF_CLK_MIICS (*DANUBE_CGU_IF_CLK & (1 << 3))\r
+#define CGU_IF_CLK_USBCS (*DANUBE_CGU_IF_CLK & (1 << 2))\r
+#define CGU_IF_CLK_PCIF (*DANUBE_CGU_IF_CLK & (1 << 1))\r
+#define CGU_IF_CLK_PCIS (*DANUBE_CGU_IF_CLK & (1 << 0))\r
+\r
+/*\r
+ * CGU Oscillator Control Register\r
+ */\r
+#define CGU_OSC_CTRL GET_BITS(*DANUBE_CGU_OSC_CTRL, 1, 0)\r
+\r
+/*\r
+ * CGU SDRAM Memory Delay Register\r
+ */\r
+#define CGU_SMD_CLKI (*DANUBE_CGU_SMD & (1 << 31))\r
+#define CGU_SMD_MIDS GET_BITS(*DANUBE_CGU_SMD, 17, 12)\r
+#define CGU_SMD_MODS GET_BITS(*DANUBE_CGU_SMD, 11, 6)\r
+#define CGU_SMD_MDSEL GET_BITS(*DANUBE_CGU_SMD, 5, 0)\r
+\r
+/*\r
+ * CGU CPU Clock Reduction Register\r
+ */\r
+#define CGU_CRD_SFTR (*DANUBE_CGU_CRD & (1 << 31))\r
+#define CGU_CRD_DIVE (*DANUBE_CGU_CRD & (1 << 16))\r
+#define CGU_CRD_CRD1 GET_BITS(*DANUBE_CGU_CRD, 3, 2)\r
+#define CGU_CRD_CRD GET_BITS(*DANUBE_CGU_CRD, 1, 0)\r
+\r
+/*\r
+ * CGU CT Status Register 1\r
+ */\r
+#define CGU_CT1SR_PDOUT GET_BITS(*DANUBE_CGU_CT1SR, 13, 0)\r
+\r
+/*\r
+ * CGU CT Status Register 2\r
+ */\r
+#define CGU_CT2SR_PLL1K GET_BITS(*DANUBE_CGU_CT2SR, 9, 0)\r
+\r
+/*\r
+ * CGU PCM Control Register\r
+ */\r
+#define CGU_PCMCR_DCL1 GET_BITS(*DANUBE_CGU_PCMCR, 27, 25)\r
+#define CGU_PCMCR_MUXDCL (*DANUBE_CGU_PCMCR & (1 << 22))\r
+#define CGU_PCMCR_MUXFSC (*DANUBE_CGU_PCMCR & (1 << 18))\r
+#define CGU_PCMCR_PCM_SL (*DANUBE_CGU_PCMCR & (1 << 13))\r
+#define CGU_PCMCR_DNTR (*DANUBE_CGU_PCMCR & (1 << 12))\r
+\r
+/*\r
+ * CGU Clock Mux Register\r
+ */\r
+#define CGU_MUX_MII_CLK (*DANUBE_CGU_MUX & (1 << 6))\r
+#define CGU_MUX_SUB_SYS GET_BITS(*DANUBE_CGU_MUX, 5, 3)\r
+#define CGU_MUX_PP32 GET_BITS(*DANUBE_CGU_MUX, 1, 0)\r
+\r
+\r
+/*\r
+ * ####################################\r
+ * Preparation of Debug on Amazon Chip\r
+ * ####################################\r
+ */\r
+\r
+/*\r
+ * If try module on Amazon chip, prepare some tricks to prevent invalid memory write.\r
+ */\r
+#if defined(DEBUG_ON_AMAZON) && DEBUG_ON_AMAZON\r
+ u32 g_pFakeRegisters[0x0100];\r
+\r
+ #undef DANUBE_CGU\r
+ #define DANUBE_CGU ((u32)g_pFakeRegisters)\r
+#endif // defined(DEBUG_ON_AMAZON) && DEBUG_ON_AMAZON\r
+\r
+\r
+/*\r
+ * ####################################\r
+ * Data Type\r
+ * ####################################\r
+ */\r
+\r
+\r
+/*\r
+ * ####################################\r
+ * Declaration\r
+ * ####################################\r
+ */\r
+\r
+/*\r
+ * Pre-declaration of File Operations\r
+ */\r
+static ssize_t cgu_read(struct file *, char *, size_t, loff_t *);\r
+static ssize_t cgu_write(struct file *, const char *, size_t, loff_t *);\r
+static int cgu_ioctl(struct inode *, struct file *, unsigned int, unsigned long);\r
+static int cgu_open(struct inode *, struct file *);\r
+static int cgu_release(struct inode *, struct file *);\r
+\r
+/*\r
+ * Pre-declaration of 64-bit Unsigned Integer Operation\r
+ */\r
+static inline void uint64_multiply(unsigned int, unsigned int, unsigned int *);\r
+static inline void uint64_divide(unsigned int *, unsigned int, unsigned int *, unsigned int *);\r
+\r
+/*\r
+ * Calculate PLL Frequency\r
+ */\r
+static inline u32 cal_dsm(u32, u32);\r
+static inline u32 mash_dsm(u32, u32, u32);\r
+static inline u32 ssff_dsm_1(u32, u32, u32);\r
+static inline u32 ssff_dsm_2(u32, u32, u32);\r
+static inline u32 dsm(u32 M, u32, u32, int, int);\r
+static inline u32 cgu_get_pll0_fosc(void);\r
+static inline u32 cgu_get_pll0_fps(void);\r
+static inline u32 cgu_get_pll0_fdiv(void);\r
+static inline u32 cgu_get_pll1_fosc(void);\r
+static inline u32 cgu_get_pll1_fps(void);\r
+static inline u32 cgu_get_pll1_fdiv(void);\r
+static inline u32 cgu_get_pll2_fosc(void);\r
+static inline u32 cgu_get_pll2_fps(void);\r
+\r
+/*\r
+ * Export Functions\r
+ */\r
+u32 cgu_get_mips_clock(int);\r
+u32 cgu_get_cpu_clock(void);\r
+u32 cgu_get_io_region_clock(void);\r
+u32 cgu_get_fpi_bus_clock(int);\r
+u32 cgu_get_pp32_clock(void);\r
+u32 cgu_get_pci_clock(void);\r
+u32 cgu_get_ethernet_clock(void);\r
+u32 cgu_get_usb_clock(void);\r
+u32 cgu_get_clockout(int);\r
+\r
+\r
+/*\r
+ * ####################################\r
+ * Local Variable\r
+ * ####################################\r
+ */\r
+\r
+static struct file_operations cgu_fops = {\r
+ owner: THIS_MODULE,\r
+ llseek: no_llseek,\r
+ read: cgu_read,\r
+ write: cgu_write,\r
+ ioctl: cgu_ioctl,\r
+ open: cgu_open,\r
+ release: cgu_release\r
+};\r
+\r
+static struct miscdevice cgu_miscdev = {\r
+ MISC_DYNAMIC_MINOR,\r
+ "danube_cgu_dev",\r
+ &cgu_fops\r
+};\r
+\r
+\r
+/*\r
+ * ####################################\r
+ * Global Variable\r
+ * ####################################\r
+ */\r
+\r
+\r
+/*\r
+ * ####################################\r
+ * Local Function\r
+ * ####################################\r
+ */\r
+\r
+static ssize_t cgu_read(struct file *file, char *buf, size_t count, loff_t *ppos)\r
+{\r
+ return -EPERM;\r
+}\r
+\r
+static ssize_t cgu_write(struct file *file, const char *buf, size_t count, loff_t *ppos)\r
+{\r
+ return -EPERM;\r
+}\r
+\r
+static int cgu_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)\r
+{\r
+ int ret = 0;\r
+ struct cgu_clock_rates rates;\r
+\r
+ if ( _IOC_TYPE(cmd) != CGU_IOC_MAGIC\r
+ || _IOC_NR(cmd) >= CGU_IOC_MAXNR )\r
+ return -ENOTTY;\r
+\r
+ if ( _IOC_DIR(cmd) & _IOC_READ )\r
+ ret = !access_ok(VERIFY_WRITE, arg, _IOC_SIZE(cmd));\r
+ else if ( _IOC_DIR(cmd) & _IOC_WRITE )\r
+ ret = !access_ok(VERIFY_READ, arg, _IOC_SIZE(cmd));\r
+ if ( ret )\r
+ return -EFAULT;\r
+\r
+ switch ( cmd )\r
+ {\r
+ case CGU_GET_CLOCK_RATES:\r
+ /* Calculate Clock Rates */\r
+ rates.mips0 = cgu_get_mips_clock(0);\r
+ rates.mips1 = cgu_get_mips_clock(1);\r
+ rates.cpu = cgu_get_cpu_clock();\r
+ rates.io_region = cgu_get_io_region_clock();\r
+ rates.fpi_bus1 = cgu_get_fpi_bus_clock(1);\r
+ rates.fpi_bus2 = cgu_get_fpi_bus_clock(2);\r
+ rates.pp32 = cgu_get_pp32_clock();\r
+ rates.pci = cgu_get_pci_clock();\r
+ rates.ethernet = cgu_get_ethernet_clock();\r
+ rates.usb = cgu_get_usb_clock();\r
+ rates.clockout0 = cgu_get_clockout(0);\r
+ rates.clockout1 = cgu_get_clockout(1);\r
+ rates.clockout2 = cgu_get_clockout(2);\r
+ rates.clockout3 = cgu_get_clockout(3);\r
+ /* Copy to User Space */\r
+ copy_to_user((char*)arg, (char*)&rates, sizeof(rates));\r
+\r
+ ret = 0;\r
+ break;\r
+ default:\r
+ ret = -ENOTTY;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+static int cgu_open(struct inode *inode, struct file *file)\r
+{\r
+ return 0;\r
+}\r
+\r
+static int cgu_release(struct inode *inode, struct file *file)\r
+{\r
+ return 0;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * calculate 64-bit multiplication result of two 32-bit unsigned integer\r
+ * Input:\r
+ * u32Multiplier1 --- u32 (32-bit), one of the multipliers\r
+ * u32Multiplier2 --- u32 (32-bit), the other multiplier\r
+ * u32Result --- u32[2], array to retrieve the multiplication result,\r
+ * index 0 is high word, index 1 is low word\r
+ * Output:\r
+* none\r
+ */\r
+static inline void uint64_multiply(u32 u32Multiplier1, u32 u32Multiplier2, u32 u32Result[2])\r
+{\r
+ u32 u32Multiplier1LowWord = u32Multiplier1 & 0xFFFF;\r
+ u32 u32Multiplier1HighWord = u32Multiplier1 >> 16;\r
+ u32 u32Multiplier2LowWord = u32Multiplier2 & 0xFFFF;\r
+ u32 u32Multiplier2HighWord = u32Multiplier2 >> 16;\r
+ u32 u32Combo1, u32Combo2, u32Combo3, u32Combo4;\r
+ u32 u32Word1, u32Word2, u32Word3, u32Word4;\r
+\r
+ u32Combo1 = u32Multiplier1LowWord * u32Multiplier2LowWord;\r
+ u32Combo2 = u32Multiplier1HighWord * u32Multiplier2LowWord;\r
+ u32Combo3 = u32Multiplier1LowWord * u32Multiplier2HighWord;\r
+ u32Combo4 = u32Multiplier1HighWord * u32Multiplier2HighWord;\r
+\r
+ u32Word1 = u32Combo1 & 0xFFFF;\r
+ u32Word2 = (u32Combo1 >> 16) + (u32Combo2 & 0xFFFF) + (u32Combo3 & 0xFFFF);\r
+ u32Word3 = (u32Combo2 >> 16) + (u32Combo3 >> 16) + (u32Combo4 & 0xFFFF) + (u32Word2 >> 16);\r
+ u32Word4 = (u32Combo4 >> 16) + (u32Word3 >> 16);\r
+\r
+ u32Result[0] = (u32Word4 << 16) | u32Word3;\r
+ u32Result[1] = (u32Word2 << 16) | u32Word1;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * divide 64-bit unsigned integer with 32-bit unsigned integer\r
+ * Input:\r
+ * u32Numerator --- u32[2], index 0 is high word of numerator, while\r
+ * index 1 is low word of numerator\r
+ * u32Denominator --- u32 (32-bit), the denominator in division, this\r
+ * parameter can not be zero, or lead to unpredictable\r
+ * result\r
+ * pu32Quotient --- u32 *, the pointer to retrieve 32-bit quotient, null\r
+ * pointer means ignore quotient\r
+ * pu32Residue --- u32 *, the pointer to retrieve 32-bit residue null\r
+ * pointer means ignore residue\r
+ * Output:\r
+ * none\r
+ */\r
+static inline void uint64_divide(u32 u32Numerator[2], u32 u32Denominator, u32 *pu32Quotient, u32 *pu32Residue)\r
+{\r
+ u32 u32DWord1, u32DWord2, u32DWord3;\r
+ u32 u32Quotient;\r
+ int i;\r
+\r
+ u32DWord3 = 0;\r
+ u32DWord2 = u32Numerator[0];\r
+ u32DWord1 = u32Numerator[1];\r
+\r
+ u32Quotient = 0;\r
+\r
+ for ( i = 0; i < 64; i++ )\r
+ {\r
+ u32DWord3 = (u32DWord3 << 1) | (u32DWord2 >> 31);\r
+ u32DWord2 = (u32DWord2 << 1) | (u32DWord1 >> 31);\r
+ u32DWord1 <<= 1;\r
+ u32Quotient <<= 1;\r
+ if ( u32DWord3 >= u32Denominator )\r
+ {\r
+ u32DWord3 -= u32Denominator;\r
+ u32Quotient |= 1;\r
+ }\r
+ }\r
+ if ( pu32Quotient )\r
+ *pu32Quotient = u32Quotient;\r
+ if ( pu32Residue )\r
+ *pu32Residue = u32DWord3;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * common routine to calculate PLL frequency\r
+ * Input:\r
+ * num --- u32, numerator\r
+ * den --- u32, denominator\r
+ * Output:\r
+ * u32 --- frequency the PLL output\r
+ */\r
+static inline u32 cal_dsm(u32 num, u32 den)\r
+{\r
+ u32 ret;\r
+ u32 temp[2];\r
+ u32 residue;\r
+\r
+ uint64_multiply(num, BASIC_INPUT_CLOCK_FREQUENCY, temp);\r
+ uint64_divide(temp, den, &ret, &residue);\r
+ if ( (residue << 1) >= den )\r
+ ret++;\r
+\r
+ return ret;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * calculate PLL frequency following MASH-DSM\r
+ * Input:\r
+ * M --- u32, denominator coefficient\r
+ * N --- u32, numerator integer coefficient\r
+ * K --- u32, numerator fraction coefficient\r
+ * Output:\r
+ * u32 --- frequency the PLL output\r
+ */\r
+static inline u32 mash_dsm(u32 M, u32 N, u32 K)\r
+{\r
+ u32 num = ((N + 1) << 10) + K;\r
+ u32 den = (M + 1) << 10;\r
+\r
+ return cal_dsm(num, den);\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * calculate PLL frequency following SSFF-DSM (0.25 < fraction < 0.75)\r
+ * Input:\r
+ * M --- u32, denominator coefficient\r
+ * N --- u32, numerator integer coefficient\r
+ * K --- u32, numerator fraction coefficient\r
+ * Output:\r
+ * u32 --- frequency the PLL output\r
+ */\r
+static inline u32 ssff_dsm_1(u32 M, u32 N, u32 K)\r
+{\r
+ u32 num = ((N + 1) << 11) + K + 512;\r
+ u32 den = (M + 1) << 11;\r
+\r
+ return cal_dsm(num, den);\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * calculate PLL frequency following SSFF-DSM\r
+ * (fraction < 0.125 || fraction > 0.875)\r
+ * Input:\r
+ * M --- u32, denominator coefficient\r
+ * N --- u32, numerator integer coefficient\r
+ * K --- u32, numerator fraction coefficient\r
+ * Output:\r
+ * u32 --- frequency the PLL output\r
+ */\r
+static inline u32 ssff_dsm_2(u32 M, u32 N, u32 K)\r
+{\r
+ u32 num = K >= 512 ? ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;\r
+ u32 den = (M + 1) << 12;\r
+\r
+ return cal_dsm(num, den);\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * calculate PLL frequency\r
+ * Input:\r
+ * M --- u32, denominator coefficient\r
+ * N --- u32, numerator integer coefficient\r
+ * K --- u32, numerator fraction coefficient\r
+ * dsmsel --- int, 0: MASH-DSM, 1: SSFF-DSM\r
+ * phase_div_en --- int, 0: 0.25 < fraction < 0.75\r
+ * 1: fraction < 0.125 || fraction > 0.875\r
+ * Output:\r
+ * u32 --- frequency the PLL output\r
+ */\r
+static inline u32 dsm(u32 M, u32 N, u32 K, int dsmsel, int phase_div_en)\r
+{\r
+ if ( !dsmsel )\r
+ return mash_dsm(M, N, K);\r
+ else\r
+ if ( !phase_div_en )\r
+ return ssff_dsm_1(M, N, K);\r
+ else\r
+ return ssff_dsm_2(M, N, K);\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * get oscillate frequency of PLL0\r
+ * Input:\r
+ * none\r
+ * Output:\r
+ * u32 --- frequency of PLL0 Fosc\r
+ */\r
+static inline u32 cgu_get_pll0_fosc(void)\r
+{\r
+ return CGU_PLL_SR0_PLLB ? BASIC_INPUT_CLOCK_FREQUENCY : dsm(CGU_PLL_NMK0_PLLM, CGU_PLL_NMK0_PLLN, CGU_PLL_NMK0_PLLK, CGU_PLL_SR0_DSMSEL, CGU_PLL_SR0_PHASE_DIV_EN);\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * get output frequency of PLL0 phase shifter\r
+ * Input:\r
+ * none\r
+ * Output:\r
+ * u32 --- frequency of PLL0 Fps\r
+ */\r
+static inline u32 cgu_get_pll0_fps(void)\r
+{\r
+ register u32 fps = cgu_get_pll0_fosc();\r
+\r
+ switch ( CGU_PLL_SR0_PLLPSE )\r
+ {\r
+ case 1:\r
+ /* 1.5 */\r
+ fps = ((fps << 1) + 1) / 3; break;\r
+ case 2:\r
+ /* 1.25 */\r
+ fps = ((fps << 2) + 2) / 5; break;\r
+ case 3:\r
+ /* 3.5 */\r
+ fps = ((fps << 1) + 3) / 7;\r
+ }\r
+ return fps;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * get output frequency of PLL0 output divider\r
+ * Input:\r
+ * none\r
+ * Output:\r
+ * u32 --- frequency of PLL0 Fdiv\r
+ */\r
+static inline u32 cgu_get_pll0_fdiv(void)\r
+{\r
+ register u32 fdiv = cgu_get_pll0_fosc();\r
+\r
+ if ( CGU_PLL_SR0_PLLDEN )\r
+ fdiv = (fdiv + (CGU_PLL_SR0_PLLDIV + 1) / 2) / (CGU_PLL_SR0_PLLDIV + 1);\r
+ return fdiv;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * get oscillate frequency of PLL1\r
+ * Input:\r
+ * none\r
+ * Output:\r
+ * u32 --- frequency of PLL1 Fosc\r
+ */\r
+static inline u32 cgu_get_pll1_fosc(void)\r
+{\r
+ return CGU_PLL_SR1_PLLB ? BASIC_INPUT_CLOCK_FREQUENCY : dsm(CGU_PLL_NMK1_PLLM, CGU_PLL_NMK1_PLLN, CGU_PLL_NMK1_PLLK, CGU_PLL_SR1_DSMSEL, CGU_PLL_SR1_PHASE_DIV_EN);\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * get output frequency of PLL1 phase shifter\r
+ * Input:\r
+ * none\r
+ * Output:\r
+ * u32 --- frequency of PLL1 Fps\r
+ */\r
+static inline u32 cgu_get_pll1_fps(void)\r
+{\r
+ register u32 fps = cgu_get_pll1_fosc();\r
+\r
+ switch ( CGU_PLL_SR1_PLLPSE )\r
+ {\r
+ case 1:\r
+ /* 1.5 */\r
+ fps = ((fps << 1) + 1) / 3; break;\r
+ case 2:\r
+ /* 1.25 */\r
+ fps = ((fps << 2) + 2) / 5; break;\r
+ case 3:\r
+ /* 3.5 */\r
+ fps = ((fps << 1) + 3) / 7;\r
+ }\r
+ return fps;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * get output frequency of PLL1 output divider\r
+ * Input:\r
+ * none\r
+ * Output:\r
+ * u32 --- frequency of PLL1 Fdiv\r
+ */\r
+static inline u32 cgu_get_pll1_fdiv(void)\r
+{\r
+ register u32 fdiv = cgu_get_pll1_fosc();\r
+\r
+ if ( CGU_PLL_SR1_PLLDEN )\r
+ fdiv = (fdiv + (CGU_PLL_SR1_PLLDIV + 1) / 2) / (CGU_PLL_SR1_PLLDIV + 1);\r
+ return fdiv;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * get oscillate frequency of PLL2\r
+ * Input:\r
+ * none\r
+ * Output:\r
+ * u32 --- frequency of PLL2 Fosc\r
+ */\r
+static inline u32 cgu_get_pll2_fosc(void)\r
+{\r
+ u32 ret;\r
+ u32 temp[2];\r
+ u32 residue;\r
+\r
+ uint64_multiply((CGU_PLL_SR2_PLLN + 1) * 8, cgu_get_pll0_fdiv(), temp);\r
+ uint64_divide(temp, CGU_PLL_SR2_PLLM + 1, &ret, &residue);\r
+ if ( (residue << 1) >= CGU_PLL_SR2_PLLM )\r
+ ret++;\r
+\r
+ return ret;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * get output frequency of PLL2 phase shifter\r
+ * Input:\r
+ * none\r
+ * Output:\r
+ * u32 --- frequency of PLL2 Fps\r
+ */\r
+static inline u32 cgu_get_pll2_fps(void)\r
+{\r
+ register u32 fps = cgu_get_pll2_fosc();\r
+\r
+ if ( CGU_PLL_SR2_PLLPE )\r
+ {\r
+ if ( CGU_PLL_SR2_PLLPS )\r
+ /* 1.25 */\r
+ fps = ((fps << 3) + 4) / 9;\r
+ else\r
+ /* 1.125 */\r
+ fps = ((fps << 2) + 2) / 5;\r
+ }\r
+\r
+ return fps;\r
+}\r
+\r
+\r
+/*\r
+ * ####################################\r
+ * Global Function\r
+ * ####################################\r
+ */\r
+\r
+/*\r
+ * Description:\r
+ * get frequency of MIPS (0: core, 1: DSP)\r
+ * Input:\r
+ * cpu --- int, 0: core, 1: DSP\r
+ * Output:\r
+ * u32 --- frequency of MIPS coprocessor (0: core, 1: DSP)\r
+ */\r
+u32 cgu_get_mips_clock(int cpu)\r
+{\r
+ register u32 ret = cgu_get_pll0_fosc();\r
+\r
+ if ( CGU_CRD_CRD )\r
+ ret = (ret + (CGU_CRD_CRD >> 1)) / (CGU_CRD_CRD + 1);\r
+ if ( cpu == 0 && CGU_CRD_CRD1 )\r
+ ret >>= CGU_CRD_CRD1;\r
+ return ret;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * get frequency of MIPS core\r
+ * Input:\r
+ * none\r
+ * Output:\r
+ * u32 --- frequency of MIPS core\r
+ */\r
+u32 cgu_get_cpu_clock(void)\r
+{\r
+ return cgu_get_mips_clock(0);\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * get frequency of sub-system and memory controller\r
+ * Input:\r
+ * none\r
+ * Output:\r
+ * u32 --- frequency of sub-system and memory controller\r
+ */\r
+u32 cgu_get_io_region_clock(void)\r
+{\r
+ register u32 ret = (CGU_MUX_SUB_SYS > 4) ? cgu_get_pll0_fosc() : cgu_get_mips_clock(1);\r
+\r
+ switch ( CGU_MUX_SUB_SYS )\r
+ {\r
+ case 0:\r
+ break;\r
+ case 1:\r
+ default:\r
+ ret = (ret + 1) >> 1; break;\r
+ case 2:\r
+ ret = (ret + 1) / 3; break;\r
+ case 3:\r
+ ret = (ret + 2) >> 2; break;\r
+ case 5:\r
+ ret = ((ret << 1) + 1) / 3; break;\r
+ case 6:\r
+ ret = ((ret << 1) + 2) / 5;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * get frequency of FPI bus\r
+ * Input:\r
+ * fpi --- int, 1: FPI bus 1 (FBS1/Fast FPI Bus), 2: FPI bus 2 (FBS2)\r
+ * Output:\r
+ * u32 --- frequency of FPI bus\r
+ */\r
+u32 cgu_get_fpi_bus_clock(int fpi)\r
+{\r
+ register u32 ret = cgu_get_io_region_clock();\r
+\r
+ if ( fpi == 2 )\r
+ ret >>= 1;\r
+ return ret;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * get frequency of PP32 processor\r
+ * Input:\r
+ * none\r
+ * Output:\r
+ * u32 --- frequency of PP32 processor\r
+ */\r
+u32 cgu_get_pp32_clock(void)\r
+{\r
+ register u32 ret;\r
+\r
+ switch ( CGU_MUX_PP32 )\r
+ {\r
+ case 0:\r
+ default:\r
+ ret = ((cgu_get_pll2_fosc() << 2) + 2) / 5; break;\r
+ case 1:\r
+ ret = ((cgu_get_pll2_fosc() << 3) + 4) / 9; break;\r
+ case 2:\r
+ ret = cgu_get_fpi_bus_clock(1); break;\r
+ case 3:\r
+ ret = cgu_get_mips_clock(1);\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * get frequency of PCI bus\r
+ * Input:\r
+ * none\r
+ * Output:\r
+ * u32 --- frequency of PCI bus\r
+ */\r
+u32 cgu_get_pci_clock(void)\r
+{\r
+ register u32 ret = 0;\r
+\r
+ if ( !CGU_IF_CLK_PCIS )\r
+ {\r
+ ret = cgu_get_pll2_fosc();\r
+ if ( CGU_IF_CLK_PCIF )\r
+ ret = (ret + 2) / 5;\r
+ else\r
+ ret = (ret + 4) / 9;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * get frequency of ethernet module (MII)\r
+ * Input:\r
+ * none\r
+ * Output:\r
+ * u32 --- frequency of ethernet module\r
+ */\r
+u32 cgu_get_ethernet_clock(void)\r
+{\r
+ register u32 ret = 0;\r
+\r
+ if ( !CGU_IF_CLK_MIICS )\r
+ {\r
+ ret = cgu_get_pll2_fosc();\r
+ if ( CGU_MUX_MII_CLK )\r
+ ret = (ret + 3) / 6;\r
+ else\r
+ ret = (ret + 6) / 12;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * get frequency of USB\r
+ * Input:\r
+ * none\r
+ * Output:\r
+ * u32 --- frequency of USB\r
+ */\r
+u32 cgu_get_usb_clock(void)\r
+{\r
+ return CGU_IF_CLK_USBCS ? 12000000 : (cgu_get_pll2_fosc() + 12) / 25;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * get frequency of CLK_OUT pin\r
+ * Input:\r
+ * clkout --- int, clock out pin number\r
+ * Output:\r
+ * u32 --- frequency of CLK_OUT pin\r
+ */\r
+u32 cgu_get_clockout(int clkout)\r
+{\r
+ u32 fosc1 = cgu_get_pll1_fosc();\r
+ u32 fosc2 = cgu_get_pll2_fosc();\r
+\r
+ if ( clkout > 3 || clkout < 0 )\r
+ return 0;\r
+\r
+ switch ( ((u32)clkout << 2) | GET_BITS(*DANUBE_CGU_IF_CLK, 21 + clkout * 2, 20 + clkout * 2) )\r
+ {\r
+ case 0: /* 32.768KHz */\r
+ case 14:\r
+ return (fosc1 + 6000) / 12000;\r
+ case 1: /* 1.536MHz */\r
+ return (fosc1 + 128) / 256;\r
+ case 2: /* 2.5MHz */\r
+ return (fosc2 + 60) / 120;\r
+ case 3: /* 12MHz */\r
+ case 5:\r
+ case 12:\r
+ return (fosc2 + 12) / 25;\r
+ case 4: /* 40MHz */\r
+ return (fosc2 * 2 + 7) / 15;\r
+ case 6: /* 24MHz */\r
+ return (fosc2 * 2 + 12) / 25;\r
+ case 7: /* 48MHz */\r
+ return (fosc2 * 4 + 12) / 25;\r
+ case 8: /* 25MHz */\r
+ case 15:\r
+ return (fosc2 + 6) / 12;\r
+ case 9: /* 50MHz */\r
+ case 13:\r
+ return (fosc2 + 3) / 6;\r
+ case 10:/* 30MHz */\r
+ return (fosc2 + 5) / 10;\r
+ case 11:/* 60MHz */\r
+ return (fosc2 + 2) / 5;\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/*\r
+ * ####################################\r
+ * Init/Cleanup API\r
+ * ####################################\r
+ */\r
+\r
+/*\r
+ * Description:\r
+ * register device\r
+ * Input:\r
+ * none\r
+ * Output:\r
+ * 0 --- successful\r
+ * else --- failure, usually it is negative value of error code\r
+ */\r
+int __init danube_cgu_init(void)\r
+{\r
+ int ret;\r
+\r
+ ret = misc_register(&cgu_miscdev);\r
+ if ( ret )\r
+ {\r
+ printk(KERN_ERR "cgu: can't misc_register\n");\r
+ return ret;\r
+ }\r
+ else\r
+ printk(KERN_INFO "cgu: misc_register on minor = %d\n", cgu_miscdev.minor);\r
+\r
+ /*\r
+ * initialize fake registers to do testing on Amazon\r
+ */\r
+#if defined(DEBUG_ON_AMAZON) && DEBUG_ON_AMAZON\r
+ #ifdef DEBUG_PRINT_INFO\r
+ #undef DEBUG_PRINT_INFO\r
+ #endif\r
+ #define DEBUG_PRINT_INFO 1\r
+\r
+ *DANUBE_CGU_DIV = 0x00010019;\r
+ *DANUBE_CGU_PLL_NMK0 = 0x416002C3;\r
+ *DANUBE_CGU_PLL_SR0 = 0x74000013;\r
+ *DANUBE_CGU_PLL_NMK1 = 0x4C60009C;\r
+ *DANUBE_CGU_PLL_SR1 = 0x54000013;\r
+ *DANUBE_CGU_PLL_SR2 = 0x58890013;\r
+ *DANUBE_CGU_IF_CLK = 0x00000000;\r
+ *DANUBE_CGU_OSC_CTRL = 0x00000000;\r
+ *DANUBE_CGU_SMD = 0x00000000;\r
+ *DANUBE_CGU_CRD = 0x00010000;\r
+ *DANUBE_CGU_CT1SR = 0x00000000;\r
+ *DANUBE_CGU_CT2SR = CGU_PLL_NMK1_PLLK;\r
+ *DANUBE_CGU_PCMCR = 0x00000000;\r
+ *DANUBE_CGU_MUX = 0x00000008;\r
+#endif // defined(DEBUG_ON_AMAZON) && DEBUG_ON_AMAZON\r
+\r
+ /*\r
+ * for testing only\r
+ */\r
+#if defined(DEBUG_PRINT_INFO) && DEBUG_PRINT_INFO\r
+ printk("pll0 N = %d, M = %d, K = %d, DIV = %d\n", CGU_PLL_NMK0_PLLN, CGU_PLL_NMK0_PLLM, CGU_PLL_NMK0_PLLK, CGU_PLL_SR0_PLLDIV);\r
+ printk("pll1 N = %d, M = %d, K = %d, DIV = %d\n", CGU_PLL_NMK1_PLLN, CGU_PLL_NMK1_PLLM, CGU_PLL_NMK1_PLLK, CGU_PLL_SR1_PLLDIV);\r
+ printk("pll2 N = %d, M = %d, DIV = %d\n", CGU_PLL_SR2_PLLN, CGU_PLL_SR2_PLLM, CGU_PLL_SR2_PLLDIV);\r
+ printk("pll0_fosc = %d\n", cgu_get_pll0_fosc());\r
+ printk("pll0_fps = %d\n", cgu_get_pll0_fps());\r
+ printk("pll0_fdiv = %d\n", cgu_get_pll0_fdiv());\r
+ printk("pll1_fosc = %d\n", cgu_get_pll1_fosc());\r
+ printk("pll1_fps = %d\n", cgu_get_pll1_fps());\r
+ printk("pll1_fdiv = %d\n", cgu_get_pll1_fdiv());\r
+ printk("pll2_fosc = %d\n", cgu_get_pll2_fosc());\r
+ printk("pll2_fps = %d\n", cgu_get_pll2_fps());\r
+ printk("mips0 clock = %d\n", cgu_get_mips_clock(0));\r
+ printk("mips1 clock = %d\n", cgu_get_mips_clock(1));\r
+ printk("cpu clock = %d\n", cgu_get_cpu_clock());\r
+ printk("IO region = %d\n", cgu_get_io_region_clock());\r
+ printk("FPI bus 1 = %d\n", cgu_get_fpi_bus_clock(1));\r
+ printk("FPI bus 2 = %d\n", cgu_get_fpi_bus_clock(2));\r
+ printk("PP32 clock = %d\n", cgu_get_pp32_clock());\r
+ printk("PCI clock = %d\n", cgu_get_pci_clock());\r
+ printk("Ethernet = %d\n", cgu_get_ethernet_clock());\r
+ printk("USB clock = %d\n", cgu_get_usb_clock());\r
+ printk("Clockout0 = %d\n", cgu_get_clockout(0));\r
+ printk("Clockout1 = %d\n", cgu_get_clockout(1));\r
+ printk("Clockout2 = %d\n", cgu_get_clockout(2));\r
+ printk("Clockout3 = %d\n", cgu_get_clockout(3));\r
+#endif // defined(DEBUG_PRINT_INFO) && DEBUG_PRINT_INFO\r
+\r
+ return 0;\r
+}\r
+\r
+/*\r
+ * Description:\r
+ * deregister device\r
+ * Input:\r
+ * none\r
+ * Output:\r
+ * none\r
+ */\r
+void __exit danube_cgu_exit(void)\r
+{\r
+ int ret;\r
+\r
+ ret = misc_deregister(&cgu_miscdev);\r
+ if ( ret )\r
+ printk(KERN_ERR "cgu: can't misc_deregister, get error number %d\n", -ret);\r
+ else\r
+ printk(KERN_INFO "cgu: misc_deregister successfully\n");\r
+}\r
+\r
+module_init(danube_cgu_init);\r
+module_exit(danube_cgu_exit);\r
--- /dev/null
+#ifndef __DANUBE_CGU_DEV_H__2005_07_20__14_26__\r
+#define __DANUBE_CGU_DEV_H__2005_07_20__14_26__\r
+\r
+\r
+/******************************************************************************\r
+ Copyright (c) 2002, Infineon Technologies. All rights reserved.\r
+\r
+ No Warranty\r
+ Because the program is licensed free of charge, there is no warranty for\r
+ the program, to the extent permitted by applicable law. Except when\r
+ otherwise stated in writing the copyright holders and/or other parties\r
+ provide the program "as is" without warranty of any kind, either\r
+ expressed or implied, including, but not limited to, the implied\r
+ warranties of merchantability and fitness for a particular purpose. The\r
+ entire risk as to the quality and performance of the program is with\r
+ you. should the program prove defective, you assume the cost of all\r
+ necessary servicing, repair or correction.\r
+\r
+ In no event unless required by applicable law or agreed to in writing\r
+ will any copyright holder, or any other party who may modify and/or\r
+ redistribute the program as permitted above, be liable to you for\r
+ damages, including any general, special, incidental or consequential\r
+ damages arising out of the use or inability to use the program\r
+ (including but not limited to loss of data or data being rendered\r
+ inaccurate or losses sustained by you or third parties or a failure of\r
+ the program to operate with any other programs), even if such holder or\r
+ other party has been advised of the possibility of such damages.\r
+******************************************************************************/\r
+\r
+\r
+/*\r
+ * ####################################\r
+ * Definition\r
+ * ####################################\r
+ */\r
+\r
+/*\r
+ * ioctl Command\r
+ */\r
+#define CGU_IOC_MAGIC 'u'\r
+#define CGU_GET_CLOCK_RATES _IOW(CGU_IOC_MAGIC, 0, struct cgu_clock_rates)\r
+#define CGU_IOC_MAXNR 1\r
+\r
+\r
+/*\r
+ * ####################################\r
+ * Data Type\r
+ * ####################################\r
+ */\r
+\r
+/*\r
+ * Data Type Used to Call ioctl(GET_CLOCK_RATES)\r
+ */\r
+struct cgu_clock_rates {\r
+ u32 mips0;\r
+ u32 mips1;\r
+ u32 cpu;\r
+ u32 io_region;\r
+ u32 fpi_bus1;\r
+ u32 fpi_bus2;\r
+ u32 pp32;\r
+ u32 pci;\r
+ u32 ethernet;\r
+ u32 usb;\r
+ u32 clockout0;\r
+ u32 clockout1;\r
+ u32 clockout2;\r
+ u32 clockout3;\r
+};\r
+\r
+\r
+/*\r
+ * ####################################\r
+ * Declaration\r
+ * ####################################\r
+ */\r
+\r
+#if defined(__KERNEL__)\r
+ extern u32 cgu_get_mips_clock(int);\r
+ extern u32 cgu_get_cpu_clock(void);\r
+ extern u32 cgu_get_io_region_clock(void);\r
+ extern u32 cgu_get_fpi_bus_clock(int);\r
+ extern u32 cgu_get_pp32_clock(void);\r
+ extern u32 cgu_get_pci_clock(void);\r
+ extern u32 cgu_get_ethernet_clock(void);\r
+ extern u32 cgu_get_usb_clock(void);\r
+ extern u32 cgu_get_clockout(int);\r
+#endif // defined(__KERNEL__)\r
+\r
+\r
+#endif // __DANUBE_CGU_DEV_H__2005_07_20__14_26__\r
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm-mips/danube.h>
+
+
+
+/*******************************************************************************
+*
+* get_cpuclk - returns the frequency of the CPU.
+*
+* NOTE:
+* This functions should be used by the hardware driver to get the correct
+* frequency of the CPU.
+*/
+
+unsigned int danube_get_ddr_hz(void)
+{
+ switch((*DANUBE_CGU_SYS) & 0x3){
+ case 0:
+ return 166666667;
+ case 1:
+ return 133333333;
+ case 2:
+ return 111111111;
+ case 3:
+ return 83333333;
+ }
+}
+
+
+uint danube_get_cpuclk(void)
+{
+#ifdef CONFIG_USE_EMULATOR
+ return EMULATOR_CPU_SPEED;
+#else //NOT CONFIG_USE_EMULATOR
+ unsigned int ddr_clock=danube_get_ddr_hz();
+ switch((*DANUBE_CGU_SYS) & 0xc){
+ case 0:
+ return 333333333;
+ case 4:
+ return ddr_clock;
+ case 8:
+ return ddr_clock << 1;
+ default:
+ break;
+ /*reserved*/
+ }
+#endif
+
+}
+
+
+uint danube_get_fpiclk(void)
+{
+#ifdef CONFIG_USE_EMULATOR
+ unsigned int clkCPU;
+ clkCPU = danube_get_cpu_hz();
+ return clkCPU >> 2;
+#else //NOT CONFIG_USE_EMULATOR
+ unsigned int ddr_clock=danube_get_ddr_hz();
+ if ((*DANUBE_CGU_SYS) & 0x40){
+ return ddr_clock >> 1;
+ }
+ return ddr_clock;
+#endif
+
+}
+
+
--- /dev/null
+
+#define IFX_CPU_RESET \
+{ *DANUBE_RCU_RST_REQ |=1<<30; \
+}
+
--- /dev/null
+/*
+ * IFX Platform Dependent CPU Initializations
+ * - for Danube
+ */
+
+#define IFX_EBU_BOOTCFG_DWORD \
+ .word INFINEON_EBU_BOOTCFG; /* EBU init code, fetched during booting */ \
+ .word 0x00000000; /* phases of the flash */
+
+#define IFX_MORE_RESERVED_VECTORS \
+ XVECENT(romExcHandle,0x400); /* Int, CauseIV=1 */ \
+ RVECENT(romReserved,129); \
+ RVECENT(romReserved,130); \
+ RVECENT(romReserved,131); \
+ RVECENT(romReserved,132); \
+ RVECENT(romReserved,133); \
+ RVECENT(romReserved,134); \
+ RVECENT(romReserved,135); \
+ RVECENT(romReserved,136); \
+ RVECENT(romReserved,137); \
+ RVECENT(romReserved,138); \
+ RVECENT(romReserved,139); \
+ RVECENT(romReserved,140); \
+ RVECENT(romReserved,141); \
+ RVECENT(romReserved,142); \
+ RVECENT(romReserved,143); \
+ RVECENT(romExcHandle,0x480); /* EJTAG debug exception */
+
+#define IFX_RESET_PRECHECK \
+ mfc0 k0, CP0_EBASE; \
+ and k0, EBASEF_CPUNUM; \
+ bne k0, zero, ifx_mips_handler_1; \
+ nop;
+
+#define IFX_CPU_EXTRA_INIT \
+ mfc0 k0, CP0_CONFIG, 7; \
+ li k1, 0x04; \
+ or k0, k1; \
+ mtc0 k0, CP0_CONFIG, 7;
+
+#define IFX_CACHE_OPER_MODE \
+ li t0, CONF_CM_CACHABLE_NO_WA;
+
+/*
+ * Stop VCPU
+ */
+#define IFX_MIPS_HANDLER_1 \
+ wait; \
+ b ifx_mips_handler_1; \
+ nop;
+
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifdef CONFIG_INCA_IP
+
+#include <common.h>
+#include <asm/inca-ip.h>
+
+
+/*******************************************************************************
+*
+* get_cpuclk - returns the frequency of the CPU.
+*
+* Gets the value directly from the INCA-IP hardware.
+*
+* RETURNS:
+* 150.000.000 for 150 MHz
+* 133.333.333 for 133 Mhz (= 400MHz/3)
+* 100.000.000 for 100 Mhz (= 400MHz/4)
+* NOTE:
+* This functions should be used by the hardware driver to get the correct
+* frequency of the CPU. Don't use the macros, which are set to init the CPU
+* frequency in the ROM code.
+*/
+uint incaip_get_cpuclk (void)
+{
+ /*-------------------------------------------------------------------------*/
+ /* CPU Clock Input Multiplexer (MUX I) */
+ /* Multiplexer MUX I selects the maximum input clock to the CPU. */
+ /*-------------------------------------------------------------------------*/
+ if (*((volatile ulong *) INCA_IP_CGU_CGU_MUXCR) &
+ INCA_IP_CGU_CGU_MUXCR_MUXI) {
+ /* MUX I set to 150 MHz clock */
+ return 150000000;
+ } else {
+ /* MUX I set to 100/133 MHz clock */
+ if (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0x40) {
+ /* Division value is 1/3, maximum CPU operating */
+ /* frequency is 133.3 MHz */
+ return 133333333;
+ } else {
+ /* Division value is 1/4, maximum CPU operating */
+ /* frequency is 100 MHz */
+ return 100000000;
+ }
+ }
+}
+
+/*******************************************************************************
+*
+* get_fpiclk - returns the frequency of the FPI bus.
+*
+* Gets the value directly from the INCA-IP hardware.
+*
+* RETURNS: Frquency in Hz
+*
+* NOTE:
+* This functions should be used by the hardware driver to get the correct
+* frequency of the CPU. Don't use the macros, which are set to init the CPU
+* frequency in the ROM code.
+* The calculation for the
+*/
+uint incaip_get_fpiclk (void)
+{
+ uint clkCPU;
+
+ clkCPU = incaip_get_cpuclk ();
+
+ switch (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0xC) {
+ case 0x4:
+ return clkCPU >> 1; /* devided by 2 */
+ break;
+ case 0x8:
+ return clkCPU >> 2; /* devided by 4 */
+ break;
+ default:
+ return clkCPU;
+ break;
+ }
+}
+
+int incaip_set_cpuclk (void)
+{
+ extern void ebu_init(long);
+ extern void cgu_init(long);
+ extern void sdram_init(long);
+ char tmp[64];
+ ulong cpuclk;
+
+ if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0) {
+ cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
+ cgu_init (cpuclk);
+ ebu_init (cpuclk);
+ sdram_init (cpuclk);
+ }
+
+ return 0;
+}
+
+#endif /* CONFIG_INCA_IP */
--- /dev/null
+/*
+ * INCA-IP Watchdog timer management code.
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+
+#ifdef CONFIG_INCA_IP
+
+#define WD_BASE 0xb8000000
+#define WD_CON0(value) 0x0020(value)
+#define WD_CON1(value) 0x0024(value)
+#define WD_DISABLE 0x00000008
+#define WD_ENABLE 0x00000000
+#define WD_WRITE_PW 0xFFFC00F8
+#define WD_WRITE_ENDINIT 0xFFFC00F3
+#define WD_WRITE_INIT 0xFFFC00F2
+
+
+ .globl disable_incaip_wdt
+disable_incaip_wdt:
+ li t0, WD_BASE
+
+ /* Calculate password.
+ */
+ lw t2, WD_CON1(t0)
+ and t2, 0xC
+
+ lw t3, WD_CON0(t0)
+ and t3, 0xFFFFFF01
+
+ or t3, t2
+ or t3, 0xF0
+
+ sw t3, WD_CON0(t0) /* write password */
+
+ /* Clear ENDINIT.
+ */
+ li t1, WD_WRITE_INIT
+ sw t1, WD_CON0(t0)
+
+
+ li t1, WD_DISABLE
+ sw t1, WD_CON1(t0) /* disable watchdog */
+ li t1, WD_WRITE_PW
+ sw t1, WD_CON0(t0) /* write password */
+ li t1, WD_WRITE_ENDINIT
+ sw t1, WD_CON0(t0) /* end command */
+
+ j ra
+ nop
+
+#endif /* CONFIG_INCA_IP */
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+void enable_interrupts(void)
+{
+}
+
+int disable_interrupts(void)
+{
+ return 0;
+}
--- /dev/null
+/*
+ * Startup Code for MIPS32 CPU-core
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#if defined(CONFIG_IFX_MIPS)
+#include "ifx_start.S"
+#endif
+
+#define RVECENT(f,n) \
+ b f; nop
+#define XVECENT(f,bev) \
+ b f ; \
+ li k0,bev
+
+ .set noreorder
+
+ .globl _start
+ .text
+_start:
+ RVECENT(reset,0) /* U-boot entry point */
+ RVECENT(reset,1) /* software reboot */
+#if defined(CONFIG_INCA_IP)
+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
+ .word 0x00000000 /* phase of the flash */
+#elif defined(CONFIG_IFX_MIPS) && defined(IFX_EBU_BOOTCFG_DWORD)
+ IFX_EBU_BOOTCFG_DWORD
+#elif defined(CONFIG_PURPLE)
+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
+#else
+ RVECENT(romReserved,2)
+#endif
+ RVECENT(romReserved,3)
+ RVECENT(romReserved,4)
+ RVECENT(romReserved,5)
+ RVECENT(romReserved,6)
+ RVECENT(romReserved,7)
+ RVECENT(romReserved,8)
+ RVECENT(romReserved,9)
+ RVECENT(romReserved,10)
+ RVECENT(romReserved,11)
+ RVECENT(romReserved,12)
+ RVECENT(romReserved,13)
+ RVECENT(romReserved,14)
+ RVECENT(romReserved,15)
+ RVECENT(romReserved,16)
+ RVECENT(romReserved,17)
+ RVECENT(romReserved,18)
+ RVECENT(romReserved,19)
+ RVECENT(romReserved,20)
+ RVECENT(romReserved,21)
+ RVECENT(romReserved,22)
+ RVECENT(romReserved,23)
+ RVECENT(romReserved,24)
+ RVECENT(romReserved,25)
+ RVECENT(romReserved,26)
+ RVECENT(romReserved,27)
+ RVECENT(romReserved,28)
+ RVECENT(romReserved,29)
+ RVECENT(romReserved,30)
+ RVECENT(romReserved,31)
+ RVECENT(romReserved,32)
+ RVECENT(romReserved,33)
+ RVECENT(romReserved,34)
+ RVECENT(romReserved,35)
+ RVECENT(romReserved,36)
+ RVECENT(romReserved,37)
+ RVECENT(romReserved,38)
+ RVECENT(romReserved,39)
+ RVECENT(romReserved,40)
+ RVECENT(romReserved,41)
+ RVECENT(romReserved,42)
+ RVECENT(romReserved,43)
+ RVECENT(romReserved,44)
+ RVECENT(romReserved,45)
+ RVECENT(romReserved,46)
+ RVECENT(romReserved,47)
+ RVECENT(romReserved,48)
+ RVECENT(romReserved,49)
+ RVECENT(romReserved,50)
+ RVECENT(romReserved,51)
+ RVECENT(romReserved,52)
+ RVECENT(romReserved,53)
+ RVECENT(romReserved,54)
+ RVECENT(romReserved,55)
+ RVECENT(romReserved,56)
+ RVECENT(romReserved,57)
+ RVECENT(romReserved,58)
+ RVECENT(romReserved,59)
+ RVECENT(romReserved,60)
+ RVECENT(romReserved,61)
+ RVECENT(romReserved,62)
+ RVECENT(romReserved,63)
+ XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
+ RVECENT(romReserved,65)
+ RVECENT(romReserved,66)
+ RVECENT(romReserved,67)
+ RVECENT(romReserved,68)
+ RVECENT(romReserved,69)
+ RVECENT(romReserved,70)
+ RVECENT(romReserved,71)
+ RVECENT(romReserved,72)
+ RVECENT(romReserved,73)
+ RVECENT(romReserved,74)
+ RVECENT(romReserved,75)
+ RVECENT(romReserved,76)
+ RVECENT(romReserved,77)
+ RVECENT(romReserved,78)
+ RVECENT(romReserved,79)
+ XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
+ RVECENT(romReserved,81)
+ RVECENT(romReserved,82)
+ RVECENT(romReserved,83)
+ RVECENT(romReserved,84)
+ RVECENT(romReserved,85)
+ RVECENT(romReserved,86)
+ RVECENT(romReserved,87)
+ RVECENT(romReserved,88)
+ RVECENT(romReserved,89)
+ RVECENT(romReserved,90)
+ RVECENT(romReserved,91)
+ RVECENT(romReserved,92)
+ RVECENT(romReserved,93)
+ RVECENT(romReserved,94)
+ RVECENT(romReserved,95)
+ XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
+ RVECENT(romReserved,97)
+ RVECENT(romReserved,98)
+ RVECENT(romReserved,99)
+ RVECENT(romReserved,100)
+ RVECENT(romReserved,101)
+ RVECENT(romReserved,102)
+ RVECENT(romReserved,103)
+ RVECENT(romReserved,104)
+ RVECENT(romReserved,105)
+ RVECENT(romReserved,106)
+ RVECENT(romReserved,107)
+ RVECENT(romReserved,108)
+ RVECENT(romReserved,109)
+ RVECENT(romReserved,110)
+ RVECENT(romReserved,111)
+ XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
+ RVECENT(romReserved,113)
+ RVECENT(romReserved,114)
+ RVECENT(romReserved,115)
+ RVECENT(romReserved,116)
+ RVECENT(romReserved,116)
+ RVECENT(romReserved,118)
+ RVECENT(romReserved,119)
+ RVECENT(romReserved,120)
+ RVECENT(romReserved,121)
+ RVECENT(romReserved,122)
+ RVECENT(romReserved,123)
+ RVECENT(romReserved,124)
+ RVECENT(romReserved,125)
+ RVECENT(romReserved,126)
+ RVECENT(romReserved,127)
+
+ /* We hope there are no more reserved vectors!
+ * 128 * 8 == 1024 == 0x400
+ * so this is address R_VEC+0x400 == 0xbfc00400
+ */
+#if defined(CONFIG_IFX_MIPS) && defined(IFX_MORE_RESERVED_VECTORS)
+ IFX_MORE_RESERVED_VECTORS
+#else
+#ifdef CONFIG_PURPLE
+/* 0xbfc00400 */
+ .word 0xdc870000
+ .word 0xfca70000
+ .word 0x20840008
+ .word 0x20a50008
+ .word 0x20c6ffff
+ .word 0x14c0fffa
+ .word 0x00000000
+ .word 0x03e00008
+ .word 0x00000000
+ .word 0x00000000
+/* 0xbfc00428 */
+ .word 0xdc870000
+ .word 0xfca70000
+ .word 0x20840008
+ .word 0x20a50008
+ .word 0x20c6ffff
+ .word 0x14c0fffa
+ .word 0x00000000
+ .word 0x03e00008
+ .word 0x00000000
+ .word 0x00000000
+#endif /* CONFIG_PURPLE */
+#endif /* CONFIG_IFX_MIPS */
+ .align 4
+reset:
+#if defined(CONFIG_IFX_MIPS) && defined(IFX_RESET_PRECHECK)
+ IFX_RESET_PRECHECK
+#endif
+ /* Clear watch registers.
+ */
+ mtc0 zero, CP0_WATCHLO
+ mtc0 zero, CP0_WATCHHI
+
+ /* STATUS register */
+#ifdef CONFIG_TB0229
+ li k0, ST0_CU0
+#else
+ mfc0 k0, CP0_STATUS
+#endif
+ li k1, ~ST0_IE
+ and k0, k1
+ mtc0 k0, CP0_STATUS
+
+ /* CAUSE register */
+ mtc0 zero, CP0_CAUSE
+
+#if defined(CONFIG_IFX_MIPS) && defined(IFX_CPU_EXTRA_INIT)
+ IFX_CPU_EXTRA_INIT
+#endif
+
+ /* Init Timer */
+ mtc0 zero, CP0_COUNT
+ mtc0 zero, CP0_COMPARE
+
+ /* CONFIG0 register */
+ li t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
+
+ /* Initialize GOT pointer.
+ */
+ bal 1f
+ nop
+ .word _GLOBAL_OFFSET_TABLE_
+ 1:
+ move gp, ra
+ lw t1, 0(ra)
+ move gp, t1
+
+#ifdef CONFIG_INCA_IP
+ /* Disable INCA-IP Watchdog.
+ */
+ la t9, disable_incaip_wdt
+ jalr t9
+ nop
+#endif
+
+ /* Initialize any external memory.
+ */
+ la t9, lowlevel_init
+ jalr t9
+ nop
+
+ /* Initialize caches...
+ */
+ la t9, mips_cache_reset
+ jalr t9
+ nop
+
+ /* ... and enable them.
+ */
+#if defined(CONFIG_IFX_MIPS) && defined(IFX_CACHE_OPER_MODE)
+ IFX_CACHE_OPER_MODE
+#else
+ li t0, CONF_CM_CACHABLE_NONCOHERENT
+#endif
+ mtc0 t0, CP0_CONFIG
+
+
+ /* Set up temporary stack.
+ */
+ li a0, CFG_INIT_SP_OFFSET
+ la t9, mips_cache_lock
+ jalr t9
+ nop
+
+ li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
+ la sp, 0(t0)
+
+ la t9, board_init_f
+ j t9
+ nop
+
+#ifdef CFG_HEAD_CODE
+/*
+ * void jump_unconditional (addr)
+ * This function simply jumps to the location pointed by a0.
+ * a0 = target_location
+ *
+ */
+ .globl jump_unconditional
+ .ent jump_unconditional
+jump_unconditional:
+ move t9, a0
+ j t9
+ nop
+ .end jump_unconditional
+
+#endif
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * a0 = addr_sp
+ * a1 = gd
+ * a2 = destination address
+ */
+ .globl relocate_code
+ .ent relocate_code
+relocate_code:
+ move sp, a0 /* Set new stack pointer */
+
+#ifdef CFG_HEAD_CODE
+ li t0, CFG_HEAD_BASE
+#else
+ li t0, CFG_MONITOR_BASE
+#endif
+ la t3, in_ram
+ lw t2, -12(t3) /* t2 <-- uboot_end_data */
+ move t1, a2
+
+ /*
+ * Fix GOT pointer:
+ *
+ * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ */
+ move t6, gp
+#ifdef CFG_HEAD_CODE
+ sub gp, CFG_HEAD_BASE
+#else
+ sub gp, CFG_MONITOR_BASE
+#endif
+ add gp, a2 /* gp now adjusted */
+ sub t6, gp, t6 /* t6 <-- relocation offset */
+
+ /*
+ * t0 = source address
+ * t1 = target address
+ * t2 = source end address
+ */
+ /* On the purple board we copy the code earlier in a special way
+ * in order to solve flash problems
+ */
+#ifndef CONFIG_PURPLE
+1:
+ lw t3, 0(t0)
+ sw t3, 0(t1)
+ addu t0, 4
+ ble t0, t2, 1b
+ addu t1, 4 /* delay slot */
+#endif
+
+ /* If caches were enabled, we would have to flush them here.
+ */
+
+ /* Jump to where we've relocated ourselves.
+ */
+ addi t0, a2, in_ram - _start
+ j t0
+ nop
+
+ .word uboot_end_data
+ .word uboot_end
+ .word num_got_entries
+
+in_ram:
+ /* Now we want to update GOT.
+ */
+ lw t3, -4(t0) /* t3 <-- num_got_entries */
+ addi t4, gp, 8 /* Skipping first two entries. */
+ li t2, 2
+1:
+ lw t1, 0(t4)
+ beqz t1, 2f
+ add t1, t6
+ sw t1, 0(t4)
+2:
+ addi t2, 1
+ blt t2, t3, 1b
+ addi t4, 4 /* delay slot */
+
+ /* Clear BSS.
+ */
+ lw t1, -12(t0) /* t1 <-- uboot_end_data */
+ lw t2, -8(t0) /* t2 <-- uboot_end */
+ add t1, t6 /* adjust pointers */
+ add t2, t6
+
+ sub t1, 4
+1: addi t1, 4
+ bltl t1, t2, 1b
+ sw zero, 0(t1) /* delay slot */
+
+ move a0, a1
+ la t9, board_init_r
+ j t9
+ move a1, a2 /* delay slot */
+
+ .end relocate_code
+
+
+ /* Exception handlers.
+ */
+romReserved:
+ b romReserved
+
+romExcHandle:
+ b romExcHandle
+
+ /* Additional handlers.
+ */
+#if defined(CONFIG_IFX_MIPS)
+#if defined(IFX_MIPS_HANDLER_1)
+ifx_mips_handler_1:
+ IFX_MIPS_HANDLER_1
+#endif
+#endif
+
--- /dev/null
+/*
+ * Startup Code for MIPS32 CPU-core
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+
+#define RVECENT(f,n) \
+ b f; nop
+#define XVECENT(f,bev) \
+ b f ; \
+ li k0,bev
+
+ .set noreorder
+
+ .globl _start_bootstrap
+ .text
+_start_bootstrap:
+ RVECENT(reset,0) /* U-boot entry point */
+ RVECENT(reset,1) /* software reboot */
+#if defined(CONFIG_INCA_IP) || defined(CONFIG_INCA_IP2)
+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
+ .word 0x00000000 /* phase of the flash */
+#elif defined(CONFIG_PURPLE)
+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
+#elif defined(CONFIG_DANUBE)
+
+ .org 0x10
+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
+ .word 0x00000000 /* phase of the flash */
+
+ .org 0x18
+ .word 0x312E3000 /* version x.x */
+ .word 0x00000000 /* phase of the flash */
+#else
+ RVECENT(romReserved,2)
+#endif
+ RVECENT(romReserved,3)
+ RVECENT(romReserved,4)
+ RVECENT(romReserved,5)
+ RVECENT(romReserved,6)
+ RVECENT(romReserved,7)
+ RVECENT(romReserved,8)
+ RVECENT(romReserved,9)
+ RVECENT(romReserved,10)
+ RVECENT(romReserved,11)
+ RVECENT(romReserved,12)
+ RVECENT(romReserved,13)
+ RVECENT(romReserved,14)
+ RVECENT(romReserved,15)
+ RVECENT(romReserved,16)
+ RVECENT(romReserved,17)
+ RVECENT(romReserved,18)
+ RVECENT(romReserved,19)
+ RVECENT(romReserved,20)
+ RVECENT(romReserved,21)
+ RVECENT(romReserved,22)
+ RVECENT(romReserved,23)
+ RVECENT(romReserved,24)
+ RVECENT(romReserved,25)
+ RVECENT(romReserved,26)
+ RVECENT(romReserved,27)
+ RVECENT(romReserved,28)
+ RVECENT(romReserved,29)
+ RVECENT(romReserved,30)
+ RVECENT(romReserved,31)
+ RVECENT(romReserved,32)
+ RVECENT(romReserved,33)
+ RVECENT(romReserved,34)
+ RVECENT(romReserved,35)
+ RVECENT(romReserved,36)
+ RVECENT(romReserved,37)
+ RVECENT(romReserved,38)
+ RVECENT(romReserved,39)
+ RVECENT(romReserved,40)
+ RVECENT(romReserved,41)
+ RVECENT(romReserved,42)
+ RVECENT(romReserved,43)
+ RVECENT(romReserved,44)
+ RVECENT(romReserved,45)
+ RVECENT(romReserved,46)
+ RVECENT(romReserved,47)
+ RVECENT(romReserved,48)
+ RVECENT(romReserved,49)
+ RVECENT(romReserved,50)
+ RVECENT(romReserved,51)
+ RVECENT(romReserved,52)
+ RVECENT(romReserved,53)
+ RVECENT(romReserved,54)
+ RVECENT(romReserved,55)
+ RVECENT(romReserved,56)
+ RVECENT(romReserved,57)
+ RVECENT(romReserved,58)
+ RVECENT(romReserved,59)
+ RVECENT(romReserved,60)
+ RVECENT(romReserved,61)
+ RVECENT(romReserved,62)
+ RVECENT(romReserved,63)
+ XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
+ RVECENT(romReserved,65)
+ RVECENT(romReserved,66)
+ RVECENT(romReserved,67)
+ RVECENT(romReserved,68)
+ RVECENT(romReserved,69)
+ RVECENT(romReserved,70)
+ RVECENT(romReserved,71)
+ RVECENT(romReserved,72)
+ RVECENT(romReserved,73)
+ RVECENT(romReserved,74)
+ RVECENT(romReserved,75)
+ RVECENT(romReserved,76)
+ RVECENT(romReserved,77)
+ RVECENT(romReserved,78)
+ RVECENT(romReserved,79)
+ XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
+ RVECENT(romReserved,81)
+ RVECENT(romReserved,82)
+ RVECENT(romReserved,83)
+ RVECENT(romReserved,84)
+ RVECENT(romReserved,85)
+ RVECENT(romReserved,86)
+ RVECENT(romReserved,87)
+ RVECENT(romReserved,88)
+ RVECENT(romReserved,89)
+ RVECENT(romReserved,90)
+ RVECENT(romReserved,91)
+ RVECENT(romReserved,92)
+ RVECENT(romReserved,93)
+ RVECENT(romReserved,94)
+ RVECENT(romReserved,95)
+ XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
+ RVECENT(romReserved,97)
+ RVECENT(romReserved,98)
+ RVECENT(romReserved,99)
+ RVECENT(romReserved,100)
+ RVECENT(romReserved,101)
+ RVECENT(romReserved,102)
+ RVECENT(romReserved,103)
+ RVECENT(romReserved,104)
+ RVECENT(romReserved,105)
+ RVECENT(romReserved,106)
+ RVECENT(romReserved,107)
+ RVECENT(romReserved,108)
+ RVECENT(romReserved,109)
+ RVECENT(romReserved,110)
+ RVECENT(romReserved,111)
+ XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
+ RVECENT(romReserved,113)
+ RVECENT(romReserved,114)
+ RVECENT(romReserved,115)
+ RVECENT(romReserved,116)
+ RVECENT(romReserved,116)
+ RVECENT(romReserved,118)
+ RVECENT(romReserved,119)
+ RVECENT(romReserved,120)
+ RVECENT(romReserved,121)
+ RVECENT(romReserved,122)
+ RVECENT(romReserved,123)
+ RVECENT(romReserved,124)
+ RVECENT(romReserved,125)
+ RVECENT(romReserved,126)
+ RVECENT(romReserved,127)
+
+ /* We hope there are no more reserved vectors!
+ * 128 * 8 == 1024 == 0x400
+ * so this is address R_VEC+0x400 == 0xbfc00400
+ */
+#ifdef CONFIG_PURPLE
+/* 0xbfc00400 */
+ .word 0xdc870000
+ .word 0xfca70000
+ .word 0x20840008
+ .word 0x20a50008
+ .word 0x20c6ffff
+ .word 0x14c0fffa
+ .word 0x00000000
+ .word 0x03e00008
+ .word 0x00000000
+ .word 0x00000000
+/* 0xbfc00428 */
+ .word 0xdc870000
+ .word 0xfca70000
+ .word 0x20840008
+ .word 0x20a50008
+ .word 0x20c6ffff
+ .word 0x14c0fffa
+ .word 0x00000000
+ .word 0x03e00008
+ .word 0x00000000
+ .word 0x00000000
+#endif /* CONFIG_PURPLE */
+ .align 4
+reset:
+#ifdef CONFIG_INCA_IP2
+ /* Check for Host or Voice CPU */
+
+ mfc0 k0, CP0_EBASE
+ and k0, EBASEF_CPUNUM
+ srl k0, EBASEB_CPUNUM
+ subu k0, EBASE_CPU_HOST
+ bne k0, zero, voice_reset_handler
+ nop
+
+#endif
+
+ /* Clear watch registers.
+ */
+ mtc0 zero, CP0_WATCHLO
+ mtc0 zero, CP0_WATCHHI
+
+ /* STATUS register */
+#ifdef CONFIG_TB0229
+ li k0, ST0_CU0
+#else
+ mfc0 k0, CP0_STATUS
+#endif
+ li k1, ~ST0_IE
+ and k0, k1
+ mtc0 k0, CP0_STATUS
+
+ /* CAUSE register */
+ mtc0 zero, CP0_CAUSE
+
+#ifdef CONFIG_INCA_IP2
+ /* CONFIG7 register */
+ mfc0 k0, CP0_CONFIG, 7
+ li k1, 4 /* Disable RPS due to E83 bug of 24KEC */
+ or k0, k1
+ mtc0 k0, CP0_CONFIG, 7
+#endif
+ /* Init Timer */
+ mtc0 zero, CP0_COUNT
+ mtc0 zero, CP0_COMPARE
+
+ /* CONFIG0 register */
+ li t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
+
+ /* Initialize GOT pointer.
+ */
+ bal 1f
+ nop
+ .word _GLOBAL_OFFSET_TABLE_
+ 1:
+ move gp, ra
+ lw t1, 0(ra)
+ move gp, t1
+
+#ifdef CONFIG_INCA_IP
+ /* Disable INCA-IP Watchdog.
+ */
+ la t9, disable_incaip_wdt
+ jalr t9
+ nop
+#endif
+
+ /* Initialize any external memory.
+ */
+ la t9, lowlevel_init
+ jalr t9
+ nop
+
+ /* Initialize caches...
+ */
+ la t9, mips_cache_reset
+ jalr t9
+ nop
+
+ /* ... and enable them.
+ */
+#ifdef CONFIG_MIPS_FORCE_CACHE_WRITE_THROUGH
+ li t0, CONF_CM_CACHABLE_NO_WA
+#else
+ li t0, CONF_CM_CACHABLE_NONCOHERENT
+#endif
+ mtc0 t0, CP0_CONFIG
+
+
+ /* Set up temporary stack.
+ */
+ li a0, CFG_INIT_SP_OFFSET
+ la t9, mips_cache_lock
+ jalr t9
+ nop
+
+ li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
+ la sp, 0(t0)
+
+ la t9, bootstrap_board_init_f
+ j t9
+ nop
+
+
+/*
+ * void bootstrap_relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * a0 = addr_sp
+ * a1 = gd
+ * a2 = destination address
+ */
+ .globl bootstrap_relocate_code
+ .ent bootstrap_relocate_code
+bootstrap_relocate_code:
+ move sp, a0 /* Set new stack pointer */
+
+ li t0, BOOTSTRAP_CFG_MONITOR_BASE
+ la t3, in_ram
+ lw t2, -12(t3) /* t2 <-- uboot_end_data_bootsrap */
+ move t1, a2
+
+ /*
+ * Fix GOT pointer:
+ *
+ * New GOT-PTR = (old GOT-PTR - BOOTSTRAP_CFG_MONITOR_BASE) + Destination Address
+ */
+ move t6, gp
+ sub gp, BOOTSTRAP_CFG_MONITOR_BASE
+ add gp, a2 /* gp now adjusted */
+ sub t6, gp, t6 /* t6 <-- relocation offset */
+
+ /*
+ * t0 = source address
+ * t1 = target address
+ * t2 = source end address
+ */
+ /* On the purple board we copy the code earlier in a special way
+ * in order to solve flash problems
+ */
+#ifndef CONFIG_PURPLE
+1:
+ lw t3, 0(t0)
+ sw t3, 0(t1)
+ addu t0, 4
+ ble t0, t2, 1b
+ addu t1, 4 /* delay slot */
+#endif
+
+ /* If caches were enabled, we would have to flush them here.
+ */
+
+ /* Jump to where we've relocated ourselves.
+ */
+ addi t0, a2, in_ram - _start_bootstrap
+ j t0
+ nop
+
+ .word uboot_end_data_bootstrap
+ .word uboot_end_bootstrap
+ .word num_got_entries
+
+in_ram:
+ /* Now we want to update GOT.
+ */
+ lw t3, -4(t0) /* t3 <-- num_got_entries */
+ addi t4, gp, 8 /* Skipping first two entries. */
+ li t2, 2
+1:
+ lw t1, 0(t4)
+ beqz t1, 2f
+ add t1, t6
+ sw t1, 0(t4)
+2:
+ addi t2, 1
+ blt t2, t3, 1b
+ addi t4, 4 /* delay slot */
+
+ /* Clear BSS.
+ */
+ lw t1, -12(t0) /* t1 <-- uboot_end_data_bootstrap */
+ lw t2, -8(t0) /* t2 <-- uboot_end_bootstrap */
+ add t1, t6 /* adjust pointers */
+ add t2, t6
+
+ sub t1, 4
+1: addi t1, 4
+ bltl t1, t2, 1b
+ sw zero, 0(t1) /* delay slot */
+
+ move a0, a1
+ la t9, bootstrap_board_init_r
+ j t9
+ move a1, a2 /* delay slot */
+
+ .end bootstrap_relocate_code
+
+
+ /* Exception handlers.
+ */
+romReserved:
+ b romReserved
+
+romExcHandle:
+ b romExcHandle
+
+#ifdef CONFIG_INCA_IP2
+voice_reset_handler:
+ wait
+ b voice_reset_handler
+ nop
+#endif
--- /dev/null
+/*
+ * DANUBE internal switch ethernet driver.
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \
+ && defined(CONFIG_DANUBE_SWITCH)
+
+#include <malloc.h>
+#include <net.h>
+#include <asm/danube.h>
+#include <asm/addrspace.h>
+#include <asm/pinstrap.h>
+
+#define MII_MODE 1
+#define REV_MII_MODE 2
+
+#define TX_CHAN_NO 7
+#define RX_CHAN_NO 6
+
+#define NUM_RX_DESC PKTBUFSRX
+#define NUM_TX_DESC 8
+#define MAX_PACKET_SIZE 1536
+#define TOUT_LOOP 100
+#define PHY0_ADDR 1 /*fixme: set the correct value here*/
+
+#define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value
+#define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
+
+#define SW_WRITE_REG(reg, value) *((volatile u32*)reg) = (u32)value
+#define SW_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
+
+typedef struct
+{
+ union
+ {
+ struct
+ {
+ volatile u32 OWN :1;
+ volatile u32 C :1;
+ volatile u32 Sop :1;
+ volatile u32 Eop :1;
+ volatile u32 reserved :3;
+ volatile u32 Byteoffset :2;
+ volatile u32 reserve :7;
+ volatile u32 DataLen :16;
+ }field;
+
+ volatile u32 word;
+ }status;
+
+ volatile u32 DataPtr;
+} danube_rx_descriptor_t;
+
+typedef struct
+{
+ union
+ {
+ struct
+ {
+ volatile u32 OWN :1;
+ volatile u32 C :1;
+ volatile u32 Sop :1;
+ volatile u32 Eop :1;
+ volatile u32 Byteoffset :5;
+ volatile u32 reserved :7;
+ volatile u32 DataLen :16;
+ }field;
+
+ volatile u32 word;
+ }status;
+
+ volatile u32 DataPtr;
+} danube_tx_descriptor_t;
+
+
+
+
+static danube_rx_descriptor_t rx_des_ring[NUM_RX_DESC] __attribute__ ((aligned(8)));
+static danube_tx_descriptor_t tx_des_ring[NUM_TX_DESC] __attribute__ ((aligned(8)));
+static int tx_num, rx_num;
+
+int danube_switch_init(struct eth_device *dev, bd_t * bis);
+int danube_switch_send(struct eth_device *dev, volatile void *packet,int length);
+int danube_switch_recv(struct eth_device *dev);
+void danube_switch_halt(struct eth_device *dev);
+static void danube_init_switch_chip(int mode);
+static void danube_dma_init(void);
+
+
+
+int danube_switch_initialize(bd_t * bis)
+{
+ struct eth_device *dev;
+
+#if 0
+ printf("Entered danube_switch_initialize()\n");
+#endif
+
+ if (!(dev = (struct eth_device *) malloc (sizeof *dev)))
+ {
+ printf("Failed to allocate memory\n");
+ return 0;
+ }
+ memset(dev, 0, sizeof(*dev));
+
+ danube_dma_init();
+ danube_init_switch_chip(REV_MII_MODE);
+
+#ifdef CLK_OUT2_25MHZ
+ *DANUBE_GPIO_P0_DIR=0x0000ae78;
+ *DANUBE_GPIO_P0_ALTSEL0=0x00008078;
+ //joelin for Mii-1 *DANUBE_GPIO_P0_ALTSEL1=0x80000080;
+ *DANUBE_GPIO_P0_ALTSEL1=0x80000000; //joelin for Mii-1
+ *DANUBE_CGU_IFCCR=0x00400010;
+ *DANUBE_GPIO_P0_OD=0x0000ae78;
+#endif
+
+ /*patch for 6996*/
+
+ *DANUBE_RCU_RST_REQ |=1;
+ mdelay(200);
+ *DANUBE_RCU_RST_REQ &=(unsigned long)~1;
+ mdelay(1);
+ /*while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
+ *DANUBE_PPE_ETOP_MDIO_ACC =0x80123602;
+ */
+ /*while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
+ *DANUBE_PPE_ETOP_MDIO_ACC =0x80123602;
+ */
+ /***************/
+ sprintf(dev->name, "danube Switch");
+ dev->init = danube_switch_init;
+ dev->halt = danube_switch_halt;
+ dev->send = danube_switch_send;
+ dev->recv = danube_switch_recv;
+
+ eth_register(dev);
+
+#if 0
+ printf("Leaving danube_switch_initialize()\n");
+#endif
+ while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
+ *DANUBE_PPE_ETOP_MDIO_ACC =0x8001840F;
+ while((*DANUBE_PPE_ETOP_MDIO_ACC)&0x80000000);
+ *DANUBE_PPE_ETOP_MDIO_ACC =0x8003840F;
+ while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
+ *DANUBE_PPE_ETOP_MDIO_ACC =0x8005840F;
+ //while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
+ //*DANUBE_PPE_ETOP_MDIO_ACC =0x8006840F;
+ while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
+ *DANUBE_PPE_ETOP_MDIO_ACC =0x8007840F;
+ while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
+ *DANUBE_PPE_ETOP_MDIO_ACC =0x8008840F;
+ while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
+ *DANUBE_PPE_ETOP_MDIO_ACC =0x8001840F;
+ while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
+ *DANUBE_PPE_ETOP_MDIO_ACC =0x80123602;
+#ifdef CLK_OUT2_25MHZ
+ while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
+ *DANUBE_PPE_ETOP_MDIO_ACC =0x80334000;
+#endif
+
+ return 1;
+}
+
+int danube_switch_init(struct eth_device *dev, bd_t * bis)
+{
+ int i;
+
+ tx_num=0;
+ rx_num=0;
+
+ /* Reset DMA
+ */
+// serial_puts("i \n\0");
+
+ *DANUBE_DMA_CS=RX_CHAN_NO;
+ *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/
+ *DANUBE_DMA_CPOLL= 0x80000040;
+ /*set descriptor base*/
+ *DANUBE_DMA_CDBA=(u32)rx_des_ring;
+ *DANUBE_DMA_CDLEN=NUM_RX_DESC;
+ *DANUBE_DMA_CIE = 0;
+ *DANUBE_DMA_CCTRL=0x30000;
+
+ *DANUBE_DMA_CS=TX_CHAN_NO;
+ *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/
+ *DANUBE_DMA_CPOLL= 0x80000040;
+ *DANUBE_DMA_CDBA=(u32)tx_des_ring;
+ *DANUBE_DMA_CDLEN=NUM_TX_DESC;
+ *DANUBE_DMA_CIE = 0;
+ *DANUBE_DMA_CCTRL=0x30100;
+
+ for(i=0;i < NUM_RX_DESC; i++)
+ {
+ danube_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_des_ring[i]);
+ rx_desc->status.word=0;
+ rx_desc->status.field.OWN=1;
+ rx_desc->status.field.DataLen=PKTSIZE_ALIGN; /* 1536 */
+ rx_desc->DataPtr=(u32)KSEG1ADDR(NetRxPackets[i]);
+ }
+
+ for(i=0;i < NUM_TX_DESC; i++)
+ {
+ danube_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_des_ring[i]);
+ memset(tx_desc, 0, sizeof(tx_des_ring[0]));
+ }
+ /* turn on DMA rx & tx channel
+ */
+ *DANUBE_DMA_CS=RX_CHAN_NO;
+ *DANUBE_DMA_CCTRL|=1;/*reset and turn on the channel*/
+
+ return 0;
+}
+
+void danube_switch_halt(struct eth_device *dev)
+{
+ int i;
+ for(i=0;i<8;i++)
+ {
+ *DANUBE_DMA_CS=i;
+ *DANUBE_DMA_CCTRL&=~1;/*stop the dma channel*/
+ }
+// udelay(1000000);
+}
+
+int danube_switch_send(struct eth_device *dev, volatile void *packet,int length)
+{
+
+ int i;
+ int res = -1;
+
+ danube_tx_descriptor_t * tx_desc= KSEG1ADDR(&tx_des_ring[tx_num]);
+
+ if (length <= 0)
+ {
+ printf ("%s: bad packet size: %d\n", dev->name, length);
+ goto Done;
+ }
+
+ for(i=0; tx_desc->status.field.OWN==1; i++)
+ {
+ if(i>=TOUT_LOOP)
+ {
+ printf("NO Tx Descriptor...");
+ goto Done;
+ }
+ }
+
+ //serial_putc('s');
+
+ tx_desc->status.field.Sop=1;
+ tx_desc->status.field.Eop=1;
+ tx_desc->status.field.C=0;
+ tx_desc->DataPtr = (u32)KSEG1ADDR(packet);
+ if(length<60)
+ tx_desc->status.field.DataLen = 60;
+ else
+ tx_desc->status.field.DataLen = (u32)length;
+
+ asm("SYNC");
+ tx_desc->status.field.OWN=1;
+
+ res=length;
+ tx_num++;
+ if(tx_num==NUM_TX_DESC) tx_num=0;
+ *DANUBE_DMA_CS=TX_CHAN_NO;
+
+ if(!(*DANUBE_DMA_CCTRL & 1))
+ *DANUBE_DMA_CCTRL|=1;
+
+Done:
+ return res;
+}
+
+int danube_switch_recv(struct eth_device *dev)
+{
+
+ int length = 0;
+
+ danube_rx_descriptor_t * rx_desc;
+ int anchor_num=0;
+ int i;
+ for (;;)
+ {
+ rx_desc = KSEG1ADDR(&rx_des_ring[rx_num]);
+
+ if ((rx_desc->status.field.C == 0) || (rx_desc->status.field.OWN == 1))
+ {
+ break;
+ }
+
+
+ length = rx_desc->status.field.DataLen;
+ if (length)
+ {
+ NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_num]), length - 4);
+ // serial_putc('*');
+ }
+ else
+ {
+ printf("Zero length!!!\n");
+ }
+
+ rx_desc->status.field.Sop=0;
+ rx_desc->status.field.Eop=0;
+ rx_desc->status.field.C=0;
+ rx_desc->status.field.DataLen=PKTSIZE_ALIGN;
+ rx_desc->status.field.OWN=1;
+ rx_num++;
+ if(rx_num==NUM_RX_DESC) rx_num=0;
+
+ }
+
+ return length;
+}
+
+
+static void danube_init_switch_chip(int mode)
+{
+ int i;
+ /*get and set mac address for MAC*/
+ static unsigned char addr[6];
+ char *tmp,*end;
+ tmp = getenv ("ethaddr");
+ if (NULL == tmp) {
+ printf("Can't get environment ethaddr!!!\n");
+ // return NULL;
+ } else {
+ printf("ethaddr=%s\n", tmp);
+ }
+ *DANUBE_PMU_PWDCR = *DANUBE_PMU_PWDCR & 0xFFFFEFDF;
+ *DANUBE_PPE32_ETOP_MDIO_CFG &= ~0x6;
+ *DANUBE_PPE32_ENET_MAC_CFG = 0x187;
+
+ // turn on port0, set to rmii and turn off port1.
+ if(mode==REV_MII_MODE)
+ {
+ *DANUBE_PPE32_ETOP_CFG = (*DANUBE_PPE32_ETOP_CFG & 0xfffffffc) | 0x0000000a;
+ }
+ else if (mode == MII_MODE)
+ {
+ *DANUBE_PPE32_ETOP_CFG = (*DANUBE_PPE32_ETOP_CFG & 0xfffffffc) | 0x00000008;
+ }
+
+ *DANUBE_PPE32_ETOP_IG_PLEN_CTRL = 0x4005ee; // set packetlen.
+ *ENET_MAC_CFG|=1<<11;/*enable the crc*/
+ return;
+}
+
+
+static void danube_dma_init(void)
+{
+ int i;
+// serial_puts("d \n\0");
+
+ *DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
+ /* Reset DMA
+ */
+ *DANUBE_DMA_CTRL|=1;
+ *DANUBE_DMA_IRNEN=0;/*disable all the interrupts first*/
+
+ /* Clear Interrupt Status Register
+ */
+ *DANUBE_DMA_IRNCR=0xfffff;
+ /*disable all the dma interrupts*/
+ *DANUBE_DMA_IRNEN=0;
+ /*disable channel 0 and channel 1 interrupts*/
+
+ *DANUBE_DMA_CS=RX_CHAN_NO;
+ *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/
+ *DANUBE_DMA_CPOLL= 0x80000040;
+ /*set descriptor base*/
+ *DANUBE_DMA_CDBA=(u32)rx_des_ring;
+ *DANUBE_DMA_CDLEN=NUM_RX_DESC;
+ *DANUBE_DMA_CIE = 0;
+ *DANUBE_DMA_CCTRL=0x30000;
+
+ *DANUBE_DMA_CS=TX_CHAN_NO;
+ *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/
+ *DANUBE_DMA_CPOLL= 0x80000040;
+ *DANUBE_DMA_CDBA=(u32)tx_des_ring;
+ *DANUBE_DMA_CDLEN=NUM_TX_DESC;
+ *DANUBE_DMA_CIE = 0;
+ *DANUBE_DMA_CCTRL=0x30100;
+ /*enable the poll function and set the poll counter*/
+ //*DANUBE_DMA_CPOLL=DANUBE_DMA_POLL_EN | (DANUBE_DMA_POLL_COUNT<<4);
+ /*set port properties, enable endian conversion for switch*/
+ *DANUBE_DMA_PS=0;
+ *DANUBE_DMA_PCTRL|=0xf<<8;/*enable 32 bit endian conversion*/
+
+ return;
+}
+
+
+
+
+
+#endif
--- /dev/null
+/******************************************************************************
+**
+** FILE NAME : LzmaWrapper.h
+** PROJECT : bootloader
+** MODULES : U-boot
+**
+** DATE : 2 Nov 2006
+** AUTHOR : Lin Mars
+** DESCRIPTION : LZMA decoder support for U-boot 1.1.5
+** COPYRIGHT : Copyright (c) 2006
+** Infineon Technologies AG
+** Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+** This program is free software; you can redistribute it and/or modify
+** it under the terms of the GNU General Public License as published by
+** the Free Software Foundation; either version 2 of the License, or
+** (at your option) any later version.
+**
+** HISTORY
+** $Date $Author $Comment
+** 2 Nov 2006 Lin Mars init version which derived from LzmaTest.c from
+** LZMA v4.43 SDK
+*******************************************************************************/
+#ifndef __LZMA_WRAPPER_H__
+#define __LZMA_WRAPPER_H__
+
+#ifndef LZMA_RESULT_OK
+#define LZMA_RESULT_OK 0
+#endif
+#ifndef LZMA_RESULT_DATA_ERROR
+#define LZMA_RESULT_DATA_ERROR 1
+#endif
+
+extern int lzma_inflate(unsigned char *source, int s_len, unsigned char *dest, int *d_len);
+
+#endif /*__LZMA_WRAPPER_H__*/
--- /dev/null
+#ifndef DANUBE_H
+#define DANUBE_H
+/******************************************************************************
+ Copyright (c) 2002, Infineon Technologies. All rights reserved.
+
+ No Warranty
+ Because the program is licensed free of charge, there is no warranty for
+ the program, to the extent permitted by applicable law. Except when
+ otherwise stated in writing the copyright holders and/or other parties
+ provide the program "as is" without warranty of any kind, either
+ expressed or implied, including, but not limited to, the implied
+ warranties of merchantability and fitness for a particular purpose. The
+ entire risk as to the quality and performance of the program is with
+ you. should the program prove defective, you assume the cost of all
+ necessary servicing, repair or correction.
+
+ In no event unless required by applicable law or agreed to in writing
+ will any copyright holder, or any other party who may modify and/or
+ redistribute the program as permitted above, be liable to you for
+ damages, including any general, special, incidental or consequential
+ damages arising out of the use or inability to use the program
+ (including but not limited to loss of data or data being rendered
+ inaccurate or losses sustained by you or third parties or a failure of
+ the program to operate with any other programs), even if such holder or
+ other party has been advised of the possibility of such damages.
+******************************************************************************/
+
+/***********************************************************************/
+/* Module : MEI register address and bits */
+/***********************************************************************/
+#define MEI_SPACE_ACCESS 0xB0100C00
+#define MEI_DATA_XFR (0x0000 + MEI_SPACE_ACCESS)
+#define MEI_VERSION (0x0200 + MEI_SPACE_ACCESS)
+#define ARC_GP_STAT (0x0204 + MEI_SPACE_ACCESS)
+#define MEI_XFR_ADDR (0x020C + MEI_SPACE_ACCESS)
+#define MEI_TO_ARC_INT (0x021C + MEI_SPACE_ACCESS)
+#define ARC_TO_MEI_INT (0x0220 + MEI_SPACE_ACCESS)
+#define ARC_TO_MEI_INT_MASK (0x0224 + MEI_SPACE_ACCESS)
+#define MEI_DEBUG_WAD (0x0228 + MEI_SPACE_ACCESS)
+#define MEI_DEBUG_RAD (0x022C + MEI_SPACE_ACCESS)
+#define MEI_DEBUG_DATA (0x0230 + MEI_SPACE_ACCESS)
+#define MEI_DEBUG_DEC (0x0234 + MEI_SPACE_ACCESS)
+#define MEI_CONTROL (0x0238 + MEI_SPACE_ACCESS)
+#define AT_CELLRDY_BC0 (0x023C + MEI_SPACE_ACCESS)
+#define AT_CELLRDY_BC1 (0x0240 + MEI_SPACE_ACCESS)
+#define AR_CELLRDY_BC0 (0x0244 + MEI_SPACE_ACCESS)
+#define AR_CELLRDY_BC1 (0x0248 + MEI_SPACE_ACCESS)
+#define AAI_ACCESS (0x024C + MEI_SPACE_ACCESS)
+#define AAITXCB0 (0x0300 + MEI_SPACE_ACCESS)
+#define AAITXCB1 (0x0304 + MEI_SPACE_ACCESS)
+#define AAIRXCB0 (0x0308 + MEI_SPACE_ACCESS)
+#define AAIRXCB1 (0x030C + MEI_SPACE_ACCESS)
+
+
+/***********************************************************************/
+/* Module : WDT register address and bits */
+/***********************************************************************/
+#define DANUBE_BIU_WDT_BASE (0xBf8803F0)
+#define DANUBE_BIU_WDT_CR (0x0000 + DANUBE_BIU_WDT_BASE)
+#define DANUBE_BIU_WDT_SR (0x0008 + DANUBE_BIU_WDT_BASE)
+
+
+/***********************************************************************/
+/* Module : PMU register address and bits */
+/***********************************************************************/
+#define DANUBE_PMU_BASE_ADDR (KSEG1+0x1F102000)
+
+/***PM Control Register***/
+#define DANUBE_PMU_CR ((volatile u32*)(0x001C + DANUBE_PMU_BASE_ADDR))
+#define DANUBE_PMU_PWDCR DANUBE_PMU_CR
+#define DANUBE_PMU_SR ((volatile u32*)(0x0020 + DANUBE_PMU_BASE_ADDR))
+
+#define DANUBE_PMU_DMA_SHIFT 5
+#define DANUBE_PMU_PPE_SHIFT 13
+#define DANUBE_PMU_ETOP_SHIFT 22
+#define DANUBE_PMU_ENET0_SHIFT 24
+#define DANUBE_PMU_ENET1_SHIFT 25
+
+
+#define DANUBE_PMU DANUBE_PMU_BASE_ADDR
+/***PM Global Enable Register***/
+#define DANUBE_PMU_PM_GEN ((volatile u32*)(DANUBE_PMU+ 0x0000))
+#define DANUBE_PMU_PM_GEN_EN16 (1 << 16)
+#define DANUBE_PMU_PM_GEN_EN15 (1 << 15)
+#define DANUBE_PMU_PM_GEN_EN14 (1 << 14)
+#define DANUBE_PMU_PM_GEN_EN13 (1 << 13)
+#define DANUBE_PMU_PM_GEN_EN12 (1 << 12)
+#define DANUBE_PMU_PM_GEN_EN11 (1 << 11)
+#define DANUBE_PMU_PM_GEN_EN10 (1 << 10)
+#define DANUBE_PMU_PM_GEN_EN9 (1 << 9)
+#define DANUBE_PMU_PM_GEN_EN8 (1 << 8)
+#define DANUBE_PMU_PM_GEN_EN7 (1 << 7)
+#define DANUBE_PMU_PM_GEN_EN6 (1 << 6)
+#define DANUBE_PMU_PM_GEN_EN5 (1 << 5)
+#define DANUBE_PMU_PM_GEN_EN4 (1 << 4)
+#define DANUBE_PMU_PM_GEN_EN3 (1 << 3)
+#define DANUBE_PMU_PM_GEN_EN2 (1 << 2)
+#define DANUBE_PMU_PM_GEN_EN0 (1 << 0)
+
+/***PM Power Down Enable Register***/
+#define DANUBE_PMU_PM_PDEN ((volatile u32*)(DANUBE_PMU+ 0x0008))
+#define DANUBE_PMU_PM_PDEN_EN16 (1 << 16)
+#define DANUBE_PMU_PM_PDEN_EN15 (1 << 15)
+#define DANUBE_PMU_PM_PDEN_EN14 (1 << 14)
+#define DANUBE_PMU_PM_PDEN_EN13 (1 << 13)
+#define DANUBE_PMU_PM_PDEN_EN12 (1 << 12)
+#define DANUBE_PMU_PM_PDEN_EN11 (1 << 11)
+#define DANUBE_PMU_PM_PDEN_EN10 (1 << 10)
+#define DANUBE_PMU_PM_PDEN_EN9 (1 << 9)
+#define DANUBE_PMU_PM_PDEN_EN8 (1 << 8)
+#define DANUBE_PMU_PM_PDEN_EN7 (1 << 7)
+#define DANUBE_PMU_PM_PDEN_EN5 (1 << 5)
+#define DANUBE_PMU_PM_PDEN_EN4 (1 << 4)
+#define DANUBE_PMU_PM_PDEN_EN3 (1 << 3)
+#define DANUBE_PMU_PM_PDEN_EN2 (1 << 2)
+#define DANUBE_PMU_PM_PDEN_EN0 (1 << 0)
+
+/***PM Wake-Up from Power Down Register***/
+#define DANUBE_PMU_PM_WUP ((volatile u32*)(DANUBE_PMU+ 0x0010))
+#define DANUBE_PMU_PM_WUP_WUP16 (1 << 16)
+#define DANUBE_PMU_PM_WUP_WUP15 (1 << 15)
+#define DANUBE_PMU_PM_WUP_WUP14 (1 << 14)
+#define DANUBE_PMU_PM_WUP_WUP13 (1 << 13)
+#define DANUBE_PMU_PM_WUP_WUP12 (1 << 12)
+#define DANUBE_PMU_PM_WUP_WUP11 (1 << 11)
+#define DANUBE_PMU_PM_WUP_WUP10 (1 << 10)
+#define DANUBE_PMU_PM_WUP_WUP9 (1 << 9)
+#define DANUBE_PMU_PM_WUP_WUP8 (1 << 8)
+#define DANUBE_PMU_PM_PDEN_EN7 (1 << 7)
+#define DANUBE_PMU_PM_PDEN_EN5 (1 << 5)
+#define DANUBE_PMU_PM_PDEN_EN4 (1 << 4)
+#define DANUBE_PMU_PM_PDEN_EN3 (1 << 3)
+#define DANUBE_PMU_PM_PDEN_EN2 (1 << 2)
+#define DANUBE_PMU_PM_PDEN_EN0 (1 << 0)
+
+/***PM Wake-Up from Power Down Register***/
+#define DANUBE_PMU_PM_WUP ((volatile u32*)(DANUBE_PMU+ 0x0010))
+#define DANUBE_PMU_PM_WUP_WUP16 (1 << 16)
+#define DANUBE_PMU_PM_WUP_WUP15 (1 << 15)
+#define DANUBE_PMU_PM_WUP_WUP14 (1 << 14)
+#define DANUBE_PMU_PM_WUP_WUP13 (1 << 13)
+#define DANUBE_PMU_PM_WUP_WUP12 (1 << 12)
+#define DANUBE_PMU_PM_WUP_WUP11 (1 << 11)
+#define DANUBE_PMU_PM_WUP_WUP10 (1 << 10)
+#define DANUBE_PMU_PM_WUP_WUP9 (1 << 9)
+#define DANUBE_PMU_PM_WUP_WUP8 (1 << 8)
+#define DANUBE_PMU_PM_WUP_WUP7 (1 << 7)
+#define DANUBE_PMU_PM_WUP_WUP5 (1 << 5)
+#define DANUBE_PMU_PM_WUP_WUP4 (1 << 4)
+#define DANUBE_PMU_PM_WUP_WUP3 (1 << 3)
+#define DANUBE_PMU_PM_WUP_WUP2 (1 << 2)
+#define DANUBE_PMU_PM_WUP_WUP0 (1 << 0)
+
+/***PM Control Register***/
+#define DANUBE_PMU_PM_CR ((volatile u32*)(DANUBE_PMU+ 0x0014))
+#define DANUBE_PMU_PM_CR_AWEN (1 << 31)
+#define DANUBE_PMU_PM_CR_SWRST (1 << 30)
+#define DANUBE_PMU_PM_CR_SWCR (1 << 2)
+#define DANUBE_PMU_PM_CR_CRD (value) (((( 1 << 2) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/* Module : RCU register address and bits */
+/***********************************************************************/
+#define DANUBE_RCU_BASE_ADDR (0xBF203000)
+
+#define DANUBE_RCU_REQ (0x0010 + DANUBE_RCU_BASE_ADDR)
+#define DANUBE_RCU_RST_REQ ((volatile u32*)(DANUBE_RCU_REQ))
+#define DANUBE_RCU_STAT (0x0014 + DANUBE_RCU_BASE_ADDR)
+#define DANUBE_RCU_RST_SR ( (volatile u32 *)(DANUBE_RCU_STAT))
+#define DANUBE_RCU_PCI_RDY ( (volatile u32 *)(DANUBE_RCU_BASE_ADDR+0x28))
+#define DANUBE_RCU_MON (0x0030 + DANUBE_RCU_BASE_ADDR)
+
+
+/***********************************************************************/
+/* Module : BCU register address and bits */
+/***********************************************************************/
+#define DANUBE_BCU_BASE_ADDR (0xB0100000)
+/***BCU Control Register (0010H)***/
+#define DANUBE_BCU_CON (0x0010 + DANUBE_BCU_BASE_ADDR)
+#define DANUBE_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24)
+#define DANUBE_BCU_BCU_CON_SPE (1 << 19)
+#define DANUBE_BCU_BCU_CON_PSE (1 << 18)
+#define DANUBE_BCU_BCU_CON_DBG (1 << 16)
+#define DANUBE_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0)
+
+
+/***BCU Error Control Capture Register (0020H)***/
+#define DANUBE_BCU_ECON (0x0020 + DANUBE_BCU_BASE_ADDR)
+#define DANUBE_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24)
+#define DANUBE_BCU_BCU_ECON_RDN (1 << 23)
+#define DANUBE_BCU_BCU_ECON_WRN (1 << 22)
+#define DANUBE_BCU_BCU_ECON_SVM (1 << 21)
+#define DANUBE_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19)
+#define DANUBE_BCU_BCU_ECON_ABT (1 << 18)
+#define DANUBE_BCU_BCU_ECON_RDY (1 << 17)
+#define DANUBE_BCU_BCU_ECON_TOUT (1 << 16)
+#define DANUBE_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0)
+#define DANUBE_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28)
+
+/***BCU Error Address Capture Register (0024 H)***/
+#define DANUBE_BCU_EADD (0x0024 + DANUBE_BCU_BASE_ADDR)
+
+/***BCU Error Data Capture Register (0028H)***/
+#define DANUBE_BCU_EDAT (0x0028 + DANUBE_BCU_BASE_ADDR)
+
+#define DANUBE_BCU_IRNEN (0x00F4 + DANUBE_BCU_BASE_ADDR)
+#define DANUBE_BCU_IRNICR (0x00F8 + DANUBE_BCU_BASE_ADDR)
+#define DANUBE_BCU_IRNCR (0x00FC + DANUBE_BCU_BASE_ADDR)
+
+
+/***********************************************************************/
+/* Module : MBC register address and bits */
+/***********************************************************************/
+
+#define DANUBE_MBC (0xBF103000)
+/***********************************************************************/
+
+
+/***Mailbox CPU Configuration Register***/
+#define DANUBE_MBC_MBC_CFG ((volatile u32*)(DANUBE_MBC+ 0x0080))
+#define DANUBE_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6)
+#define DANUBE_MBC_MBC_CFG_RES (1 << 5)
+#define DANUBE_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1)
+#define DANUBE_MBC_MBC_CFG_SIZE (1 << 0)
+
+/***Mailbox CPU Interrupt Status Register***/
+#define DANUBE_MBC_MBC_ISR ((volatile u32*)(DANUBE_MBC+ 0x0084))
+#define DANUBE_MBC_MBC_ISR_B3DA (1 << 31)
+#define DANUBE_MBC_MBC_ISR_B2DA (1 << 30)
+#define DANUBE_MBC_MBC_ISR_B1E (1 << 29)
+#define DANUBE_MBC_MBC_ISR_B0E (1 << 28)
+#define DANUBE_MBC_MBC_ISR_WDT (1 << 27)
+#define DANUBE_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
+
+/***Mailbox CPU Mask Register***/
+#define DANUBE_MBC_MBC_MSK ((volatile u32*)(DANUBE_MBC+ 0x0088))
+#define DANUBE_MBC_MBC_MSK_B3DA (1 << 31)
+#define DANUBE_MBC_MBC_MSK_B2DA (1 << 30)
+#define DANUBE_MBC_MBC_MSK_B1E (1 << 29)
+#define DANUBE_MBC_MBC_MSK_B0E (1 << 28)
+#define DANUBE_MBC_MBC_MSK_WDT (1 << 27)
+#define DANUBE_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
+
+/***Mailbox CPU Mask 01 Register***/
+#define DANUBE_MBC_MBC_MSK01 ((volatile u32*)(DANUBE_MBC+ 0x008C))
+#define DANUBE_MBC_MBC_MSK01_B3DA (1 << 31)
+#define DANUBE_MBC_MBC_MSK01_B2DA (1 << 30)
+#define DANUBE_MBC_MBC_MSK01_B1E (1 << 29)
+#define DANUBE_MBC_MBC_MSK01_B0E (1 << 28)
+#define DANUBE_MBC_MBC_MSK01_WDT (1 << 27)
+#define DANUBE_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
+
+/***Mailbox CPU Mask 10 Register***/
+#define DANUBE_MBC_MBC_MSK10 ((volatile u32*)(DANUBE_MBC+ 0x0090))
+#define DANUBE_MBC_MBC_MSK10_B3DA (1 << 31)
+#define DANUBE_MBC_MBC_MSK10_B2DA (1 << 30)
+#define DANUBE_MBC_MBC_MSK10_B1E (1 << 29)
+#define DANUBE_MBC_MBC_MSK10_B0E (1 << 28)
+#define DANUBE_MBC_MBC_MSK10_WDT (1 << 27)
+#define DANUBE_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0)
+
+/***Mailbox CPU Short Command Register***/
+#define DANUBE_MBC_MBC_CMD ((volatile u32*)(DANUBE_MBC+ 0x0094))
+#define DANUBE_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0)
+
+/***Mailbox CPU Input Data of Buffer 0***/
+#define DANUBE_MBC_MBC_ID0 ((volatile u32*)(DANUBE_MBC+ 0x0000))
+#define DANUBE_MBC_MBC_ID0_INDATA
+
+/***Mailbox CPU Input Data of Buffer 1***/
+#define DANUBE_MBC_MBC_ID1 ((volatile u32*)(DANUBE_MBC+ 0x0020))
+#define DANUBE_MBC_MBC_ID1_INDATA
+
+/***Mailbox CPU Output Data of Buffer 2***/
+#define DANUBE_MBC_MBC_OD2 ((volatile u32*)(DANUBE_MBC+ 0x0040))
+#define DANUBE_MBC_MBC_OD2_OUTDATA
+
+/***Mailbox CPU Output Data of Buffer 3***/
+#define DANUBE_MBC_MBC_OD3 ((volatile u32*)(DANUBE_MBC+ 0x0060))
+#define DANUBE_MBC_MBC_OD3_OUTDATA
+
+/***Mailbox CPU Control Register of Buffer 0***/
+#define DANUBE_MBC_MBC_CR0 ((volatile u32*)(DANUBE_MBC+ 0x0004))
+#define DANUBE_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
+
+/***Mailbox CPU Control Register of Buffer 1***/
+#define DANUBE_MBC_MBC_CR1 ((volatile u32*)(DANUBE_MBC+ 0x0024))
+#define DANUBE_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
+
+/***Mailbox CPU Control Register of Buffer 2***/
+#define DANUBE_MBC_MBC_CR2 ((volatile u32*)(DANUBE_MBC+ 0x0044))
+#define DANUBE_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
+
+/***Mailbox CPU Control Register of Buffer 3***/
+#define DANUBE_MBC_MBC_CR3 ((volatile u32*)(DANUBE_MBC+ 0x0064))
+#define DANUBE_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0)
+
+/***Mailbox CPU Free Space of Buffer 0***/
+#define DANUBE_MBC_MBC_FS0 ((volatile u32*)(DANUBE_MBC+ 0x0008))
+#define DANUBE_MBC_MBC_FS0_FS
+
+/***Mailbox CPU Free Space of Buffer 1***/
+#define DANUBE_MBC_MBC_FS1 ((volatile u32*)(DANUBE_MBC+ 0x0028))
+#define DANUBE_MBC_MBC_FS1_FS
+
+/***Mailbox CPU Free Space of Buffer 2***/
+#define DANUBE_MBC_MBC_FS2 ((volatile u32*)(DANUBE_MBC+ 0x0048))
+#define DANUBE_MBC_MBC_FS2_FS
+
+/***Mailbox CPU Free Space of Buffer 3***/
+#define DANUBE_MBC_MBC_FS3 ((volatile u32*)(DANUBE_MBC+ 0x0068))
+#define DANUBE_MBC_MBC_FS3_FS
+
+/***Mailbox CPU Data Available in Buffer 0***/
+#define DANUBE_MBC_MBC_DA0 ((volatile u32*)(DANUBE_MBC+ 0x000C))
+#define DANUBE_MBC_MBC_DA0_DA
+
+/***Mailbox CPU Data Available in Buffer 1***/
+#define DANUBE_MBC_MBC_DA1 ((volatile u32*)(DANUBE_MBC+ 0x002C))
+#define DANUBE_MBC_MBC_DA1_DA
+
+/***Mailbox CPU Data Available in Buffer 2***/
+#define DANUBE_MBC_MBC_DA2 ((volatile u32*)(DANUBE_MBC+ 0x004C))
+#define DANUBE_MBC_MBC_DA2_DA
+
+/***Mailbox CPU Data Available in Buffer 3***/
+#define DANUBE_MBC_MBC_DA3 ((volatile u32*)(DANUBE_MBC+ 0x006C))
+#define DANUBE_MBC_MBC_DA3_DA
+
+/***Mailbox CPU Input Absolute Pointer of Buffer 0***/
+#define DANUBE_MBC_MBC_IABS0 ((volatile u32*)(DANUBE_MBC+ 0x0010))
+#define DANUBE_MBC_MBC_IABS0_IABS
+
+/***Mailbox CPU Input Absolute Pointer of Buffer 1***/
+#define DANUBE_MBC_MBC_IABS1 ((volatile u32*)(DANUBE_MBC+ 0x0030))
+#define DANUBE_MBC_MBC_IABS1_IABS
+
+/***Mailbox CPU Input Absolute Pointer of Buffer 2***/
+#define DANUBE_MBC_MBC_IABS2 ((volatile u32*)(DANUBE_MBC+ 0x0050))
+#define DANUBE_MBC_MBC_IABS2_IABS
+
+/***Mailbox CPU Input Absolute Pointer of Buffer 3***/
+#define DANUBE_MBC_MBC_IABS3 ((volatile u32*)(DANUBE_MBC+ 0x0070))
+#define DANUBE_MBC_MBC_IABS3_IABS
+
+/***Mailbox CPU Input Temporary Pointer of Buffer 0***/
+#define DANUBE_MBC_MBC_ITMP0 ((volatile u32*)(DANUBE_MBC+ 0x0014))
+#define DANUBE_MBC_MBC_ITMP0_ITMP
+
+/***Mailbox CPU Input Temporary Pointer of Buffer 1***/
+#define DANUBE_MBC_MBC_ITMP1 ((volatile u32*)(DANUBE_MBC+ 0x0034))
+#define DANUBE_MBC_MBC_ITMP1_ITMP
+
+/***Mailbox CPU Input Temporary Pointer of Buffer 2***/
+#define DANUBE_MBC_MBC_ITMP2 ((volatile u32*)(DANUBE_MBC+ 0x0054))
+#define DANUBE_MBC_MBC_ITMP2_ITMP
+
+/***Mailbox CPU Input Temporary Pointer of Buffer 3***/
+#define DANUBE_MBC_MBC_ITMP3 ((volatile u32*)(DANUBE_MBC+ 0x0074))
+#define DANUBE_MBC_MBC_ITMP3_ITMP
+
+/***Mailbox CPU Output Absolute Pointer of Buffer 0***/
+#define DANUBE_MBC_MBC_OABS0 ((volatile u32*)(DANUBE_MBC+ 0x0018))
+#define DANUBE_MBC_MBC_OABS0_OABS
+
+/***Mailbox CPU Output Absolute Pointer of Buffer 1***/
+#define DANUBE_MBC_MBC_OABS1 ((volatile u32*)(DANUBE_MBC+ 0x0038))
+#define DANUBE_MBC_MBC_OABS1_OABS
+
+/***Mailbox CPU Output Absolute Pointer of Buffer 2***/
+#define DANUBE_MBC_MBC_OABS2 ((volatile u32*)(DANUBE_MBC+ 0x0058))
+#define DANUBE_MBC_MBC_OABS2_OABS
+
+/***Mailbox CPU Output Absolute Pointer of Buffer 3***/
+#define DANUBE_MBC_MBC_OABS3 ((volatile u32*)(DANUBE_MBC+ 0x0078))
+#define DANUBE_MBC_MBC_OABS3_OABS
+
+/***Mailbox CPU Output Temporary Pointer of Buffer 0***/
+#define DANUBE_MBC_MBC_OTMP0 ((volatile u32*)(DANUBE_MBC+ 0x001C))
+#define DANUBE_MBC_MBC_OTMP0_OTMP
+
+/***Mailbox CPU Output Temporary Pointer of Buffer 1***/
+#define DANUBE_MBC_MBC_OTMP1 ((volatile u32*)(DANUBE_MBC+ 0x003C))
+#define DANUBE_MBC_MBC_OTMP1_OTMP
+
+/***Mailbox CPU Output Temporary Pointer of Buffer 2***/
+#define DANUBE_MBC_MBC_OTMP2 ((volatile u32*)(DANUBE_MBC+ 0x005C))
+#define DANUBE_MBC_MBC_OTMP2_OTMP
+
+/***Mailbox CPU Output Temporary Pointer of Buffer 3***/
+#define DANUBE_MBC_MBC_OTMP3 ((volatile u32*)(DANUBE_MBC+ 0x007C))
+#define DANUBE_MBC_MBC_OTMP3_OTMP
+
+/***DSP Control Register***/
+#define DANUBE_MBC_DCTRL ((volatile u32*)(DANUBE_MBC+ 0x00A0))
+#define DANUBE_MBC_DCTRL_BA (1 << 0)
+#define DANUBE_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1)
+#define DANUBE_MBC_DCTRL_IDL (1 << 4)
+#define DANUBE_MBC_DCTRL_RES (1 << 15)
+
+/***DSP Status Register***/
+#define DANUBE_MBC_DSTA ((volatile u32*)(DANUBE_MBC+ 0x00A4))
+#define DANUBE_MBC_DSTA_IDLE (1 << 0)
+#define DANUBE_MBC_DSTA_PD (1 << 1)
+
+/***DSP Test 1 Register***/
+#define DANUBE_MBC_DTST1 ((volatile u32*)(DANUBE_MBC+ 0x00A8))
+#define DANUBE_MBC_DTST1_ABORT (1 << 0)
+#define DANUBE_MBC_DTST1_HWF32 (1 << 1)
+#define DANUBE_MBC_DTST1_HWF4M (1 << 2)
+#define DANUBE_MBC_DTST1_HWFOP (1 << 3)
+
+
+/***********************************************************************/
+/* Module : SSC1 register address and bits */
+/***********************************************************************/
+#define DANUBE_SSC1 (KSEG1+0x1e100800)
+/***********************************************************************/
+/***SSC Clock Control Register***/
+#define DANUBE_SSC_CLC (0x0000)
+#define DANUBE_SSC_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8)
+#define DANUBE_SSC_CLC_DISS (1 << 1)
+#define DANUBE_SSC_CLC_DISR (1 << 0)
+/***SSC Port Input Selection Register***/
+#define DANUBE_SSC_PISEL (0x0004)
+/***SSC Identification Register***/
+#define DANUBE_SSC_ID (0x0008)
+/***Control Register (Programming Mode)***/
+#define DANUBE_SSC_CON (0x0010)
+#define DANUBE_SSC_CON_RUEN (1 << 12)
+#define DANUBE_SSC_CON_TUEN (1 << 11)
+#define DANUBE_SSC_CON_AEN (1 << 10)
+#define DANUBE_SSC_CON_REN (1 << 9)
+#define DANUBE_SSC_CON_TEN (1 << 8)
+#define DANUBE_SSC_CON_LB (1 << 7)
+#define DANUBE_SSC_CON_PO (1 << 6)
+#define DANUBE_SSC_CON_PH (1 << 5)
+#define DANUBE_SSC_CON_HB (1 << 4)
+#define DANUBE_SSC_CON_BM(value) (((( 1 << 5) - 1) & (value)) << 16)
+#define DANUBE_SSC_CON_RX_OFF (1 << 1)
+#define DANUBE_SSC_CON_TX_OFF (1 << 0)
+/***SCC Status Register***/
+#define DANUBE_SSC_STATE (0x0014)
+#define DANUBE_SSC_STATE_EN (1 << 0)
+#define DANUBE_SSC_STATE_MS (1 << 1)
+#define DANUBE_SSC_STATE_BSY (1 << 13)
+#define DANUBE_SSC_STATE_RUE (1 << 12)
+#define DANUBE_SSC_STATE_TUE (1 << 11)
+#define DANUBE_SSC_STATE_AE (1 << 10)
+#define DANUBE_SSC_STATE_RE (1 << 9)
+#define DANUBE_SSC_STATE_TE (1 << 8)
+#define DANUBE_SSC_STATE_BC(value) (((( 1 << 5) - 1) & (value)) << 16)
+/***SSC Write Hardware Modified Control Register***/
+#define DANUBE_SSC_WHBSTATE ( 0x0018)
+#define DANUBE_SSC_WHBSTATE_SETBE (1 << 15)
+#define DANUBE_SSC_WHBSTATE_SETPE (1 << 14)
+#define DANUBE_SSC_WHBSTATE_SETRE (1 << 13)
+#define DANUBE_SSC_WHBSTATE_SETTE (1 << 12)
+#define DANUBE_SSC_WHBSTATE_CLRBE (1 << 11)
+#define DANUBE_SSC_WHBSTATE_CLRPE (1 << 10)
+#define DANUBE_SSC_WHBSTATE_CLRRE (1 << 9)
+#define DANUBE_SSC_WHBSTATE_CLRTE (1 << 8)
+/***SSC Transmitter Buffer Register***/
+#define DANUBE_SSC_TB (0x0020)
+#define DANUBE_SSC_TB_TB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0)
+/***SSC Receiver Buffer Register***/
+#define DANUBE_SSC_RB (0x0024)
+#define DANUBE_SSC_RB_RB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0)
+/***SSC Receive FIFO Control Register***/
+#define DANUBE_SSC_RXFCON (0x0030)
+#define DANUBE_SSC_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
+#define DANUBE_SSC_RXFCON_RXTMEN (1 << 2)
+#define DANUBE_SSC_RXFCON_RXFLU (1 << 1)
+#define DANUBE_SSC_RXFCON_RXFEN (1 << 0)
+/***SSC Transmit FIFO Control Register***/
+#define DANUBE_SSC_TXFCON ( 0x0034)
+#define DANUBE_SSC_TXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8)
+#define DANUBE_SSC_TXFCON_TXTMEN (1 << 2)
+#define DANUBE_SSC_TXFCON_TXFLU (1 << 1)
+#define DANUBE_SSC_TXFCON_TXFEN (1 << 0)
+/***SSC FIFO Status Register***/
+#define DANUBE_SSC_FSTAT (0x0038)
+#define DANUBE_SSC_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8)
+#define DANUBE_SSC_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0)
+/***SSC Baudrate Timer Reload Register***/
+#define DANUBE_SSC_BR (0x0040)
+#define DANUBE_SSC_BR_BR_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0)
+#define DANUBE_SSC_BRSTAT (0x0044)
+#define DANUBE_SSC_SFCON (0x0060)
+#define DANUBE_SSC_SFSTAT (0x0064)
+#define DANUBE_SSC_GPOCON (0x0070)
+#define DANUBE_SSC_GPOSTAT (0x0074)
+#define DANUBE_SSC_WHBGPOSTAT (0x0078)
+#define DANUBE_SSC_RXREQ (0x0080)
+#define DANUBE_SSC_RXCNT (0x0084)
+/*DMA Registers in Bus Clock Domain*/
+#define DANUBE_SSC_DMA_CON (0x00EC)
+/*interrupt Node Registers in Bus Clock Domain*/
+#define DANUBE_SSC_IRNEN (0x00F4)
+#define DANUBE_SSC_IRNCR (0x00F8)
+#define DANUBE_SSC_IRNICR (0x00FC)
+#define DANUBE_SSC_IRN_FIR 0x8
+#define DANUBE_SSC_IRN_EIR 0x4
+#define DANUBE_SSC_IRN_RIR 0x2
+#define DANUBE_SSC_IRN_TIR 0x1
+
+
+#define DANUBE_SSC1_CLC ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CLC))
+#define DANUBE_SSC1_ID ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_ID))
+#define DANUBE_SSC1_CON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CON))
+#define DANUBE_SSC1_STATE ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_STATE))
+#define DANUBE_SSC1_WHBSTATE ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBSTATE))
+#define DANUBE_SSC1_TB ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TB))
+#define DANUBE_SSC1_RB ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RB))
+#define DANUBE_SSC1_FSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_FSTAT))
+#define DANUBE_SSC1_PISEL ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_PISEL))
+#define DANUBE_SSC1_RXFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXFCON))
+#define DANUBE_SSC1_TXFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TXFCON))
+#define DANUBE_SSC1_BR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BR))
+#define DANUBE_SSC1_BRSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BRSTAT))
+#define DANUBE_SSC1_SFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFCON))
+#define DANUBE_SSC1_SFSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFSTAT))
+#define DANUBE_SSC1_GPOCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOCON))
+#define DANUBE_SSC1_GPOSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOSTAT))
+#define DANUBE_SSC1_WHBGPOSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBGPOSTAT))
+#define DANUBE_SSC1_RXREQ ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXREQ))
+#define DANUBE_SSC1_RXCNT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXCNT))
+#define DANUBE_SSC1_DMA_CON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_DMA_CON))
+#define DANUBE_SSC1_IRNEN ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNEN))
+#define DANUBE_SSC1_IRNICR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNICR))
+#define DANUBE_SSC1_IRNCR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNCR))
+
+/***********************************************************************/
+/* Module : GPIO register address and bits */
+/***********************************************************************/
+#define DANUBE_GPIO (0xBE100B00)
+/***Port 0 Data Output Register (0010H)***/
+#define DANUBE_GPIO_P0_OUT ((volatile u32 *)(DANUBE_GPIO+ 0x0010))
+/***Port 1 Data Output Register (0040H)***/
+#define DANUBE_GPIO_P1_OUT ((volatile u32 *)(DANUBE_GPIO+ 0x0040))
+/***Port 0 Data Input Register (0014H)***/
+#define DANUBE_GPIO_P0_IN ((volatile u32 *)(DANUBE_GPIO+ 0x0014))
+/***Port 1 Data Input Register (0044H)***/
+#define DANUBE_GPIO_P1_IN ((volatile u32 *)(DANUBE_GPIO+ 0x0044))
+/***Port 0 Direction Register (0018H)***/
+#define DANUBE_GPIO_P0_DIR ((volatile u32 *)(DANUBE_GPIO+ 0x0018))
+/***Port 1 Direction Register (0048H)***/
+#define DANUBE_GPIO_P1_DIR ((volatile u32 *)(DANUBE_GPIO+ 0x0048))
+/***Port 0 Alternate Function Select Register 0 (001C H) ***/
+#define DANUBE_GPIO_P0_ALTSEL0 ((volatile u32 *)(DANUBE_GPIO+ 0x001C))
+/***Port 1 Alternate Function Select Register 0 (004C H) ***/
+#define DANUBE_GPIO_P1_ALTSEL0 ((volatile u32 *)(DANUBE_GPIO+ 0x004C))
+/***Port 0 Alternate Function Select Register 1 (0020 H) ***/
+#define DANUBE_GPIO_P0_ALTSEL1 ((volatile u32 *)(DANUBE_GPIO+ 0x0020))
+/***Port 1 Alternate Function Select Register 0 (0050 H) ***/
+#define DANUBE_GPIO_P1_ALTSEL1 ((volatile u32 *)(DANUBE_GPIO+ 0x0050))
+/***Port 0 Open Drain Control Register (0024H)***/
+#define DANUBE_GPIO_P0_OD ((volatile u32 *)(DANUBE_GPIO+ 0x0024))
+/***Port 1 Open Drain Control Register (0054H)***/
+#define DANUBE_GPIO_P1_OD ((volatile u32 *)(DANUBE_GPIO+ 0x0054))
+/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/
+#define DANUBE_GPIO_P0_STOFF ((volatile u32 *)(DANUBE_GPIO+ 0x0028))
+/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/
+#define DANUBE_GPIO_P1_STOFF ((volatile u32 *)(DANUBE_GPIO+ 0x0058))
+/***Port 0 Pull Up/Pull Down Select Register (002C H)***/
+#define DANUBE_GPIO_P0_PUDSEL ((volatile u32 *)(DANUBE_GPIO+ 0x002C))
+/***Port 1 Pull Up/Pull Down Select Register (005C H)***/
+#define DANUBE_GPIO_P1_PUDSEL ((volatile u32 *)(DANUBE_GPIO+ 0x005C))
+/***Port 0 Pull Up Device Enable Register (0030 H)***/
+#define DANUBE_GPIO_P0_PUDEN ((volatile u32 *)(DANUBE_GPIO+ 0x0030))
+/***Port 1 Pull Up Device Enable Register (0060 H)***/
+#define DANUBE_GPIO_P1_PUDEN ((volatile u32 *)(DANUBE_GPIO+ 0x0060))
+/***********************************************************************/
+/* Module : CGU register address and bits */
+/***********************************************************************/
+
+#define DANUBE_CGU (0xBF103000)
+/***********************************************************************/
+
+/***CGU Clock PLL0 ***/
+#define DANUBE_CGU_PLL0_CFG ((volatile u32*)(DANUBE_CGU+ 0x0004))
+/***CGU Clock PLL1 ***/
+#define DANUBE_CGU_PLL1_CFG ((volatile u32*)(DANUBE_CGU+ 0x0008))
+/***CGU Clock SYS Mux Register***/
+#define DANUBE_CGU_SYS ((volatile u32*)(DANUBE_CGU+ 0x0010))
+/***CGU Interface Clock Control Register***/
+#define DANUBE_CGU_IFCCR ((volatile u32*)(DANUBE_CGU+ 0x0018))
+/***CGU PCI Clock Control Register**/
+#define DANUBE_CGU_PCICR ((volatile u32*)(DANUBE_CGU+ 0x0034))
+
+
+/***********************************************************************/
+/* Module : PCI register address and bits */
+/***********************************************************************/
+#define PCI_CR_PR_OFFSET 0xBE105400
+#define PCI_CR_CLK_CTRL_REG (PCI_CR_PR_OFFSET + 0x0000)
+
+#define PCI_CR_PCI_ID_REG (PCI_CR_PR_OFFSET + 0x0004)
+#define PCI_CR_SFT_RST_REG (PCI_CR_PR_OFFSET + 0x0010)
+#define PCI_CR_PCI_FPI_ERR_ADDR_REG (PCI_CR_PR_OFFSET + 0x0014)
+#define PCI_CR_FCI_PCI_ERR_ADDR_REG (PCI_CR_PR_OFFSET + 0x0018)
+#define PCI_CR_FPI_ERR_TAG_REG (PCI_CR_PR_OFFSET + 0x001C)
+#define PCI_CR_PCI_IRR_REG (PCI_CR_PR_OFFSET + 0x0020)
+#define PCI_CR_PCI_IRA_REG (PCI_CR_PR_OFFSET + 0x0024)
+#define PCI_CR_PCI_IRM_REG (PCI_CR_PR_OFFSET + 0x0028)
+#define PCI_CR_PCI_EOI_REG (PCI_CR_PR_OFFSET + 0x002C)
+#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
+#define PCI_CR_DV_ID_REG (PCI_CR_PR_OFFSET + 0x0034)
+#define PCI_CR_SUBSYS_ID_REG (PCI_CR_PR_OFFSET + 0x0038)
+#define PCI_CR_PCI_PM_REG (PCI_CR_PR_OFFSET + 0x003C)
+#define PCI_CR_CLASS_CODE1_REG (PCI_CR_PR_OFFSET + 0x0040)
+#define PCI_CR_BAR11MASK_REG (PCI_CR_PR_OFFSET + 0x0044)
+#define PCI_CR_BAR12MASK_REG (PCI_CR_PR_OFFSET + 0x0048)
+#define PCI_CR_BAR13MASK_REG (PCI_CR_PR_OFFSET + 0x004C)
+#define PCI_CR_BAR14MASK_REG (PCI_CR_PR_OFFSET + 0x0050)
+#define PCI_CR_BAR15MASK_REG (PCI_CR_PR_OFFSET + 0x0054)
+#define PCI_CR_BAR16MASK_REG (PCI_CR_PR_OFFSET + 0x0058)
+#define PCI_CR_CIS_PT1_REG (PCI_CR_PR_OFFSET + 0x005C)
+#define PCI_CR_SUBSYS_ID1_REG (PCI_CR_PR_OFFSET + 0x0060)
+#define PCI_CR_PCI_ADDR_MAP11_REG (PCI_CR_PR_OFFSET + 0x0064)
+#define PCI_CR_PCI_ADDR_MAP12_REG (PCI_CR_PR_OFFSET + 0x0068)
+#define PCI_CR_PCI_ADDR_MAP13_REG (PCI_CR_PR_OFFSET + 0x006C)
+#define PCI_CR_PCI_ADDR_MAP14_REG (PCI_CR_PR_OFFSET + 0x0070)
+#define PCI_CR_PCI_ADDR_MAP15_REG (PCI_CR_PR_OFFSET + 0x0074)
+#define PCI_CR_PCI_ADDR_MAP16_REG (PCI_CR_PR_OFFSET + 0x0078)
+#define PCI_CR_FPI_SEG_EN_REG (PCI_CR_PR_OFFSET + 0x007C)
+#define PCI_CR_PC_ARB_REG (PCI_CR_PR_OFFSET + 0x0080)
+#define PCI_CR_BAR21MASK_REG (PCI_CR_PR_OFFSET + 0x0084)
+#define PCI_CR_BAR22MASK_REG (PCI_CR_PR_OFFSET + 0x0088)
+#define PCI_CR_BAR23MASK_REG (PCI_CR_PR_OFFSET + 0x008C)
+#define PCI_CR_BAR24MASK_REG (PCI_CR_PR_OFFSET + 0x0090)
+#define PCI_CR_BAR25MASK_REG (PCI_CR_PR_OFFSET + 0x0094)
+#define PCI_CR_BAR26MASK_REG (PCI_CR_PR_OFFSET + 0x0098)
+#define PCI_CR_CIS_PT2_REG (PCI_CR_PR_OFFSET + 0x009C)
+#define PCI_CR_SUBSYS_ID2_REG (PCI_CR_PR_OFFSET + 0x00A0)
+#define PCI_CR_PCI_ADDR_MAP21_REG (PCI_CR_PR_OFFSET + 0x00A4)
+#define PCI_CR_PCI_ADDR_MAP22_REG (PCI_CR_PR_OFFSET + 0x00A8)
+#define PCI_CR_PCI_ADDR_MAP23_REG (PCI_CR_PR_OFFSET + 0x00AC)
+
+
+/***********************************************************************/
+/* Module : MCD register address and bits */
+/***********************************************************************/
+#define DANUBE_MCD (KSEG1+0x1F106000)
+
+/***Manufacturer Identification Register***/
+#define DANUBE_MCD_MANID ((volatile u32*)(DANUBE_MCD+ 0x0024))
+#define DANUBE_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5)
+
+/***Chip Identification Register***/
+#define DANUBE_MCD_CHIPID ((volatile u32*)(DANUBE_MCD+ 0x0028))
+#define DANUBE_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
+#define DANUBE_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
+#define DANUBE_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1))
+#define DANUBE_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
+#define DANUBE_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1))
+#define DANUBE_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1)
+
+#define DANUBE_CHIPID_STANDARD 0x00EB
+#define DANUBE_CHIPID_YANGTSE 0x00ED
+
+/***Redesign Tracing Identification Register***/
+#define DANUBE_MCD_RTID ((volatile u32*)(DANUBE_MCD+ 0x002C))
+#define DANUBE_MCD_RTID_LC (1 << 15)
+#define DANUBE_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0)
+
+
+/***********************************************************************/
+/* Module : EBU register address and bits */
+/***********************************************************************/
+
+#define DANUBE_EBU (0xBE105300)
+#define EBU_ADDR_SEL_0 (volatile u32*)(DANUBE_EBU + 0x20)
+#define EBU_ADDR_SEL_1 (volatile u32*)(DANUBE_EBU + 0x24)
+#define EBU_CON_0 (volatile u32*)(DANUBE_EBU + 0x60)
+#define EBU_CON_1 (volatile u32*)(DANUBE_EBU + 0x64)
+#define EBU_NAND_CON (volatile u32*)(DANUBE_EBU + 0xB0)
+#define EBU_NAND_WAIT (volatile u32*)(DANUBE_EBU + 0xB4)
+#define EBU_NAND_ECC0 (volatile u32*)(DANUBE_EBU + 0xB8)
+#define EBU_NAND_ECC_AC (volatile u32*)(DANUBE_EBU + 0xBC)
+
+/***********************************************************************/
+
+
+/***EBU Clock Control Register***/
+#define DANUBE_EBU_CLC ((volatile u32*)(DANUBE_EBU+ 0x0000))
+#define DANUBE_EBU_CLC_DISS (1 << 1)
+#define DANUBE_EBU_CLC_DISR (1 << 0)
+
+/***EBU Global Control Register***/
+#define DANUBE_EBU_CON ((volatile u32*)(DANUBE_EBU+ 0x0010))
+#define DANUBE_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20)
+#define DANUBE_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16)
+#define DANUBE_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8)
+#define DANUBE_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6)
+#define DANUBE_EBU_CON_ARBSYNC (1 << 5)
+#define DANUBE_EBU_CON_1 (1 << 3)
+
+/***EBU Address Select Register 0***/
+#define DANUBE_EBU_ADDSEL0 ((volatile u32*)(DANUBE_EBU+ 0x0020))
+#define DANUBE_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
+#define DANUBE_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_EBU_ADDSEL0_MIRRORE (1 << 1)
+#define DANUBE_EBU_ADDSEL0_REGEN (1 << 0)
+
+/***EBU Address Select Register 1***/
+#define DANUBE_EBU_ADDSEL1 ((volatile u32*)(DANUBE_EBU+ 0x0024))
+#define DANUBE_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
+#define DANUBE_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_EBU_ADDSEL1_MIRRORE (1 << 1)
+#define DANUBE_EBU_ADDSEL1_REGEN (1 << 0)
+
+/***EBU Address Select Register 2***/
+#define DANUBE_EBU_ADDSEL2 ((volatile u32*)(DANUBE_EBU+ 0x0028))
+#define DANUBE_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
+#define DANUBE_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_EBU_ADDSEL2_MIRRORE (1 << 1)
+#define DANUBE_EBU_ADDSEL2_REGEN (1 << 0)
+
+/***EBU Address Select Register 3***/
+#define DANUBE_EBU_ADDSEL3 ((volatile u32*)(DANUBE_EBU+ 0x0028))
+#define DANUBE_EBU_ADDSEL3_BASE (value) (((( 1 << 20) - 1) & (value)) << 12)
+#define DANUBE_EBU_ADDSEL3_MASK (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_EBU_ADDSEL3_MIRRORE (1 << 1)
+#define DANUBE_EBU_ADDSEL3_REGEN (1 << 0)
+
+/***EBU Bus Configuration Register 0***/
+#define DANUBE_EBU_BUSCON0 ((volatile u32*)(DANUBE_EBU+ 0x0060))
+#define DANUBE_EBU_BUSCON0_WRDIS (1 << 31)
+#define DANUBE_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
+#define DANUBE_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
+#define DANUBE_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
+#define DANUBE_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
+#define DANUBE_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
+#define DANUBE_EBU_BUSCON0_WAITINV (1 << 19)
+#define DANUBE_EBU_BUSCON0_SETUP (1 << 18)
+#define DANUBE_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
+#define DANUBE_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
+#define DANUBE_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
+#define DANUBE_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
+#define DANUBE_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
+#define DANUBE_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
+
+/***EBU Bus Configuration Register 1***/
+#define DANUBE_EBU_BUSCON1 ((volatile u32*)(DANUBE_EBU+ 0x0064))
+#define DANUBE_EBU_BUSCON1_WRDIS (1 << 31)
+#define DANUBE_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
+#define DANUBE_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
+#define DANUBE_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
+#define DANUBE_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
+#define DANUBE_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
+#define DANUBE_EBU_BUSCON1_WAITINV (1 << 19)
+#define DANUBE_EBU_BUSCON1_SETUP (1 << 18)
+#define DANUBE_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
+#define DANUBE_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
+#define DANUBE_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
+#define DANUBE_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
+#define DANUBE_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
+#define DANUBE_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
+
+/***EBU Bus Configuration Register 2***/
+#define DANUBE_EBU_BUSCON2 ((volatile u32*)(DANUBE_EBU+ 0x0068))
+#define DANUBE_EBU_BUSCON2_WRDIS (1 << 31)
+#define DANUBE_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29)
+#define DANUBE_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27)
+#define DANUBE_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24)
+#define DANUBE_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22)
+#define DANUBE_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20)
+#define DANUBE_EBU_BUSCON2_WAITINV (1 << 19)
+#define DANUBE_EBU_BUSCON2_SETUP (1 << 18)
+#define DANUBE_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16)
+#define DANUBE_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9)
+#define DANUBE_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6)
+#define DANUBE_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4)
+#define DANUBE_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2)
+#define DANUBE_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/* Module : SDRAM register address and bits */
+/***********************************************************************/
+
+#define DANUBE_SDRAM (0xBF800000)
+/***********************************************************************/
+
+
+/***MC Access Error Cause Register***/
+#define DANUBE_SDRAM_MC_ERRCAUSE ((volatile u32*)(DANUBE_SDRAM+ 0x0100))
+#define DANUBE_SDRAM_MC_ERRCAUSE_ERR (1 << 31)
+#define DANUBE_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16)
+#define DANUBE_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0)
+#define DANUBE_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN)
+
+/***MC Access Error Address Register***/
+#define DANUBE_SDRAM_MC_ERRADDR ((volatile u32*)(DANUBE_SDRAM+ 0x0108))
+#define DANUBE_SDRAM_MC_ERRADDR_ADDR
+
+/***MC I/O General Purpose Register***/
+#define DANUBE_SDRAM_MC_IOGP ((volatile u32*)(DANUBE_SDRAM+ 0x0800))
+#define DANUBE_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28)
+#define DANUBE_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24)
+#define DANUBE_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20)
+#define DANUBE_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16)
+#define DANUBE_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12)
+#define DANUBE_SDRAM_MC_IOGP_CPS (1 << 11)
+#define DANUBE_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8)
+#define DANUBE_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0)
+
+/***MC Self Refresh Register***/
+#define DANUBE_SDRAM_MC_SELFRFSH ((volatile u32*)(DANUBE_SDRAM+ 0x0A00))
+#define DANUBE_SDRAM_MC_SELFRFSH_PWDS (1 << 1)
+#define DANUBE_SDRAM_MC_SELFRFSH_PWD (1 << 0)
+#define DANUBE_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2)
+
+/***MC Enable Register***/
+#define DANUBE_SDRAM_MC_CTRLENA ((volatile u32*)(DANUBE_SDRAM+ 0x1000))
+#define DANUBE_SDRAM_MC_CTRLENA_ENA (1 << 0)
+#define DANUBE_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1)
+
+/***MC Mode Register Setup Code***/
+#define DANUBE_SDRAM_MC_MRSCODE ((volatile u32*)(DANUBE_SDRAM+ 0x1008))
+#define DANUBE_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7)
+#define DANUBE_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4)
+#define DANUBE_SDRAM_MC_MRSCODE_WT (1 << 3)
+#define DANUBE_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0)
+
+/***MC Configuration Data-word Width Register***/
+#define DANUBE_SDRAM_MC_CFGDW ((volatile u32*)(DANUBE_SDRAM+ 0x1010))
+#define DANUBE_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0)
+#define DANUBE_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4)
+
+/***MC Configuration Physical Bank 0 Register***/
+#define DANUBE_SDRAM_MC_CFGPB0 ((volatile u32*)(DANUBE_SDRAM+ 0x1018))
+#define DANUBE_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12)
+#define DANUBE_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8)
+#define DANUBE_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0)
+#define DANUBE_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16)
+
+/***MC Latency Register***/
+#define DANUBE_SDRAM_MC_LATENCY ((volatile u32*)(DANUBE_SDRAM+ 0x1038))
+#define DANUBE_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16)
+#define DANUBE_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12)
+#define DANUBE_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8)
+#define DANUBE_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0)
+#define DANUBE_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20)
+
+/***MC Refresh Cycle Time Register***/
+#define DANUBE_SDRAM_MC_TREFRESH ((volatile u32*)(DANUBE_SDRAM+ 0x1040))
+#define DANUBE_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0)
+#define DANUBE_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13)
+
+
+/***********************************************************************/
+/* Module : GPTU register address and bits */
+/***********************************************************************/
+
+#define DANUBE_GPTU (0xB8000300)
+/***********************************************************************/
+
+
+/***GPT Clock Control Register***/
+#define DANUBE_GPTU_GPT_CLC ((volatile u32*)(DANUBE_GPTU+ 0x0000))
+#define DANUBE_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8)
+#define DANUBE_GPTU_GPT_CLC_DISS (1 << 1)
+#define DANUBE_GPTU_GPT_CLC_DISR (1 << 0)
+
+/***GPT Timer 3 Control Register***/
+#define DANUBE_GPTU_GPT_T3CON ((volatile u32*)(DANUBE_GPTU+ 0x0014))
+#define DANUBE_GPTU_GPT_T3CON_T3RDIR (1 << 15)
+#define DANUBE_GPTU_GPT_T3CON_T3CHDIR (1 << 14)
+#define DANUBE_GPTU_GPT_T3CON_T3EDGE (1 << 13)
+#define DANUBE_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11)
+#define DANUBE_GPTU_GPT_T3CON_T3OTL (1 << 10)
+#define DANUBE_GPTU_GPT_T3CON_T3UD (1 << 7)
+#define DANUBE_GPTU_GPT_T3CON_T3R (1 << 6)
+#define DANUBE_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3)
+#define DANUBE_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0)
+
+/***GPT Write Hardware Modified Timer 3 Control Register
+If set and clear bit are written concurrently with 1, the associated bit is not changed.***/
+#define DANUBE_GPTU_GPT_WHBT3CON ((volatile u32*)(DANUBE_GPTU+ 0x004C))
+#define DANUBE_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15)
+#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14)
+#define DANUBE_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13)
+#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12)
+#define DANUBE_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11)
+#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10)
+
+/***GPT Timer 2 Control Register***/
+#define DANUBE_GPTU_GPT_T2CON ((volatile u32*)(DANUBE_GPTU+ 0x0010))
+#define DANUBE_GPTU_GPT_T2CON_TxRDIR (1 << 15)
+#define DANUBE_GPTU_GPT_T2CON_TxCHDIR (1 << 14)
+#define DANUBE_GPTU_GPT_T2CON_TxEDGE (1 << 13)
+#define DANUBE_GPTU_GPT_T2CON_TxIRDIS (1 << 12)
+#define DANUBE_GPTU_GPT_T2CON_TxRC (1 << 9)
+#define DANUBE_GPTU_GPT_T2CON_TxUD (1 << 7)
+#define DANUBE_GPTU_GPT_T2CON_TxR (1 << 6)
+#define DANUBE_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3)
+#define DANUBE_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0)
+
+/***GPT Timer 4 Control Register***/
+#define DANUBE_GPTU_GPT_T4CON ((volatile u32*)(DANUBE_GPTU+ 0x0018))
+#define DANUBE_GPTU_GPT_T4CON_TxRDIR (1 << 15)
+#define DANUBE_GPTU_GPT_T4CON_TxCHDIR (1 << 14)
+#define DANUBE_GPTU_GPT_T4CON_TxEDGE (1 << 13)
+#define DANUBE_GPTU_GPT_T4CON_TxIRDIS (1 << 12)
+#define DANUBE_GPTU_GPT_T4CON_TxRC (1 << 9)
+#define DANUBE_GPTU_GPT_T4CON_TxUD (1 << 7)
+#define DANUBE_GPTU_GPT_T4CON_TxR (1 << 6)
+#define DANUBE_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3)
+#define DANUBE_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0)
+
+/***GPT Write HW Modified Timer 2 Control Register If set
+ and clear bit are written concurrently with 1, the associated bit is not changed.***/
+#define DANUBE_GPTU_GPT_WHBT2CON ((volatile u32*)(DANUBE_GPTU+ 0x0048))
+#define DANUBE_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15)
+#define DANUBE_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14)
+#define DANUBE_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13)
+#define DANUBE_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12)
+
+/***GPT Write HW Modified Timer 4 Control Register If set
+ and clear bit are written concurrently with 1, the associated bit is not changed.***/
+#define DANUBE_GPTU_GPT_WHBT4CON ((volatile u32*)(DANUBE_GPTU+ 0x0050))
+#define DANUBE_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15)
+#define DANUBE_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14)
+#define DANUBE_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13)
+#define DANUBE_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12)
+
+/***GPT Capture Reload Register***/
+#define DANUBE_GPTU_GPT_CAPREL ((volatile u32*)(DANUBE_GPTU+ 0x0030))
+#define DANUBE_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 2 Register***/
+#define DANUBE_GPTU_GPT_T2 ((volatile u32*)(DANUBE_GPTU+ 0x0034))
+#define DANUBE_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 3 Register***/
+#define DANUBE_GPTU_GPT_T3 ((volatile u32*)(DANUBE_GPTU+ 0x0038))
+#define DANUBE_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 4 Register***/
+#define DANUBE_GPTU_GPT_T4 ((volatile u32*)(DANUBE_GPTU+ 0x003C))
+#define DANUBE_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 5 Register***/
+#define DANUBE_GPTU_GPT_T5 ((volatile u32*)(DANUBE_GPTU+ 0x0040))
+#define DANUBE_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 6 Register***/
+#define DANUBE_GPTU_GPT_T6 ((volatile u32*)(DANUBE_GPTU+ 0x0044))
+#define DANUBE_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 6 Control Register***/
+#define DANUBE_GPTU_GPT_T6CON ((volatile u32*)(DANUBE_GPTU+ 0x0020))
+#define DANUBE_GPTU_GPT_T6CON_T6SR (1 << 15)
+#define DANUBE_GPTU_GPT_T6CON_T6CLR (1 << 14)
+#define DANUBE_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11)
+#define DANUBE_GPTU_GPT_T6CON_T6OTL (1 << 10)
+#define DANUBE_GPTU_GPT_T6CON_T6UD (1 << 7)
+#define DANUBE_GPTU_GPT_T6CON_T6R (1 << 6)
+#define DANUBE_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3)
+#define DANUBE_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0)
+
+/***GPT Write HW Modified Timer 6 Control Register If set
+ and clear bit are written concurrently with 1, the associated bit is not changed.***/
+#define DANUBE_GPTU_GPT_WHBT6CON ((volatile u32*)(DANUBE_GPTU+ 0x0054))
+#define DANUBE_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11)
+#define DANUBE_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10)
+
+/***GPT Timer 5 Control Register***/
+#define DANUBE_GPTU_GPT_T5CON ((volatile u32*)(DANUBE_GPTU+ 0x001C))
+#define DANUBE_GPTU_GPT_T5CON_T5SC (1 << 15)
+#define DANUBE_GPTU_GPT_T5CON_T5CLR (1 << 14)
+#define DANUBE_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12)
+#define DANUBE_GPTU_GPT_T5CON_T5CC (1 << 11)
+#define DANUBE_GPTU_GPT_T5CON_CT3 (1 << 10)
+#define DANUBE_GPTU_GPT_T5CON_T5RC (1 << 9)
+#define DANUBE_GPTU_GPT_T5CON_T5UDE (1 << 8)
+#define DANUBE_GPTU_GPT_T5CON_T5UD (1 << 7)
+#define DANUBE_GPTU_GPT_T5CON_T5R (1 << 6)
+#define DANUBE_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3)
+#define DANUBE_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0)
+
+
+/***********************************************************************/
+/* Module : IOM register address and bits */
+/***********************************************************************/
+
+#define DANUBE_IOM (0xBF105000)
+/***********************************************************************/
+
+
+/***Receive FIFO***/
+#define DANUBE_IOM_RFIFO ((volatile u32*)(DANUBE_IOM+ 0x0000))
+#define DANUBE_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Transmit FIFO***/
+#define DANUBE_IOM_XFIFO ((volatile u32*)(DANUBE_IOM+ 0x0000))
+#define DANUBE_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Interrupt Status Register HDLC***/
+#define DANUBE_IOM_ISTAH ((volatile u32*)(DANUBE_IOM+ 0x0080))
+#define DANUBE_IOM_ISTAH_RME (1 << 7)
+#define DANUBE_IOM_ISTAH_RPF (1 << 6)
+#define DANUBE_IOM_ISTAH_RFO (1 << 5)
+#define DANUBE_IOM_ISTAH_XPR (1 << 4)
+#define DANUBE_IOM_ISTAH_XMR (1 << 3)
+#define DANUBE_IOM_ISTAH_XDU (1 << 2)
+
+/***Interrupt Mask Register HDLC***/
+#define DANUBE_IOM_MASKH ((volatile u32*)(DANUBE_IOM+ 0x0080))
+#define DANUBE_IOM_MASKH_RME (1 << 7)
+#define DANUBE_IOM_MASKH_RPF (1 << 6)
+#define DANUBE_IOM_MASKH_RFO (1 << 5)
+#define DANUBE_IOM_MASKH_XPR (1 << 4)
+#define DANUBE_IOM_MASKH_XMR (1 << 3)
+#define DANUBE_IOM_MASKH_XDU (1 << 2)
+
+/***Status Register***/
+#define DANUBE_IOM_STAR ((volatile u32*)(DANUBE_IOM+ 0x0084))
+#define DANUBE_IOM_STAR_XDOV (1 << 7)
+#define DANUBE_IOM_STAR_XFW (1 << 6)
+#define DANUBE_IOM_STAR_RACI (1 << 3)
+#define DANUBE_IOM_STAR_XACI (1 << 1)
+
+/***Command Register***/
+#define DANUBE_IOM_CMDR ((volatile u32*)(DANUBE_IOM+ 0x0084))
+#define DANUBE_IOM_CMDR_RMC (1 << 7)
+#define DANUBE_IOM_CMDR_RRES (1 << 6)
+#define DANUBE_IOM_CMDR_XTF (1 << 3)
+#define DANUBE_IOM_CMDR_XME (1 << 1)
+#define DANUBE_IOM_CMDR_XRES (1 << 0)
+
+/***Mode Register***/
+#define DANUBE_IOM_MODEH ((volatile u32*)(DANUBE_IOM+ 0x0088))
+#define DANUBE_IOM_MODEH_MDS2 (1 << 7)
+#define DANUBE_IOM_MODEH_MDS1 (1 << 6)
+#define DANUBE_IOM_MODEH_MDS0 (1 << 5)
+#define DANUBE_IOM_MODEH_RAC (1 << 3)
+#define DANUBE_IOM_MODEH_DIM2 (1 << 2)
+#define DANUBE_IOM_MODEH_DIM1 (1 << 1)
+#define DANUBE_IOM_MODEH_DIM0 (1 << 0)
+
+/***Extended Mode Register***/
+#define DANUBE_IOM_EXMR ((volatile u32*)(DANUBE_IOM+ 0x008C))
+#define DANUBE_IOM_EXMR_XFBS (1 << 7)
+#define DANUBE_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5)
+#define DANUBE_IOM_EXMR_SRA (1 << 4)
+#define DANUBE_IOM_EXMR_XCRC (1 << 3)
+#define DANUBE_IOM_EXMR_RCRC (1 << 2)
+#define DANUBE_IOM_EXMR_ITF (1 << 0)
+
+/***SAPI1 Register***/
+#define DANUBE_IOM_SAP1 ((volatile u32*)(DANUBE_IOM+ 0x0094))
+#define DANUBE_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2)
+#define DANUBE_IOM_SAP1_MHA (1 << 0)
+
+/***Receive Frame Byte Count Low***/
+#define DANUBE_IOM_RBCL ((volatile u32*)(DANUBE_IOM+ 0x0098))
+#define DANUBE_IOM_RBCL_RBC(value) (1 << value)
+
+
+/***SAPI2 Register***/
+#define DANUBE_IOM_SAP2 ((volatile u32*)(DANUBE_IOM+ 0x0098))
+#define DANUBE_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2)
+#define DANUBE_IOM_SAP2_MLA (1 << 0)
+
+/***Receive Frame Byte Count High***/
+#define DANUBE_IOM_RBCH ((volatile u32*)(DANUBE_IOM+ 0x009C))
+#define DANUBE_IOM_RBCH_OV (1 << 4)
+#define DANUBE_IOM_RBCH_RBC11 (1 << 3)
+#define DANUBE_IOM_RBCH_RBC10 (1 << 2)
+#define DANUBE_IOM_RBCH_RBC9 (1 << 1)
+#define DANUBE_IOM_RBCH_RBC8 (1 << 0)
+
+/***TEI1 Register 1***/
+#define DANUBE_IOM_TEI1 ((volatile u32*)(DANUBE_IOM+ 0x009C))
+#define DANUBE_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1)
+#define DANUBE_IOM_TEI1_EA (1 << 0)
+
+/***Receive Status Register***/
+#define DANUBE_IOM_RSTA ((volatile u32*)(DANUBE_IOM+ 0x00A0))
+#define DANUBE_IOM_RSTA_VFR (1 << 7)
+#define DANUBE_IOM_RSTA_RDO (1 << 6)
+#define DANUBE_IOM_RSTA_CRC (1 << 5)
+#define DANUBE_IOM_RSTA_RAB (1 << 4)
+#define DANUBE_IOM_RSTA_SA1 (1 << 3)
+#define DANUBE_IOM_RSTA_SA0 (1 << 2)
+#define DANUBE_IOM_RSTA_TA (1 << 0)
+#define DANUBE_IOM_RSTA_CR (1 << 1)
+
+/***TEI2 Register***/
+#define DANUBE_IOM_TEI2 ((volatile u32*)(DANUBE_IOM+ 0x00A0))
+#define DANUBE_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1)
+#define DANUBE_IOM_TEI2_EA (1 << 0)
+
+/***Test Mode Register HDLC***/
+#define DANUBE_IOM_TMH ((volatile u32*)(DANUBE_IOM+ 0x00A4))
+#define DANUBE_IOM_TMH_TLP (1 << 0)
+
+/***Command/Indication Receive 0***/
+#define DANUBE_IOM_CIR0 ((volatile u32*)(DANUBE_IOM+ 0x00B8))
+#define DANUBE_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_IOM_CIR0_CIC0 (1 << 3)
+#define DANUBE_IOM_CIR0_CIC1 (1 << 2)
+#define DANUBE_IOM_CIR0_SG (1 << 1)
+#define DANUBE_IOM_CIR0_BAS (1 << 0)
+
+/***Command/Indication Transmit 0***/
+#define DANUBE_IOM_CIX0 ((volatile u32*)(DANUBE_IOM+ 0x00B8))
+#define DANUBE_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4)
+#define DANUBE_IOM_CIX0_TBA2 (1 << 3)
+#define DANUBE_IOM_CIX0_TBA1 (1 << 2)
+#define DANUBE_IOM_CIX0_TBA0 (1 << 1)
+#define DANUBE_IOM_CIX0_BAC (1 << 0)
+
+/***Command/Indication Receive 1***/
+#define DANUBE_IOM_CIR1 ((volatile u32*)(DANUBE_IOM+ 0x00BC))
+#define DANUBE_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2)
+
+/***Command/Indication Transmit 1***/
+#define DANUBE_IOM_CIX1 ((volatile u32*)(DANUBE_IOM+ 0x00BC))
+#define DANUBE_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2)
+#define DANUBE_IOM_CIX1_CICW (1 << 1)
+#define DANUBE_IOM_CIX1_CI1E (1 << 0)
+
+/***Controller Data Access Reg. (CH10)***/
+#define DANUBE_IOM_CDA10 ((volatile u32*)(DANUBE_IOM+ 0x0100))
+#define DANUBE_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Controller Data Access Reg. (CH11)***/
+#define DANUBE_IOM_CDA11 ((volatile u32*)(DANUBE_IOM+ 0x0104))
+#define DANUBE_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Controller Data Access Reg. (CH20)***/
+#define DANUBE_IOM_CDA20 ((volatile u32*)(DANUBE_IOM+ 0x0108))
+#define DANUBE_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Controller Data Access Reg. (CH21)***/
+#define DANUBE_IOM_CDA21 ((volatile u32*)(DANUBE_IOM+ 0x010C))
+#define DANUBE_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH10)***/
+#define DANUBE_IOM_CDA_TSDP10 ((volatile u32*)(DANUBE_IOM+ 0x0110))
+#define DANUBE_IOM_CDA_TSDP10_DPS (1 << 7)
+#define DANUBE_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH11)***/
+#define DANUBE_IOM_CDA_TSDP11 ((volatile u32*)(DANUBE_IOM+ 0x0114))
+#define DANUBE_IOM_CDA_TSDP11_DPS (1 << 7)
+#define DANUBE_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH20)***/
+#define DANUBE_IOM_CDA_TSDP20 ((volatile u32*)(DANUBE_IOM+ 0x0118))
+#define DANUBE_IOM_CDA_TSDP20_DPS (1 << 7)
+#define DANUBE_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH21)***/
+#define DANUBE_IOM_CDA_TSDP21 ((volatile u32*)(DANUBE_IOM+ 0x011C))
+#define DANUBE_IOM_CDA_TSDP21_DPS (1 << 7)
+#define DANUBE_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH10)***/
+#define DANUBE_IOM_CO_TSDP10 ((volatile u32*)(DANUBE_IOM+ 0x0120))
+#define DANUBE_IOM_CO_TSDP10_DPS (1 << 7)
+#define DANUBE_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH11)***/
+#define DANUBE_IOM_CO_TSDP11 ((volatile u32*)(DANUBE_IOM+ 0x0124))
+#define DANUBE_IOM_CO_TSDP11_DPS (1 << 7)
+#define DANUBE_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH20)***/
+#define DANUBE_IOM_CO_TSDP20 ((volatile u32*)(DANUBE_IOM+ 0x0128))
+#define DANUBE_IOM_CO_TSDP20_DPS (1 << 7)
+#define DANUBE_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH21)***/
+#define DANUBE_IOM_CO_TSDP21 ((volatile u32*)(DANUBE_IOM+ 0x012C))
+#define DANUBE_IOM_CO_TSDP21_DPS (1 << 7)
+#define DANUBE_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Ctrl. Reg. Contr. Data Access CH1x***/
+#define DANUBE_IOM_CDA1_CR ((volatile u32*)(DANUBE_IOM+ 0x0138))
+#define DANUBE_IOM_CDA1_CR_EN_TBM (1 << 5)
+#define DANUBE_IOM_CDA1_CR_EN_I1 (1 << 4)
+#define DANUBE_IOM_CDA1_CR_EN_I0 (1 << 3)
+#define DANUBE_IOM_CDA1_CR_EN_O1 (1 << 2)
+#define DANUBE_IOM_CDA1_CR_EN_O0 (1 << 1)
+#define DANUBE_IOM_CDA1_CR_SWAP (1 << 0)
+
+/***Ctrl. Reg. Contr. Data Access CH1x***/
+#define DANUBE_IOM_CDA2_CR ((volatile u32*)(DANUBE_IOM+ 0x013C))
+#define DANUBE_IOM_CDA2_CR_EN_TBM (1 << 5)
+#define DANUBE_IOM_CDA2_CR_EN_I1 (1 << 4)
+#define DANUBE_IOM_CDA2_CR_EN_I0 (1 << 3)
+#define DANUBE_IOM_CDA2_CR_EN_O1 (1 << 2)
+#define DANUBE_IOM_CDA2_CR_EN_O0 (1 << 1)
+#define DANUBE_IOM_CDA2_CR_SWAP (1 << 0)
+
+/***Control Register B-Channel Data***/
+#define DANUBE_IOM_BCHA_CR ((volatile u32*)(DANUBE_IOM+ 0x0144))
+#define DANUBE_IOM_BCHA_CR_EN_BC2 (1 << 4)
+#define DANUBE_IOM_BCHA_CR_EN_BC1 (1 << 3)
+
+/***Control Register B-Channel Data***/
+#define DANUBE_IOM_BCHB_CR ((volatile u32*)(DANUBE_IOM+ 0x0148))
+#define DANUBE_IOM_BCHB_CR_EN_BC2 (1 << 4)
+#define DANUBE_IOM_BCHB_CR_EN_BC1 (1 << 3)
+
+/***Control Reg. for HDLC and CI1 Data***/
+#define DANUBE_IOM_DCI_CR ((volatile u32*)(DANUBE_IOM+ 0x014C))
+#define DANUBE_IOM_DCI_CR_DPS_CI1 (1 << 7)
+#define DANUBE_IOM_DCI_CR_EN_CI1 (1 << 6)
+#define DANUBE_IOM_DCI_CR_EN_D (1 << 5)
+
+/***Control Reg. for HDLC and CI1 Data***/
+#define DANUBE_IOM_DCIC_CR ((volatile u32*)(DANUBE_IOM+ 0x014C))
+#define DANUBE_IOM_DCIC_CR_DPS_CI0 (1 << 7)
+#define DANUBE_IOM_DCIC_CR_EN_CI0 (1 << 6)
+#define DANUBE_IOM_DCIC_CR_DPS_D (1 << 5)
+
+/***Control Reg. Serial Data Strobe x***/
+#define DANUBE_IOM_SDS_CR ((volatile u32*)(DANUBE_IOM+ 0x0154))
+#define DANUBE_IOM_SDS_CR_ENS_TSS (1 << 7)
+#define DANUBE_IOM_SDS_CR_ENS_TSS_1 (1 << 6)
+#define DANUBE_IOM_SDS_CR_ENS_TSS_3 (1 << 5)
+#define DANUBE_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Control Register IOM Data***/
+#define DANUBE_IOM_IOM_CR ((volatile u32*)(DANUBE_IOM+ 0x015C))
+#define DANUBE_IOM_IOM_CR_SPU (1 << 7)
+#define DANUBE_IOM_IOM_CR_CI_CS (1 << 5)
+#define DANUBE_IOM_IOM_CR_TIC_DIS (1 << 4)
+#define DANUBE_IOM_IOM_CR_EN_BCL (1 << 3)
+#define DANUBE_IOM_IOM_CR_CLKM (1 << 2)
+#define DANUBE_IOM_IOM_CR_Res (1 << 1)
+#define DANUBE_IOM_IOM_CR_DIS_IOM (1 << 0)
+
+/***Synchronous Transfer Interrupt***/
+#define DANUBE_IOM_STI ((volatile u32*)(DANUBE_IOM+ 0x0160))
+#define DANUBE_IOM_STI_STOV21 (1 << 7)
+#define DANUBE_IOM_STI_STOV20 (1 << 6)
+#define DANUBE_IOM_STI_STOV11 (1 << 5)
+#define DANUBE_IOM_STI_STOV10 (1 << 4)
+#define DANUBE_IOM_STI_STI21 (1 << 3)
+#define DANUBE_IOM_STI_STI20 (1 << 2)
+#define DANUBE_IOM_STI_STI11 (1 << 1)
+#define DANUBE_IOM_STI_STI10 (1 << 0)
+
+/***Acknowledge Synchronous Transfer Interrupt***/
+#define DANUBE_IOM_ASTI ((volatile u32*)(DANUBE_IOM+ 0x0160))
+#define DANUBE_IOM_ASTI_ACK21 (1 << 3)
+#define DANUBE_IOM_ASTI_ACK20 (1 << 2)
+#define DANUBE_IOM_ASTI_ACK11 (1 << 1)
+#define DANUBE_IOM_ASTI_ACK10 (1 << 0)
+
+/***Mask Synchronous Transfer Interrupt***/
+#define DANUBE_IOM_MSTI ((volatile u32*)(DANUBE_IOM+ 0x0164))
+#define DANUBE_IOM_MSTI_STOV21 (1 << 7)
+#define DANUBE_IOM_MSTI_STOV20 (1 << 6)
+#define DANUBE_IOM_MSTI_STOV11 (1 << 5)
+#define DANUBE_IOM_MSTI_STOV10 (1 << 4)
+#define DANUBE_IOM_MSTI_STI21 (1 << 3)
+#define DANUBE_IOM_MSTI_STI20 (1 << 2)
+#define DANUBE_IOM_MSTI_STI11 (1 << 1)
+#define DANUBE_IOM_MSTI_STI10 (1 << 0)
+
+/***Configuration Register for Serial Data Strobes***/
+#define DANUBE_IOM_SDS_CONF ((volatile u32*)(DANUBE_IOM+ 0x0168))
+#define DANUBE_IOM_SDS_CONF_SDS_BCL (1 << 0)
+
+/***Monitoring CDA Bits***/
+#define DANUBE_IOM_MCDA ((volatile u32*)(DANUBE_IOM+ 0x016C))
+#define DANUBE_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6)
+#define DANUBE_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4)
+#define DANUBE_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2)
+#define DANUBE_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/* Module : ASC0 register address and bits */
+/***********************************************************************/
+#define DANUBE_ASC0 (KSEG1+0x1E100400)
+/***********************************************************************/
+#define DANUBE_ASC0_TBUF ((volatile u32*)(DANUBE_ASC0 + 0x0020))
+#define DANUBE_ASC0_RBUF ((volatile u32*)(DANUBE_ASC0 + 0x0024))
+#define DANUBE_ASC0_FSTAT ((volatile u32*)(DANUBE_ASC0 + 0x0048))
+#define DANUBE_ASC0_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1))
+#define DANUBE_ASC0_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24)
+#define DANUBE_ASC0_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1))
+#define DANUBE_ASC0_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16)
+#define DANUBE_ASC0_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1))
+#define DANUBE_ASC0_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8)
+#define DANUBE_ASC0_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1))
+#define DANUBE_ASC0_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0)
+
+
+/***********************************************************************/
+/* Module : ASC1 register address and bits */
+/***********************************************************************/
+
+#define DANUBE_ASC1 (KSEG1+0x1E100C00)
+ /***********************************************************************/
+
+#define DANUBE_ASC1_TBUF ((volatile u32*)(DANUBE_ASC1 + 0x0020))
+#define DANUBE_ASC1_RBUF ((volatile u32*)(DANUBE_ASC1 + 0x0024))
+#define DANUBE_ASC1_FSTAT ((volatile u32*)(DANUBE_ASC1 + 0x0048))
+#define DANUBE_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1))
+#define DANUBE_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24)
+#define DANUBE_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1))
+#define DANUBE_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16)
+#define DANUBE_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1))
+#define DANUBE_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8)
+#define DANUBE_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1))
+#define DANUBE_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/* Module : DMA register address and bits */
+/***********************************************************************/
+/***********************************************************************/
+/* Module : DMA register address and bits */
+/***********************************************************************/
+
+#define DANUBE_DMA (0xBE104100)
+/***********************************************************************/
+
+#define DANUBE_DMA_BASE DANUBE_DMA
+#define DANUBE_DMA_CLC (volatile u32*)DANUBE_DMA_BASE
+#define DANUBE_DMA_ID (volatile u32*)(DANUBE_DMA_BASE+0x08)
+#define DANUBE_DMA_CTRL (volatile u32*)(DANUBE_DMA_BASE+0x10)
+#define DANUBE_DMA_CPOLL (volatile u32*)(DANUBE_DMA_BASE+0x14)
+#define DANUBE_DMA_CS (volatile u32*)(DANUBE_DMA_BASE+0x18)
+#define DANUBE_DMA_CCTRL (volatile u32*)(DANUBE_DMA_BASE+0x1C)
+#define DANUBE_DMA_CDBA (volatile u32*)(DANUBE_DMA_BASE+0x20)
+#define DANUBE_DMA_CDLEN (volatile u32*)(DANUBE_DMA_BASE+0x24)
+#define DANUBE_DMA_CIS (volatile u32*)(DANUBE_DMA_BASE+0x28)
+#define DANUBE_DMA_CIE (volatile u32*)(DANUBE_DMA_BASE+0x2C)
+
+#define DANUBE_DMA_PS (volatile u32*)(DANUBE_DMA_BASE+0x40)
+#define DANUBE_DMA_PCTRL (volatile u32*)(DANUBE_DMA_BASE+0x44)
+
+#define DANUBE_DMA_IRNEN (volatile u32*)(DANUBE_DMA_BASE+0xf4)
+#define DANUBE_DMA_IRNCR (volatile u32*)(DANUBE_DMA_BASE+0xf8)
+#define DANUBE_DMA_IRNICR (volatile u32*)(DANUBE_DMA_BASE+0xfc)
+/***********************************************************************/
+/* Module : Debug register address and bits */
+/***********************************************************************/
+
+#define DANUBE_Debug (0xBF106000)
+/***********************************************************************/
+
+
+/***MCD Break Bus Switch Register***/
+#define DANUBE_Debug_MCD_BBS ((volatile u32*)(DANUBE_Debug+ 0x0000))
+#define DANUBE_Debug_MCD_BBS_BTP1 (1 << 19)
+#define DANUBE_Debug_MCD_BBS_BTP0 (1 << 18)
+#define DANUBE_Debug_MCD_BBS_BSP1 (1 << 17)
+#define DANUBE_Debug_MCD_BBS_BSP0 (1 << 16)
+#define DANUBE_Debug_MCD_BBS_BT5EN (1 << 15)
+#define DANUBE_Debug_MCD_BBS_BT4EN (1 << 14)
+#define DANUBE_Debug_MCD_BBS_BT5 (1 << 13)
+#define DANUBE_Debug_MCD_BBS_BT4 (1 << 12)
+#define DANUBE_Debug_MCD_BBS_BS5EN (1 << 7)
+#define DANUBE_Debug_MCD_BBS_BS4EN (1 << 6)
+#define DANUBE_Debug_MCD_BBS_BS5 (1 << 5)
+#define DANUBE_Debug_MCD_BBS_BS4 (1 << 4)
+
+/***MCD Multiplexer Control Register***/
+#define DANUBE_Debug_MCD_MCR ((volatile u32*)(DANUBE_Debug+ 0x0008))
+#define DANUBE_Debug_MCD_MCR_MUX5 (1 << 4)
+#define DANUBE_Debug_MCD_MCR_MUX4 (1 << 3)
+#define DANUBE_Debug_MCD_MCR_MUX1 (1 << 0)
+
+
+/***********************************************************************/
+/* Module : SRAM register address and bits */
+/***********************************************************************/
+
+#define DANUBE_SRAM (0xBF980000)
+/***********************************************************************/
+
+
+/***SRAM Size Register***/
+#define DANUBE_SRAM_SRAM_SIZE ((volatile u32*)(DANUBE_SRAM+ 0x0800))
+#define DANUBE_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/* Module : BIU register address and bits */
+/***********************************************************************/
+
+#define DANUBE_BIU (0xBFA80000)
+/***********************************************************************/
+
+
+/***BIU Identification Register***/
+#define DANUBE_BIU_BIU_ID ((volatile u32*)(DANUBE_BIU+ 0x0000))
+#define DANUBE_BIU_BIU_ID_ARCH (1 << 16)
+#define DANUBE_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8)
+#define DANUBE_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0)
+
+/***BIU Access Error Cause Register***/
+#define DANUBE_BIU_BIU_ERRCAUSE ((volatile u32*)(DANUBE_BIU+ 0x0100))
+#define DANUBE_BIU_BIU_ERRCAUSE_ERR (1 << 31)
+#define DANUBE_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16)
+#define DANUBE_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0)
+
+/***BIU Access Error Address Register***/
+#define DANUBE_BIU_BIU_ERRADDR ((volatile u32*)(DANUBE_BIU+ 0x0108))
+#define DANUBE_BIU_BIU_ERRADDR_ADDR
+
+
+/***********************************************************************/
+/* Module : ICU register address and bits */
+/***********************************************************************/
+
+#define DANUBE_ICU (0xBF880200)
+#define DANUBE_ICU (0xBF880200)
+#define DANUBE_ICU_EXI (0xBF101000)
+/***********************************************************************/
+
+
+/***IM0 Interrupt Status Register***/
+#define DANUBE_ICU_IM0_ISR ((volatile u32*)(DANUBE_ICU+ 0x0000))
+#define DANUBE_ICU_IM0_ISR_IR(value) (1 << (value))
+
+
+/***IM1 Interrupt Status Register***/
+#define DANUBE_ICU_IM1_ISR ((volatile u32*)(DANUBE_ICU+ 0x0020))
+#define DANUBE_ICU_IM1_ISR_IR(value) (1 << (value))
+
+
+/***IM2 Interrupt Status Register***/
+#define DANUBE_ICU_IM2_ISR ((volatile u32*)(DANUBE_ICU+ 0x0040))
+#define DANUBE_ICU_IM2_ISR_IR(value) (1 << (value))
+
+/***IM3 Interrupt Status Register***/
+#define DANUBE_ICU_IM3_ISR ((volatile u32*)(DANUBE_ICU+ 0x0060))
+#define DANUBE_ICU_IM3_ISR_IR(value) (1 << (value))
+
+/***IM4 Interrupt Status Register***/
+#define DANUBE_ICU_IM4_ISR ((volatile u32*)(DANUBE_ICU+ 0x0080))
+#define DANUBE_ICU_IM4_ISR_IR(value) (1 << (value))
+
+
+/***IM0 Interrupt Enable Register***/
+#define DANUBE_ICU_IM0_IER ((volatile u32*)(DANUBE_ICU+ 0x0008))
+#define DANUBE_ICU_IM0_IER_IR(value) (1 << (value))
+
+
+/***IM1 Interrupt Enable Register***/
+#define DANUBE_ICU_IM1_IER ((volatile u32*)(DANUBE_ICU+ 0x0028))
+#define DANUBE_ICU_IM1_IER_IR(value) (1 << (value))
+
+
+/***IM2 Interrupt Enable Register***/
+#define DANUBE_ICU_IM2_IER ((volatile u32*)(DANUBE_ICU+ 0x0048))
+#define DANUBE_ICU_IM2_IER_IR(value) (1 << (value)8
+
+/***IM3 Interrupt Enable Register***/
+#define DANUBE_ICU_IM3_IER ((volatile u32*)(DANUBE_ICU+ 0x0068))
+#define DANUBE_ICU_IM3_IER_IR(value) (1 << (value))
+
+/***IM4 Interrupt Enable Register***/
+#define DANUBE_ICU_IM4_IER ((volatile u32*)(DANUBE_ICU+ 0x0088))
+#define DANUBE_ICU_IM4_IER_IR(value) (1 << (value))
+
+
+/***IM0 Interrupt Output Status Register***/
+#define DANUBE_ICU_IM0_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0010))
+#define DANUBE_ICU_IM0_IOSR_IR(value) (1 << (value))
+
+
+/***IM1 Interrupt Output Status Register***/
+#define DANUBE_ICU_IM1_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0030))
+#define DANUBE_ICU_IM1_IOSR_IR(value) (1 << (value))
+
+
+/***IM2 Interrupt Output Status Register***/
+#define DANUBE_ICU_IM2_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0050))
+#define DANUBE_ICU_IM2_IOSR_IR(value) (1 << (value))
+
+/***IM3 Interrupt Output Status Register***/
+#define DANUBE_ICU_IM3_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0070))
+#define DANUBE_ICU_IM3_IOSR_IR(value) (1 << (value))
+
+/***IM4 Interrupt Output Status Register***/
+#define DANUBE_ICU_IM4_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0090))
+#define DANUBE_ICU_IM4_IOSR_IR(value) (1 << (value))
+
+
+/***IM0 Interrupt Request Set Register***/
+#define DANUBE_ICU_IM0_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0018))
+#define DANUBE_ICU_IM0_IRSR_IR(value) (1 << (value))
+
+
+/***IM1 Interrupt Request Set Register***/
+#define DANUBE_ICU_IM1_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0038))
+#define DANUBE_ICU_IM1_IRSR_IR(value) (1 << (value))
+
+
+/***IM2 Interrupt Request Set Register***/
+#define DANUBE_ICU_IM2_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0058))
+#define DANUBE_ICU_IM2_IRSR_IR(value) (1 << (value))
+
+/***IM3 Interrupt Request Set Register***/
+#define DANUBE_ICU_IM3_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0078))
+#define DANUBE_ICU_IM3_IRSR_IR(value) (1 << (value))
+
+/***IM4 Interrupt Request Set Register***/
+#define DANUBE_ICU_IM4_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0098))
+#define DANUBE_ICU_IM4_IRSR_IR(value) (1 << (value))
+
+/***Interrupt Vector Value Register***/
+#define DANUBE_ICU_IM_VEC ((volatile u32*)(DANUBE_ICU+ 0x0060))
+
+/***Interrupt Vector Value Mask***/
+#define DANUBE_ICU_IM0_VEC_MASK 0x0000001f
+#define DANUBE_ICU_IM1_VEC_MASK 0x000003e0
+#define DANUBE_ICU_IM2_VEC_MASK 0x00007c00
+#define DANUBE_ICU_IM3_VEC_MASK 0x000f8000
+#define DANUBE_ICU_IM4_VEC_MASK 0x01f00000
+
+/***DMA Interrupt Mask Value***/
+#define DANUBE_DMA_H_MASK 0x00000fff
+
+/***External Interrupt Control Register***/
+#define DANUBE_ICU_EXTINTCR ((volatile u32*)(DANUBE_ICU_EXI+ 0x0000))
+#define DANUBE_ICU_IRNICR ((volatile u32*)(DANUBE_ICU_EXI+ 0x0004))
+#define DANUBE_ICU_IRNCR ((volatile u32*)(DANUBE_ICU_EXI+ 0x0008))
+#define DANUBE_ICU_IRNEN ((volatile u32*)(DANUBE_ICU_EXI+ 0x000c))
+#define DANUBE_ICU_NMI_CR ((volatile u32*)(DANUBE_ICU_EXI+ 0x00f0))
+#define DANUBE_ICU_NMI_SR ((volatile u32*)(DANUBE_ICU_EXI+ 0x00f4))
+
+/***********************************************************************/
+/* Module : MPS register address and bits */
+/***********************************************************************/
+
+#define DANUBE_MPS (KSEG1+0x1F107000)
+/***********************************************************************/
+
+#define DANUBE_MPS_CHIPID ((volatile u32*)(DANUBE_MPS + 0x0344))
+#define DANUBE_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
+#define DANUBE_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
+#define DANUBE_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
+#define DANUBE_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
+#define DANUBE_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
+#define DANUBE_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1)
+
+
+/* voice channel 0 ... 3 interrupt enable register */
+#define DANUBE_MPS_VC0ENR ((volatile u32*)(DANUBE_MPS + 0x0000))
+#define DANUBE_MPS_VC1ENR ((volatile u32*)(DANUBE_MPS + 0x0004))
+#define DANUBE_MPS_VC2ENR ((volatile u32*)(DANUBE_MPS + 0x0008))
+#define DANUBE_MPS_VC3ENR ((volatile u32*)(DANUBE_MPS + 0x000C))
+/* voice channel 0 ... 3 interrupt status read register */
+#define DANUBE_MPS_RVC0SR ((volatile u32*)(DANUBE_MPS + 0x0010))
+#define DANUBE_MPS_RVC1SR ((volatile u32*)(DANUBE_MPS + 0x0014))
+#define DANUBE_MPS_RVC2SR ((volatile u32*)(DANUBE_MPS + 0x0018))
+#define DANUBE_MPS_RVC3SR ((volatile u32*)(DANUBE_MPS + 0x001C))
+/* voice channel 0 ... 3 interrupt status set register */
+#define DANUBE_MPS_SVC0SR ((volatile u32*)(DANUBE_MPS + 0x0020))
+#define DANUBE_MPS_SVC1SR ((volatile u32*)(DANUBE_MPS + 0x0024))
+#define DANUBE_MPS_SVC2SR ((volatile u32*)(DANUBE_MPS + 0x0028))
+#define DANUBE_MPS_SVC3SR ((volatile u32*)(DANUBE_MPS + 0x002C))
+/* voice channel 0 ... 3 interrupt status clear register */
+#define DANUBE_MPS_CVC0SR ((volatile u32*)(DANUBE_MPS + 0x0030))
+#define DANUBE_MPS_CVC1SR ((volatile u32*)(DANUBE_MPS + 0x0034))
+#define DANUBE_MPS_CVC2SR ((volatile u32*)(DANUBE_MPS + 0x0038))
+#define DANUBE_MPS_CVC3SR ((volatile u32*)(DANUBE_MPS + 0x003C))
+/* common status 0 and 1 read register */
+#define DANUBE_MPS_RAD0SR ((volatile u32*)(DANUBE_MPS + 0x0040))
+#define DANUBE_MPS_RAD1SR ((volatile u32*)(DANUBE_MPS + 0x0044))
+/* common status 0 and 1 set register */
+#define DANUBE_MPS_SAD0SR ((volatile u32*)(DANUBE_MPS + 0x0048))
+#define DANUBE_MPS_SAD1SR ((volatile u32*)(DANUBE_MPS + 0x004C))
+/* common status 0 and 1 clear register */
+#define DANUBE_MPS_CAD0SR ((volatile u32*)(DANUBE_MPS + 0x0050))
+#define DANUBE_MPS_CAD1SR ((volatile u32*)(DANUBE_MPS + 0x0054))
+/* common status 0 and 1 enable register */
+#define DANUBE_MPS_AD0ENR ((volatile u32*)(DANUBE_MPS + 0x0058))
+#define DANUBE_MPS_AD1ENR ((volatile u32*)(DANUBE_MPS + 0x005C))
+/* notification enable register */
+#define DANUBE_MPS_CPU0_NFER ((volatile u32*)(DANUBE_MPS + 0x0060))
+#define DANUBE_MPS_CPU1_NFER ((volatile u32*)(DANUBE_MPS + 0x0064))
+/* CPU to CPU interrup request register */
+#define DANUBE_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(DANUBE_MPS + 0x0070))
+#define DANUBE_MPS_CPU0_2_CPU1_IER ((volatile u32*)(DANUBE_MPS + 0x0074))
+/* Global interrupt request and request enable register */
+#define DANUBE_MPS_GIRR ((volatile u32*)(DANUBE_MPS + 0x0078))
+#define DANUBE_MPS_GIER ((volatile u32*)(DANUBE_MPS + 0x007C))
+
+
+#define DANUBE_MPS_CPU0_SMP0 ((volatile u32*)(DANUBE_MPS + 0x00100))
+
+#define DANUBE_MPS_CPU1_SMP0 ((volatile u32*)(DANUBE_MPS + 0x00200))
+
+/************************************************************************/
+/* Module : DEU register address and bits */
+/************************************************************************/
+#define DANUBE_DEU_BASE_ADDR (0xBE102000)
+/* DEU Control Register */
+#define DANUBE_DEU_CLK ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0000))
+#define DANUBE_DEU_ID ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0008))
+
+/* DEU control register */
+#define DANUBE_DEU_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0010))
+#define DANUBE_DEU_IHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0014))
+#define DANUBE_DEU_ILR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0018))
+#define DANUBE_DEU_K1HR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x001C))
+#define DANUBE_DEU_K1LR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0020))
+#define DANUBE_DEU_K3HR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0024))
+#define DANUBE_DEU_K3LR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0028))
+#define DANUBE_DEU_IVHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x002C))
+#define DANUBE_DEU_IVLR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0030))
+#define DANUBE_DEU_OHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0040))
+#define DANUBE_DEU_OLR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0050))
+
+/* AES DEU register */
+#define DANUBE_AES_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0050))
+#define DANUBE_AES_ID3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0054))
+#define DANUBE_AES_ID2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0058))
+#define DANUBE_AES_ID1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x005C))
+#define DANUBE_AES_ID0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0060))
+
+/* AES Key register */
+#define DANUBE_AES_K7R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0064))
+#define DANUBE_AES_K6R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0068))
+#define DANUBE_AES_K5R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x006C))
+#define DANUBE_AES_K4R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0070))
+#define DANUBE_AES_K3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0074))
+#define DANUBE_AES_K2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0078))
+#define DANUBE_AES_K1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x007C))
+#define DANUBE_AES_K0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0080))
+
+/* AES vector register */
+#define DANUBE_AES_IV3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0084))
+#define DANUBE_AES_IV2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0088))
+#define DANUBE_AES_IV1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x008C))
+#define DANUBE_AES_IV0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0090))
+#define DANUBE_AES_0D3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0094))
+#define DANUBE_AES_0D2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0098))
+#define DANUBE_AES_OD1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x009C))
+#define DANUBE_AES_OD0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00A0))
+
+/* hash control registe */
+#define DANUBE_HASH_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B0))
+#define DANUBE_HASH_MR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B4))
+#define DANUBE_HASH_D1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B8 ))
+#define DANUBE_HASH_D2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00BC ))
+#define DANUBE_HASH_D3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C0 ))
+#define DANUBE_HASH_D4R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C4))
+#define DANUBE_HASH_D5R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C8))
+
+#define DANUBE_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00EC))
+
+
+
+
+/************************************************************************/
+/* Module : PPE register address and bits */
+/************************************************************************/
+#define DANUBE_PPE_BASE_ADDR (KSEG1 + 0x1E180000)
+#define DANUBE_PPE_PP32_DEBUG_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0000) << 2)))
+#define DANUBE_PPE_PPM_INT_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0030) << 2)))
+#define DANUBE_PPE_PP32_INTERNAL_RES_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0040) << 2)))
+#define DANUBE_PPE_PPE_CLOCK_CONTROL_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0100) << 2)))
+#define DANUBE_PPE_CDM_CODE_MEMORY_RAM0_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x1000) << 2)))
+#define DANUBE_PPE_CDM_CODE_MEMORY_RAM1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x2000) << 2)))
+#define DANUBE_PPE_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x4000) << 2)))
+#define DANUBE_PPE_PP32_DATA_MEMORY_RAM1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x5000) << 2)))
+#define DANUBE_PPE_PPM_INT_UNIT_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6000) << 2)))
+#define DANUBE_PPE_PPM_TIMER0_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6100) << 2)))
+#define DANUBE_PPE_PPM_TASK_IND_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6200) << 2)))
+#define DANUBE_PPE_PPS_BRK_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6300) << 2)))
+#define DANUBE_PPE_PPM_TIMER1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6400) << 2)))
+#define DANUBE_PPE_SB_RAM0_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x8000) << 2)))
+#define DANUBE_PPE_SB_RAM1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x8400) << 2)))
+#define DANUBE_PPE_SB_RAM2_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x8C00) << 2)))
+#define DANUBE_PPE_SB_RAM3_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x9600) << 2)))
+
+#define DANUBE_PPE_PP32_SLEEP DANUBE_PPE_REG_ADDR(0x0010) /* PP32 Power Saving Register */
+#define DANUBE_PPE_CDM_CFG DANUBE_PPE_REG_ADDR(0x0100) /* Code/Data Memory (CDM) Register */
+
+/* Mailbox Registers */
+#define DANUBE_PPE_MBOX_IGU0_ISRS DANUBE_PPE_REG_ADDR(0x0200)
+#define DANUBE_PPE_MBOX_IGU0_ISRC DANUBE_PPE_REG_ADDR(0x0201)
+#define DANUBE_PPE_MBOX_IGU0_ISR DANUBE_PPE_REG_ADDR(0x0202)
+#define DANUBE_PPE_MBOX_IGU0_IER DANUBE_PPE_REG_ADDR(0x0203)
+#define DANUBE_PPE_MBOX_IGU1_ISRS0 DANUBE_PPE_REG_ADDR(0x0204)
+#define DANUBE_PPE_MBOX_IGU1_ISRC0 DANUBE_PPE_REG_ADDR(0x0205)
+#define DANUBE_PPE_MBOX_IGU1_ISR0 DANUBE_PPE_REG_ADDR(0x0206)
+#define DANUBE_PPE_MBOX_IGU1_IER0 DANUBE_PPE_REG_ADDR(0x0207)
+#define DANUBE_PPE_MBOX_IGU1_ISRS1 DANUBE_PPE_REG_ADDR(0x0208)
+#define DANUBE_PPE_MBOX_IGU1_ISRC1 DANUBE_PPE_REG_ADDR(0x0209)
+#define DANUBE_PPE_MBOX_IGU1_ISR1 DANUBE_PPE_REG_ADDR(0x020A)
+#define DANUBE_PPE_MBOX_IGU1_IER1 DANUBE_PPE_REG_ADDR(0x020B)
+#define DANUBE_PPE_MBOX_IGU1_ISRS2 DANUBE_PPE_REG_ADDR(0x020C)
+#define DANUBE_PPE_MBOX_IGU1_ISRC2 DANUBE_PPE_REG_ADDR(0x020D)
+#define DANUBE_PPE_MBOX_IGU1_ISR2 DANUBE_PPE_REG_ADDR(0x020E)
+#define DANUBE_PPE_MBOX_IGU1_IER2 DANUBE_PPE_REG_ADDR(0x020F)
+#define DANUBE_PPE_MBOX_IGU2_ISRS DANUBE_PPE_REG_ADDR(0x0210)
+#define DANUBE_PPE_MBOX_IGU2_ISRC DANUBE_PPE_REG_ADDR(0x0211)
+#define DANUBE_PPE_MBOX_IGU2_ISR DANUBE_PPE_REG_ADDR(0x0212)
+#define DANUBE_PPE_MBOX_IGU2_IER DANUBE_PPE_REG_ADDR(0x0213)
+#define DANUBE_PPE_MBOX_IGU3_ISRS DANUBE_PPE_REG_ADDR(0x0214)
+#define DANUBE_PPE_MBOX_IGU3_ISRC DANUBE_PPE_REG_ADDR(0x0215)
+#define DANUBE_PPE_MBOX_IGU3_ISR DANUBE_PPE_REG_ADDR(0x0216)
+#define DANUBE_PPE_MBOX_IGU3_IER DANUBE_PPE_REG_ADDR(0x0217)
+#define DANUBE_PPE_MBOX_IGU4_ISRS DANUBE_PPE_REG_ADDR(0x0218)
+#define DANUBE_PPE_MBOX_IGU4_ISRC DANUBE_PPE_REG_ADDR(0x0219)
+#define DANUBE_PPE_MBOX_IGU4_ISR DANUBE_PPE_REG_ADDR(0x021A)
+#define DANUBE_PPE_MBOX_IGU4_IER DANUBE_PPE_REG_ADDR(0x021B)
+/*
+ * Shared Buffer (SB) Registers
+ */
+#define DANUBE_PPE_SB_MST_PRI0 DANUBE_PPE_REG_ADDR(0x0300)
+#define DANUBE_PPE_SB_MST_PRI1 DANUBE_PPE_REG_ADDR(0x0301)
+#define DANUBE_PPE_SB_MST_PRI2 DANUBE_PPE_REG_ADDR(0x0302)
+#define DANUBE_PPE_SB_MST_PRI3 DANUBE_PPE_REG_ADDR(0x0303)
+#define DANUBE_PPE_SB_MST_PRI4 DANUBE_PPE_REG_ADDR(0x0304)
+#define DANUBE_PPE_SB_MST_SEL DANUBE_PPE_REG_ADDR(0x0305)
+/*
+ * RTHA Registers
+ */
+#define DANUBE_PPE_RFBI_CFG DANUBE_PPE_REG_ADDR(0x0400)
+#define DANUBE_PPE_RBA_CFG0 DANUBE_PPE_REG_ADDR(0x0404)
+#define DANUBE_PPE_RBA_CFG1 DANUBE_PPE_REG_ADDR(0x0405)
+#define DANUBE_PPE_RCA_CFG0 DANUBE_PPE_REG_ADDR(0x0408)
+#define DANUBE_PPE_RCA_CFG1 DANUBE_PPE_REG_ADDR(0x0409)
+#define DANUBE_PPE_RDES_CFG0 DANUBE_PPE_REG_ADDR(0x040C)
+#define DANUBE_PPE_RDES_CFG1 DANUBE_PPE_REG_ADDR(0x040D)
+#define DANUBE_PPE_SFSM_STATE0 DANUBE_PPE_REG_ADDR(0x0410)
+#define DANUBE_PPE_SFSM_STATE1 DANUBE_PPE_REG_ADDR(0x0411)
+#define DANUBE_PPE_SFSM_DBA0 DANUBE_PPE_REG_ADDR(0x0412)
+#define DANUBE_PPE_SFSM_DBA1 DANUBE_PPE_REG_ADDR(0x0413)
+#define DANUBE_PPE_SFSM_CBA0 DANUBE_PPE_REG_ADDR(0x0414)
+#define DANUBE_PPE_SFSM_CBA1 DANUBE_PPE_REG_ADDR(0x0415)
+#define DANUBE_PPE_SFSM_CFG0 DANUBE_PPE_REG_ADDR(0x0416)
+#define DANUBE_PPE_SFSM_CFG1 DANUBE_PPE_REG_ADDR(0x0417)
+#define DANUBE_PPE_SFSM_PGCNT0 DANUBE_PPE_REG_ADDR(0x041C)
+#define DANUBE_PPE_SFSM_PGCNT1 DANUBE_PPE_REG_ADDR(0x041D)
+/*
+ * TTHA Registers
+ */
+#define DANUBE_PPE_FFSM_DBA0 DANUBE_PPE_REG_ADDR(0x0508)
+#define DANUBE_PPE_FFSM_DBA1 DANUBE_PPE_REG_ADDR(0x0509)
+#define DANUBE_PPE_FFSM_CFG0 DANUBE_PPE_REG_ADDR(0x050A)
+#define DANUBE_PPE_FFSM_CFG1 DANUBE_PPE_REG_ADDR(0x050B)
+#define DANUBE_PPE_FFSM_IDLE_HEAD_BC0 DANUBE_PPE_REG_ADDR(0x050E)
+#define DANUBE_PPE_FFSM_IDLE_HEAD_BC1 DANUBE_PPE_REG_ADDR(0x050F)
+#define DANUBE_PPE_FFSM_PGCNT0 DANUBE_PPE_REG_ADDR(0x0514)
+#define DANUBE_PPE_FFSM_PGCNT1 DANUBE_PPE_REG_ADDR(0x0515)
+/*
+ * ETOP MDIO Registers
+ */
+#define DANUBE_PPE_ETOP_MDIO_CFG DANUBE_PPE_REG_ADDR(0x0600)
+#define DANUBE_PPE_ETOP_MDIO_ACC DANUBE_PPE_REG_ADDR(0x0601)
+#define DANUBE_PPE_ETOP_CFG DANUBE_PPE_REG_ADDR(0x0602)
+#define DANUBE_PPE_ETOP_IG_VLAN_COS DANUBE_PPE_REG_ADDR(0x0603)
+#define DANUBE_PPE_ETOP_IG_DSCP_COS3 DANUBE_PPE_REG_ADDR(0x0604)
+#define DANUBE_PPE_ETOP_IG_DSCP_COS2 DANUBE_PPE_REG_ADDR(0x0605)
+#define DANUBE_PPE_ETOP_IG_DSCP_COS1 DANUBE_PPE_REG_ADDR(0x0606)
+#define DANUBE_PPE_ETOP_IG_DSCP_COS0 DANUBE_PPE_REG_ADDR(0x0607)
+#define DANUBE_PPE_ETOP_IG_PLEN_CTRL0 DANUBE_PPE_REG_ADDR(0x0608)
+#define DANUBE_PPE_ETOP_IG_PLEN_CTRL1 DANUBE_PPE_REG_ADDR(0x0609)
+#define DANUBE_PPE_ETOP_ISR DANUBE_PPE_REG_ADDR(0x060A)
+#define DANUBE_PPE_ETOP_IER DANUBE_PPE_REG_ADDR(0x060B)
+#define DANUBE_PPE_ETOP_VPID DANUBE_PPE_REG_ADDR(0x060C)
+#define DANUBE_PPE_ENET_MAC_CFG DANUBE_PPE_REG_ADDR(0x0610)
+#define DANUBE_PPE_ENETS_DBA DANUBE_PPE_REG_ADDR(0x0612)
+#define DANUBE_PPE_ENETS_CBA DANUBE_PPE_REG_ADDR(0x0613)
+#define DANUBE_PPE_ENETS_CFG DANUBE_PPE_REG_ADDR(0x0614)
+#define DANUBE_PPE_ENETS_PGCNT DANUBE_PPE_REG_ADDR(0x0615)
+#define DANUBE_PPE_ENETS_PGCNT_DSRC_PP32 (0x00020000)
+#define DANUBE_PPE_ENETS_PGCNT_DVAL_SHIFT (9)
+#define DANUBE_PPE_ENETS_PGCNT_DCMD (0x00000100)
+#define DANUBE_PPE_ENETS_PKTCNT DANUBE_PPE_REG_ADDR(0x0616)
+#define DANUBE_PPE_ENETS_PKTCNT_DSRC_PP32 (0x00000200)
+#define DANUBE_PPE_ENETS_PKTCNT_DCMD (0x00000100)
+#define DANUBE_PPE_ENETS_PKTCNT_UPKT (0x000000FF)
+#define DANUBE_PPE_ENETS_BUF_CTRL DANUBE_PPE_REG_ADDR(0x0617)
+#define DANUBE_PPE_ENETS_COS_CFG DANUBE_PPE_REG_ADDR(0x0618)
+#define DANUBE_PPE_ENETS_IGDROP DANUBE_PPE_REG_ADDR(0x0619)
+#define DANUBE_PPE_ENETF_DBA DANUBE_PPE_REG_ADDR(0x0630)
+#define DANUBE_PPE_ENETF_CBA DANUBE_PPE_REG_ADDR(0x0631)
+#define DANUBE_PPE_ENETF_CFG DANUBE_PPE_REG_ADDR(0x0632)
+#define DANUBE_PPE_ENETF_PGCNT DANUBE_PPE_REG_ADDR(0x0633)
+#define DANUBE_PPE_ENETF_PGCNT_ISRC_PP32 (0x00020000)
+#define DANUBE_PPE_ENETF_PGCNT_IVAL_SHIFT (9)
+#define DANUBE_PPE_ENETF_PGCNT_ICMD (0x00000100)
+#define DANUBE_PPE_ENETF_PKTCNT DANUBE_PPE_REG_ADDR(0x0634)
+#define DANUBE_PPE_ENETF_PKTCNT_ISRC_PP32 (0x00000200)
+#define DANUBE_PPE_ENETF_PKTCNT_ICMD (0x00000100)
+#define DANUBE_PPE_ENETF_PKTCNT_VPKT (0x000000FF)
+#define DANUBE_PPE_ENETF_HFCTRL DANUBE_PPE_REG_ADDR(0x0635)
+#define DANUBE_PPE_ENETF_TXCTRL DANUBE_PPE_REG_ADDR(0x0636)
+#define DANUBE_PPE_ENETF_VLCOS0 DANUBE_PPE_REG_ADDR(0x0638)
+#define DANUBE_PPE_ENETF_VLCOS1 DANUBE_PPE_REG_ADDR(0x0639)
+#define DANUBE_PPE_ENETF_VLCOS2 DANUBE_PPE_REG_ADDR(0x063A)
+#define DANUBE_PPE_ENETF_VLCOS3 DANUBE_PPE_REG_ADDR(0x063B)
+#define DANUBE_PPE_ENETF_EGERR DANUBE_PPE_REG_ADDR(0x063C)
+#define DANUBE_PPE_ENETF_EGDROP DANUBE_PPE_REG_ADDR(0x063D)
+/*
+ * DPLUS Registers
+ */
+#define DANUBE_PPE_DPLUS_TXDB DANUBE_PPE_REG_ADDR(0x0700)
+#define DANUBE_PPE_DPLUS_TXCB DANUBE_PPE_REG_ADDR(0x0701)
+#define DANUBE_PPE_DPLUS_TXCFG DANUBE_PPE_REG_ADDR(0x0702)
+#define DANUBE_PPE_DPLUS_TXPGCNT DANUBE_PPE_REG_ADDR(0x0703)
+#define DANUBE_PPE_DPLUS_RXDB DANUBE_PPE_REG_ADDR(0x0710)
+#define DANUBE_PPE_DPLUS_RXCB DANUBE_PPE_REG_ADDR(0x0711)
+#define DANUBE_PPE_DPLUS_RXCFG DANUBE_PPE_REG_ADDR(0x0712)
+#define DANUBE_PPE_DPLUS_RXPGCNT DANUBE_PPE_REG_ADDR(0x0713)
+/*
+ * BMC Registers
+ */
+#define DANUBE_PPE_BMC_CMD3 DANUBE_PPE_REG_ADDR(0x0800)
+#define DANUBE_PPE_BMC_CMD2 DANUBE_PPE_REG_ADDR(0x0801)
+#define DANUBE_PPE_BMC_CMD1 DANUBE_PPE_REG_ADDR(0x0802)
+#define DANUBE_PPE_BMC_CMD0 DANUBE_PPE_REG_ADDR(0x0803)
+#define DANUBE_PPE_BMC_CFG0 DANUBE_PPE_REG_ADDR(0x0804)
+#define DANUBE_PPE_BMC_CFG1 DANUBE_PPE_REG_ADDR(0x0805)
+#define DANUBE_PPE_BMC_POLY0 DANUBE_PPE_REG_ADDR(0x0806)
+#define DANUBE_PPE_BMC_POLY1 DANUBE_PPE_REG_ADDR(0x0807)
+#define DANUBE_PPE_BMC_CRC0 DANUBE_PPE_REG_ADDR(0x0808)
+#define DANUBE_PPE_BMC_CRC1 DANUBE_PPE_REG_ADDR(0x0809)
+/*
+ * SLL Registers
+ */
+#define DANUBE_PPE_SLL_CMD1 DANUBE_PPE_REG_ADDR(0x0900)
+#define DANUBE_PPE_SLL_CMD0 DANUBE_PPE_REG_ADDR(0x0901)
+#define DANUBE_PPE_SLL_KEY0 DANUBE_PPE_REG_ADDR(0x0910)
+#define DANUBE_PPE_SLL_KEY1 DANUBE_PPE_REG_ADDR(0x0911)
+#define DANUBE_PPE_SLL_KEY2 DANUBE_PPE_REG_ADDR(0x0912)
+#define DANUBE_PPE_SLL_KEY3 DANUBE_PPE_REG_ADDR(0x0913)
+#define DANUBE_PPE_SLL_KEY4 DANUBE_PPE_REG_ADDR(0x0914)
+#define DANUBE_PPE_SLL_KEY5 DANUBE_PPE_REG_ADDR(0x0915)
+#define DANUBE_PPE_SLL_RESULT DANUBE_PPE_REG_ADDR(0x0920)
+/*
+ * EMA Registers
+ */
+#define DANUBE_PPE_EMA_CMD2 DANUBE_PPE_REG_ADDR(0x0A00)
+#define DANUBE_PPE_EMA_CMD1 DANUBE_PPE_REG_ADDR(0x0A01)
+#define DANUBE_PPE_EMA_CMD0 DANUBE_PPE_REG_ADDR(0x0A02)
+#define DANUBE_PPE_EMA_ISR DANUBE_PPE_REG_ADDR(0x0A04)
+#define DANUBE_PPE_EMA_IER DANUBE_PPE_REG_ADDR(0x0A05)
+#define DANUBE_PPE_EMA_CFG DANUBE_PPE_REG_ADDR(0x0A06)
+/*
+ * UTPS Registers
+ */
+#define DANUBE_PPE_UTP_TXCA0 DANUBE_PPE_REG_ADDR(0x0B00)
+#define DANUBE_PPE_UTP_TXNA0 DANUBE_PPE_REG_ADDR(0x0B01)
+#define DANUBE_PPE_UTP_TXCA1 DANUBE_PPE_REG_ADDR(0x0B02)
+#define DANUBE_PPE_UTP_TXNA1 DANUBE_PPE_REG_ADDR(0x0B03)
+#define DANUBE_PPE_UTP_RXCA0 DANUBE_PPE_REG_ADDR(0x0B10)
+#define DANUBE_PPE_UTP_RXNA0 DANUBE_PPE_REG_ADDR(0x0B11)
+#define DANUBE_PPE_UTP_RXCA1 DANUBE_PPE_REG_ADDR(0x0B12)
+#define DANUBE_PPE_UTP_RXNA1 DANUBE_PPE_REG_ADDR(0x0B13)
+#define DANUBE_PPE_UTP_CFG DANUBE_PPE_REG_ADDR(0x0B20)
+#define DANUBE_PPE_UTP_ISR DANUBE_PPE_REG_ADDR(0x0B30)
+#define DANUBE_PPE_UTP_IER DANUBE_PPE_REG_ADDR(0x0B31)
+/*
+ * QSB Registers
+ */
+#define DANUBE_PPE_QSB_RELOG DANUBE_PPE_REG_ADDR(0x0C00)
+#define DANUBE_PPE_QSB_EMIT0 DANUBE_PPE_REG_ADDR(0x0C01)
+#define DANUBE_PPE_QSB_EMIT1 DANUBE_PPE_REG_ADDR(0x0C02)
+#define DANUBE_PPE_QSB_ICDV DANUBE_PPE_REG_ADDR(0x0C07)
+#define DANUBE_PPE_QSB_SBL DANUBE_PPE_REG_ADDR(0x0C09)
+#define DANUBE_PPE_QSB_CFG DANUBE_PPE_REG_ADDR(0x0C0A)
+#define DANUBE_PPE_QSB_RTM DANUBE_PPE_REG_ADDR(0x0C0B)
+#define DANUBE_PPE_QSB_RTD DANUBE_PPE_REG_ADDR(0x0C0C)
+#define DANUBE_PPE_QSB_RAMAC DANUBE_PPE_REG_ADDR(0x0C0D)
+#define DANUBE_PPE_QSB_ISTAT DANUBE_PPE_REG_ADDR(0x0C0E)
+#define DANUBE_PPE_QSB_IMR DANUBE_PPE_REG_ADDR(0x0C0F)
+#define DANUBE_PPE_QSB_SRC DANUBE_PPE_REG_ADDR(0x0C10)
+/*
+ * DSP User Registers
+ */
+#define DANUBE_PPE_DREG_A_VERSION DANUBE_PPE_REG_ADDR(0x0D00)
+#define DANUBE_PPE_DREG_A_CFG DANUBE_PPE_REG_ADDR(0x0D01)
+#define DANUBE_PPE_DREG_AT_CTRL DANUBE_PPE_REG_ADDR(0x0D02)
+#define DANUBE_PPE_DREG_AR_CTRL DANUBE_PPE_REG_ADDR(0x0D08)
+#define DANUBE_PPE_DREG_A_UTPCFG DANUBE_PPE_REG_ADDR(0x0D0E)
+#define DANUBE_PPE_DREG_A_STATUS DANUBE_PPE_REG_ADDR(0x0D0F)
+#define DANUBE_PPE_DREG_AT_CFG0 DANUBE_PPE_REG_ADDR(0x0D20)
+#define DANUBE_PPE_DREG_AT_CFG1 DANUBE_PPE_REG_ADDR(0x0D21)
+#define DANUBE_PPE_DREG_FB_SIZE0 DANUBE_PPE_REG_ADDR(0x0D22)
+#define DANUBE_PPE_DREG_FB_SIZE1 DANUBE_PPE_REG_ADDR(0x0D23)
+#define DANUBE_PPE_DREG_AT_CELL0 DANUBE_PPE_REG_ADDR(0x0D24)
+#define DANUBE_PPE_DREG_AT_CELL1 DANUBE_PPE_REG_ADDR(0x0D25)
+#define DANUBE_PPE_DREG_AT_IDLE_CNT0 DANUBE_PPE_REG_ADDR(0x0D26)
+#define DANUBE_PPE_DREG_AT_IDLE_CNT1 DANUBE_PPE_REG_ADDR(0x0D27)
+#define DANUBE_PPE_DREG_AT_IDLE0 DANUBE_PPE_REG_ADDR(0x0D28)
+#define DANUBE_PPE_DREG_AT_IDLE1 DANUBE_PPE_REG_ADDR(0x0D29)
+#define DANUBE_PPE_DREG_AR_CFG0 DANUBE_PPE_REG_ADDR(0x0D60)
+#define DANUBE_PPE_DREG_AR_CFG1 DANUBE_PPE_REG_ADDR(0x0D61)
+#define DANUBE_PPE_DREG_AR_FB_START0 DANUBE_PPE_REG_ADDR(0x0D62)
+#define DANUBE_PPE_DREG_AR_FB_START1 DANUBE_PPE_REG_ADDR(0x0D63)
+#define DANUBE_PPE_DREG_AR_FB_END0 DANUBE_PPE_REG_ADDR(0x0D64)
+#define DANUBE_PPE_DREG_AR_FB_END1 DANUBE_PPE_REG_ADDR(0x0D65)
+#define DANUBE_PPE_DREG_AR_ATM_STAT0 DANUBE_PPE_REG_ADDR(0x0D66)
+#define DANUBE_PPE_DREG_AR_ATM_STAT1 DANUBE_PPE_REG_ADDR(0x0D67)
+#define DANUBE_PPE_DREG_AR_CELL0 DANUBE_PPE_REG_ADDR(0x0D68)
+#define DANUBE_PPE_DREG_AR_CELL1 DANUBE_PPE_REG_ADDR(0x0D69)
+#define DANUBE_PPE_DREG_AR_IDLE_CNT0 DANUBE_PPE_REG_ADDR(0x0D6A)
+#define DANUBE_PPE_DREG_AR_IDLE_CNT1 DANUBE_PPE_REG_ADDR(0x0D6B)
+#define DANUBE_PPE_DREG_AR_AIIDLE_CNT0 DANUBE_PPE_REG_ADDR(0x0D6C)
+#define DANUBE_PPE_DREG_AR_AIIDLE_CNT1 DANUBE_PPE_REG_ADDR(0x0D6D)
+#define DANUBE_PPE_DREG_AR_BE_CNT0 DANUBE_PPE_REG_ADDR(0x0D6E)
+#define DANUBE_PPE_DREG_AR_BE_CNT1 DANUBE_PPE_REG_ADDR(0x0D6F)
+#define DANUBE_PPE_DREG_AR_HEC_CNT0 DANUBE_PPE_REG_ADDR(0x0D70)
+#define DANUBE_PPE_DREG_AR_HEC_CNT1 DANUBE_PPE_REG_ADDR(0x0D71)
+#define DANUBE_PPE_DREG_AR_CD_CNT0 DANUBE_PPE_REG_ADDR(0x0D72)
+#define DANUBE_PPE_DREG_AR_CD_CNT1 DANUBE_PPE_REG_ADDR(0x0D73)
+#define DANUBE_PPE_DREG_AR_IDLE0 DANUBE_PPE_REG_ADDR(0x0D74)
+#define DANUBE_PPE_DREG_AR_IDLE1 DANUBE_PPE_REG_ADDR(0x0D75)
+#define DANUBE_PPE_DREG_AR_DELIN0 DANUBE_PPE_REG_ADDR(0x0D76)
+#define DANUBE_PPE_DREG_AR_DELIN1 DANUBE_PPE_REG_ADDR(0x0D77)
+#define DANUBE_PPE_DREG_RESV0 DANUBE_PPE_REG_ADDR(0x0D78)
+#define DANUBE_PPE_DREG_RESV1 DANUBE_PPE_REG_ADDR(0x0D79)
+#define DANUBE_PPE_DREG_RX_MIB_CMD0 DANUBE_PPE_REG_ADDR(0x0D80)
+#define DANUBE_PPE_DREG_RX_MIB_CMD1 DANUBE_PPE_REG_ADDR(0x0D81)
+#define DANUBE_PPE_DREG_AR_OVDROP_CNT0 DANUBE_PPE_REG_ADDR(0x0D98)
+#define DANUBE_PPE_DREG_AR_OVDROP_CNT1 DANUBE_PPE_REG_ADDR(0x0D99)
+
+
+/************************************************************************/
+/* Module : PPE register address and bits */
+/************************************************************************/
+#define DANUBE_PPE32_BASE 0xBE180000
+#define DANUBE_PPE32_DEBUG_BREAK_TRACE_REG (DANUBE_PPE32_BASE + (0x0000 * 4))
+#define DANUBE_PPE32_INT_MASK_STATUS_REG (DANUBE_PPE32_BASE + (0x0030 * 4))
+#define DANUBE_PPE32_INT_RESOURCE_REG (DANUBE_PPE32_BASE + (0x0040 * 4))
+#define DANUBE_PPE32_CDM_CODE_MEM_B0 (DANUBE_PPE32_BASE + (0x1000 * 4))
+#define DANUBE_PPE32_CDM_CODE_MEM_B1 (DANUBE_PPE32_BASE + (0x2000 * 4))
+#define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4))
+
+/************************************************************************/
+/* Module : PPE register address and bits */
+/************************************************************************/
+#define DANUBE_PPE32_BASE 0xBE180000
+#define DANUBE_PPE32_DEBUG_BREAK_TRACE_REG (DANUBE_PPE32_BASE + (0x0000 * 4))
+#define DANUBE_PPE32_INT_MASK_STATUS_REG (DANUBE_PPE32_BASE + (0x0030 * 4))
+#define DANUBE_PPE32_INT_RESOURCE_REG (DANUBE_PPE32_BASE + (0x0040 * 4))
+#define DANUBE_PPE32_CDM_CODE_MEM_B0 (DANUBE_PPE32_BASE + (0x1000 * 4))
+#define DANUBE_PPE32_CDM_CODE_MEM_B1 (DANUBE_PPE32_BASE + (0x2000 * 4))
+#define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4))
+
+/*
+ * ETOP MDIO Registers
+ */
+#define ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4)))
+#define ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4)))
+#define ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4)))
+#define ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4)))
+#define ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4)))
+#define ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4)))
+#define ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4)))
+#define ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4)))
+#define ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4)))
+#define ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4)))
+#define ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4)))
+#define ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4)))
+#define ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
+#define ENETS_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4)))
+#define ENETS_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4)))
+#define ENETS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4)))
+#define ENETS_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4)))
+#define ENETS_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4)))
+#define ENETS_BUF_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4)))
+#define ENETS_COS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
+#define ENETS_IGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
+#define ENETS_IGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4)))
+#define ENET_MAC_DA0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4)))
+#define ENET_MAC_DA1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4)))
+
+#define ENETF_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4)))
+#define ENETF_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4)))
+#define ENETF_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4)))
+#define ENETF_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4)))
+#define ENETF_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4)))
+#define ENETF_HFCTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4)))
+#define ENETF_TXCTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4)))
+
+#define ENETF_VLCOS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4)))
+#define ENETF_VLCOS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4)))
+#define ENETF_VLCOS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4)))
+#define ENETF_VLCOS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4)))
+#define ENETF_EGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4)))
+#define ENETF_EGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4)))
+
+
+/*
+ * ETOP MDIO Registers
+ */
+#define DANUBE_PPE32_ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4)))
+#define DANUBE_PPE32_ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4)))
+#define DANUBE_PPE32_ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4)))
+#define DANUBE_PPE32_ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4)))
+#define DANUBE_PPE32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4)))
+#define DANUBE_PPE32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4)))
+#define DANUBE_PPE32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4)))
+#define DANUBE_PPE32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4)))
+#define DANUBE_PPE32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4)))
+#define DANUBE_PPE32_ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4)))
+#define DANUBE_PPE32_ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4)))
+#define DANUBE_PPE32_ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4)))
+
+
+/* ENET Register */
+#define DANUBE_PPE32_ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4)))
+#define DANUBE_PPE32_ENET_IG_PKTDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4)))
+#define DANUBE_PPE32_ENET_CoS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4)))
+
+/*********LED register definition****************/
+
+#define DANUBE_LED 0xBE100BB0
+#define DANUBE_LED_CON0 ((volatile u32*)(DANUBE_LED + 0x0000))
+#define DANUBE_LED_CON1 ((volatile u32*)(DANUBE_LED + 0x0004))
+#define DANUBE_LED_CPU0 ((volatile u32*)(DANUBE_LED + 0x0008))
+#define DANUBE_LED_CPU1 ((volatile u32*)(DANUBE_LED + 0x000C))
+#define DANUBE_LED_AR ((volatile u32*)(DANUBE_LED + 0x0010))
+
+
+
+
+/***********************************************************************/
+#define DANUBE_REG32(addr) *((volatile u32 *)(addr))
+/***********************************************************************/
+#endif //DANUBE_H
--- /dev/null
+#ifndef _ARM_ERRNO_H
+#define _ARM_ERRNO_H
+
+#define EPERM 1 /* Operation not permitted */
+#define ENOENT 2 /* No such file or directory */
+#define ESRCH 3 /* No such process */
+#define EINTR 4 /* Interrupted system call */
+#define EIO 5 /* I/O error */
+#define ENXIO 6 /* No such device or address */
+#define E2BIG 7 /* Arg list too long */
+#define ENOEXEC 8 /* Exec format error */
+#define EBADF 9 /* Bad file number */
+#define ECHILD 10 /* No child processes */
+#define EAGAIN 11 /* Try again */
+#define ENOMEM 12 /* Out of memory */
+#define EACCES 13 /* Permission denied */
+#define EFAULT 14 /* Bad address */
+#define ENOTBLK 15 /* Block device required */
+#define EBUSY 16 /* Device or resource busy */
+#define EEXIST 17 /* File exists */
+#define EXDEV 18 /* Cross-device link */
+#define ENODEV 19 /* No such device */
+#define ENOTDIR 20 /* Not a directory */
+#define EISDIR 21 /* Is a directory */
+#define EINVAL 22 /* Invalid argument */
+#define ENFILE 23 /* File table overflow */
+#define EMFILE 24 /* Too many open files */
+#define ENOTTY 25 /* Not a typewriter */
+#define ETXTBSY 26 /* Text file busy */
+#define EFBIG 27 /* File too large */
+#define ENOSPC 28 /* No space left on device */
+#define ESPIPE 29 /* Illegal seek */
+#define EROFS 30 /* Read-only file system */
+#define EMLINK 31 /* Too many links */
+#define EPIPE 32 /* Broken pipe */
+#define EDOM 33 /* Math argument out of domain of func */
+#define ERANGE 34 /* Math result not representable */
+#define EDEADLK 35 /* Resource deadlock would occur */
+#define ENAMETOOLONG 36 /* File name too long */
+#define ENOLCK 37 /* No record locks available */
+#define ENOSYS 38 /* Function not implemented */
+#define ENOTEMPTY 39 /* Directory not empty */
+#define ELOOP 40 /* Too many symbolic links encountered */
+#define EWOULDBLOCK EAGAIN /* Operation would block */
+#define ENOMSG 42 /* No message of desired type */
+#define EIDRM 43 /* Identifier removed */
+#define ECHRNG 44 /* Channel number out of range */
+#define EL2NSYNC 45 /* Level 2 not synchronized */
+#define EL3HLT 46 /* Level 3 halted */
+#define EL3RST 47 /* Level 3 reset */
+#define ELNRNG 48 /* Link number out of range */
+#define EUNATCH 49 /* Protocol driver not attached */
+#define ENOCSI 50 /* No CSI structure available */
+#define EL2HLT 51 /* Level 2 halted */
+#define EBADE 52 /* Invalid exchange */
+#define EBADR 53 /* Invalid request descriptor */
+#define EXFULL 54 /* Exchange full */
+#define ENOANO 55 /* No anode */
+#define EBADRQC 56 /* Invalid request code */
+#define EBADSLT 57 /* Invalid slot */
+#define EDEADLOCK 58 /* File locking deadlock error */
+#define EBFONT 59 /* Bad font file format */
+#define ENOSTR 60 /* Device not a stream */
+#define ENODATA 61 /* No data available */
+#define ETIME 62 /* Timer expired */
+#define ENOSR 63 /* Out of streams resources */
+#define ENONET 64 /* Machine is not on the network */
+#define ENOPKG 65 /* Package not installed */
+#define EREMOTE 66 /* Object is remote */
+#define ENOLINK 67 /* Link has been severed */
+#define EADV 68 /* Advertise error */
+#define ESRMNT 69 /* Srmount error */
+#define ECOMM 70 /* Communication error on send */
+#define EPROTO 71 /* Protocol error */
+#define EMULTIHOP 72 /* Multihop attempted */
+#define EDOTDOT 73 /* RFS specific error */
+#define EBADMSG 74 /* Not a data message */
+#define EOVERFLOW 75 /* Value too large for defined data type */
+#define ENOTUNIQ 76 /* Name not unique on network */
+#define EBADFD 77 /* File descriptor in bad state */
+#define EREMCHG 78 /* Remote address changed */
+#define ELIBACC 79 /* Can not access a needed shared library */
+#define ELIBBAD 80 /* Accessing a corrupted shared library */
+#define ELIBSCN 81 /* .lib section in a.out corrupted */
+#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
+#define ELIBEXEC 83 /* Cannot exec a shared library directly */
+#define EILSEQ 84 /* Illegal byte sequence */
+#define ERESTART 85 /* Interrupted system call should be restarted */
+#define ESTRPIPE 86 /* Streams pipe error */
+#define EUSERS 87 /* Too many users */
+#define ENOTSOCK 88 /* Socket operation on non-socket */
+#define EDESTADDRREQ 89 /* Destination address required */
+#define EMSGSIZE 90 /* Message too long */
+#define EPROTOTYPE 91 /* Protocol wrong type for socket */
+#define ENOPROTOOPT 92 /* Protocol not available */
+#define EPROTONOSUPPORT 93 /* Protocol not supported */
+#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
+#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT 96 /* Protocol family not supported */
+#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
+#define EADDRINUSE 98 /* Address already in use */
+#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
+#define ENETDOWN 100 /* Network is down */
+#define ENETUNREACH 101 /* Network is unreachable */
+#define ENETRESET 102 /* Network dropped connection because of reset */
+#define ECONNABORTED 103 /* Software caused connection abort */
+#define ECONNRESET 104 /* Connection reset by peer */
+#define ENOBUFS 105 /* No buffer space available */
+#define EISCONN 106 /* Transport endpoint is already connected */
+#define ENOTCONN 107 /* Transport endpoint is not connected */
+#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS 109 /* Too many references: cannot splice */
+#define ETIMEDOUT 110 /* Connection timed out */
+#define ECONNREFUSED 111 /* Connection refused */
+#define EHOSTDOWN 112 /* Host is down */
+#define EHOSTUNREACH 113 /* No route to host */
+#define EALREADY 114 /* Operation already in progress */
+#define EINPROGRESS 115 /* Operation now in progress */
+#define ESTALE 116 /* Stale NFS file handle */
+#define EUCLEAN 117 /* Structure needs cleaning */
+#define ENOTNAM 118 /* Not a XENIX named type file */
+#define ENAVAIL 119 /* No XENIX semaphores available */
+#define EISNAM 120 /* Is a named type file */
+#define EREMOTEIO 121 /* Remote I/O error */
+#define EDQUOT 122 /* Quota exceeded */
+
+#define ENOMEDIUM 123 /* No medium found */
+#define EMEDIUMTYPE 124 /* Wrong medium type */
+
+/* Should never be seen by user programs */
+#define ERESTARTSYS 512
+#define ERESTARTNOINTR 513
+#define ERESTARTNOHAND 514 /* restart if no handler.. */
+#define ENOIOCTLCMD 515 /* No ioctl command */
+
+#define _LAST_ERRNO 515
+
+#endif
--- /dev/null
+/*****************************************************************************
+ * DANUBE BootROM
+ * Copyright (c) 2005, Infineon Technologies AG, All rights reserved
+ * IFAP DC COM SD
+ *****************************************************************************/
+#ifndef __ASC_H
+#define __ASC_H
+
+#define DANUBEASC_TXFIFO_FL 1
+#define DANUBEASC_RXFIFO_FL 1
+#define DANUBEASC_TXFIFO_FULL 16
+
+/* channel operating modes */
+#define ASCOPT_CSIZE 0x00000003
+#define ASCOPT_CS7 0x00000001
+#define ASCOPT_CS8 0x00000002
+#define ASCOPT_PARENB 0x00000004
+#define ASCOPT_STOPB 0x00000008
+#define ASCOPT_PARODD 0x00000010
+#define ASCOPT_CREAD 0x00000020
+
+#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
+
+/* ASC input select (0 or 1) */
+#define CONSOLE_TTY 0
+
+#define DANUBEASC_TXFIFO_FL 1
+#define DANUBEASC_RXFIFO_FL 1
+#define DANUBEASC_TXFIFO_FULL 16
+
+/* interrupt lines masks for the ASC device interrupts*/
+/* change these macroses if it's necessary */
+#define DANUBEASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */
+
+#define DANUBEASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */
+#define DANUBEASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */
+#define DANUBEASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */
+#define DANUBEASC_IRQ_LINE_EIR 0x00000008 /* Error Int */
+#define DANUBEASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */
+#define DANUBEASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */
+#define DANUBEASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */
+
+/* interrupt controller access macros */
+#define ASC_INTERRUPTS_ENABLE(X) \
+*((volatile unsigned int*) DANUBE_ICU_IM0_IER) |= X;
+#define ASC_INTERRUPTS_DISABLE(X) \
+*((volatile unsigned int*) DANUBE_ICU_IM0_IER) &= ~X;
+#define ASC_INTERRUPTS_CLEAR(X) \
+*((volatile unsigned int*) DANUBE_ICU_IM0_ISR) = X;
+
+/* CLC register's bits and bitfields */
+#define ASCCLC_DISR 0x00000001
+#define ASCCLC_DISS 0x00000002
+#define ASCCLC_RMCMASK 0x0000FF00
+#define ASCCLC_RMCOFFSET 8
+
+/* CON register's bits and bitfields */
+#define ASCCON_MODEMASK 0x0000000f
+#define ASCCON_M_8ASYNC 0x0
+#define ASCCON_M_8IRDA 0x1
+#define ASCCON_M_7ASYNC 0x2
+#define ASCCON_M_7IRDA 0x3
+#define ASCCON_WLSMASK 0x0000000c
+#define ASCCON_WLSOFFSET 2
+#define ASCCON_WLS_8BIT 0x0
+#define ASCCON_WLS_7BIT 0x1
+#define ASCCON_PEN 0x00000010
+#define ASCCON_ODD 0x00000020
+#define ASCCON_SP 0x00000040
+#define ASCCON_STP 0x00000080
+#define ASCCON_BRS 0x00000100
+#define ASCCON_FDE 0x00000200
+#define ASCCON_ERRCLK 0x00000400
+#define ASCCON_EMMASK 0x00001800
+#define ASCCON_EMOFFSET 11
+#define ASCCON_EM_ECHO_OFF 0x0
+#define ASCCON_EM_ECHO_AB 0x1
+#define ASCCON_EM_ECHO_ON 0x2
+#define ASCCON_LB 0x00002000
+#define ASCCON_ACO 0x00004000
+#define ASCCON_R 0x00008000
+#define ASCCON_PAL 0x00010000
+#define ASCCON_FEN 0x00020000
+#define ASCCON_RUEN 0x00040000
+#define ASCCON_ROEN 0x00080000
+#define ASCCON_TOEN 0x00100000
+#define ASCCON_BEN 0x00200000
+#define ASCCON_TXINV 0x01000000
+#define ASCCON_RXINV 0x02000000
+#define ASCCON_TXMSB 0x04000000
+#define ASCCON_RXMSB 0x08000000
+
+/* STATE register's bits and bitfields */
+#define ASCSTATE_REN 0x00000001
+#define ASCSTATE_PE 0x00010000
+#define ASCSTATE_FE 0x00020000
+#define ASCSTATE_RUE 0x00040000
+#define ASCSTATE_ROE 0x00080000
+#define ASCSTATE_TOE 0x00100000
+#define ASCSTATE_BE 0x00200000
+#define ASCSTATE_TXBVMASK 0x07000000
+#define ASCSTATE_TXBVOFFSET 24
+#define ASCSTATE_TXEOM 0x08000000
+#define ASCSTATE_RXBVMASK 0x70000000
+#define ASCSTATE_RXBVOFFSET 28
+#define ASCSTATE_RXEOM 0x80000000
+
+/* WHBSTATE register's bits and bitfields */
+#define ASCWHBSTATE_CLRREN 0x00000001
+#define ASCWHBSTATE_SETREN 0x00000002
+#define ASCWHBSTATE_CLRPE 0x00000004
+#define ASCWHBSTATE_CLRFE 0x00000008
+#define ASCWHBSTATE_CLRRUE 0x00000010
+#define ASCWHBSTATE_CLRROE 0x00000020
+#define ASCWHBSTATE_CLRTOE 0x00000040
+#define ASCWHBSTATE_CLRBE 0x00000080
+#define ASCWHBSTATE_SETPE 0x00000100
+#define ASCWHBSTATE_SETFE 0x00000200
+#define ASCWHBSTATE_SETRUE 0x00000400
+#define ASCWHBSTATE_SETROE 0x00000800
+#define ASCWHBSTATE_SETTOE 0x00001000
+#define ASCWHBSTATE_SETBE 0x00002000
+
+/* ABCON register's bits and bitfields */
+#define ASCABCON_ABEN 0x0001
+#define ASCABCON_AUREN 0x0002
+#define ASCABCON_ABSTEN 0x0004
+#define ASCABCON_ABDETEN 0x0008
+#define ASCABCON_FCDETEN 0x0010
+
+/* FDV register mask, offset and bitfields*/
+#define ASCFDV_VALUE_MASK 0x000001FF
+
+/* WHBABCON register's bits and bitfields */
+#define ASCWHBABCON_CLRABEN 0x0001
+#define ASCWHBABCON_SETABEN 0x0002
+
+/* ABSTAT register's bits and bitfields */
+#define ASCABSTAT_FCSDET 0x0001
+#define ASCABSTAT_FCCDET 0x0002
+#define ASCABSTAT_SCSDET 0x0004
+#define ASCABSTAT_SCCDET 0x0008
+#define ASCABSTAT_DETWAIT 0x0010
+
+/* WHBABSTAT register's bits and bitfields */
+#define ASCWHBABSTAT_CLRFCSDET 0x0001
+#define ASCWHBABSTAT_SETFCSDET 0x0002
+#define ASCWHBABSTAT_CLRFCCDET 0x0004
+#define ASCWHBABSTAT_SETFCCDET 0x0008
+#define ASCWHBABSTAT_CLRSCSDET 0x0010
+#define ASCWHBABSTAT_SETSCSDET 0x0020
+#define ASCWHBABSTAT_CLRSCCDET 0x0040
+#define ASCWHBABSTAT_SETSCCDET 0x0080
+#define ASCWHBABSTAT_CLRDETWAIT 0x0100
+#define ASCWHBABSTAT_SETDETWAIT 0x0200
+
+/* TXFCON register's bits and bitfields */
+#define ASCTXFCON_TXFIFO1 0x00000400
+#define ASCTXFCON_TXFEN 0x0001
+#define ASCTXFCON_TXFFLU 0x0002
+#define ASCTXFCON_TXFITLMASK 0x3F00
+#define ASCTXFCON_TXFITLOFF 8
+
+/* RXFCON register's bits and bitfields */
+#define ASCRXFCON_RXFIFO1 0x00000400
+#define ASCRXFCON_RXFEN 0x0001
+#define ASCRXFCON_RXFFLU 0x0002
+#define ASCRXFCON_RXFITLMASK 0x3F00
+#define ASCRXFCON_RXFITLOFF 8
+
+/* FSTAT register's bits and bitfields */
+#define ASCFSTAT_RXFFLMASK 0x003F
+#define ASCFSTAT_TXFFLMASK 0x3F00
+#define ASCFSTAT_TXFFLOFF 8
+
+typedef struct /* DanubeAsc_t */
+{
+ volatile unsigned long asc_clc; /*0x0000*/
+ volatile unsigned long asc_pisel; /*0x0004*/
+ volatile unsigned long asc_id; /*0x0008*/
+ volatile unsigned long asc_rsvd1[1]; /* for mapping */ /*0x000C*/
+ volatile unsigned long asc_con; /*0x0010*/
+ volatile unsigned long asc_state; /*0x0014*/
+ volatile unsigned long asc_whbstate; /*0x0018*/
+ volatile unsigned long asc_rsvd2[1]; /* for mapping */ /*0x001C*/
+ volatile unsigned long asc_tbuf; /*0x0020*/
+ volatile unsigned long asc_rbuf; /*0x0024*/
+ volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0028*/
+ volatile unsigned long asc_abcon; /*0x0030*/
+ volatile unsigned long asc_abstat; /* not used */ /*0x0034*/
+ volatile unsigned long asc_whbabcon; /*0x0038*/
+ volatile unsigned long asc_whbabstat; /* not used */ /*0x003C*/
+ volatile unsigned long asc_rxfcon; /*0x0040*/
+ volatile unsigned long asc_txfcon; /*0x0044*/
+ volatile unsigned long asc_fstat; /*0x0048*/
+ volatile unsigned long asc_rsvd4[1]; /* for mapping */ /*0x004C*/
+ volatile unsigned long asc_bg; /*0x0050*/
+ volatile unsigned long asc_bg_timer; /*0x0054*/
+ volatile unsigned long asc_fdv; /*0x0058*/
+ volatile unsigned long asc_pmw; /*0x005C*/
+ volatile unsigned long asc_modcon; /*0x0060*/
+ volatile unsigned long asc_modstat; /*0x0064*/
+ volatile unsigned long asc_rsvd5[2]; /* for mapping */ /*0x0068*/
+ volatile unsigned long asc_sfcc; /*0x0070*/
+ volatile unsigned long asc_rsvd6[3]; /* for mapping */ /*0x0074*/
+ volatile unsigned long asc_eomcon; /*0x0080*/
+ volatile unsigned long asc_rsvd7[26]; /* for mapping */ /*0x0084*/
+ volatile unsigned long asc_dmacon; /*0x00EC*/
+ volatile unsigned long asc_rsvd8[1]; /* for mapping */ /*0x00F0*/
+ volatile unsigned long asc_irnen; /*0x00F4*/
+ volatile unsigned long asc_irnicr; /*0x00F8*/
+ volatile unsigned long asc_irncr; /*0x00FC*/
+} DanubeAsc_t;
+
+int asc_init (void);
+void asc_puts (const char *s);
+void asc_putc (const char c);
+int asc_getc (void);
+
+#endif /* __ASC_H */
--- /dev/null
+/************************************************************************
+ *
+ * Copyright (c) 2005
+ * Infineon Technologies AG
+ * St. Martin Strasse 53; 81669 Muenchen; Germany
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ ************************************************************************/
+
+/***********************************************************************/
+/* Module : DMA register address and bits */
+/***********************************************************************/
+
+#define INCA_IP2_DMA (KSEG1+0x14101000)
+/***********************************************************************/
+#define CONFIGURATION_REGISTERS_CLC (INCA_IP2_DMA + 0x00)
+#define CONFIGURATION_REGISTERS_ID (INCA_IP2_DMA + 0x08)
+#define GENERAL_REGISTERS_DMA_CTRL (INCA_IP2_DMA + 0x10)
+#define CHANNEL_RELATED_REGISTERS_DMA_CS (INCA_IP2_DMA + 0x18)
+#define CHANNEL_RELATED_REGISTERS_DMA_CCTRL (INCA_IP2_DMA + 0x1C)
+#define CHANNEL_RELATED_REGISTERS_DMA_CDBA (INCA_IP2_DMA + 0x20)
+#define CHANNEL_RELATED_REGISTERS_DMA_CDLEN (INCA_IP2_DMA + 0x24)
+#define CHANNEL_RELATED_REGISTERS_DMA_CIE (INCA_IP2_DMA + 0x2C)
+#define CHANNEL_RELATED_REGISTERS_DMA_CIS (INCA_IP2_DMA + 0x28)
+#define CHANNEL_RELATED_REGISTERS_DMA_CPOLL (INCA_IP2_DMA + 0x14)
+
+#define PORT_RELATED_REGISTERS_DMA_PS (INCA_IP2_DMA + 0x40)
+#define PORT_RELATED_REGISTERS_DMA_PCTRL (INCA_IP2_DMA + 0x44)
+
+#define INTERRUPT_NODE_REGISTERS_DMA_IRNEN (INCA_IP2_DMA + 0xF4)
+#define INTERRUPT_NODE_REGISTERS_DMA_IRNCR (INCA_IP2_DMA + 0xF8)
+#define INTERRUPT_NODE_REGISTERS_DMA_IRNICR (INCA_IP2_DMA + 0xFC)
+
+#if 0
+/* ISR */
+#define DMA_ISR_RDERR 0x20
+#define DMA_ISR_CMDCPT 0x10
+#define DMA_ISR_CPT 0x8
+#define DMA_ISR_DURR 0x4
+#define DMA_ISR_EOP 0x2
+#endif
+#define DMA_RESET_CHANNEL 0x00000002
+#define DMA_ENABLE_CHANNEL 0x00000001
+#define DMA_DESC_BYTEOFF_SHIFT 22
+
+#define DMA_POLLING_ENABLE 0x80000000
+#define DMA_POLLING_CNT 0x50 /*minimum 0x10, max 0xfff0*/
+
+/***********************************************************************/
+/* Module : ICU register address and bits */
+/***********************************************************************/
+
+#define INCA_IP2_ICU (KSEG1+0x1F880200)
+/***********************************************************************/
+
+#define INCA_IP2_ICU_IM0_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0000))
+#define INCA_IP2_ICU_IM0_IER ((volatile u32*)(INCA_IP2_ICU + 0x0008))
+#define INCA_IP2_ICU_IM0_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0010))
+#define INCA_IP2_ICU_IM0_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0018))
+#define INCA_IP2_ICU_IM0_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0020))
+#define INCA_IP2_ICU_IM0_IMR_IID (1 << 31)
+#define INCA_IP2_ICU_IM0_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
+#define INCA_IP2_ICU_IM0_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
+#define INCA_IP2_ICU_IM0_IR(value) (1 << (value))
+
+#define INCA_IP2_ICU_IM1_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0028))
+#define INCA_IP2_ICU_IM1_IER ((volatile u32*)(INCA_IP2_ICU + 0x0030))
+#define INCA_IP2_ICU_IM1_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0038))
+#define INCA_IP2_ICU_IM1_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0040))
+#define INCA_IP2_ICU_IM1_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0048))
+#define INCA_IP2_ICU_IM1_IMR_IID (1 << 31)
+#define INCA_IP2_ICU_IM1_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
+#define INCA_IP2_ICU_IM1_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
+#define INCA_IP2_ICU_IM1_IR(value) (1 << (value))
+
+#define INCA_IP2_ICU_IM2_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0050))
+#define INCA_IP2_ICU_IM2_IER ((volatile u32*)(INCA_IP2_ICU + 0x0058))
+#define INCA_IP2_ICU_IM2_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0060))
+#define INCA_IP2_ICU_IM2_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0068))
+#define INCA_IP2_ICU_IM2_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0070))
+#define INCA_IP2_ICU_IM2_IMR_IID (1 << 31)
+#define INCA_IP2_ICU_IM2_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
+#define INCA_IP2_ICU_IM2_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
+#define INCA_IP2_ICU_IM2_IR(value) (1 << (value))
+
+#define INCA_IP2_ICU_IM3_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0078))
+#define INCA_IP2_ICU_IM3_IER ((volatile u32*)(INCA_IP2_ICU + 0x0080))
+#define INCA_IP2_ICU_IM3_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0088))
+#define INCA_IP2_ICU_IM3_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0090))
+#define INCA_IP2_ICU_IM3_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0098))
+#define INCA_IP2_ICU_IM3_IMR_IID (1 << 31)
+#define INCA_IP2_ICU_IM3_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
+#define INCA_IP2_ICU_IM3_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
+#define INCA_IP2_ICU_IM3_IR(value) (1 << (value))
+
+#define INCA_IP2_ICU_IM4_ISR ((volatile u32*)(INCA_IP2_ICU + 0x00A0))
+#define INCA_IP2_ICU_IM4_IER ((volatile u32*)(INCA_IP2_ICU + 0x00A8))
+#define INCA_IP2_ICU_IM4_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x00B0))
+#define INCA_IP2_ICU_IM4_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x00B8))
+#define INCA_IP2_ICU_IM4_IMR ((volatile u32*)(INCA_IP2_ICU + 0x00C0))
+#define INCA_IP2_ICU_IM4_IMR_IID (1 << 31)
+#define INCA_IP2_ICU_IM4_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
+#define INCA_IP2_ICU_IM4_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
+#define INCA_IP2_ICU_IM4_IR(value) (1 << (value))
+
+#define INCA_IP2_ICU_IM5_ISR ((volatile u32*)(INCA_IP2_ICU + 0x00C8))
+#define INCA_IP2_ICU_IM5_IER ((volatile u32*)(INCA_IP2_ICU + 0x00D0))
+#define INCA_IP2_ICU_IM5_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x00D8))
+#define INCA_IP2_ICU_IM5_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x00E0))
+#define INCA_IP2_ICU_IM5_IMR ((volatile u32*)(INCA_IP2_ICU + 0x00E8))
+#define INCA_IP2_ICU_IM5_IMR_IID (1 << 31)
+#define INCA_IP2_ICU_IM5_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1))
+#define INCA_IP2_ICU_IM5_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0)
+#define INCA_IP2_ICU_IM5_IR(value) (1 << (value))
+
+
+/***********************************************************************/
+/* Module : CGU register address and bits */
+/***********************************************************************/
+
+#define INCA_IP2_CGU (KSEG1+0x1F100800)
+/***********************************************************************/
+
+#define INCA_IP2_CGU_PLL2CR ((volatile u32*)(INCA_IP2_CGU + 0x0008))
+#define INCA_IP2_CGU_FBSCR ((volatile u32*)(INCA_IP2_CGU + 0x0018))
+#define INCA_IP2_CGU_FBSCR_LPBSDIV_GET(value) (((value) >> 6) & ((1 << 2) - 1))
+#define INCA_IP2_CGU_FBSCR_DIV0_GET(value) (((value) >> 0) & ((1 << 3) - 1))
+#define INCA_IP2_CGU_FBSCR_DIV1_GET(value) (((value) >> 4) & ((1 << 2) - 1))
+
+/***********************************************************************/
+/* Module : MPS register address and bits */
+/***********************************************************************/
+
+#define INCA_IP2_MPS (KSEG1+0x1F101400)
+/***********************************************************************/
+
+#define INCA_IP2_MPS_CHIPID ((volatile u32*)(INCA_IP2_MPS + 0x0344))
+#define INCA_IP2_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
+#define INCA_IP2_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28)
+#define INCA_IP2_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
+#define INCA_IP2_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12)
+#define INCA_IP2_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
+#define INCA_IP2_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1)
+
+
+/* voice channel 0 ... 3 interrupt enable register */
+#define INCA_IP2_MPS_VC0ENR ((volatile u32*)(INCA_IP2_MPS + 0x0000))
+#define INCA_IP2_MPS_VC1ENR ((volatile u32*)(INCA_IP2_MPS + 0x0004))
+#define INCA_IP2_MPS_VC2ENR ((volatile u32*)(INCA_IP2_MPS + 0x0008))
+#define INCA_IP2_MPS_VC3ENR ((volatile u32*)(INCA_IP2_MPS + 0x000C))
+/* voice channel 0 ... 3 interrupt status read register */
+#define INCA_IP2_MPS_RVC0SR ((volatile u32*)(INCA_IP2_MPS + 0x0010))
+#define INCA_IP2_MPS_RVC1SR ((volatile u32*)(INCA_IP2_MPS + 0x0014))
+#define INCA_IP2_MPS_RVC2SR ((volatile u32*)(INCA_IP2_MPS + 0x0018))
+#define INCA_IP2_MPS_RVC3SR ((volatile u32*)(INCA_IP2_MPS + 0x001C))
+/* voice channel 0 ... 3 interrupt status set register */
+#define INCA_IP2_MPS_SVC0SR ((volatile u32*)(INCA_IP2_MPS + 0x0020))
+#define INCA_IP2_MPS_SVC1SR ((volatile u32*)(INCA_IP2_MPS + 0x0024))
+#define INCA_IP2_MPS_SVC2SR ((volatile u32*)(INCA_IP2_MPS + 0x0028))
+#define INCA_IP2_MPS_SVC3SR ((volatile u32*)(INCA_IP2_MPS + 0x002C))
+/* voice channel 0 ... 3 interrupt status clear register */
+#define INCA_IP2_MPS_CVC0SR ((volatile u32*)(INCA_IP2_MPS + 0x0030))
+#define INCA_IP2_MPS_CVC1SR ((volatile u32*)(INCA_IP2_MPS + 0x0034))
+#define INCA_IP2_MPS_CVC2SR ((volatile u32*)(INCA_IP2_MPS + 0x0038))
+#define INCA_IP2_MPS_CVC3SR ((volatile u32*)(INCA_IP2_MPS + 0x003C))
+/* common status 0 and 1 read register */
+#define INCA_IP2_MPS_RAD0SR ((volatile u32*)(INCA_IP2_MPS + 0x0040))
+#define INCA_IP2_MPS_RAD1SR ((volatile u32*)(INCA_IP2_MPS + 0x0044))
+/* common status 0 and 1 set register */
+#define INCA_IP2_MPS_SAD0SR ((volatile u32*)(INCA_IP2_MPS + 0x0048))
+#define INCA_IP2_MPS_SAD1SR ((volatile u32*)(INCA_IP2_MPS + 0x004C))
+/* common status 0 and 1 clear register */
+#define INCA_IP2_MPS_CAD0SR ((volatile u32*)(INCA_IP2_MPS + 0x0050))
+#define INCA_IP2_MPS_CAD1SR ((volatile u32*)(INCA_IP2_MPS + 0x0054))
+/* notification enable register */
+#define INCA_IP2_MPS_CPU0_NFER ((volatile u32*)(INCA_IP2_MPS + 0x0060))
+#define INCA_IP2_MPS_CPU1_NFER ((volatile u32*)(INCA_IP2_MPS + 0x0064))
+/* CPU to CPU interrup request register */
+#define INCA_IP2_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(INCA_IP2_MPS + 0x0070))
+#define INCA_IP2_MPS_CPU0_2_CPU1_IER ((volatile u32*)(INCA_IP2_MPS + 0x0074))
+/* Global interrupt request and request enable register */
+#define INCA_IP2_MPS_GIRR ((volatile u32*)(INCA_IP2_MPS + 0x0078))
+#define INCA_IP2_MPS_GIER ((volatile u32*)(INCA_IP2_MPS + 0x007C))
+
+/* Addresses of enable registers not yet defined
+#define INCA_IP2_MPS_AD0ENR ((volatile u32*)(INCA_IP2_MPS + 0x????))
+#define INCA_IP2_MPS_AD1ENR ((volatile u32*)(INCA_IP2_MPS + 0x????))
+*/
+
+
+/***********************************************************************/
+/* Module : ASC0 register address and bits */
+/***********************************************************************/
+
+#define INCA_IP2_ASC0 (KSEG1+0x1E000400)
+/***********************************************************************/
+
+#define INCA_IP2_ASC0_TBUF ((volatile u32*)(INCA_IP2_ASC0 + 0x0020))
+#define INCA_IP2_ASC0_RBUF ((volatile u32*)(INCA_IP2_ASC0 + 0x0024))
+#define INCA_IP2_ASC0_FSTAT ((volatile u32*)(INCA_IP2_ASC0 + 0x0048))
+#define INCA_IP2_ASC0_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1))
+#define INCA_IP2_ASC0_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24)
+#define INCA_IP2_ASC0_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1))
+#define INCA_IP2_ASC0_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16)
+#define INCA_IP2_ASC0_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1))
+#define INCA_IP2_ASC0_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8)
+#define INCA_IP2_ASC0_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1))
+#define INCA_IP2_ASC0_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0)
+
+
+/***********************************************************************/
+/* Module : ASC1 register address and bits */
+/***********************************************************************/
+
+#define INCA_IP2_ASC1 (KSEG1+0x1E000800)
+/***********************************************************************/
+
+#define INCA_IP2_ASC1_TBUF ((volatile u32*)(INCA_IP2_ASC1 + 0x0020))
+#define INCA_IP2_ASC1_RBUF ((volatile u32*)(INCA_IP2_ASC1 + 0x0024))
+#define INCA_IP2_ASC1_FSTAT ((volatile u32*)(INCA_IP2_ASC1 + 0x0048))
+#define INCA_IP2_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1))
+#define INCA_IP2_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24)
+#define INCA_IP2_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1))
+#define INCA_IP2_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16)
+#define INCA_IP2_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1))
+#define INCA_IP2_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8)
+#define INCA_IP2_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1))
+#define INCA_IP2_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0)
+
+
+/***********************************************************************/
+/* Module : RCU register address and bits */
+/***********************************************************************/
+
+#define INCA_IP2_RCU (KSEG1+0x1E001C00)
+/***********************************************************************/
+
+/***Reset Request Register***/
+#define INCA_IP2_RCU_RST_REQ ((volatile u32*)(INCA_IP2_RCU + 0x0000))
+#define INCA_IP2_RCU_RST_REQ_CPU0 (1 << 31)
+#define INCA_IP2_RCU_RST_REQ_CPU1 (1 << 30)
+#define INCA_IP2_RCU_RST_REQ_CPUSUB (1 << 29)
+#define INCA_IP2_RCU_RST_REQ_HRST (1 << 28)
+#define INCA_IP2_RCU_RST_REQ_WDT0 (1 << 27)
+#define INCA_IP2_RCU_RST_REQ_WDT1 (1 << 26)
+#define INCA_IP2_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1))
+#define INCA_IP2_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23)
+#define INCA_IP2_RCU_RST_REQ_SWTBOOT (1 << 22)
+#define INCA_IP2_RCU_RST_REQ_DMA (1 << 21)
+#define INCA_IP2_RCU_RST_REQ_ETHPHY1 (1 << 20)
+#define INCA_IP2_RCU_RST_REQ_ETHPHY0 (1 << 19)
+#define INCA_IP2_RCU_RST_REQ_CPU0_BR (1 << 18)
+
+/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */
+#define INCA_IP2_RCU_RST_REQ_ALL 0xFC380000
+
+/***NMI Status Register***/
+#define INCA_IP2_RCU_NMISR ((volatile u32*)(INCA_IP2_RCU + 0x00F4))
+#define INCA_IP2_RCU_NMISR_NMIEXT (1 << 2)
+#define INCA_IP2_RCU_NMISR_NMIPLL2 (1 << 1)
+#define INCA_IP2_RCU_NMISR_NMIPLL1 (1 << 0)
+
+
+/***********************************************************************/
+/* Module : WDT register address and bits */
+/***********************************************************************/
+
+#define INCA_IP2_WDT (KSEG1+0x1F880000)
+/***********************************************************************/
+
+/***Watchdog Timer Control Register ***/
+#define INCA_IP2_WDT_BIU_WDT_CR ((volatile u32*)(INCA_IP2_WDT + 0x03F0))
+#define INCA_IP2_WDT_BIU_WDT_CR_GEN (1 << 31)
+#define INCA_IP2_WDT_BIU_WDT_CR_DSEN (1 << 30)
+#define INCA_IP2_WDT_BIU_WDT_CR_LPEN (1 << 29)
+#define INCA_IP2_WDT_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1))
+#define INCA_IP2_WDT_BIU_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26)
+#define INCA_IP2_WDT_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
+#define INCA_IP2_WDT_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24)
+#define INCA_IP2_WDT_BIU_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1))
+#define INCA_IP2_WDT_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16)
+#define INCA_IP2_WDT_BIU_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1))
+#define INCA_IP2_WDT_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
+
+/***Watchdog Timer Status Register***/
+#define INCA_IP2_WDT_BIU_WDT_SR ((volatile u32*)(INCA_IP2_WDT + 0x03F8))
+#define INCA_IP2_WDT_BIU_WDT_SR_EN (1 << 31)
+#define INCA_IP2_WDT_BIU_WDT_SR_AE (1 << 30)
+#define INCA_IP2_WDT_BIU_WDT_SR_PRW (1 << 29)
+#define INCA_IP2_WDT_BIU_WDT_SR_EXP (1 << 28)
+#define INCA_IP2_WDT_BIU_WDT_SR_PWD (1 << 27)
+#define INCA_IP2_WDT_BIU_WDT_SR_DS (1 << 26)
+#define INCA_IP2_WDT_BIU_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1))
+#define INCA_IP2_WDT_BIU_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
+
+
+/***********************************************************************/
+/* Module : BCU0 register address and bits */
+/***********************************************************************/
+
+#define INCA_IP2_BCU0 (KSEG1+0x14100000)
+/***********************************************************************/
+
+#define INCA_IP2_BCU0_CON ((volatile u32*)(INCA_IP2_BCU0 + 0x0010))
+#define INCA_IP2_BCU0_ECON ((volatile u32*)(INCA_IP2_BCU0 + 0x0020))
+#define INCA_IP2_BCU0_EADD ((volatile u32*)(INCA_IP2_BCU0 + 0x0024))
+#define INCA_IP2_BCU0_EDAT ((volatile u32*)(INCA_IP2_BCU0 + 0x0028))
+#define INCA_IP2_BCU0_IRNCR1 ((volatile u32*)(INCA_IP2_BCU0 + 0x00F8))
+#define INCA_IP2_BCU0_IRNCR0 ((volatile u32*)(INCA_IP2_BCU0 + 0x00FC))
+
+
+/***********************************************************************/
+/* Module : BCU1 register address and bits */
+/***********************************************************************/
+
+#define INCA_IP2_BCU1 (KSEG1+0x1E000000)
+/***********************************************************************/
+
+#define INCA_IP2_BCU1_CON ((volatile u32*)(INCA_IP2_BCU1 + 0x0010))
+#define INCA_IP2_BCU1_ECON ((volatile u32*)(INCA_IP2_BCU1 + 0x0020))
+#define INCA_IP2_BCU1_EADD ((volatile u32*)(INCA_IP2_BCU1 + 0x0024))
+#define INCA_IP2_BCU1_EDAT ((volatile u32*)(INCA_IP2_BCU1 + 0x0028))
+#define INCA_IP2_BCU1_IRNCR1 ((volatile u32*)(INCA_IP2_BCU1 + 0x00F8))
+#define INCA_IP2_BCU1_IRNCR0 ((volatile u32*)(INCA_IP2_BCU1 + 0x00FC))
+
+
+/***********************************************************************/
+/* Module : MC register address and bits */
+/***********************************************************************/
+
+#define INCA_IP2_MC (KSEG1+0x1F800000)
+/***********************************************************************/
+
+#define INCA_IP2_MC_ERRCAUSE ((volatile u32*)(INCA_IP2_MC + 0x0010))
+#define INCA_IP2_MC_ERRADDR ((volatile u32*)(INCA_IP2_MC + 0x0020))
+#define INCA_IP2_MC_CON ((volatile u32*)(INCA_IP2_MC + 0x0060))
+
+/***********************************************************************/
+/* Module : MC SDRAM register address and bits */
+/***********************************************************************/
+#define INCA_IP2_SDRAM (KSEG1+0x1F800200)
+/***********************************************************************/
+#define INCA_IP2_SDRAM_MC_CFGPB0 ((volatile u32*)(INCA_IP2_SDRAM + 0x0040))
+
+/***********************************************************************/
+/* Module : MC DDR register address and bits */
+/***********************************************************************/
+#define INCA_IP2_DDR (KSEG1+0x1F801000)
+/***********************************************************************/
+#define INCA_IP2_DDR_MC_DC19 ((volatile u32*)(INCA_IP2_DDR + 0x0130))
+#define INCA_IP2_DDR_MC_DC20 ((volatile u32*)(INCA_IP2_DDR + 0x0140))
+
+
+/***********************************************************************/
+/* Module : PMS register address and bits */
+/***********************************************************************/
+
+#define INCA_IP2_PMS (KSEG1 + 0x1F100C00)
+
+#define INCA_IP2_PMS_PMS_SR ((volatile u32*) (INCA_IP2_PMS + 0x0000))
+#define INCA_IP2_PMS_PMS_SR_ASC1 (1 << 14)
+#define INCA_IP2_PMS_PMS_SR_ASC0 (1 << 13)
+#define INCA_IP2_PMS_PMS_GEN ((volatile u32*) (INCA_IP2_PMS + 0x0004))
+#define INCA_IP2_PMS_PMS_GEN_DMA (1 << 16)
+#define INCA_IP2_PMS_PMS_GEN_ASC1 (1 << 14)
+#define INCA_IP2_PMS_PMS_GEN_ASC0 (1 << 13)
+#define INCA_IP2_PMS_PMS_GEN_SPI0 (1 << 11)
+#define INCA_IP2_PMS_PMS_GEN_SPI1 (1 << 12)
+#define INCA_IP2_PMS_PMS_CFG ((volatile u32*) (INCA_IP2_PMS + 0x0008))
+
+
+/***********************************************************************/
+/* Module : GPIO register address and bits */
+/***********************************************************************/
+
+#define INCA_IP2_GPIO (KSEG1 + 0x1F102600)
+
+#define INCA_IP2_GPIO_OUT ((volatile u32*) (INCA_IP2_GPIO + 0x0000))
+#define INCA_IP2_GPIO_IN ((volatile u32*) (INCA_IP2_GPIO + 0x0004))
+#define INCA_IP2_GPIO_DIR ((volatile u32*) (INCA_IP2_GPIO + 0x0008))
+#define INCA_IP2_GPIO_ALTSEL1 ((volatile u32*) (INCA_IP2_GPIO + 0x000C))
+#define INCA_IP2_GPIO_ALTSEL2 ((volatile u32*) (INCA_IP2_GPIO + 0x0010))
+#define INCA_IP2_GPIO_STOFF ((volatile u32*) (INCA_IP2_GPIO + 0x0014))
+#define INCA_IP2_GPIO_OD ((volatile u32*) (INCA_IP2_GPIO + 0x0018))
+#define INCA_IP2_GPIO_PUDEB ((volatile u32*) (INCA_IP2_GPIO + 0x001C))
+
+/***********************************************************************/
+/* Module : RCU register address and bits */
+/***********************************************************************/
+
+#define INCA_IP2_RCU (KSEG1+0x1E001C00)
+/***********************************************************************/
+
+/***Reset Request Register***/
+#define INCA_IP2_RCU_RST_REQ ((volatile u32*)(INCA_IP2_RCU + 0x0000))
+#define INCA_IP2_RCU_RST_REQ_CPU0 (1 << 31)
+#define INCA_IP2_RCU_RST_REQ_CPU1 (1 << 30)
+#define INCA_IP2_RCU_RST_REQ_CPUSUB (1 << 29)
+#define INCA_IP2_RCU_RST_REQ_HRST (1 << 28)
+#define INCA_IP2_RCU_RST_REQ_WDT0 (1 << 27)
+#define INCA_IP2_RCU_RST_REQ_WDT1 (1 << 26)
+#define INCA_IP2_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1))
+#define INCA_IP2_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23)
+#define INCA_IP2_RCU_RST_REQ_SWTBOOT (1 << 22)
+#define INCA_IP2_RCU_RST_REQ_DMA (1 << 21)
+#define INCA_IP2_RCU_RST_REQ_ETHPHY1 (1 << 20)
+#define INCA_IP2_RCU_RST_REQ_ETHPHY0 (1 << 19)
+#define INCA_IP2_RCU_RST_REQ_CPU0_BR (1 << 18)
+
+/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */
+#define INCA_IP2_RCU_RST_REQ_ALL 0xFC380000
+
+/***Reset Status Register***/
+#define INCA_IP2_RCU_SR ((volatile u32*)(INCA_IP2_RCU + 0x0008))
+
+/***NMI Status Register***/
+#define INCA_IP2_RCU_NMISR ((volatile u32*)(INCA_IP2_RCU + 0x00F4))
+#define INCA_IP2_RCU_NMISR_NMIEXT (1 << 2)
+#define INCA_IP2_RCU_NMISR_NMIPLL2 (1 << 1)
+#define INCA_IP2_RCU_NMISR_NMIPLL1 (1 << 0)
+
+/***********************************************************************/
+/* Module : EBU register address and bits */
+/***********************************************************************/
+
+#define INCA_IP2_EBU (KSEG1+0x14102000)
+/***********************************************************************/
+
+#define INCA_IP2_EBU_ADDSEL0 ((volatile u32*)(INCA_IP2_EBU + 0x0020))
+#define INCA_IP2_EBU_ADDSEL1 ((volatile u32*)(INCA_IP2_EBU + 0x0024))
+#define INCA_IP2_EBU_ADDSEL2 ((volatile u32*)(INCA_IP2_EBU + 0x0028))
+#define INCA_IP2_EBU_ADDSEL3 ((volatile u32*)(INCA_IP2_EBU + 0x002C))
+#define INCA_IP2_EBU_CON0 ((volatile u32*)(INCA_IP2_EBU + 0x0060))
+#define INCA_IP2_EBU_CON1 ((volatile u32*)(INCA_IP2_EBU + 0x0064))
+#define INCA_IP2_EBU_CON2 ((volatile u32*)(INCA_IP2_EBU + 0x0068))
+#define INCA_IP2_EBU_CON3 ((volatile u32*)(INCA_IP2_EBU + 0x006C))
+#define INCA_IP2_EBU_CON_WRDIS (1 << 31)
+
+
+
+
+/***********************************************************************/
+/* Module : SWITCH register address and bits */
+/***********************************************************************/
+
+#define INCA_IP2_SWITCH (KSEG1+0x18000000)
+/***********************************************************************/
+
+/* PR Base address */
+#define PR_BASE (INCA_IP2_SWITCH + 0x00008000)
+
+/* SE Base Address */
+#define SE_BASE (INCA_IP2_SWITCH + 0x00009000)
+
+#define PR_CTRL_REG (PR_BASE + 0x0000)
+#define MA_LEARN_REG (PR_BASE + 0x0004)
+#define DST_LOOKUP_REG (PR_BASE + 0x0008)
+
+#define COS_SEL_REG (PR_BASE + 0x000c)
+#define PRI2_COS_REG (PR_BASE + 0x0010)
+#define UNKNOWN_DEST_REG (PR_BASE + 0x0014)
+
+#define CPU_ACS_CTRL_REG (PR_BASE + 0x0018)
+#define CPU_ACS_DATA_REG (PR_BASE + 0x001c)
+
+#define MA_READ_REG (PR_BASE + 0x0020)
+#define TB_CTRL_REG (PR_BASE + 0x0024)
+#define RATE_REG (PR_BASE + 0x0028)
+#define BURST_REG (PR_BASE + 0x0048)
+#define EBURST_REG (PR_BASE + 0x0068)
+
+#define RULE_SEL_REG (PR_BASE + 0x0088)
+
+#define GEN_SFT_AGE_STB (PR_BASE + 0x008C)
+#define PR_ISR_REG (PR_BASE + 0x0090)
+#define PR_IMR_REG (PR_BASE + 0x0094)
+#define PR_IPR_REG (PR_BASE + 0x0098)
+#define BPDU_REG (PR_BASE + 0x00A4)
+
+/* Switching Engine Register Description */
+#define QLL_CMD_REG (SE_BASE)
+#define QLL_DATA_REG0 (SE_BASE + 0x0004)
+#define QLL_DATA_REG1 (SE_BASE + 0x0008)
+
+#define VLAN_MIBS_CMD_REG (SE_BASE + 0x000c)
+#define VLAN_MIBS_DATA_REG (SE_BASE + 0x0010)
+
+#define SD_CMD_REG (SE_BASE + 0x0014)
+#define SD_DATA_REGS0 (SE_BASE + 0x0018)
+#define SD_DATA_REGS1 (SE_BASE + 0x001C)
+#define SD_DATA_REGS2 (SE_BASE + 0x0020)
+
+#define VLAN_TBL_CMD_REG (SE_BASE + 0x0024)
+#define VLAN_TBL_DATA_REG (SE_BASE + 0x0028)
+
+#define FD_TBL_CMD_REG (SE_BASE + 0x002c)
+#define FD_TBL_DATA_REG (SE_BASE + 0x0030)
+
+#define SYMM_VLAN_REG (SE_BASE + 0x0038)
+#define PORT_AUTH (SE_BASE + 0x0048)
+#define CPU_LINK_OK_REG (SE_BASE + 0x0050)
+/* #define TRUNK_CTRL_REGS (SE_BASE + 0x0054) */
+#define MIRROR_PORT_REG (SE_BASE + 0x0064)
+
+#define ST_PT_REG (SE_BASE + 0x0068)
+#define JUMBO_ENABLE_REG (SE_BASE + 0x006C)
+#define STACK_PORT_REG (SE_BASE + 0x0074)
+#define EG_MON_REG (SE_BASE + 0x007C)
+#define VR_MIB_REG (SE_BASE + 0x0080)
+#define QUEUE_CMD_REGS (SE_BASE + 0x0090)
+
+#define GLOBAL_RX_WM_REG (SE_BASE + 0x0200)
+#define PORT0_RX_WM_REG0 (SE_BASE + 0x0204)
+#define PORT1_RX_WM_REG0 (SE_BASE + 0x0208)
+#define PORT2_RX_WM_REG0 (SE_BASE + 0x020C)
+
+#define PORT_RX_WM_REGS (SE_BASE + 0x0200)
+#define PORT_TX_WM_REGS (SE_BASE + 0x0300)
+#define PORT0_TX_WM_REG0 (SE_BASE + 0x0330)
+#define PORT1_TX_WM_REG0 (SE_BASE + 0x0338)
+#define PORT2_TX_WM_REG0 (SE_BASE + 0x0340)
+#define PORT0_TX_WM_REG1 (SE_BASE + 0x0334)
+#define PORT1_TX_WM_REG1 (SE_BASE + 0x033C)
+#define PORT2_TX_WM_REG1 (SE_BASE + 0x0344)
+
+
+#define QUEUE_STATUS_REGS (SE_BASE + 0x0400)
+
+#define SE_INT_STS_REG (SE_BASE + 0x08e0)
+#define SE_INT_MSK_REG_RD (SE_BASE + 0x08e4)
+#define SE_INT_MSK_REG_WR (SE_BASE + 0x08e8)
+#define SE_INT_PRI_REG_RD (SE_BASE + 0x08ec)
+#define SE_INT_PRI_REG_WR (SE_BASE + 0x08f0) /* address too be defined*/
+
+/***********************************************************************/
+/* Module : Ethernet Switch port related addresses and bits */
+/***********************************************************************/
+#define GPORT0_BASE (KSEG1+0x18006000)
+#define GPORT1_BASE (KSEG1+0x18007000)
+#define GPORT2_BASE (KSEG1+0x1800C000)
+
+#define PORTREG_BASE GPORT0_BASE
+
+#define SWITCH_P0_GMAC_REG (GPORT0_BASE + 0x0004)
+#define SWITCH_P0_GMAC_CTRL (GPORT0_BASE + 0x000C)
+#define SWITCH_P0_RTX_INT_STATUS (GPORT0_BASE + 0x0010)
+#define SWITCH_P0_RTX_INT_MASK (GPORT0_BASE + 0x0014)
+#define SWITCH_P0_INT_PRIORITY (GPORT0_BASE + 0x0018)
+#define SWITCH_P0_RX_CONF (GPORT0_BASE + 0x0400)
+#define SWITCH_P0_OFFSET0_REG (GPORT0_BASE + 0x0404)
+#define SWITCH_P0_OFFSET1_REG (GPORT0_BASE + 0x0408)
+#define SWITCH_P0_PORT_MASK0_REG (GPORT0_BASE + 0x0420)
+#define SWITCH_P0_PORT_MASK1_REG (GPORT0_BASE + 0x0424)
+#define SWITCH_P0_PORT_MASK2_REG (GPORT0_BASE + 0x0428)
+#define SWITCH_P0_PORT_MASK3_REG (GPORT0_BASE + 0x042C)
+#define SWITCH_P0_PORT_RULE0_REG (GPORT0_BASE + 0x0430)
+#define SWITCH_P0_PORT_RULE1_REG (GPORT0_BASE + 0x0434)
+#define SWITCH_P0_PORT_RULE2_REG (GPORT0_BASE + 0x0438)
+#define SWITCH_P0_PORT_RULE3_REG (GPORT0_BASE + 0x043C)
+#define SWITCH_P0_PORT_IKEY_SEL (GPORT0_BASE + 0x0440)
+#define SWITCH_P0_PORT_RX_VLAN_ID (GPORT0_BASE + 0x0450)
+#define SWITCH_P0_TX_CONF (GPORT0_BASE + 0x0800)
+#define SWITCH_P0_PORT_TX_VLAN_ID (GPORT0_BASE + 0x0804)
+#define SWITCH_P0_PORT_MIB_REG_0 (GPORT0_BASE + 0x0C00)
+#define SWITCH_P0_GMAC_MIB_REG_0 (GPORT0_BASE + 0x0C54)
+
+#define SWITCH_P1_GMAC_REG (GPORT1_BASE + 0x0004)
+#define SWITCH_P1_GMAC_CTRL (GPORT1_BASE + 0x000C)
+#define SWITCH_P1_RTX_INT_STATUS (GPORT1_BASE + 0x0010)
+#define SWITCH_P1_RTX_INT_MASK (GPORT1_BASE + 0x0014)
+#define SWITCH_P1_INT_PRIORITY (GPORT1_BASE + 0x0018)
+#define SWITCH_P1_RX_CONF (GPORT1_BASE + 0x0400)
+#define SWITCH_P1_OFFSET0_REG (GPORT1_BASE + 0x0404)
+#define SWITCH_P1_OFFSET1_REG (GPORT1_BASE + 0x0408)
+#define SWITCH_P1_PORT_MASK0_REG (GPORT1_BASE + 0x0420)
+#define SWITCH_P1_PORT_MASK1_REG (GPORT1_BASE + 0x0424)
+#define SWITCH_P1_PORT_MASK2_REG (GPORT1_BASE + 0x0428)
+#define SWITCH_P1_PORT_MASK3_REG (GPORT1_BASE + 0x042C)
+#define SWITCH_P1_PORT_RULE0_REG (GPORT1_BASE + 0x0430)
+#define SWITCH_P1_PORT_RULE1_REG (GPORT1_BASE + 0x0434)
+#define SWITCH_P1_PORT_RULE2_REG (GPORT1_BASE + 0x0438)
+#define SWITCH_P1_PORT_RULE3_REG (GPORT1_BASE + 0x043C)
+#define SWITCH_P1_PORT_IKEY_SEL (GPORT1_BASE + 0x0440)
+#define SWITCH_P1_PORT_RX_VLAN_ID (GPORT1_BASE + 0x0450)
+#define SWITCH_P1_TX_CONF (GPORT1_BASE + 0x0800)
+#define SWITCH_P1_PORT_TX_VLAN_ID (GPORT1_BASE + 0x0804)
+#define SWITCH_P1_PORT_MIB_REG_0 (GPORT1_BASE + 0x0C00)
+#define SWITCH_P1_GMAC_MIB_REG_0 (GPORT1_BASE + 0x0C54)
+
+#define SWITCH_P2_GMAC_REG (GPORT2_BASE + 0x0004)
+#define SWITCH_P2_GMAC_CTRL (GPORT2_BASE + 0x000C)
+#define SWITCH_P2_RTX_INT_STATUS (GPORT2_BASE + 0x0010)
+#define SWITCH_P2_RTX_INT_MASK (GPORT2_BASE + 0x0014)
+#define SWITCH_P2_INT_PRIORITY (GPORT2_BASE + 0x0018)
+#define SWITCH_P2_MDIO_ID_1 (GPORT2_BASE + 0x00A8)
+#define SWITCH_P2_PAUSE_CTL_1 (GPORT2_BASE + 0x00B0)
+#define SWITCH_P2_MDIO_MOD_SEL (GPORT2_BASE + 0x00B4)
+#define SWITCH_P2_MDIO_ACC_0 (GPORT2_BASE + 0x00B8)
+#define SWITCH_P2_RX_CONF (GPORT2_BASE + 0x0400)
+#define SWITCH_P2_OFFSET0_REG (GPORT2_BASE + 0x0404)
+#define SWITCH_P2_OFFSET1_REG (GPORT2_BASE + 0x0408)
+#define SWITCH_P2_PORT_MASK0_REG (GPORT2_BASE + 0x0420)
+#define SWITCH_P2_PORT_MASK1_REG (GPORT2_BASE + 0x0424)
+#define SWITCH_P2_PORT_MASK2_REG (GPORT2_BASE + 0x0428)
+#define SWITCH_P2_PORT_MASK3_REG (GPORT2_BASE + 0x042C)
+#define SWITCH_P2_PORT_RULE0_REG (GPORT2_BASE + 0x0430)
+#define SWITCH_P2_PORT_RULE1_REG (GPORT2_BASE + 0x0434)
+#define SWITCH_P2_PORT_RULE2_REG (GPORT2_BASE + 0x0438)
+#define SWITCH_P2_PORT_RULE3_REG (GPORT2_BASE + 0x043C)
+#define SWITCH_P2_PORT_IKEY_SEL (GPORT2_BASE + 0x0440)
+#define SWITCH_P2_PORT_RX_VLAN_ID (GPORT2_BASE + 0x0450)
+#define SWITCH_P2_TX_CONF (GPORT2_BASE + 0x0800)
+#define SWITCH_P2_PORT_TX_VLAN_ID (GPORT2_BASE + 0x0804)
+#define SWITCH_P2_PORT_MIB_REG_0 (GPORT2_BASE + 0x0C00)
+#define SWITCH_P2_GMAC_MIB_REG_0 (GPORT2_BASE + 0x0C54)
+
+#define MDIO_MOD_SEL SWITCH_P2_MDIO_MOD_SEL
+#define SWITCH_MDIO_ACC SWITCH_P2_MDIO_ACC_0
+#define SWITCH_MDIO_ID SWITCH_P2_MDIO_ID_1
+/* #define TX_CONFIG_REG SWITCH_P0_TX_CONF */
+
+#define SWITCH_PMAC_HD_CTL (GPORT2_BASE + 0x0070)
+#define SWITCH_PMAC_SA1 (GPORT2_BASE + 0x0074)
+#define SWITCH_PMAC_SA2 (GPORT2_BASE + 0x0078)
+#define SWITCH_PMAC_DA1 (GPORT2_BASE + 0x007C)
+#define SWITCH_PMAC_DA2 (GPORT2_BASE + 0x0080)
+#define SWITCH_PMAC_VLAN (GPORT2_BASE + 0x0084)
+#define SWITCH_PMAC_TX_IPG (GPORT2_BASE + 0x0088)
+#define SWITCH_PMAC_RX_IPG (GPORT2_BASE + 0x008C)
+
--- /dev/null
+#define FLASH_STRAP 0x1
+#define MII_0_STRAP 0x2
+#define MII_1_STRAP 0x3
+#define ASC_STRAP 0x4
+#define SFLASH_STRAP 0x5
+#define RESERVE_STRAP 0x6
+#define PRODUCT_TEST_STRAP 0x7
+#define PIN_STRAP_MASK 0x001C0000
+#define PIN_STRAP_SHIFT 18
+#define PIN_STRAP 0xB0100914
+#define SDRAM_WIDTH_MASK 0x400000
+#define SDRAM_WIDTH_SHIFT 22
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for the DANUBE board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+#define EXCEPTION_BASE 0x200
+
+/*****************************************************************************
+ * DANUBE
+ *****************************************************************************/
+/* lock cache for C program stack */
+/* points to ROM */
+/* stack size is 16K */
+#define LOCK_DCACHE_ADDR 0x9FC00000
+#define LOCK_DCACHE_SIZE 0x1000
+#define CFG_EBU_BOOTWORD 0x688c688c
+
+#define CFG_HZ (danube_get_cpuclk() / 2)
+
+
+/*
+ * Memory layout
+ */
+//#define CFG_SDRAM_BASE 0x80080000
+#define CFG_CACHE_LOCK_SIZE LOCK_DCACHE_SIZE
+#define CFG_INIT_SP_OFFSET CFG_CACHE_LOCK_SIZE
+
+/*
+ * Cache settings
+ */
+#define CFG_CACHE_SIZE 16384
+#define CFG_CACHE_LINES 32
+#define CFG_CACHE_WAYS 4
+#define CFG_CACHE_SETS 128
+
+#define CFG_ICACHE_SIZE CFG_CACHE_SIZE
+#define CFG_DCACHE_SIZE CFG_CACHE_SIZE
+#define CFG_CACHELINE_SIZE CFG_CACHE_LINES
+
+#endif /* __CONFIG_H */
--- /dev/null
+#ifndef _BOOT_H
+#define _BOOT_H
+
+/* All this should be defined somewhere in danube.h later... */
+
+#define MPS_SRAM_BASE_ADDRESS 0xBF200000
+#define MPS_SRAM_BOOT_OFFSET 0x1C0
+
+/* Offset for CPU1 (both CPUs have same register set) */
+#define BOOT_BASE_ADDRESS (MPS_SRAM_BASE_ADDRESS + MPS_SRAM_BOOT_OFFSET)
+#define BOOT_CPU_OFFSET 0x20
+
+
+#ifdef __ASSEMBLY__
+#define BOOT_RVEC (BOOT_BASE_ADDRESS + 0x00)
+#define BOOT_NVEC (BOOT_BASE_ADDRESS + 0x04)
+#define BOOT_EVEC (BOOT_BASE_ADDRESS + 0x08)
+#define BOOT_CP0_CAUSE (BOOT_BASE_ADDRESS + 0x0C)
+#define BOOT_CP0_EPC (BOOT_BASE_ADDRESS + 0x10)
+#define BOOT_CP0_EEPC (BOOT_BASE_ADDRESS + 0x14)
+#define BOOT_SIZE (BOOT_BASE_ADDRESS + 0x18) /* for CPU1 */
+#define BOOT_RCU_SR (BOOT_BASE_ADDRESS + 0x18) /* for CPU0 */
+#define BOOT_CFG_STAT (BOOT_BASE_ADDRESS + 0x1C)
+#else
+#define BOOT_RVEC(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x00)
+#define BOOT_NVEC(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x04)
+#define BOOT_EVEC(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x08)
+#define BOOT_CP0_STATUS(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x0C)
+#define BOOT_CP0_EPC(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x10)
+#define BOOT_CP0_EEPC(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x14)
+#define BOOT_SIZE(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x18) /* for CPU1 */
+#define BOOT_RCU_SR(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x18) /* for CPU0 */
+#define BOOT_CFG_STAT(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x1C)
+#endif
+
+#define BOOT_CFG_NOR 0x01
+#define BOOT_CFG_MII 0x02
+#define BOOT_CFG_PCI 0x03
+#define BOOT_CFG_ASC 0x04
+#define BOOT_CFG_SFLASH 0x05
+#define BOOT_CFG_NAND 0x06
+#define BOOT_CFG_RMII 0x07
+#define BOOT_CFG_TEST 0x00
+
+#define BOOT_NUM_RETRY 3
+
+#define BOOT_STAT_MASK_ALL 0x0000FFFF
+#define BOOT_STAT_MASK_STAT 0x0000F000
+#define BOOT_STAT_MASK_BERR 0x00000F00
+#define BOOT_STAT_MASK_BSTRAP 0x000000F0
+#define BOOT_STAT_MASK_BMODULE 0x0000000F
+
+#define BOOT_STAT_INIT 0x00000000
+#define BOOT_STAT_BSTRAP 0x00001000
+#define BOOT_STAT_RETRY 0x00002000
+#define BOOT_STAT_START 0x00003000
+#define BOOT_STAT_HALT 0x0000F000
+
+#define BOOT_ERR_NO_RVEC 0x00000100
+#define BOOT_ERR_NO_NVEC 0x00000200
+#define BOOT_ERR_NO_EVEC 0x00000300
+#define BOOT_ERR_BSTRAP 0x00000400
+#define BOOT_ERR_EXC 0x00000800
+
+#ifndef __ASSEMBLY__
+void boot_set_status( u32 status, u32 mask);
+void boot_set_config( u32 config);
+void boot_set_rvec( u32 vector);
+void boot_set_size( u32 size);
+void boot_sdbg( u8* string, u32 value);
+void boot_error( u32 berr);
+int boot_from_ebu(void);
+void _boot_rvec(void);
+typedef struct
+{
+ u32 cpu; /** CPU number */
+ u32 config; /** Boot configuration */
+ u32 endian; /** CPU endianess */
+ u32 debug; /** Debug mode */
+ u32 (*exit)(void); /** application vector */
+} boot_data;
+
+extern boot_data bootrom;
+#endif
+
+#endif /* #ifdef _BOOT_H */
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for the danube board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/ifx_cfg.h>
+
+#define USE_REFERENCE_BOARD
+//#define USE_EVALUATION_BOARD
+
+#define DANUBE_BOOT_FROM_EBU
+#define DANUBE_USE_DDR_RAM
+
+#ifdef DANUBE_USE_DDR_RAM
+//#define DANUBE_DDR_RAM_111M
+#define DANUBE_DDR_RAM_166M
+//#define PROMOSDDR400
+//#define DDR_SAMSUNG_166M
+//#define DDR_PSC_166M
+//#define DANUBE_DDR_RAM_133M
+#define DANUBE_DDR_RAM_SIZE 32 /* 32M DDR-DRAM for reference board */
+#endif
+#define CLK_OUT2_25MHZ
+#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
+#define CONFIG_DANUBE 1 /* on a danube Board */
+#define RAM_SIZE 0x2000000 /*32M ram*/
+
+#define CPU_CLOCK_RATE 235000000 /* 235 MHz clock for the MIPS core */
+
+#define INFINEON_EBU_BOOTCFG 0x688C688C /* CMULT = 8 for 150 MHz */
+
+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
+
+#define CONFIG_BAUDRATE 115200
+
+#define DEBUG_PARSER 2
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 300, 9600, 19200, 38400, 57600, 115200 }
+
+#ifndef CFG_HEAD_CODE
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#endif
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+/* by MarsLin 2005/05/10, to support different hardware configuations */
+//#define CONFIG_EXTRA_ENV_SETTINGS <configs/ifx_extra_env.h>
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ethaddr=11:22:33:44:55:66\0" \
+ "serverip=192.168.45.100\0" \
+ "ipaddr=192.168.45.108\0" \
+ "update_uboot=tftp 0x80500000 u-boot.ifx;era 1:0-10; cp.b 0x80500000 0xb0000000 0x10000\0"
+
+#define CONFIG_BOOTCOMMAND "run flash_flash"
+
+#define CONFIG_COMMANDS_YES (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DHRYSTONE | \
+ CFG_CMD_NET )
+
+#define CONFIG_COMMANDS_NO (CFG_CMD_NFS | \
+ CFG_CMD_FPGA | \
+ CFG_CMD_IMLS | \
+ CFG_CMD_ITEST | \
+ CFG_CMD_XING | \
+ CFG_CMD_IMI | \
+ CFG_CMD_BMP | \
+ CFG_CMD_BOOTD | \
+ CFG_CMD_CONSOLE | \
+ CFG_CMD_LOADS | \
+ CFG_CMD_LOADB )
+
+#define CONFIG_COMMANDS (CONFIG_COMMANDS_YES & ~CONFIG_COMMANDS_NO)
+
+#if 0
+ CFG_CMD_DHCP
+ CFG_CMD_ELF
+ CFG_CMD_NAND
+#endif
+
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "DANUBE # " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args*/
+
+#define CFG_MALLOC_LEN 128*1024
+
+#define CFG_BOOTPARAMS_LEN 128*1024
+
+#define CFG_HZ (CPU_CLOCK_RATE / 2)
+
+#define CFG_LOAD_ADDR 0x80100000 /* default load address */
+
+#define CFG_MEMTEST_START 0x80100000
+#define CFG_MEMTEST_END 0x80400000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT (135) /* max number of sectors on one chip */
+
+#define PHYS_FLASH_1 0xB0000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2 0xB4000000 /* Flash Bank #2 */
+
+#define BOOTSTRAP_TEXT_BASE 0xb0000000
+
+/* The following #defines are needed to get flash environment right */
+#define CFG_MONITOR_BASE UBOOT_RAM_TEXT_BASE /* board/danube/config.mk. = 0xA0800000 */
+#define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE /* board/danube/config.mk. = 0xA0800000 */
+#define CFG_MONITOR_LEN (256 << 10)
+
+#define CFG_INIT_SP_OFFSET 0x400000
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (20 * CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (20 * CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH 1
+//#define CFG_ENV_IS_NOWHERE 1
+//#define CFG_ENV_IS_IN_NVRAM 1
+/* Address and size of Primary Environment Sector */
+#define CFG_ENV_ADDR IFX_CFG_FLASH_UBOOT_CFG_START_ADDR
+#define CFG_ENV_SIZE IFX_CFG_FLASH_UBOOT_CFG_SIZE
+
+#define CONFIG_FLASH_16BIT
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_DANUBE_SWITCH
+#define CONFIG_NET_MULTI
+#define CONFIG_ENV_OVERWRITE
+
+#define EXCEPTION_BASE 0x200
+
+/**
+ *\brief definition for nand
+ *
+ */
+#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_ChipID_UNKNOWN 0x00
+#define SECTORSIZE 512
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+
+#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
+#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
+
+#define NAND_DISABLE_CE(nand)
+#define NAND_ENABLE_CE(nand)
+#define NAND_WAIT_READY(nand)
+#define WRITE_NAND_COMMAND(d, adr)
+#define WRITE_NAND_ADDRESS(d, adr)
+#define WRITE_NAND(d, adr)
+#define READ_NAND(adr)
+/* the following are NOP's in our implementation */
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+
+
+
+#define NAND_BASE_ADDRESS 0xB4000000
+
+#define NAND_WRITE(addr, val) *((u8*)(NAND_BASE_ADDRESS | (addr))) = val;while((*EBU_NAND_WAIT & 0x08) == 0);
+#define NAND_READ(addr, val) val = *((u8*)(NAND_BASE_ADDRESS | (addr)))
+#define NAND_CE_SET
+#define NAND_CE_CLEAR
+#define NAND_READY ( ((*EBU_NAND_WAIT)&0x07) == 7)
+#define NAND_READY_CLEAR *EBU_NAND_WAIT = 0;
+#define WRITE_CMD 0x18
+#define WRITE_ADDR 0x14
+#define WRITE_LADDR 0x10
+#define WRITE_DATA 0x10
+#define READ_DATA 0x10
+#define READ_LDATA 0x00
+#define ACCESS_WAIT
+#define IFX_ATC_NAND 0xc176
+#define IFX_BTC_NAND 0xc166
+#define ST_512WB2_NAND 0x2076
+
+#define NAND_OK 0x00000000 /* Bootstrap succesful, start address in BOOT_RVEC */
+#define NAND_ERR 0x80000000
+#define NAND_ACC_TIMEOUT (NAND_ERR | 0x00000001)
+#define NAND_ACC_ERR (NAND_ERR | 0x00000002)
+
+
+/*****************************************************************************
+ * DANUBE
+ *****************************************************************************/
+/* lock cache for C program stack */
+/* points to ROM */
+/* stack size is 16K */
+#define LOCK_DCACHE_ADDR 0x9FC00000
+#define LOCK_DCACHE_SIZE 0x1000
+
+/*
+ * Memory layout
+ */
+#define CFG_SDRAM_BASE 0x80000000
+#define CFG_SDRAM_BASE_UNCACHE 0xA0000000
+#define CFG_CACHE_LOCK_SIZE LOCK_DCACHE_SIZE
+
+/*
+ * Cache settings
+ */
+#define CFG_CACHE_SIZE 16384
+#define CFG_CACHE_LINES 32
+#define CFG_CACHE_WAYS 4
+#define CFG_CACHE_SETS 128
+
+#define CFG_ICACHE_SIZE CFG_CACHE_SIZE
+#define CFG_DCACHE_SIZE CFG_CACHE_SIZE
+#define CFG_CACHELINE_SIZE CFG_CACHE_LINES
+
+#endif /* __CONFIG_H */
--- /dev/null
+/* ============================================================================
+ * Copyright (C) 2003[- 2004] ? Infineon Technologies AG.
+ *
+ * All rights reserved.
+ * ============================================================================
+ *
+ * ============================================================================
+ *
+ * This document contains proprietary information belonging to Infineon
+ * Technologies AG. Passing on and copying of this document, and communication
+ * of its contents is not permitted without prior written authorisation.
+ *
+ * ============================================================================
+ *
+ * File Name: ifx_cfg.h
+ * Author : Mars Lin (mars.lin@infineon.com)
+ * Date:
+ *
+ * ===========================================================================
+ *
+ * Project:
+ * Block:
+ *
+ * ===========================================================================
+ * Contents: This file contains the data structures and definitions used
+ * by the core iptables and the sip alg modules.
+ * ===========================================================================
+ * References:
+ */
+
+/*
+ * This file contains the configuration parameters for the IFX board.
+ */
+#ifndef _DANUBE_CFG_H_
+#define _DANUBE_CFG_H_
+
+/*-----------------------------------------------------------------------
+ * U-Boot/Kernel configurations
+ */
+#define IFX_CFG_UBOOT_DEFAULT_CFG_IPADDR "172.20.80.100"
+#define IFX_CFG_UBOOT_DEFAULT_CFG_SERVERIP "172.20.80.2"
+#define IFX_CFG_UBOOT_DEFAULT_CFG_ETHADDR "00:E0:92:00:01:40"
+#define IFX_CFG_UBOOT_DEFAULT_CFG_NETDEV "eth1"
+#define IFX_CFG_UBOOT_DEFAULT_CFG_BAUDRATE "115200"
+#define IFX_CFG_UBOOT_LOAD_ADDRESS "0x80800000"
+
+/* End of U-Boot/Kernel configurations
+ *-----------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------
+ * Board specific configurations
+ */
+#ifdef IFX_CONFIG_MEMORY_SIZE
+ #define IFX_CFG_MEM_SIZE 31
+#else
+ #error "ERROR!! Define memory size first!"
+#endif
+
+//2MB flash partition
+#if (IFX_CONFIG_FLASH_SIZE == 2)
+#define IFX_CFG_FLASH_PARTITIONS_INFO \
+ "part0_begin=0xB0000000\0" \
+ "part1_begin=0xB0010000\0" \
+ "part2_begin=0xB0050000\0" \
+ "total_part=3\0"
+
+#define IFX_CFG_FLASH_DATA_BLOCKS_INFO \
+ "data_block0=" IFX_CFG_FLASH_UBOOT_IMAGE_BLOCK_NAME "\0" \
+ "data_block1=" IFX_CFG_FLASH_FIRMWARE_IMAGE_BLOCK_NAME "\0" \
+ "data_block2=" IFX_CFG_FLASH_ROOTFS_IMAGE_BLOCK_NAME "\0" \
+ "data_block3=" IFX_CFG_FLASH_KERNEL_IMAGE_BLOCK_NAME "\0" \
+ "data_block4=" IFX_CFG_FLASH_SYSTEM_CFG_BLOCK_NAME "\0" \
+ "data_block5=" IFX_CFG_FLASH_UBOOT_CFG_BLOCK_NAME "\0" \
+ "data_block6=" IFX_CFG_FLASH_FIRMWARE_DIAG_BLOCK_NAME "\0" \
+ "data_block7=" IFX_CFG_FLASH_CALIBRATION_CFG_BLOCK_NAME "\0" \
+ "total_db=8\0"
+
+ #define IFX_CFG_FLASH_UBOOT_IMAGE_BLOCK_NAME "uboot"
+ #define IFX_CFG_FLASH_UBOOT_IMAGE_START_ADDR 0xB0000000
+ #define IFX_CFG_FLASH_UBOOT_IMAGE_SIZE 0
+ #define IFX_CFG_FLASH_UBOOT_IMAGE_MTDBLOCK_NAME "/dev/mtdblock0"
+
+ #define IFX_CFG_FLASH_FIRMWARE_IMAGE_BLOCK_NAME "firmware"
+ #define IFX_CFG_FLASH_FIRMWARE_IMAGE_START_ADDR 0xB0010000
+ #define IFX_CFG_FLASH_FIRMWARE_IMAGE_SIZE 0
+ #define IFX_CFG_FLASH_FIRMWARE_IMAGE_MTDBLOCK_NAME "/dev/mtdblock1"
+
+ #define IFX_CFG_FLASH_ROOTFS_IMAGE_BLOCK_NAME "rootfs"
+ #define IFX_CFG_FLASH_ROOTFS_IMAGE_START_ADDR 0xB0050000
+ #define IFX_CFG_FLASH_ROOTFS_IMAGE_SIZE 0
+ #define IFX_CFG_FLASH_ROOTFS_IMAGE_MTDBLOCK_NAME "/dev/mtdblock2"
+
+ #define IFX_CFG_FLASH_KERNEL_IMAGE_BLOCK_NAME "kernel"
+ #define IFX_CFG_FLASH_KERNEL_IMAGE_START_ADDR 0xB01FCFFF
+ #define IFX_CFG_FLASH_KERNEL_IMAGE_SIZE 0
+
+ #define IFX_CFG_FLASH_SYSTEM_CFG_BLOCK_NAME "sysconfig"
+ #define IFX_CFG_FLASH_SYSTEM_CFG_START_ADDR 0xB01FD000
+ #define IFX_CFG_FLASH_SYSTEM_CFG_SIZE 0
+ #define IFX_CFG_FLASH_SYSTEM_CFG_END_ADDR 0xB01FEFFF
+
+ #define IFX_CFG_FLASH_UBOOT_CFG_BLOCK_NAME "ubootconfig"
+ #define IFX_CFG_FLASH_UBOOT_CFG_START_ADDR 0xB01FF000
+ #define IFX_CFG_FLASH_UBOOT_CFG_SIZE 0x0C00
+ #define IFX_CFG_FLASH_UBOOT_CFG_END_ADDR 0xB01FFBFF
+
+ #define IFX_CFG_FLASH_FIRMWARE_DIAG_BLOCK_NAME "fwdiag"
+ #define IFX_CFG_FLASH_FIRMWARE_DIAG_START_ADDR 0xB31FFC00
+ #define IFX_CFG_FLASH_FIRMWARE_DIAG_SIZE 0x0200
+ #define IFX_CFG_FLASH_FIRMWARE_DIAG_END_ADDR 0xB01FFDFF
+
+ #define IFX_CFG_FLASH_CALIBRATION_CFG_BLOCK_NAME "calibration"
+ #define IFX_CFG_FLASH_CALIBRATION_CFG_START_ADDR 0xB01FFE00
+ #define IFX_CFG_FLASH_CALIBRATION_CFG_SIZE 0x0200
+ #define IFX_CFG_FLASH_CALIBRATION_CFG_END_ADDR 0xB01FFFFF
+
+ #define IFX_CFG_FLASH_END_ADDR 0xB01FFFFF
+
+//4MB flash partition
+#elif (IFX_CONFIG_FLASH_SIZE == 4)
+#define IFX_CFG_FLASH_PARTITIONS_INFO \
+ "part0_begin=0xB0000000\0" \
+ "part1_begin=0xB0020000\0" \
+ "part2_begin=0xB0060000\0" \
+ "total_part=3\0"
+
+#define IFX_CFG_FLASH_DATA_BLOCKS_INFO \
+ "data_block0=" IFX_CFG_FLASH_UBOOT_IMAGE_BLOCK_NAME "\0" \
+ "data_block1=" IFX_CFG_FLASH_FIRMWARE_IMAGE_BLOCK_NAME "\0" \
+ "data_block2=" IFX_CFG_FLASH_ROOTFS_IMAGE_BLOCK_NAME "\0" \
+ "data_block3=" IFX_CFG_FLASH_KERNEL_IMAGE_BLOCK_NAME "\0" \
+ "data_block4=" IFX_CFG_FLASH_SYSTEM_CFG_BLOCK_NAME "\0" \
+ "data_block5=" IFX_CFG_FLASH_UBOOT_CFG_BLOCK_NAME "\0" \
+ "data_block6=" IFX_CFG_FLASH_VOIP_CFG_BLOCK_NAME "\0" \
+ "data_block7=" IFX_CFG_FLASH_FIRMWARE_DIAG_BLOCK_NAME "\0" \
+ "data_block8=" IFX_CFG_FLASH_CALIBRATION_CFG_BLOCK_NAME "\0" \
+ "total_db=9\0"
+
+ #define IFX_CFG_FLASH_UBOOT_IMAGE_BLOCK_NAME "uboot"
+ #define IFX_CFG_FLASH_UBOOT_IMAGE_START_ADDR 0xB0000000
+ #define IFX_CFG_FLASH_UBOOT_IMAGE_SIZE 0
+ #define IFX_CFG_FLASH_UBOOT_IMAGE_MTDBLOCK_NAME "/dev/mtdblock0"
+
+ #define IFX_CFG_FLASH_FIRMWARE_IMAGE_BLOCK_NAME "firmware"
+ #define IFX_CFG_FLASH_FIRMWARE_IMAGE_START_ADDR 0xB0020000
+ #define IFX_CFG_FLASH_FIRMWARE_IMAGE_SIZE 0
+ #define IFX_CFG_FLASH_FIRMWARE_IMAGE_MTDBLOCK_NAME "/dev/mtdblock1"
+
+ #define IFX_CFG_FLASH_ROOTFS_IMAGE_BLOCK_NAME "rootfs"
+ #define IFX_CFG_FLASH_ROOTFS_IMAGE_START_ADDR 0xB0060000
+ #define IFX_CFG_FLASH_ROOTFS_IMAGE_SIZE 0
+ #define IFX_CFG_FLASH_ROOTFS_IMAGE_MTDBLOCK_NAME "/dev/mtdblock2"
+
+ #define IFX_CFG_FLASH_KERNEL_IMAGE_BLOCK_NAME "kernel"
+ #define IFX_CFG_FLASH_KERNEL_IMAGE_START_ADDR 0xB03F4FFF
+ #define IFX_CFG_FLASH_KERNEL_IMAGE_SIZE 0
+
+ #define IFX_CFG_FLASH_SYSTEM_CFG_BLOCK_NAME "sysconfig"
+ #define IFX_CFG_FLASH_SYSTEM_CFG_START_ADDR 0xB03F5000
+ #define IFX_CFG_FLASH_SYSTEM_CFG_SIZE 0x2000
+ #define IFX_CFG_FLASH_SYSTEM_CFG_END_ADDR 0xB03F6FFF
+
+ #define IFX_CFG_FLASH_UBOOT_CFG_BLOCK_NAME "ubootconfig"
+ #define IFX_CFG_FLASH_UBOOT_CFG_START_ADDR 0xB03F7000
+ #define IFX_CFG_FLASH_UBOOT_CFG_SIZE 0x0C00
+ #define IFX_CFG_FLASH_UBOOT_CFG_END_ADDR 0xB03F7BFF
+
+ #define IFX_CFG_FLASH_VOIP_CFG_BLOCK_NAME "voip"
+ #define IFX_CFG_FLASH_VOIP_CFG_START_ADDR 0xB03F7C00
+ #define IFX_CFG_FLASH_VOIP_CFG_SIZE 0x8000
+ #define IFX_CFG_FLASH_VOIP_CFG_END_ADDR 0xB03FFBFF
+
+ #define IFX_CFG_FLASH_FIRMWARE_DIAG_BLOCK_NAME "fwdiag"
+ #define IFX_CFG_FLASH_FIRMWARE_DIAG_START_ADDR 0xB03FFC00
+ #define IFX_CFG_FLASH_FIRMWARE_DIAG_SIZE 0x0200
+ #define IFX_CFG_FLASH_FIRMWARE_DIAG_END_ADDR 0xB03FFDFF
+
+ #define IFX_CFG_FLASH_CALIBRATION_CFG_BLOCK_NAME "calibration"
+ #define IFX_CFG_FLASH_CALIBRATION_CFG_START_ADDR 0xB03FFE00
+ #define IFX_CFG_FLASH_CALIBRATION_CFG_SIZE 0x0200
+ #define IFX_CFG_FLASH_CALIBRATION_CFG_END_ADDR 0xB03FFFFF
+
+ #define IFX_CFG_FLASH_END_ADDR 0xB03FFFFF
+//8MB flash definition
+#elif (IFX_CONFIG_FLASH_SIZE == 8)
+#define IFX_CFG_FLASH_PARTITIONS_INFO \
+ "part0_begin=0xB0000000\0" \
+ "part1_begin=0xB0080000\0" \
+ "part2_begin=0xB0280000\0" \
+ "part3_begin=0xB0790000\0" \
+ "part4_begin=0xB07A0000\0" \
+ "part5_begin=0xB07E0000\0" \
+ "total_part=6\0"
+
+#define IFX_CFG_FLASH_DATA_BLOCKS_INFO \
+ "data_block0=" IFX_CFG_FLASH_UBOOT_IMAGE_BLOCK_NAME "\0" \
+ "data_block1=" IFX_CFG_FLASH_KERNEL_IMAGE_BLOCK_NAME "\0" \
+ "data_block2=" IFX_CFG_FLASH_ROOTFS_IMAGE_BLOCK_NAME "\0" \
+ "data_block3=" IFX_CFG_FLASH_SYSTEM_CFG_BLOCK_NAME "\0" \
+ "data_block4=" IFX_CFG_FLASH_FIRMWARE_IMAGE_BLOCK_NAME "\0" \
+ "data_block5=" IFX_CFG_FLASH_UBOOT_CFG_BLOCK_NAME "\0" \
+ "total_db=6\0"
+
+ #define IFX_CFG_FLASH_UBOOT_IMAGE_BLOCK_NAME "uboot"
+ #define IFX_CFG_FLASH_UBOOT_IMAGE_START_ADDR 0xB0000000
+ #define IFX_CFG_FLASH_UBOOT_IMAGE_END_ADDR 0xB007FFFF
+ #define IFX_CFG_FLASH_UBOOT_IMAGE_SIZE 0x00080000
+ #define IFX_CFG_FLASH_UBOOT_IMAGE_MTDBLOCK_NAME "/dev/mtdblock0"
+
+ #define IFX_CFG_FLASH_KERNEL_IMAGE_BLOCK_NAME "kernel"
+ #define IFX_CFG_FLASH_KERNEL_IMAGE_START_ADDR 0xB0080000
+ #define IFX_CFG_FLASH_KERNEL_IMAGE_SIZE 0x200000
+ #define IFX_CFG_FLASH_KERNEL_IMAGE_END_ADDR 0xB017FFFF
+ #define IFX_CFG_FLASH_KERNEL_IMAGE_MTDBLOCK_NAME "/dev/mtdblock1"
+
+ #define IFX_CFG_FLASH_ROOTFS_IMAGE_BLOCK_NAME "rootfs"
+ #define IFX_CFG_FLASH_ROOTFS_IMAGE_START_ADDR 0xB0280000
+ #define IFX_CFG_FLASH_ROOTFS_IMAGE_SIZE 0x00510000
+ #define IFX_CFG_FLASH_ROOTFS_IMAGE_END_ADDR 0xB078FFFF
+ #define IFX_CFG_FLASH_ROOTFS_IMAGE_MTDBLOCK_NAME "/dev/mtdblock2"
+
+ #define IFX_CFG_FLASH_SYSTEM_CFG_BLOCK_NAME "sysconfig"
+ #define IFX_CFG_FLASH_SYSTEM_CFG_START_ADDR 0xB0790000
+ #define IFX_CFG_FLASH_SYSTEM_CFG_SIZE 0x10000
+ #define IFX_CFG_FLASH_SYSTEM_CFG_END_ADDR 0xB079FFFF
+ #define IFX_CFG_FLASH_SYSTEM_CFG_MTDBLOCK_NAME "/dev/mtdblock3"
+
+ #define IFX_CFG_FLASH_FIRMWARE_IMAGE_BLOCK_NAME "firmware"
+ #define IFX_CFG_FLASH_FIRMWARE_IMAGE_START_ADDR 0xB07A0000
+ #define IFX_CFG_FLASH_FIRMWARE_IMAGE_SIZE 0x40000
+ #define IFX_CFG_FLASH_FIRMWARE_IMAGE_END_ADDR 0xB07DFFFF
+ #define IFX_CFG_FLASH_FIRMWARE_IMAGE_MTDBLOCK_NAME "/dev/mtdblock4"
+
+ #define IFX_CFG_FLASH_UBOOT_CFG_BLOCK_NAME "ubootconfig"
+ #define IFX_CFG_FLASH_UBOOT_CFG_START_ADDR 0xB07E0000
+ #define IFX_CFG_FLASH_UBOOT_CFG_END_ADDR 0xB07FFFFF
+ #define IFX_CFG_FLASH_UBOOT_CFG_SIZE 0x20000
+ #define IFX_CFG_FLASH_UBOOT_CFG_MTDBLOCK_NAME "/dev/mtdblock5"
+
+ #define IFX_CFG_FLASH_END_ADDR 0xB07FFFFF
+#else
+ #error "ERROR!! Define flash size first!"
+#endif
+/* End of Board specific configurations
+ *-----------------------------------------------------------------------
+ */
+
+#endif
--- /dev/null
+/* ============================================================================
+ * Copyright (C) 2003[- 2004] ? Infineon Technologies AG.
+ *
+ * All rights reserved.
+ * ============================================================================
+ *
+ * ============================================================================
+ *
+ * This document contains proprietary information belonging to Infineon
+ * Technologies AG. Passing on and copying of this document, and communication
+ * of its contents is not permitted without prior written authorisation.
+ *
+ * ============================================================================
+ *
+ * File Name: ifx_extra_env.h
+ * Author : Mars Lin (mars.lin@infineon.com)
+ * Date:
+ *
+ * ===========================================================================
+ *
+ * Project:
+ * Block:
+ *
+ * ===========================================================================
+ * Contents: This file contains the data structures and definitions used
+ * by the core iptables and the sip alg modules.
+ * ===========================================================================
+ * References:
+ */
+ "mem=" MK_STR(IFX_CONFIG_MEMORY_SIZE) "M\0"
+ "ipaddr=" IFX_CFG_UBOOT_DEFAULT_CFG_IPADDR "\0"
+ "serverip=" IFX_CFG_UBOOT_DEFAULT_CFG_SERVERIP "\0"
+ "ethaddr=" IFX_CFG_UBOOT_DEFAULT_CFG_ETHADDR "\0"
+ "netdev=eth0\0"
+ "baudrate=" IFX_CFG_UBOOT_DEFAULT_CFG_BAUDRATE "\0"
+ "loadaddr=" IFX_CFG_UBOOT_LOAD_ADDRESS "\0"
+ "rootpath=/tftpboot/nfsrootfs\0"
+ "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0"
+ "ramargs=setenv bootargs root=/dev/ram rw\0"
+ "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):$(netdev):on\0"
+ "addmisc=setenv bootargs $(bootargs) console=ttyS1,$(baudrate) ethaddr=$(ethaddr) mem=$(mem) panic=1\0"
+ "flash_nfs=run nfsargs addip addmisc;bootm $(kernel_addr)\0"
+ "ramdisk_addr=B0100000\0"
+ "flash_self=run ramargs addip addmisc;bootm $(kernel_addr) $(ramdisk_addr)\0"
+ "bootfile=uImage\0"
+ "net_nfs=tftp $(loadaddr) $(bootfile);run nfsargs addip addmisc;bootm\0"
+ "net_flash=tftp $(loadaddr) $(bootfile); run flashargs addip addmisc; bootm\0"
+ "u-boot=u-boot.ifx\0"
+ "jffs2fs=jffs2.img\0"
+ "rootfs=rootfs.img\0"
+ "firmware=firmware.img\0"
+ "load=tftp $(loadaddr) $(u-boot)\0"
+ "update=protect off 1:0-2;era 1:0-2;cp.b $(loadaddr) B0000000 $(filesize)\0"
+ "flashargs=setenv bootargs root=/dev/mtdblock2 ro rootfstype=squashfs\0"
+ "mtdargs=setenv bootargs root=/dev/mtdblock2 rw rootfstype=jffs2\0"
+ "flash_flash=run flashargs addip addmisc; bootm $(f_kernel_addr)\0"
+ "net_mtd=tftp $(loadaddr) $(bootfile); run mtdargs addip addmisc; bootm\0"
+ "flash_mtd=run mtdargs addip addmisc; bootm $(f_kernel_addr)\0"
+ "update_uboot=tftpboot $(loadaddr) $(u-boot);upgrade uboot $(loadaddr) $(filesize) 0\0"
+ "update_kernel=tftpboot $(loadaddr) $(bootfile);upgrade kernel $(loadaddr) $(filesize) 0\0"
+ "update_rootfs=tftpboot $(loadaddr) $(rootfs); upgrade rootfs $(loadaddr) $(filesize) 0\0"
+ "update_rootfs_1=tftpboot $(loadaddr) $(rootfs); erase 1:47-132; cp.b $(loadaddr) $(f_rootfs_addr) $(filesize)\0"
+ "update_jffs2=tftpboot $(loadaddr) $(rootfs); upgrade rootfs $(loadaddr) $(filesize) 0\0"
+ "update_jffs2_1=tftpboot $(loadaddr) $(jffs2fs); erase 1:47-132; cp.b $(loadaddr) $(f_rootfs_addr) $(filesize)\0"
+ "update_firmware=tftpboot $(loadaddr) $(firmware);upgrade firmware $(loadaddr) $(filesize) 0\0"
+ "reset_uboot_config=erase " MK_STR(IFX_CFG_FLASH_UBOOT_CFG_START_ADDR) " " MK_STR(IFX_CFG_FLASH_UBOOT_CFG_END_ADDR) "\0"
+ IFX_CFG_FLASH_PARTITIONS_INFO
+ "flash_end=" MK_STR(IFX_CFG_FLASH_END_ADDR) "\0"
+ IFX_CFG_FLASH_DATA_BLOCKS_INFO
+ "f_uboot_addr=" MK_STR(IFX_CFG_FLASH_UBOOT_IMAGE_START_ADDR) "\0"
+ "f_uboot_size=" MK_STR(IFX_CFG_FLASH_UBOOT_IMAGE_SIZE) "\0"
+ "f_ubootconfig_addr=" MK_STR(IFX_CFG_FLASH_UBOOT_CFG_START_ADDR) "\0"
+ "f_ubootconfig_size=" MK_STR(IFX_CFG_FLASH_UBOOT_CFG_SIZE) "\0"
+ "f_ubootconfig_end=" MK_STR(IFX_CFG_FLASH_UBOOT_CFG_END_ADDR) "\0"
+ "f_kernel_addr=" MK_STR(IFX_CFG_FLASH_KERNEL_IMAGE_START_ADDR) "\0"
+ "f_kernel_size=" MK_STR(IFX_CFG_FLASH_KERNEL_IMAGE_SIZE) "\0"
+ "f_kernel_end=" MK_STR(IFX_CFG_FLASH_KERNEL_IMAGE_END_ADDR) "\0"
+ "f_rootfs_addr=" MK_STR(IFX_CFG_FLASH_ROOTFS_IMAGE_START_ADDR) "\0"
+ "f_rootfs_size=" MK_STR(IFX_CFG_FLASH_ROOTFS_IMAGE_SIZE) "\0"
+ "f_rootfs_end=" MK_STR(IFX_CFG_FLASH_ROOTFS_IMAGE_END_ADDR) "\0"
+ "f_firmware_addr=" MK_STR(IFX_CFG_FLASH_FIRMWARE_IMAGE_START_ADDR) "\0"
+ "f_firmware_size=" MK_STR(IFX_CFG_FLASH_FIRMWARE_IMAGE_SIZE) "\0"
+ "f_sysconfig_addr=" MK_STR(IFX_CFG_FLASH_SYSTEM_CFG_START_ADDR) "\0"
+ "f_sysconfig_size=" MK_STR(IFX_CFG_FLASH_SYSTEM_CFG_SIZE) "\0"
+ /*
+ "f_fwdiag_addr=" MK_STR(IFX_CFG_FLASH_FIRMWARE_DIAG_START_ADDR) "\0"
+ "f_fwdiag_size=" MK_STR(IFX_CFG_FLASH_FIRMWARE_DIAG_SIZE) "\0"
+ "f_calibration_addr=" MK_STR(IFX_CFG_FLASH_CALIBRATION_CFG_START_ADDR) "\0"
+ "f_calibration_size=" MK_STR(IFX_CFG_FLASH_CALIBRATION_CFG_SIZE) "\0"
+#if (IFX_CONFIG_FLASH_SIZE == 4) || (IFX_CONFIG_FLASH_SIZE == 8)
+ "f_voip_addr=" MK_STR(IFX_CFG_FLASH_VOIP_CFG_START_ADDR) "\0"
+ "f_voip_size=" MK_STR(IFX_CFG_FLASH_VOIP_CFG_SIZE) "\0"
+#endif
+ */
--- /dev/null
+/*
+ LzmaDecode.c
+ LZMA Decoder (optimized for Speed version)
+
+ LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
+ http://www.7-zip.org/
+
+ LZMA SDK is licensed under two licenses:
+ 1) GNU Lesser General Public License (GNU LGPL)
+ 2) Common Public License (CPL)
+ It means that you can select one of these two licenses and
+ follow rules of that license.
+
+ SPECIAL EXCEPTION:
+ Igor Pavlov, as the author of this Code, expressly permits you to
+ statically or dynamically link your Code (or bind by name) to the
+ interfaces of this file without subjecting your linked Code to the
+ terms of the CPL or GNU LGPL. Any modifications or additions
+ to this file, however, are subject to the LGPL or CPL terms.
+*/
+
+#ifdef CONFIG_LZMA
+
+#include "LzmaDecode.h"
+
+#define kNumTopBits 24
+#define kTopValue ((UInt32)1 << kNumTopBits)
+
+#define kNumBitModelTotalBits 11
+#define kBitModelTotal (1 << kNumBitModelTotalBits)
+#define kNumMoveBits 5
+
+#define RC_READ_BYTE (*Buffer++)
+
+#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \
+ { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}
+
+#ifdef _LZMA_IN_CB
+
+
+#if 0
+#define RC_TEST { if (Buffer == BufferLim) \
+ { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) { printf("ERROR, %s, %d\n", __FILE__, __LINE__); return result; } \
+ BufferLim = Buffer + size; if (size == 0) { printf("ERROR, %s, %d\n", __FILE__, __LINE__); return LZMA_RESULT_DATA_ERROR; } }}
+#else
+
+#define RC_TEST { if (Buffer == BufferLim) \
+ { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) { return result; } \
+ BufferLim = Buffer + size; if (size == 0) { return LZMA_RESULT_DATA_ERROR; } }}
+#endif
+
+#define RC_INIT Buffer = BufferLim = 0; RC_INIT2
+
+#else
+
+#if 0
+#define RC_TEST { if (Buffer == BufferLim) { printf("ERROR, %s, %d\n", __FILE__, __LINE__); return LZMA_RESULT_DATA_ERROR; } }
+#else
+#define RC_TEST { if (Buffer == BufferLim) { return LZMA_RESULT_DATA_ERROR; } }
+#endif
+
+#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2
+
+#endif
+
+#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }
+
+#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)
+#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;
+#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;
+
+#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \
+ { UpdateBit0(p); mi <<= 1; A0; } else \
+ { UpdateBit1(p); mi = (mi + mi) + 1; A1; }
+
+#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)
+
+#define RangeDecoderBitTreeDecode(probs, numLevels, res) \
+ { int i = numLevels; res = 1; \
+ do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \
+ res -= (1 << numLevels); }
+
+
+#define kNumPosBitsMax 4
+#define kNumPosStatesMax (1 << kNumPosBitsMax)
+
+#define kLenNumLowBits 3
+#define kLenNumLowSymbols (1 << kLenNumLowBits)
+#define kLenNumMidBits 3
+#define kLenNumMidSymbols (1 << kLenNumMidBits)
+#define kLenNumHighBits 8
+#define kLenNumHighSymbols (1 << kLenNumHighBits)
+
+#define LenChoice 0
+#define LenChoice2 (LenChoice + 1)
+#define LenLow (LenChoice2 + 1)
+#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))
+#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))
+#define kNumLenProbs (LenHigh + kLenNumHighSymbols)
+
+
+#define kNumStates 12
+#define kNumLitStates 7
+
+#define kStartPosModelIndex 4
+#define kEndPosModelIndex 14
+#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))
+
+#define kNumPosSlotBits 6
+#define kNumLenToPosStates 4
+
+#define kNumAlignBits 4
+#define kAlignTableSize (1 << kNumAlignBits)
+
+#define kMatchMinLen 2
+
+#define IsMatch 0
+#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))
+#define IsRepG0 (IsRep + kNumStates)
+#define IsRepG1 (IsRepG0 + kNumStates)
+#define IsRepG2 (IsRepG1 + kNumStates)
+#define IsRep0Long (IsRepG2 + kNumStates)
+#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))
+#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))
+#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)
+#define LenCoder (Align + kAlignTableSize)
+#define RepLenCoder (LenCoder + kNumLenProbs)
+#define Literal (RepLenCoder + kNumLenProbs)
+
+#if Literal != LZMA_BASE_SIZE
+StopCompilingDueBUG
+#endif
+
+int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)
+{
+ unsigned char prop0;
+ if (size < LZMA_PROPERTIES_SIZE)
+ {
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf("ERROR: %s, %d\n", __FILE__, __LINE__);
+#endif
+ return LZMA_RESULT_DATA_ERROR;
+ }
+ prop0 = propsData[0];
+ if (prop0 >= (9 * 5 * 5))
+ {
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf("ERROR: %s, %d\n", __FILE__, __LINE__);
+#endif
+ return LZMA_RESULT_DATA_ERROR;
+ }
+ {
+ for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));
+ for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);
+ propsRes->lc = prop0;
+ /*
+ unsigned char remainder = (unsigned char)(prop0 / 9);
+ propsRes->lc = prop0 % 9;
+ propsRes->pb = remainder / 5;
+ propsRes->lp = remainder % 5;
+ */
+ }
+
+ #ifdef _LZMA_OUT_READ
+ {
+ int i;
+ propsRes->DictionarySize = 0;
+ for (i = 0; i < 4; i++)
+ propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8);
+ if (propsRes->DictionarySize == 0)
+ propsRes->DictionarySize = 1;
+ }
+ #endif
+ return LZMA_RESULT_OK;
+}
+
+#define kLzmaStreamWasFinishedId (-1)
+
+int LzmaDecode(CLzmaDecoderState *vs,
+ #ifdef _LZMA_IN_CB
+ ILzmaInCallback *InCallback,
+ #else
+ const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
+ #endif
+ unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)
+{
+ CProb *p = vs->Probs;
+ SizeT nowPos = 0;
+ Byte previousByte = 0;
+ UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;
+ UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;
+ int lc = vs->Properties.lc;
+
+ #ifdef _LZMA_OUT_READ
+
+ UInt32 Range = vs->Range;
+ UInt32 Code = vs->Code;
+ #ifdef _LZMA_IN_CB
+ const Byte *Buffer = vs->Buffer;
+ const Byte *BufferLim = vs->BufferLim;
+ #else
+ const Byte *Buffer = inStream;
+ const Byte *BufferLim = inStream + inSize;
+ #endif
+ int state = vs->State;
+ UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];
+ int len = vs->RemainLen;
+ UInt32 globalPos = vs->GlobalPos;
+ UInt32 distanceLimit = vs->DistanceLimit;
+
+ Byte *dictionary = vs->Dictionary;
+ UInt32 dictionarySize = vs->Properties.DictionarySize;
+ UInt32 dictionaryPos = vs->DictionaryPos;
+
+ Byte tempDictionary[4];
+
+ #ifndef _LZMA_IN_CB
+ *inSizeProcessed = 0;
+ #endif
+ *outSizeProcessed = 0;
+ if (len == kLzmaStreamWasFinishedId)
+ return LZMA_RESULT_OK;
+
+ if (dictionarySize == 0)
+ {
+ dictionary = tempDictionary;
+ dictionarySize = 1;
+ tempDictionary[0] = vs->TempDictionary[0];
+ }
+
+ if (len == kLzmaNeedInitId)
+ {
+ {
+ UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
+ UInt32 i;
+ for (i = 0; i < numProbs; i++)
+ p[i] = kBitModelTotal >> 1;
+ rep0 = rep1 = rep2 = rep3 = 1;
+ state = 0;
+ globalPos = 0;
+ distanceLimit = 0;
+ dictionaryPos = 0;
+ dictionary[dictionarySize - 1] = 0;
+ #ifdef _LZMA_IN_CB
+ RC_INIT;
+ #else
+ RC_INIT(inStream, inSize);
+ #endif
+ }
+ len = 0;
+ }
+ while(len != 0 && nowPos < outSize)
+ {
+ UInt32 pos = dictionaryPos - rep0;
+ if (pos >= dictionarySize)
+ pos += dictionarySize;
+ outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];
+ if (++dictionaryPos == dictionarySize)
+ dictionaryPos = 0;
+ len--;
+ }
+ if (dictionaryPos == 0)
+ previousByte = dictionary[dictionarySize - 1];
+ else
+ previousByte = dictionary[dictionaryPos - 1];
+
+ #else /* if !_LZMA_OUT_READ */
+
+ int state = 0;
+ UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;
+ int len = 0;
+ const Byte *Buffer;
+ const Byte *BufferLim;
+ UInt32 Range;
+ UInt32 Code;
+
+ #ifndef _LZMA_IN_CB
+ *inSizeProcessed = 0;
+ #endif
+ *outSizeProcessed = 0;
+
+ {
+ UInt32 i;
+ UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
+ for (i = 0; i < numProbs; i++)
+ p[i] = kBitModelTotal >> 1;
+ }
+
+ #ifdef _LZMA_IN_CB
+ RC_INIT;
+ #else
+ RC_INIT(inStream, inSize);
+ #endif
+
+ #endif /* _LZMA_OUT_READ */
+
+ while(nowPos < outSize)
+ {
+ CProb *prob;
+ UInt32 bound;
+ int posState = (int)(
+ (nowPos
+ #ifdef _LZMA_OUT_READ
+ + globalPos
+ #endif
+ )
+ & posStateMask);
+
+ prob = p + IsMatch + (state << kNumPosBitsMax) + posState;
+ IfBit0(prob)
+ {
+ int symbol = 1;
+ UpdateBit0(prob)
+ prob = p + Literal + (LZMA_LIT_SIZE *
+ (((
+ (nowPos
+ #ifdef _LZMA_OUT_READ
+ + globalPos
+ #endif
+ )
+ & literalPosMask) << lc) + (previousByte >> (8 - lc))));
+
+ if (state >= kNumLitStates)
+ {
+ int matchByte;
+ #ifdef _LZMA_OUT_READ
+ UInt32 pos = dictionaryPos - rep0;
+ if (pos >= dictionarySize)
+ pos += dictionarySize;
+ matchByte = dictionary[pos];
+ #else
+ matchByte = outStream[nowPos - rep0];
+ #endif
+ do
+ {
+ int bit;
+ CProb *probLit;
+ matchByte <<= 1;
+ bit = (matchByte & 0x100);
+ probLit = prob + 0x100 + bit + symbol;
+ RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)
+ }
+ while (symbol < 0x100);
+ }
+ while (symbol < 0x100)
+ {
+ CProb *probLit = prob + symbol;
+ RC_GET_BIT(probLit, symbol)
+ }
+ previousByte = (Byte)symbol;
+
+ outStream[nowPos++] = previousByte;
+ #ifdef _LZMA_OUT_READ
+ if (distanceLimit < dictionarySize)
+ distanceLimit++;
+
+ dictionary[dictionaryPos] = previousByte;
+ if (++dictionaryPos == dictionarySize)
+ dictionaryPos = 0;
+ #endif
+ if (state < 4) state = 0;
+ else if (state < 10) state -= 3;
+ else state -= 6;
+ }
+ else
+ {
+ UpdateBit1(prob);
+ prob = p + IsRep + state;
+ IfBit0(prob)
+ {
+ UpdateBit0(prob);
+ rep3 = rep2;
+ rep2 = rep1;
+ rep1 = rep0;
+ state = state < kNumLitStates ? 0 : 3;
+ prob = p + LenCoder;
+ }
+ else
+ {
+ UpdateBit1(prob);
+ prob = p + IsRepG0 + state;
+ IfBit0(prob)
+ {
+ UpdateBit0(prob);
+ prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;
+ IfBit0(prob)
+ {
+ #ifdef _LZMA_OUT_READ
+ UInt32 pos;
+ #endif
+ UpdateBit0(prob);
+
+ #ifdef _LZMA_OUT_READ
+ if (distanceLimit == 0)
+ #else
+ if (nowPos == 0)
+ #endif
+ {
+
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf("ERROR: %s, %d\n", __FILE__, __LINE__);
+#endif
+ return LZMA_RESULT_DATA_ERROR;
+ }
+
+ state = state < kNumLitStates ? 9 : 11;
+ #ifdef _LZMA_OUT_READ
+ pos = dictionaryPos - rep0;
+ if (pos >= dictionarySize)
+ pos += dictionarySize;
+ previousByte = dictionary[pos];
+ dictionary[dictionaryPos] = previousByte;
+ if (++dictionaryPos == dictionarySize)
+ dictionaryPos = 0;
+ #else
+ previousByte = outStream[nowPos - rep0];
+ #endif
+ outStream[nowPos++] = previousByte;
+ #ifdef _LZMA_OUT_READ
+ if (distanceLimit < dictionarySize)
+ distanceLimit++;
+ #endif
+
+ continue;
+ }
+ else
+ {
+ UpdateBit1(prob);
+ }
+ }
+ else
+ {
+ UInt32 distance;
+ UpdateBit1(prob);
+ prob = p + IsRepG1 + state;
+ IfBit0(prob)
+ {
+ UpdateBit0(prob);
+ distance = rep1;
+ }
+ else
+ {
+ UpdateBit1(prob);
+ prob = p + IsRepG2 + state;
+ IfBit0(prob)
+ {
+ UpdateBit0(prob);
+ distance = rep2;
+ }
+ else
+ {
+ UpdateBit1(prob);
+ distance = rep3;
+ rep3 = rep2;
+ }
+ rep2 = rep1;
+ }
+ rep1 = rep0;
+ rep0 = distance;
+ }
+ state = state < kNumLitStates ? 8 : 11;
+ prob = p + RepLenCoder;
+ }
+ {
+ int numBits, offset;
+ CProb *probLen = prob + LenChoice;
+ IfBit0(probLen)
+ {
+ UpdateBit0(probLen);
+ probLen = prob + LenLow + (posState << kLenNumLowBits);
+ offset = 0;
+ numBits = kLenNumLowBits;
+ }
+ else
+ {
+ UpdateBit1(probLen);
+ probLen = prob + LenChoice2;
+ IfBit0(probLen)
+ {
+ UpdateBit0(probLen);
+ probLen = prob + LenMid + (posState << kLenNumMidBits);
+ offset = kLenNumLowSymbols;
+ numBits = kLenNumMidBits;
+ }
+ else
+ {
+ UpdateBit1(probLen);
+ probLen = prob + LenHigh;
+ offset = kLenNumLowSymbols + kLenNumMidSymbols;
+ numBits = kLenNumHighBits;
+ }
+ }
+ RangeDecoderBitTreeDecode(probLen, numBits, len);
+ len += offset;
+ }
+
+ if (state < 4)
+ {
+ int posSlot;
+ state += kNumLitStates;
+ prob = p + PosSlot +
+ ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) <<
+ kNumPosSlotBits);
+ RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);
+ if (posSlot >= kStartPosModelIndex)
+ {
+ int numDirectBits = ((posSlot >> 1) - 1);
+ rep0 = (2 | ((UInt32)posSlot & 1));
+ if (posSlot < kEndPosModelIndex)
+ {
+ rep0 <<= numDirectBits;
+ prob = p + SpecPos + rep0 - posSlot - 1;
+ }
+ else
+ {
+ numDirectBits -= kNumAlignBits;
+ do
+ {
+ RC_NORMALIZE
+ Range >>= 1;
+ rep0 <<= 1;
+ if (Code >= Range)
+ {
+ Code -= Range;
+ rep0 |= 1;
+ }
+ }
+ while (--numDirectBits != 0);
+ prob = p + Align;
+ rep0 <<= kNumAlignBits;
+ numDirectBits = kNumAlignBits;
+ }
+ {
+ int i = 1;
+ int mi = 1;
+ do
+ {
+ CProb *prob3 = prob + mi;
+ RC_GET_BIT2(prob3, mi, ; , rep0 |= i);
+ i <<= 1;
+ }
+ while(--numDirectBits != 0);
+ }
+ }
+ else
+ rep0 = posSlot;
+ if (++rep0 == (UInt32)(0))
+ {
+ /* it's for stream version */
+ len = kLzmaStreamWasFinishedId;
+ break;
+ }
+ }
+
+ len += kMatchMinLen;
+ #ifdef _LZMA_OUT_READ
+ if (rep0 > distanceLimit)
+ #else
+ if (rep0 > nowPos)
+ #endif
+ {
+
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf("ERROR: %s, %d\n", __FILE__, __LINE__);
+#endif
+ return LZMA_RESULT_DATA_ERROR;
+ }
+
+ #ifdef _LZMA_OUT_READ
+ if (dictionarySize - distanceLimit > (UInt32)len)
+ distanceLimit += len;
+ else
+ distanceLimit = dictionarySize;
+ #endif
+
+ do
+ {
+ #ifdef _LZMA_OUT_READ
+ UInt32 pos = dictionaryPos - rep0;
+ if (pos >= dictionarySize)
+ pos += dictionarySize;
+ previousByte = dictionary[pos];
+ dictionary[dictionaryPos] = previousByte;
+ if (++dictionaryPos == dictionarySize)
+ dictionaryPos = 0;
+ #else
+ previousByte = outStream[nowPos - rep0];
+ #endif
+ len--;
+ outStream[nowPos++] = previousByte;
+ }
+ while(len != 0 && nowPos < outSize);
+ }
+ }
+ RC_NORMALIZE;
+
+ #ifdef _LZMA_OUT_READ
+ vs->Range = Range;
+ vs->Code = Code;
+ vs->DictionaryPos = dictionaryPos;
+ vs->GlobalPos = globalPos + (UInt32)nowPos;
+ vs->DistanceLimit = distanceLimit;
+ vs->Reps[0] = rep0;
+ vs->Reps[1] = rep1;
+ vs->Reps[2] = rep2;
+ vs->Reps[3] = rep3;
+ vs->State = state;
+ vs->RemainLen = len;
+ vs->TempDictionary[0] = tempDictionary[0];
+ #endif
+
+ #ifdef _LZMA_IN_CB
+ vs->Buffer = Buffer;
+ vs->BufferLim = BufferLim;
+ #else
+ *inSizeProcessed = (SizeT)(Buffer - inStream);
+ #endif
+ *outSizeProcessed = nowPos;
+ return LZMA_RESULT_OK;
+}
+
+#endif /* CONFIG_LZMA */
--- /dev/null
+/*
+ LzmaDecode.h
+ LZMA Decoder interface
+
+ LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
+ http://www.7-zip.org/
+
+ LZMA SDK is licensed under two licenses:
+ 1) GNU Lesser General Public License (GNU LGPL)
+ 2) Common Public License (CPL)
+ It means that you can select one of these two licenses and
+ follow rules of that license.
+
+ SPECIAL EXCEPTION:
+ Igor Pavlov, as the author of this code, expressly permits you to
+ statically or dynamically link your code (or bind by name) to the
+ interfaces of this file without subjecting your linked code to the
+ terms of the CPL or GNU LGPL. Any modifications or additions
+ to this file, however, are subject to the LGPL or CPL terms.
+*/
+
+#ifndef __LZMADECODE_H
+#define __LZMADECODE_H
+
+#include "LzmaTypes.h"
+
+/* #define _LZMA_IN_CB */
+/* Use callback for input data */
+
+/* #define _LZMA_OUT_READ */
+/* Use read function for output data */
+
+/* #define _LZMA_PROB32 */
+/* It can increase speed on some 32-bit CPUs,
+ but memory usage will be doubled in that case */
+
+/* #define _LZMA_LOC_OPT */
+/* Enable local speed optimizations inside code */
+
+#ifdef _LZMA_PROB32
+#define CProb UInt32
+#else
+#define CProb UInt16
+#endif
+
+#define LZMA_RESULT_OK 0
+#define LZMA_RESULT_DATA_ERROR 1
+
+#ifdef _LZMA_IN_CB
+typedef struct _ILzmaInCallback
+{
+ int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize);
+} ILzmaInCallback;
+#endif
+
+#define LZMA_BASE_SIZE 1846
+#define LZMA_LIT_SIZE 768
+
+#define LZMA_PROPERTIES_SIZE 5
+
+typedef struct _CLzmaProperties
+{
+ int lc;
+ int lp;
+ int pb;
+ #ifdef _LZMA_OUT_READ
+ UInt32 DictionarySize;
+ #endif
+}CLzmaProperties;
+
+int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);
+
+#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))
+
+#define kLzmaNeedInitId (-2)
+
+typedef struct _CLzmaDecoderState
+{
+ CLzmaProperties Properties;
+ CProb *Probs;
+
+ #ifdef _LZMA_IN_CB
+ const unsigned char *Buffer;
+ const unsigned char *BufferLim;
+ #endif
+
+ #ifdef _LZMA_OUT_READ
+ unsigned char *Dictionary;
+ UInt32 Range;
+ UInt32 Code;
+ UInt32 DictionaryPos;
+ UInt32 GlobalPos;
+ UInt32 DistanceLimit;
+ UInt32 Reps[4];
+ int State;
+ int RemainLen;
+ unsigned char TempDictionary[4];
+ #endif
+} CLzmaDecoderState;
+
+#ifdef _LZMA_OUT_READ
+#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; }
+#endif
+
+int LzmaDecode(CLzmaDecoderState *vs,
+ #ifdef _LZMA_IN_CB
+ ILzmaInCallback *inCallback,
+ #else
+ const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
+ #endif
+ unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);
+
+#endif
--- /dev/null
+/*
+LzmaTypes.h
+
+Types for LZMA Decoder
+
+This file written and distributed to public domain by Igor Pavlov.
+This file is part of LZMA SDK 4.40 (2006-05-01)
+*/
+
+#ifndef __LZMATYPES_H
+#define __LZMATYPES_H
+
+#ifndef _7ZIP_BYTE_DEFINED
+#define _7ZIP_BYTE_DEFINED
+typedef unsigned char Byte;
+#endif
+
+#ifndef _7ZIP_UINT16_DEFINED
+#define _7ZIP_UINT16_DEFINED
+typedef unsigned short UInt16;
+#endif
+
+#ifndef _7ZIP_UINT32_DEFINED
+#define _7ZIP_UINT32_DEFINED
+#ifdef _LZMA_UINT32_IS_ULONG
+typedef unsigned long UInt32;
+#else
+typedef unsigned int UInt32;
+#endif
+#endif
+
+/* #define _LZMA_SYSTEM_SIZE_T */
+/* Use system's size_t. You can use it to enable 64-bit sizes supporting */
+
+#ifndef _7ZIP_SIZET_DEFINED
+#define _7ZIP_SIZET_DEFINED
+#ifdef _LZMA_SYSTEM_SIZE_T
+#include <stddef.h>
+typedef size_t SizeT;
+#else
+typedef UInt32 SizeT;
+#endif
+#endif
+
+#endif
--- /dev/null
+/******************************************************************************
+**
+** FILE NAME : LzmaWrapper.c
+** PROJECT : bootloader
+** MODULES : U-boot
+**
+** DATE : 2 Nov 2006
+** AUTHOR : Lin Mars
+** DESCRIPTION : LZMA decoder support for U-boot 1.1.5
+** COPYRIGHT : Copyright (c) 2006
+** Infineon Technologies AG
+** Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+** This program is free software; you can redistribute it and/or modify
+** it under the terms of the GNU General Public License as published by
+** the Free Software Foundation; either version 2 of the License, or
+** (at your option) any later version.
+**
+** HISTORY
+** $Date $Author $Comment
+** 2 Nov 2006 Lin Mars init version which derived from LzmaTest.c from
+** LZMA v4.43 SDK
+*******************************************************************************/
+#define LZMA_NO_STDIO
+#ifndef LZMA_NO_STDIO
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#endif
+
+#include <config.h>
+#include <common.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <malloc.h>
+
+#ifdef CONFIG_LZMA
+
+#include "LzmaDecode.h"
+#include "LzmaWrapper.h"
+
+static const char *kCantReadMessage = "Can not read from source buffer";
+static const char *kCantAllocateMessage = "Not enough buffer for decompression";
+
+static size_t rpos=0, dpos=0;
+
+static int MyReadFileAndCheck(unsigned char *src, void *dest, size_t size)
+{
+ if (size == 0)
+ return 0;
+ memcpy(dest, src + rpos, size);
+ rpos += size;
+ return 1;
+}
+
+int lzma_inflate(unsigned char *source, int s_len, unsigned char *dest, int *d_len)
+{
+ /* We use two 32-bit integers to construct 64-bit integer for file size.
+ You can remove outSizeHigh, if you don't need >= 4GB supporting,
+ or you can use UInt64 outSize, if your compiler supports 64-bit integers*/
+ UInt32 outSize = 0;
+ UInt32 outSizeHigh = 0;
+ SizeT outSizeFull;
+ unsigned char *outStream;
+
+ int waitEOS = 1;
+ /* waitEOS = 1, if there is no uncompressed size in headers,
+ so decoder will wait EOS (End of Stream Marker) in compressed stream */
+
+ SizeT compressedSize;
+ unsigned char *inStream;
+
+ CLzmaDecoderState state; /* it's about 24-80 bytes structure, if int is 32-bit */
+ unsigned char properties[LZMA_PROPERTIES_SIZE];
+
+ int res;
+
+ if (sizeof(UInt32) < 4)
+ {
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf("LZMA decoder needs correct UInt32\n");
+#endif
+ return LZMA_RESULT_DATA_ERROR;
+ }
+
+ {
+ long length=s_len;
+ if ((long)(SizeT)length != length)
+ {
+
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf("Too big compressed stream\n");
+#endif
+ return LZMA_RESULT_DATA_ERROR;
+ }
+ compressedSize = (SizeT)(length - (LZMA_PROPERTIES_SIZE + 8));
+ }
+
+ /* Read LZMA properties for compressed stream */
+
+ if (!MyReadFileAndCheck(source, properties, sizeof(properties)))
+ {
+
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf("%s\n", kCantReadMessage);
+#endif
+ return LZMA_RESULT_DATA_ERROR;
+ }
+
+ /* Read uncompressed size */
+ {
+ int i;
+ for (i = 0; i < 8; i++)
+ {
+ unsigned char b;
+ if (!MyReadFileAndCheck(source, &b, 1))
+ {
+
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf("%s\n", kCantReadMessage);
+#endif
+ return LZMA_RESULT_DATA_ERROR;
+ }
+ if (b != 0xFF)
+ waitEOS = 0;
+ if (i < 4)
+ outSize += (UInt32)(b) << (i * 8);
+ else
+ outSizeHigh += (UInt32)(b) << ((i - 4) * 8);
+ }
+
+ if (waitEOS)
+ {
+
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf("Stream with EOS marker is not supported");
+#endif
+ return LZMA_RESULT_DATA_ERROR;
+ }
+ outSizeFull = (SizeT)outSize;
+ if (sizeof(SizeT) >= 8)
+ outSizeFull |= (((SizeT)outSizeHigh << 16) << 16);
+ else if (outSizeHigh != 0 || (UInt32)(SizeT)outSize != outSize)
+ {
+
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf("Too big uncompressed stream");
+#endif
+ return LZMA_RESULT_DATA_ERROR;
+ }
+ }
+
+ /* Decode LZMA properties and allocate memory */
+ if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK)
+ {
+
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf("Incorrect stream properties");
+#endif
+ return LZMA_RESULT_DATA_ERROR;
+ }
+ state.Probs = (CProb *)malloc(LzmaGetNumProbs(&state.Properties) * sizeof(CProb));
+
+ if (outSizeFull == 0)
+ outStream = 0;
+ else
+ {
+ if (outSizeFull > d_len)
+ outStream = 0;
+ else
+ outStream = dest;
+ }
+
+ if (compressedSize == 0)
+ inStream = 0;
+ else
+ {
+ if ((compressedSize+rpos) > s_len )
+ inStream = 0;
+ else
+ inStream = source + rpos;
+ }
+
+ if (state.Probs == 0
+ || (outStream == 0 && outSizeFull != 0)
+ || (inStream == 0 && compressedSize != 0)
+ )
+ {
+ free(state.Probs);
+
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf("%s\n", kCantAllocateMessage);
+#endif
+ return LZMA_RESULT_DATA_ERROR;
+ }
+
+ /* Decompress */
+ {
+ SizeT inProcessed;
+ SizeT outProcessed;
+ res = LzmaDecode(&state,
+ inStream, compressedSize, &inProcessed,
+ outStream, outSizeFull, &outProcessed);
+ if (res != 0)
+ {
+
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf("\nDecoding error = %d\n", res);
+#endif
+ res = 1;
+ }
+ else
+ {
+ *d_len = outProcessed;
+ }
+ }
+
+ free(state.Probs);
+ return res;
+}
+
+#endif /* CONFIG_LZMA */
--- /dev/null
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = libbootstrap.a
+
+#OBJS_PRINTF_ENABLED = bootstrap_board.o time.o console.o LzmaWrapper.o LzmaDecode.o crc32.o ctype.o display_options.o string.o vsprintf.o lists.o devices.o
+#OBJS_PRINTF_DISBALED = bootstrap_board.o LzmaDecode.o string.o crc32.o LzmaWrapper.o
+
+OBJS = bootstrap_board_$(BOARDDIR).o LzmaDecode.o string.o crc32.o LzmaWrapper.o
+
+ifeq ($(BOOTSTRAP_PRINTF_STATUS), BOOTSTRAP_PRINTF_ENABLED)
+#overwrite objs
+OBJS = bootstrap_board_$(BOARDDIR).o time.o console.o LzmaWrapper.o LzmaDecode.o crc32.o ctype.o display_options.o string.o vsprintf.o lists.o devices.o
+CFLAGS += -DDEBUG_ENABLE_BOOTSTRAP_PRINTF
+endif
+
+all: .depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(OBJS:.o=.c)
+ echo "make libbootstrap.a with HEAD_SIZE $(HEAD_SIZE)"
+ $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <devices.h>
+#include <version.h>
+#include <net.h>
+#include <environment.h>
+#ifdef CONFIG_DANUBE
+#include <asm-mips/danube.h>
+#include <configs/danube.h>
+#endif
+#include "LzmaWrapper.h"
+
+//#define DEBUG_ENABLE_BOOTSTRAP_PRINTF
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < BOOTSTRAP_CFG_MONITOR_BASE) || \
+ (CFG_ENV_ADDR >= (BOOTSTRAP_CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \
+ defined(CFG_ENV_IS_IN_NVRAM)
+#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE)
+#else
+#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
+#endif
+
+#undef DEBUG
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+extern unsigned long nand_init(void);
+#endif
+
+#ifdef CONFIG_SERIAL_FLASH
+extern int serial_flash_init (void);
+#endif
+
+extern int timer_init(void);
+
+extern int incaip_set_cpuclk(void);
+
+extern ulong uboot_end_data_bootstrap;
+extern ulong uboot_end_bootstrap;
+
+ulong monitor_flash_len;
+
+const char version_string[] =
+ U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")";
+
+static char *failed = "*** failed ***\n";
+
+/*
+ * Begin and End of memory area for malloc(), and current "brk"
+ */
+static ulong mem_malloc_start;
+static ulong mem_malloc_end;
+static ulong mem_malloc_brk;
+
+
+/*
+ * The Malloc area is immediately below the monitor copy in DRAM
+ */
+static void mem_malloc_init (ulong dest_addr)
+{
+// ulong dest_addr = BOOTSTRAP_CFG_MONITOR_BASE + gd->reloc_off;
+
+ mem_malloc_end = dest_addr;
+ mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN;
+ mem_malloc_brk = mem_malloc_start;
+
+ memset ((void *) mem_malloc_start,
+ 0,
+ mem_malloc_end - mem_malloc_start);
+}
+
+void *malloc(unsigned int size)
+{
+ if(size < (mem_malloc_end - mem_malloc_start))
+ {
+ mem_malloc_start += size;
+ return (void *)(mem_malloc_start - size);
+ }
+ return NULL;
+}
+
+void *realloc(void *src,unsigned int size)
+{
+ return NULL;
+}
+
+void free(void *src)
+{
+ return;
+}
+
+
+void *sbrk (ptrdiff_t increment)
+{
+ ulong old = mem_malloc_brk;
+ ulong new = old + increment;
+
+ if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
+ return (NULL);
+ }
+ mem_malloc_brk = new;
+ return ((void *) old);
+}
+
+
+static int init_func_ram (void)
+{
+#ifdef CONFIG_BOARD_TYPES
+ int board_type = gd->board_type;
+#else
+ int board_type = 0; /* use dummy arg */
+#endif
+
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ puts ("DRAM: ");
+#endif
+
+ if ((gd->ram_size = initdram (board_type)) > 0) {
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ print_size (gd->ram_size, "\n");
+#endif
+ return (0);
+ }
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ puts (failed);
+#endif
+ return (1);
+}
+
+static int display_banner(void)
+{
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf ("\n\n%s\n\n", version_string);
+#endif
+ return (0);
+}
+
+static int init_baudrate (void)
+{
+#if 0
+ char tmp[64]; /* long enough for environment variables */
+ int i = getenv_r ("baudrate", tmp, sizeof (tmp));
+
+ gd->baudrate = (i > 0)
+ ? (int) simple_strtoul (tmp, NULL, 10)
+ : CONFIG_BAUDRATE;
+#endif
+
+ gd->baudrate = CONFIG_BAUDRATE;
+
+ return (0);
+}
+#ifdef CONFIG_DANUBE
+static void init_led(void)
+{
+
+ *(unsigned long *)0xBE100B18 |= 0x70;
+ *(unsigned long *)0xBE100B1C |= 0x70;
+ *(unsigned long *)0xBE100B20 &= ~0x70;
+ *(unsigned long *)0xBE100B24 |= 0x70;
+#ifdef USE_REFERENCE_BOARD
+
+ *DANUBE_LED_CON1 = 0x00000003;
+ *DANUBE_LED_CPU0 = 0x0000010;
+ *DANUBE_LED_CPU1 = 0x00000000;
+ *DANUBE_LED_AR = 0x00000000;
+ *DANUBE_LED_CON0 = 0x84000000;
+
+#else
+
+ *DANUBE_LED_CON1 = 0x00000007;
+ *DANUBE_LED_CPU0 = 0x00001000;
+ *DANUBE_LED_CPU1 = 0x00000000;
+ *DANUBE_LED_AR = 0x00000000;
+ *DANUBE_LED_CON0 = 0x84000000;
+
+#endif
+
+}
+#endif
+/*
+ * Breath some life into the board...
+ *
+ * The first part of initialization is running from Flash memory;
+ * its main purpose is to initialize the RAM so that we
+ * can relocate the monitor code to RAM.
+ */
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependend #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+typedef int (init_fnc_t) (void);
+
+init_fnc_t *init_sequence[] = {
+ //timer_init,
+ //env_init, /* initialize environment */
+#ifdef CONFIG_INCA_IP
+ incaip_set_cpuclk, /* set cpu clock according to environment variable */
+#endif
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ init_baudrate, /* initialze baudrate settings */
+ serial_init, /* serial communications setup */
+ console_init_f,
+ display_banner, /* say that we are here */
+#endif
+ init_func_ram,
+ //checkboard,
+ NULL,
+};
+
+
+void bootstrap_board_init_f(ulong bootflag)
+{
+ gd_t gd_data, *id;
+ bd_t *bd;
+ init_fnc_t **init_fnc_ptr;
+ ulong addr, addr_sp, len = (ulong)&uboot_end_bootstrap - BOOTSTRAP_CFG_MONITOR_BASE;
+ ulong *s;
+ ulong lzmaImageaddr = 0;
+#ifdef CONFIG_PURPLE
+ void copy_code (ulong);
+#endif
+
+ /* Pointer is writable since we allocated a register for it.
+ */
+ gd = &gd_data;
+ /* compiler optimization barrier needed for GCC >= 3.4 */
+ __asm__ __volatile__("": : :"memory");
+
+ memset ((void *)gd, 0, sizeof (gd_t));
+
+ for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+ if ((*init_fnc_ptr)() != 0) {
+ hang ();
+ }
+ }
+
+ /*
+ * Now that we have DRAM mapped and working, we can
+ * relocate the code and continue running from DRAM.
+ */
+ addr = CFG_SDRAM_BASE + gd->ram_size;
+
+ /* We can reserve some RAM "on top" here.
+ */
+
+ /* round down to next 4 kB limit.
+ */
+ addr &= ~(4096 - 1);
+ debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
+
+ /* Reserve memory for U-Boot code, data & bss
+ * round down to next 16 kB limit
+ */
+ addr -= len;
+ addr &= ~(16 * 1024 - 1);
+
+ debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
+
+ /* Reserve memory for malloc() arena.
+ */
+ addr_sp = addr - TOTAL_MALLOC_LEN;
+ debug ("Reserving %dk for malloc() at: %08lx\n",
+ TOTAL_MALLOC_LEN >> 10, addr_sp);
+
+ /*
+ * (permanently) allocate a Board Info struct
+ * and a permanent copy of the "global" data
+ */
+ addr_sp -= sizeof(bd_t);
+ bd = (bd_t *)addr_sp;
+ gd->bd = bd;
+ debug ("Reserving %d Bytes for Board Info at: %08lx\n",
+ sizeof(bd_t), addr_sp);
+
+ addr_sp -= sizeof(gd_t);
+ id = (gd_t *)addr_sp;
+ debug ("Reserving %d Bytes for Global Data at: %08lx\n",
+ sizeof (gd_t), addr_sp);
+
+ /* Reserve memory for boot params.
+ */
+ addr_sp -= CFG_BOOTPARAMS_LEN;
+ bd->bi_boot_params = addr_sp;
+ debug ("Reserving %dk for boot params() at: %08lx\n",
+ CFG_BOOTPARAMS_LEN >> 10, addr_sp);
+
+ /*
+ * Finally, we set up a new (bigger) stack.
+ *
+ * Leave some safety gap for SP, force alignment on 16 byte boundary
+ * Clear initial stack frame
+ */
+ addr_sp -= 16;
+ addr_sp &= ~0xF;
+ s = (ulong *)addr_sp;
+ *s-- = 0;
+ *s-- = 0;
+ addr_sp = (ulong)s;
+ debug ("Stack Pointer at: %08lx\n", addr_sp);
+
+ /*
+ * Save local variables to board info struct
+ */
+ bd->bi_memstart = CFG_SDRAM_BASE; /* start of DRAM memory */
+ bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
+ bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
+
+ memcpy (id, (void *)gd, sizeof (gd_t));
+
+ /* On the purple board we copy the code in a special way
+ * in order to solve flash problems
+ */
+#ifdef CONFIG_PURPLE
+ copy_code(addr);
+#endif
+
+ lzmaImageaddr = (ulong)&uboot_end_data_bootstrap;
+
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf ("\n relocating to address %08x ", addr);
+#endif
+
+ bootstrap_relocate_code (addr_sp, id, addr);
+
+ /* NOTREACHED - relocate_code() does not return */
+}
+/************************************************************************
+ *
+ * This is the next part if the initialization sequence: we are now
+ * running from RAM and have a "normal" C environment, i. e. global
+ * data can be written, BSS has been cleared, the stack size in not
+ * that critical any more, etc.
+ *
+ ************************************************************************
+ */
+#define CONFIG_LZMA
+
+void bootstrap_board_init_r (gd_t *id, ulong dest_addr)
+{
+ int i;
+
+ ulong addr;
+ ulong data, len, checksum;
+ ulong *len_ptr;
+ image_header_t header;
+ image_header_t *hdr = &header;
+ unsigned int destLen;
+ int (*fn)();
+
+#if 1
+#endif
+
+
+
+ /* initialize malloc() area */
+ mem_malloc_init(dest_addr);
+
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf("\n Compressed Image at %08x \n ", (BOOTSTRAP_CFG_MONITOR_BASE + ((ulong)&uboot_end_data_bootstrap - dest_addr)));
+#endif
+
+ addr = (char *)(BOOTSTRAP_CFG_MONITOR_BASE + ((ulong)&uboot_end_data_bootstrap - dest_addr));
+ memmove (&header, (char *)addr, sizeof(image_header_t));
+
+ if (ntohl(hdr->ih_magic) != IH_MAGIC) {
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf ("Bad Magic Number at address 0x%08lx\n",addr);
+#endif
+ return;
+ }
+
+ data = (ulong)&header;
+ len = sizeof(image_header_t);
+
+ checksum = ntohl(hdr->ih_hcrc);
+ hdr->ih_hcrc = 0;
+ if (crc32 (0, (char *)data, len) != checksum) {
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf ("Bad Header Checksum\n");
+#endif
+ return;
+ }
+
+ data = addr + sizeof(image_header_t);
+ len = ntohl(hdr->ih_size);
+
+ len_ptr = (ulong *)data;
+
+
+
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf ("Disabling all the interrupts\n");
+#endif
+ disable_interrupts();
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf (" Uncompressing UBoot Image ... \n" );
+#endif
+
+ /*
+ * If we've got less than 4 MB of malloc() space,
+ * use slower decompression algorithm which requires
+ * at most 2300 KB of memory.
+ */
+ destLen = 0x0;
+
+#ifdef CONFIG_BZIP2
+ i = BZ2_bzBuffToBuffDecompress ((char*)ntohl(hdr->ih_load),
+ 0x400000, (char *)data, len,
+ CFG_MALLOC_LEN < (4096 * 1024), 0);
+ if (i != BZ_OK) {
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf ("BUNZIP2 ERROR %d - must RESET board to recover\n", i);
+#endif
+ return;
+ }
+#endif /* CONFIG_BZIP2 */
+
+#ifdef CONFIG_MICROBZIP2
+ i = micro_bzBuffToBuffDecompress ((char*)ntohl(hdr->ih_load),
+ &destLen, (char *)data, len,
+ CFG_MALLOC_LEN < (4096 * 1024), 0);
+ if (i != RETVAL_OK) {
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf ("MICRO_BUNZIP2 ERROR %d - must RESET board to recover\n", i);
+#endif
+ //do_reset (cmdtp, flag, argc, argv);
+ return;
+ }
+#endif
+
+#ifdef CONFIG_LZMA
+#if 0
+ i = lzmaBuffToBuffDecompress ((char*)ntohl(hdr->ih_load),
+ &destLen, (char *)data, len);
+#endif
+
+ i = lzma_inflate ((unsigned char *)data, len, (unsigned char*)ntohl(hdr->ih_load), &destLen);
+ if (i != LZMA_RESULT_OK) {
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf ("LZMA ERROR %d - must RESET board to recover\n", i);
+#endif
+ //do_reset (cmdtp, flag, argc, argv);
+ return;
+ }
+#endif
+
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ printf (" Uncompression completed successfully with destLen %d\n ",destLen );
+#endif
+
+ fn = ntohl(hdr->ih_load);
+
+ (*fn)();
+
+ hang ();
+
+}
+
+void hang (void)
+{
+
+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF
+ puts ("### ERROR ### Please RESET the board ###\n");
+#endif
+ for (;;);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <stdarg.h>
+#include <malloc.h>
+#include <console.h>
+#include <exports.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_AMIGAONEG3SE
+int console_changed = 0;
+#endif
+
+#ifdef CFG_CONSOLE_IS_IN_ENV
+/*
+ * if overwrite_console returns 1, the stdin, stderr and stdout
+ * are switched to the serial port, else the settings in the
+ * environment are used
+ */
+#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE
+extern int overwrite_console (void);
+#define OVERWRITE_CONSOLE overwrite_console ()
+#else
+#define OVERWRITE_CONSOLE 0
+#endif /* CFG_CONSOLE_OVERWRITE_ROUTINE */
+
+#endif /* CFG_CONSOLE_IS_IN_ENV */
+
+static int console_setfile (int file, device_t * dev)
+{
+ int error = 0;
+
+ if (dev == NULL)
+ return -1;
+
+ switch (file) {
+ case stdin:
+ case stdout:
+ case stderr:
+ /* Start new device */
+ if (dev->start) {
+ error = dev->start ();
+ /* If it's not started dont use it */
+ if (error < 0)
+ break;
+ }
+
+ /* Assign the new device (leaving the existing one started) */
+ stdio_devices[file] = dev;
+
+ /*
+ * Update monitor functions
+ * (to use the console stuff by other applications)
+ */
+ switch (file) {
+ case stdin:
+ gd->jt[XF_getc] = dev->getc;
+ gd->jt[XF_tstc] = dev->tstc;
+ break;
+ case stdout:
+ gd->jt[XF_putc] = dev->putc;
+ gd->jt[XF_puts] = dev->puts;
+ gd->jt[XF_printf] = printf;
+ break;
+ }
+ break;
+
+ default: /* Invalid file ID */
+ error = -1;
+ }
+ return error;
+}
+
+/** U-Boot INITIAL CONSOLE-NOT COMPATIBLE FUNCTIONS *************************/
+
+void serial_printf (const char *fmt, ...)
+{
+ va_list args;
+ uint i;
+ char printbuffer[CFG_PBSIZE];
+
+ va_start (args, fmt);
+
+ /* For this to work, printbuffer must be larger than
+ * anything we ever want to print.
+ */
+ i = vsprintf (printbuffer, fmt, args);
+ va_end (args);
+
+ serial_puts (printbuffer);
+}
+
+int fgetc (int file)
+{
+ if (file < MAX_FILES)
+ return stdio_devices[file]->getc ();
+
+ return -1;
+}
+
+int ftstc (int file)
+{
+ if (file < MAX_FILES)
+ return stdio_devices[file]->tstc ();
+
+ return -1;
+}
+
+void fputc (int file, const char c)
+{
+ if (file < MAX_FILES)
+ stdio_devices[file]->putc (c);
+}
+
+void fputs (int file, const char *s)
+{
+ if (file < MAX_FILES)
+ stdio_devices[file]->puts (s);
+}
+
+void fprintf (int file, const char *fmt, ...)
+{
+ va_list args;
+ uint i;
+ char printbuffer[CFG_PBSIZE];
+
+ va_start (args, fmt);
+
+ /* For this to work, printbuffer must be larger than
+ * anything we ever want to print.
+ */
+ i = vsprintf (printbuffer, fmt, args);
+ va_end (args);
+
+ /* Send to desired file */
+ fputs (file, printbuffer);
+}
+
+/** U-Boot INITIAL CONSOLE-COMPATIBLE FUNCTION *****************************/
+
+int getc (void)
+{
+ if (gd->flags & GD_FLG_DEVINIT) {
+ /* Get from the standard input */
+ return fgetc (stdin);
+ }
+
+ /* Send directly to the handler */
+ return serial_getc ();
+}
+
+int tstc (void)
+{
+ if (gd->flags & GD_FLG_DEVINIT) {
+ /* Test the standard input */
+ return ftstc (stdin);
+ }
+
+ /* Send directly to the handler */
+ return serial_tstc ();
+}
+
+void putc (const char c)
+{
+#ifdef CONFIG_SILENT_CONSOLE
+ if (gd->flags & GD_FLG_SILENT)
+ return;
+#endif
+
+ if (gd->flags & GD_FLG_DEVINIT) {
+ /* Send to the standard output */
+ fputc (stdout, c);
+ } else {
+ /* Send directly to the handler */
+ serial_putc (c);
+ }
+}
+
+void puts (const char *s)
+{
+#ifdef CONFIG_SILENT_CONSOLE
+ if (gd->flags & GD_FLG_SILENT)
+ return;
+#endif
+
+ if (gd->flags & GD_FLG_DEVINIT) {
+ /* Send to the standard output */
+ fputs (stdout, s);
+ } else {
+ /* Send directly to the handler */
+ serial_puts (s);
+ }
+}
+
+void printf (const char *fmt, ...)
+{
+ va_list args;
+ uint i;
+ char printbuffer[CFG_PBSIZE];
+
+ va_start (args, fmt);
+
+ /* For this to work, printbuffer must be larger than
+ * anything we ever want to print.
+ */
+ i = vsprintf (printbuffer, fmt, args);
+ va_end (args);
+
+ /* Print the string */
+ puts (printbuffer);
+}
+
+void vprintf (const char *fmt, va_list args)
+{
+ uint i;
+ char printbuffer[CFG_PBSIZE];
+
+ /* For this to work, printbuffer must be larger than
+ * anything we ever want to print.
+ */
+ i = vsprintf (printbuffer, fmt, args);
+
+ /* Print the string */
+ puts (printbuffer);
+}
+
+/* test if ctrl-c was pressed */
+static int ctrlc_disabled = 0; /* see disable_ctrl() */
+static int ctrlc_was_pressed = 0;
+int ctrlc (void)
+{
+ if (!ctrlc_disabled && gd->have_console) {
+ if (tstc ()) {
+ switch (getc ()) {
+ case 0x03: /* ^C - Control C */
+ ctrlc_was_pressed = 1;
+ return 1;
+ default:
+ break;
+ }
+ }
+ }
+ return 0;
+}
+
+/* pass 1 to disable ctrlc() checking, 0 to enable.
+ * returns previous state
+ */
+int disable_ctrlc (int disable)
+{
+ int prev = ctrlc_disabled; /* save previous state */
+
+ ctrlc_disabled = disable;
+ return prev;
+}
+
+int had_ctrlc (void)
+{
+ return ctrlc_was_pressed;
+}
+
+void clear_ctrlc (void)
+{
+ ctrlc_was_pressed = 0;
+}
+
+#ifdef CONFIG_MODEM_SUPPORT_DEBUG
+char screen[1024];
+char *cursor = screen;
+int once = 0;
+inline void dbg(const char *fmt, ...)
+{
+ va_list args;
+ uint i;
+ char printbuffer[CFG_PBSIZE];
+
+ if (!once) {
+ memset(screen, 0, sizeof(screen));
+ once++;
+ }
+
+ va_start(args, fmt);
+
+ /* For this to work, printbuffer must be larger than
+ * anything we ever want to print.
+ */
+ i = vsprintf(printbuffer, fmt, args);
+ va_end(args);
+
+ if ((screen + sizeof(screen) - 1 - cursor) < strlen(printbuffer)+1) {
+ memset(screen, 0, sizeof(screen));
+ cursor = screen;
+ }
+ sprintf(cursor, printbuffer);
+ cursor += strlen(printbuffer);
+
+}
+#else
+inline void dbg(const char *fmt, ...)
+{
+}
+#endif
+
+/** U-Boot INIT FUNCTIONS *************************************************/
+
+int console_assign (int file, char *devname)
+{
+ int flag, i;
+
+ /* Check for valid file */
+ switch (file) {
+ case stdin:
+ flag = DEV_FLAGS_INPUT;
+ break;
+ case stdout:
+ case stderr:
+ flag = DEV_FLAGS_OUTPUT;
+ break;
+ default:
+ return -1;
+ }
+
+ /* Check for valid device name */
+
+ for (i = 1; i <= ListNumItems (devlist); i++) {
+ device_t *dev = ListGetPtrToItem (devlist, i);
+
+ if (strcmp (devname, dev->name) == 0) {
+ if (dev->flags & flag)
+ return console_setfile (file, dev);
+
+ return -1;
+ }
+ }
+
+ return -1;
+}
+
+/* Called before relocation - use serial functions */
+int console_init_f (void)
+{
+ gd->have_console = 1;
+
+#ifdef CONFIG_SILENT_CONSOLE
+ if (getenv("silent") != NULL)
+ gd->flags |= GD_FLG_SILENT;
+#endif
+
+ return (0);
+}
+
+#if defined(CFG_CONSOLE_IS_IN_ENV) || defined(CONFIG_SPLASH_SCREEN) || defined(CONFIG_SILENT_CONSOLE)
+/* search a device */
+device_t *search_device (int flags, char *name)
+{
+ int i, items;
+ device_t *dev = NULL;
+
+ items = ListNumItems (devlist);
+ if (name == NULL)
+ return dev;
+
+ for (i = 1; i <= items; i++) {
+ dev = ListGetPtrToItem (devlist, i);
+ if ((dev->flags & flags) && (strcmp (name, dev->name) == 0)) {
+ break;
+ }
+ }
+ return dev;
+}
+#endif /* CFG_CONSOLE_IS_IN_ENV || CONFIG_SPLASH_SCREEN */
+
+#ifdef CFG_CONSOLE_IS_IN_ENV
+/* Called after the relocation - use desired console functions */
+int console_init_r (void)
+{
+ char *stdinname, *stdoutname, *stderrname;
+ device_t *inputdev = NULL, *outputdev = NULL, *errdev = NULL;
+#ifdef CFG_CONSOLE_ENV_OVERWRITE
+ int i;
+#endif /* CFG_CONSOLE_ENV_OVERWRITE */
+
+ /* set default handlers at first */
+ gd->jt[XF_getc] = serial_getc;
+ gd->jt[XF_tstc] = serial_tstc;
+ gd->jt[XF_putc] = serial_putc;
+ gd->jt[XF_puts] = serial_puts;
+ gd->jt[XF_printf] = serial_printf;
+
+ /* stdin stdout and stderr are in environment */
+ /* scan for it */
+ stdinname = getenv ("stdin");
+ stdoutname = getenv ("stdout");
+ stderrname = getenv ("stderr");
+
+ if (OVERWRITE_CONSOLE == 0) { /* if not overwritten by config switch */
+ inputdev = search_device (DEV_FLAGS_INPUT, stdinname);
+ outputdev = search_device (DEV_FLAGS_OUTPUT, stdoutname);
+ errdev = search_device (DEV_FLAGS_OUTPUT, stderrname);
+ }
+ /* if the devices are overwritten or not found, use default device */
+ if (inputdev == NULL) {
+ inputdev = search_device (DEV_FLAGS_INPUT, "serial");
+ }
+ if (outputdev == NULL) {
+ outputdev = search_device (DEV_FLAGS_OUTPUT, "serial");
+ }
+ if (errdev == NULL) {
+ errdev = search_device (DEV_FLAGS_OUTPUT, "serial");
+ }
+ /* Initializes output console first */
+ if (outputdev != NULL) {
+ console_setfile (stdout, outputdev);
+ }
+ if (errdev != NULL) {
+ console_setfile (stderr, errdev);
+ }
+ if (inputdev != NULL) {
+ console_setfile (stdin, inputdev);
+ }
+
+ gd->flags |= GD_FLG_DEVINIT; /* device initialization completed */
+
+#ifndef CFG_CONSOLE_INFO_QUIET
+ /* Print information */
+ puts ("In: ");
+ if (stdio_devices[stdin] == NULL) {
+ puts ("No input devices available!\n");
+ } else {
+ printf ("%s\n", stdio_devices[stdin]->name);
+ }
+
+ puts ("Out: ");
+ if (stdio_devices[stdout] == NULL) {
+ puts ("No output devices available!\n");
+ } else {
+ printf ("%s\n", stdio_devices[stdout]->name);
+ }
+
+ puts ("Err: ");
+ if (stdio_devices[stderr] == NULL) {
+ puts ("No error devices available!\n");
+ } else {
+ printf ("%s\n", stdio_devices[stderr]->name);
+ }
+#endif /* CFG_CONSOLE_INFO_QUIET */
+
+#ifdef CFG_CONSOLE_ENV_OVERWRITE
+ /* set the environment variables (will overwrite previous env settings) */
+ for (i = 0; i < 3; i++) {
+ setenv (stdio_names[i], stdio_devices[i]->name);
+ }
+#endif /* CFG_CONSOLE_ENV_OVERWRITE */
+
+#if 0
+ /* If nothing usable installed, use only the initial console */
+ if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL))
+ return (0);
+#endif
+ return (0);
+}
+
+#else /* CFG_CONSOLE_IS_IN_ENV */
+#if 0
+/* Called after the relocation - use desired console functions */
+int console_init_r (void)
+{
+ device_t *inputdev = NULL, *outputdev = NULL;
+ int i, items = ListNumItems (devlist);
+
+#ifdef CONFIG_SPLASH_SCREEN
+ /* suppress all output if splash screen is enabled and we have
+ a bmp to display */
+ if (getenv("splashimage") != NULL)
+ outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev");
+#endif
+
+#ifdef CONFIG_SILENT_CONSOLE
+ /* Suppress all output if "silent" mode requested */
+ if (gd->flags & GD_FLG_SILENT)
+ outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev");
+#endif
+
+ /* Scan devices looking for input and output devices */
+ for (i = 1;
+ (i <= items) && ((inputdev == NULL) || (outputdev == NULL));
+ i++
+ ) {
+ device_t *dev = ListGetPtrToItem (devlist, i);
+
+ if ((dev->flags & DEV_FLAGS_INPUT) && (inputdev == NULL)) {
+ inputdev = dev;
+ }
+ if ((dev->flags & DEV_FLAGS_OUTPUT) && (outputdev == NULL)) {
+ outputdev = dev;
+ }
+ }
+
+ /* Initializes output console first */
+ if (outputdev != NULL) {
+ console_setfile (stdout, outputdev);
+ console_setfile (stderr, outputdev);
+ }
+
+ /* Initializes input console */
+ if (inputdev != NULL) {
+ console_setfile (stdin, inputdev);
+ }
+
+ gd->flags |= GD_FLG_DEVINIT; /* device initialization completed */
+
+#ifndef CFG_CONSOLE_INFO_QUIET
+ /* Print information */
+ puts ("In: ");
+ if (stdio_devices[stdin] == NULL) {
+ puts ("No input devices available!\n");
+ } else {
+ printf ("%s\n", stdio_devices[stdin]->name);
+ }
+
+ puts ("Out: ");
+ if (stdio_devices[stdout] == NULL) {
+ puts ("No output devices available!\n");
+ } else {
+ printf ("%s\n", stdio_devices[stdout]->name);
+ }
+
+ puts ("Err: ");
+ if (stdio_devices[stderr] == NULL) {
+ puts ("No error devices available!\n");
+ } else {
+ printf ("%s\n", stdio_devices[stderr]->name);
+ }
+#endif /* CFG_CONSOLE_INFO_QUIET */
+
+ /* Setting environment variables */
+ for (i = 0; i < 3; i++) {
+ setenv (stdio_names[i], stdio_devices[i]->name);
+ }
+
+#if 0
+ /* If nothing usable installed, use only the initial console */
+ if ((stdio_devices[stdin] == NULL) && (stdio_devices[stdout] == NULL))
+ return (0);
+#endif
+
+ return (0);
+}
+#endif
+
+#endif /* CFG_CONSOLE_IS_IN_ENV */
--- /dev/null
+/*
+ * This file is derived from crc32.c from the zlib-1.1.3 distribution
+ * by Jean-loup Gailly and Mark Adler.
+ */
+
+/* crc32.c -- compute the CRC-32 of a data stream
+ * Copyright (C) 1995-1998 Mark Adler
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+#ifndef USE_HOSTCC /* Shut down "ANSI does not permit..." warnings */
+#include <common.h> /* to get command definitions like CFG_CMD_JFFS2 */
+#endif
+
+#include "zlib.h"
+
+#define local static
+#define ZEXPORT /* empty */
+unsigned long crc32 (unsigned long, const unsigned char *, unsigned int);
+
+#ifdef DYNAMIC_CRC_TABLE
+
+local int crc_table_empty = 1;
+local uLongf crc_table[256];
+local void make_crc_table OF((void));
+
+/*
+ Generate a table for a byte-wise 32-bit CRC calculation on the polynomial:
+ x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1.
+
+ Polynomials over GF(2) are represented in binary, one bit per coefficient,
+ with the lowest powers in the most significant bit. Then adding polynomials
+ is just exclusive-or, and multiplying a polynomial by x is a right shift by
+ one. If we call the above polynomial p, and represent a byte as the
+ polynomial q, also with the lowest power in the most significant bit (so the
+ byte 0xb1 is the polynomial x^7+x^3+x+1), then the CRC is (q*x^32) mod p,
+ where a mod b means the remainder after dividing a by b.
+
+ This calculation is done using the shift-register method of multiplying and
+ taking the remainder. The register is initialized to zero, and for each
+ incoming bit, x^32 is added mod p to the register if the bit is a one (where
+ x^32 mod p is p+x^32 = x^26+...+1), and the register is multiplied mod p by
+ x (which is shifting right by one and adding x^32 mod p if the bit shifted
+ out is a one). We start with the highest power (least significant bit) of
+ q and repeat for all eight bits of q.
+
+ The table is simply the CRC of all possible eight bit values. This is all
+ the information needed to generate CRC's on data a byte at a time for all
+ combinations of CRC register values and incoming bytes.
+*/
+local void make_crc_table()
+{
+ uLong c;
+ int n, k;
+ uLong poly; /* polynomial exclusive-or pattern */
+ /* terms of polynomial defining this crc (except x^32): */
+ static const Byte p[] = {0,1,2,4,5,7,8,10,11,12,16,22,23,26};
+
+ /* make exclusive-or pattern from polynomial (0xedb88320L) */
+ poly = 0L;
+ for (n = 0; n < sizeof(p)/sizeof(Byte); n++)
+ poly |= 1L << (31 - p[n]);
+
+ for (n = 0; n < 256; n++)
+ {
+ c = (uLong)n;
+ for (k = 0; k < 8; k++)
+ c = c & 1 ? poly ^ (c >> 1) : c >> 1;
+ crc_table[n] = c;
+ }
+ crc_table_empty = 0;
+}
+#else
+/* ========================================================================
+ * Table of CRC-32's of all single-byte values (made by make_crc_table)
+ */
+local const uLongf crc_table[256] = {
+ 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
+ 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
+ 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
+ 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL,
+ 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L,
+ 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L,
+ 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L,
+ 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,
+ 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L,
+ 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL,
+ 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L,
+ 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L,
+ 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L,
+ 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL,
+ 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL,
+ 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,
+ 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL,
+ 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L,
+ 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L,
+ 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L,
+ 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL,
+ 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L,
+ 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L,
+ 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,
+ 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L,
+ 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L,
+ 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L,
+ 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L,
+ 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L,
+ 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL,
+ 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL,
+ 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,
+ 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L,
+ 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL,
+ 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL,
+ 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L,
+ 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL,
+ 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L,
+ 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL,
+ 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,
+ 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL,
+ 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L,
+ 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L,
+ 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL,
+ 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L,
+ 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L,
+ 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L,
+ 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,
+ 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L,
+ 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L,
+ 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL,
+ 0x2d02ef8dL
+};
+#endif
+
+#if 0
+/* =========================================================================
+ * This function can be used by asm versions of crc32()
+ */
+const uLongf * ZEXPORT get_crc_table()
+{
+#ifdef DYNAMIC_CRC_TABLE
+ if (crc_table_empty) make_crc_table();
+#endif
+ return (const uLongf *)crc_table;
+}
+#endif
+
+/* ========================================================================= */
+#define DO1(buf) crc = crc_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8);
+#define DO2(buf) DO1(buf); DO1(buf);
+#define DO4(buf) DO2(buf); DO2(buf);
+#define DO8(buf) DO4(buf); DO4(buf);
+
+/* ========================================================================= */
+uLong ZEXPORT crc32(crc, buf, len)
+ uLong crc;
+ const Bytef *buf;
+ uInt len;
+{
+#ifdef DYNAMIC_CRC_TABLE
+ if (crc_table_empty)
+ make_crc_table();
+#endif
+ crc = crc ^ 0xffffffffL;
+ while (len >= 8)
+ {
+ DO8(buf);
+ len -= 8;
+ }
+ if (len) do {
+ DO1(buf);
+ } while (--len);
+ return crc ^ 0xffffffffL;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+
+/* No ones complement version. JFFS2 (and other things ?)
+ * don't use ones compliment in their CRC calculations.
+ */
+uLong ZEXPORT crc32_no_comp(uLong crc, const Bytef *buf, uInt len)
+{
+#ifdef DYNAMIC_CRC_TABLE
+ if (crc_table_empty)
+ make_crc_table();
+#endif
+ while (len >= 8)
+ {
+ DO8(buf);
+ len -= 8;
+ }
+ if (len) do {
+ DO1(buf);
+ } while (--len);
+
+ return crc;
+}
+
+#endif /* CFG_CMD_JFFS2 */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * linux/lib/ctype.c
+ *
+ * Copyright (C) 1991, 1992 Linus Torvalds
+ */
+
+#include <linux/ctype.h>
+
+unsigned char _ctype[] = {
+_C,_C,_C,_C,_C,_C,_C,_C, /* 0-7 */
+_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C, /* 8-15 */
+_C,_C,_C,_C,_C,_C,_C,_C, /* 16-23 */
+_C,_C,_C,_C,_C,_C,_C,_C, /* 24-31 */
+_S|_SP,_P,_P,_P,_P,_P,_P,_P, /* 32-39 */
+_P,_P,_P,_P,_P,_P,_P,_P, /* 40-47 */
+_D,_D,_D,_D,_D,_D,_D,_D, /* 48-55 */
+_D,_D,_P,_P,_P,_P,_P,_P, /* 56-63 */
+_P,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U, /* 64-71 */
+_U,_U,_U,_U,_U,_U,_U,_U, /* 72-79 */
+_U,_U,_U,_U,_U,_U,_U,_U, /* 80-87 */
+_U,_U,_U,_P,_P,_P,_P,_P, /* 88-95 */
+_P,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L, /* 96-103 */
+_L,_L,_L,_L,_L,_L,_L,_L, /* 104-111 */
+_L,_L,_L,_L,_L,_L,_L,_L, /* 112-119 */
+_L,_L,_L,_P,_P,_P,_P,_C, /* 120-127 */
+0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
+0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
+_S|_SP,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 160-175 */
+_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 176-191 */
+_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U, /* 192-207 */
+_U,_U,_U,_U,_U,_U,_U,_P,_U,_U,_U,_U,_U,_U,_U,_L, /* 208-223 */
+_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L, /* 224-239 */
+_L,_L,_L,_L,_L,_L,_L,_P,_L,_L,_L,_L,_L,_L,_L,_L}; /* 240-255 */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <stdarg.h>
+#include <malloc.h>
+#include <devices.h>
+#include <serial.h>
+#ifdef CONFIG_LOGBUFFER
+#include <logbuff.h>
+#endif
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#include <i2c.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+list_t devlist = 0;
+device_t *stdio_devices[] = { NULL, NULL, NULL };
+char *stdio_names[MAX_FILES] = { "stdin", "stdout", "stderr" };
+
+#if defined(CONFIG_SPLASH_SCREEN) && !defined(CFG_DEVICE_NULLDEV)
+#define CFG_DEVICE_NULLDEV 1
+#endif
+
+
+#ifdef CFG_DEVICE_NULLDEV
+void nulldev_putc(const char c)
+{
+ /* nulldev is empty! */
+}
+
+void nulldev_puts(const char *s)
+{
+ /* nulldev is empty! */
+}
+
+int nulldev_input(void)
+{
+ /* nulldev is empty! */
+ return 0;
+}
+#endif
+
+/**************************************************************************
+ * SYSTEM DRIVERS
+ **************************************************************************
+ */
+
+static void drv_system_init (void)
+{
+ device_t dev;
+
+ memset (&dev, 0, sizeof (dev));
+
+ strcpy (dev.name, "serial");
+ dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
+ dev.putc = serial_buffered_putc;
+ dev.puts = serial_buffered_puts;
+ dev.getc = serial_buffered_getc;
+ dev.tstc = serial_buffered_tstc;
+#else
+ dev.putc = serial_putc;
+ dev.puts = serial_puts;
+ dev.getc = serial_getc;
+ dev.tstc = serial_tstc;
+#endif
+
+ device_register (&dev);
+
+#ifdef CFG_DEVICE_NULLDEV
+ memset (&dev, 0, sizeof (dev));
+
+ strcpy (dev.name, "nulldev");
+ dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+ dev.putc = nulldev_putc;
+ dev.puts = nulldev_puts;
+ dev.getc = nulldev_input;
+ dev.tstc = nulldev_input;
+
+ device_register (&dev);
+#endif
+}
+
+/**************************************************************************
+ * DEVICES
+ **************************************************************************
+ */
+
+int device_register (device_t * dev)
+{
+ ListInsertItem (devlist, dev, LIST_END);
+ return 0;
+}
+
+/* deregister the device "devname".
+ * returns 0 if success, -1 if device is assigned and 1 if devname not found
+ */
+#ifdef CFG_DEVICE_DEREGISTER
+int device_deregister(char *devname)
+{
+ int i,l,dev_index;
+ device_t *dev = NULL;
+ char temp_names[3][8];
+
+ dev_index=-1;
+ for (i=1; i<=ListNumItems(devlist); i++) {
+ dev = ListGetPtrToItem (devlist, i);
+ if(strcmp(dev->name,devname)==0) {
+ dev_index=i;
+ break;
+ }
+ }
+ if(dev_index<0) /* device not found */
+ return 0;
+ /* get stdio devices (ListRemoveItem changes the dev list) */
+ for (l=0 ; l< MAX_FILES; l++) {
+ if (stdio_devices[l] == dev) {
+ /* Device is assigned -> report error */
+ return -1;
+ }
+ memcpy (&temp_names[l][0],
+ stdio_devices[l]->name,
+ sizeof(stdio_devices[l]->name));
+ }
+ ListRemoveItem(devlist,NULL,dev_index);
+ /* reassign Device list */
+ for (i=1; i<=ListNumItems(devlist); i++) {
+ dev = ListGetPtrToItem (devlist, i);
+ for (l=0 ; l< MAX_FILES; l++) {
+ if(strcmp(dev->name,temp_names[l])==0) {
+ stdio_devices[l] = dev;
+ }
+ }
+ }
+ return 0;
+}
+#endif /* CFG_DEVICE_DEREGISTER */
+
+int devices_init (void)
+{
+#ifndef CONFIG_ARM /* already relocated for current ARM implementation */
+ ulong relocation_offset = gd->reloc_off;
+ int i;
+
+ /* relocate device name pointers */
+ for (i = 0; i < (sizeof (stdio_names) / sizeof (char *)); ++i) {
+ stdio_names[i] = (char *) (((ulong) stdio_names[i]) +
+ relocation_offset);
+ }
+#endif
+
+ /* Initialize the list */
+ devlist = ListCreate (sizeof (device_t));
+
+ if (devlist == NULL) {
+ eputs ("Cannot initialize the list of devices!\n");
+ return -1;
+ }
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+ i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+#endif
+#ifdef CONFIG_LCD
+ drv_lcd_init ();
+#endif
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+ drv_video_init ();
+#endif
+#ifdef CONFIG_KEYBOARD
+ drv_keyboard_init ();
+#endif
+#ifdef CONFIG_LOGBUFFER
+ drv_logbuff_init ();
+#endif
+ drv_system_init ();
+#ifdef CONFIG_SERIAL_MULTI
+ serial_devices_init ();
+#endif
+#ifdef CONFIG_USB_TTY
+ drv_usbtty_init ();
+#endif
+#ifdef CONFIG_NETCONSOLE
+ drv_nc_init ();
+#endif
+
+ return (0);
+}
+
+int devices_done (void)
+{
+ ListDispose (devlist);
+
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int display_options (void)
+{
+ extern char version_string[];
+
+#if defined(BUILD_TAG)
+ printf ("\n\n%s, Build: %s\n\n", version_string, BUILD_TAG);
+#else
+ printf ("\n\n%s\n\n", version_string);
+#endif
+ return 0;
+}
+
+/*
+ * print sizes as "xxx kB", "xxx.y kB", "xxx MB" or "xxx.y MB" as needed;
+ * allow for optional trailing string (like "\n")
+ */
+void print_size (ulong size, const char *s)
+{
+ ulong m, n;
+ ulong d = 1 << 20; /* 1 MB */
+ char c = 'M';
+
+ if (size < d) { /* print in kB */
+ c = 'k';
+ d = 1 << 10;
+ }
+
+ n = size / d;
+
+ m = (10 * (size - (n * d)) + (d / 2) ) / d;
+
+ if (m >= 10) {
+ m -= 10;
+ n += 1;
+ }
+
+ printf ("%2ld", n);
+ if (m) {
+ printf (".%ld", m);
+ }
+ printf (" %cB%s", c, s);
+}
--- /dev/null
+#include <common.h>
+#include <malloc.h>
+#include <lists.h>
+
+#define MAX(a,b) (((a)>(b)) ? (a) : (b))
+#define MIN(a,b) (((a)<(b)) ? (a) : (b))
+#define CAT4CHARS(a,b,c,d) ((a<<24) | (b<<16) | (c<<8) | d)
+
+/* increase list size by 10% every time it is full */
+#define kDefaultAllocationPercentIncrease 10
+
+/* always increase list size by 4 items when it is full */
+#define kDefaultAllocationminNumItemsIncrease 4
+
+/*
+ * how many items to expand the list by when it becomes full
+ * = current listSize (in items) + (hiword percent of list size) + loword
+ */
+#define NUMITEMSPERALLOC(list) MAX(((*list)->listSize * \
+ ((*list)->percentIncrease + 100)) / 100, \
+ (*list)->minNumItemsIncrease )
+
+#define ITEMPTR(list,item) &(((char *)&(*list)->itemList)[(*(list))->itemSize * (item)])
+
+#define LIST_SIGNATURE CAT4CHARS('L', 'I', 'S', 'T');
+
+#define calloc(size,num) malloc(size*num)
+
+/********************************************************************/
+
+Handle NewHandle (unsigned int numBytes)
+{
+ void *memPtr;
+ HandleRecord *hanPtr;
+
+ memPtr = calloc (numBytes, 1);
+ hanPtr = (HandleRecord *) calloc (sizeof (HandleRecord), 1);
+ if (hanPtr && (memPtr || numBytes == 0)) {
+ hanPtr->ptr = memPtr;
+ hanPtr->size = numBytes;
+ return (Handle) hanPtr;
+ } else {
+ free (memPtr);
+ free (hanPtr);
+ return NULL;
+ }
+}
+/********************************************************************/
+
+void DisposeHandle (Handle handle)
+{
+ if (handle) {
+ free (*handle);
+ free ((void *) handle);
+ }
+}
+/********************************************************************/
+
+unsigned int GetHandleSize (Handle handle)
+{
+ return ((HandleRecord *) handle)->size;
+}
+/********************************************************************/
+
+int SetHandleSize (Handle handle, unsigned int newSize)
+{
+ HandleRecord *hanRecPtr = (HandleRecord *) handle;
+ void *newPtr, *oldPtr;
+ unsigned int oldSize;
+
+
+ oldPtr = hanRecPtr->ptr;
+ oldSize = hanRecPtr->size;
+
+ if (oldSize == newSize)
+ return 1;
+
+ if (oldPtr == NULL) {
+ newPtr = malloc (newSize);
+ } else {
+ newPtr = realloc (oldPtr, newSize);
+ }
+ if (newPtr || (newSize == 0)) {
+ hanRecPtr->ptr = newPtr;
+ hanRecPtr->size = newSize;
+ if (newSize > oldSize)
+ memset ((char *) newPtr + oldSize, 0, newSize - oldSize);
+ return 1;
+ } else
+ return 0;
+}
+
+#ifdef CFG_ALL_LIST_FUNCTIONS
+
+/* Used to compare list elements by their raw data contents */
+static int ListMemBlockCmp (void *a, void *b, int size)
+{
+ return memcmp (a, b, size);
+}
+
+/***************************************************************************/
+
+/*
+ * Binary search numElements of size elementSize in array for a match
+ * to the. item. Return the index of the element that matches
+ * (0 - numElements - 1). If no match is found return the -i-1 where
+ * i is the index (0 - numElements) where the item should be placed.
+ * (*theCmp)(a,b) should return <0 if a<b, 0 if a==b, >0 if a>b.
+ *
+ * This function is like the C-Library function bsearch() except that
+ * this function returns the index where the item should be placed if
+ * it is not found.
+ */
+int BinSearch ( void *array, int numElements, int elementSize,
+ void *itemPtr, CompareFunction compareFunction)
+{
+ int low, high, mid, cmp;
+ void *arrayItemPtr;
+
+ for (low = 0, high = numElements - 1, mid = 0, cmp = -1; low <= high;) {
+ mid = (low + high) >> 1;
+
+ arrayItemPtr = (void *) (((char *) array) + (mid * elementSize));
+ cmp = compareFunction
+ ? compareFunction (itemPtr, arrayItemPtr)
+ : ListMemBlockCmp (itemPtr, arrayItemPtr, elementSize);
+ if (cmp == 0) {
+ return mid;
+ } else if (cmp < 0) {
+ high = mid - 1;
+ } else {
+ low = mid + 1;
+ }
+ }
+ if (cmp > 0)
+ mid++;
+
+ return -mid - 1;
+}
+
+#endif /* CFG_ALL_LIST_FUNCTIONS */
+
+/*******************************************************************************/
+
+/*
+ * If numNewItems == 0 then expand the list by the number of items
+ * indicated by its allocation policy.
+ * If numNewItems > 0 then expand the list by exactly the number of
+ * items indicated.
+ * If numNewItems < 0 then expand the list by the absolute value of
+ * numNewItems plus the number of items indicated by its allocation
+ * policy.
+ * Returns 1 for success, 0 if out of memory
+*/
+static int ExpandListSpace (list_t list, int numNewItems)
+{
+ if (numNewItems == 0) {
+ numNewItems = NUMITEMSPERALLOC (list);
+ } else if (numNewItems < 0) {
+ numNewItems = (-numNewItems) + NUMITEMSPERALLOC (list);
+ }
+
+ if (SetHandleSize ((Handle) list,
+ sizeof (ListStruct) +
+ ((*list)->listSize +
+ numNewItems) * (*list)->itemSize)) {
+ (*list)->listSize += numNewItems;
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/*******************************/
+
+#ifdef CFG_ALL_LIST_FUNCTIONS
+
+/*
+ * This function reallocate the list, minus any currently unused
+ * portion of its allotted memory.
+ */
+void ListCompact (list_t list)
+{
+
+ if (!SetHandleSize ((Handle) list,
+ sizeof (ListStruct) +
+ (*list)->numItems * (*list)->itemSize)) {
+ return;
+ }
+
+ (*list)->listSize = (*list)->numItems;
+}
+
+#endif /* CFG_ALL_LIST_FUNCTIONS */
+
+/*******************************/
+
+list_t ListCreate (int elementSize)
+{
+ list_t list;
+
+ list = (list_t) (NewHandle (sizeof (ListStruct))); /* create empty list */
+ if (list) {
+ (*list)->signature = LIST_SIGNATURE;
+ (*list)->numItems = 0;
+ (*list)->listSize = 0;
+ (*list)->itemSize = elementSize;
+ (*list)->percentIncrease = kDefaultAllocationPercentIncrease;
+ (*list)->minNumItemsIncrease =
+ kDefaultAllocationminNumItemsIncrease;
+ }
+
+ return list;
+}
+
+/*******************************/
+
+void ListSetAllocationPolicy (list_t list, int minItemsPerAlloc,
+ int percentIncreasePerAlloc)
+{
+ (*list)->percentIncrease = percentIncreasePerAlloc;
+ (*list)->minNumItemsIncrease = minItemsPerAlloc;
+}
+
+/*******************************/
+
+void ListDispose (list_t list)
+{
+ DisposeHandle ((Handle) list);
+}
+/*******************************/
+
+#ifdef CFG_ALL_LIST_FUNCTIONS
+
+void ListDisposePtrList (list_t list)
+{
+ int index;
+ int numItems;
+
+ if (list) {
+ numItems = ListNumItems (list);
+
+ for (index = 1; index <= numItems; index++)
+ free (*(void **) ListGetPtrToItem (list, index));
+
+ ListDispose (list);
+ }
+}
+
+/*******************************/
+
+/*
+ * keeps memory, resets the number of items to 0
+ */
+void ListClear (list_t list)
+{
+ if (!list)
+ return;
+ (*list)->numItems = 0;
+}
+
+/*******************************/
+
+/*
+ * copy is only as large as necessary
+ */
+list_t ListCopy (list_t originalList)
+{
+ list_t tempList = NULL;
+ int numItems;
+
+ if (!originalList)
+ return NULL;
+
+ tempList = ListCreate ((*originalList)->itemSize);
+ if (tempList) {
+ numItems = ListNumItems (originalList);
+
+ if (!SetHandleSize ((Handle) tempList,
+ sizeof (ListStruct) +
+ numItems * (*tempList)->itemSize)) {
+ ListDispose (tempList);
+ return NULL;
+ }
+
+ (*tempList)->numItems = (*originalList)->numItems;
+ (*tempList)->listSize = (*originalList)->numItems;
+ (*tempList)->itemSize = (*originalList)->itemSize;
+ (*tempList)->percentIncrease = (*originalList)->percentIncrease;
+ (*tempList)->minNumItemsIncrease =
+ (*originalList)->minNumItemsIncrease;
+
+ memcpy (ITEMPTR (tempList, 0), ITEMPTR (originalList, 0),
+ numItems * (*tempList)->itemSize);
+ }
+
+ return tempList;
+}
+
+/********************************/
+
+/*
+ * list1 = list1 + list2
+ */
+int ListAppend (list_t list1, list_t list2)
+{
+ int numItemsL1, numItemsL2;
+
+ if (!list2)
+ return 1;
+
+ if (!list1)
+ return 0;
+ if ((*list1)->itemSize != (*list2)->itemSize)
+ return 0;
+
+ numItemsL1 = ListNumItems (list1);
+ numItemsL2 = ListNumItems (list2);
+
+ if (numItemsL2 == 0)
+ return 1;
+
+ if (!SetHandleSize ((Handle) list1,
+ sizeof (ListStruct) + (numItemsL1 + numItemsL2) *
+ (*list1)->itemSize)) {
+ return 0;
+ }
+
+ (*list1)->numItems = numItemsL1 + numItemsL2;
+ (*list1)->listSize = numItemsL1 + numItemsL2;
+
+ memmove (ITEMPTR (list1, numItemsL1),
+ ITEMPTR (list2, 0),
+ numItemsL2 * (*list2)->itemSize);
+
+ return 1;
+}
+
+#endif /* CFG_ALL_LIST_FUNCTIONS */
+
+/*******************************/
+
+/*
+ * returns 1 if the item is inserted, returns 0 if out of memory or
+ * bad arguments were passed.
+ */
+int ListInsertItem (list_t list, void *ptrToItem, int itemPosition)
+{
+ return ListInsertItems (list, ptrToItem, itemPosition, 1);
+}
+
+/*******************************/
+
+int ListInsertItems (list_t list, void *ptrToItems, int firstItemPosition,
+ int numItemsToInsert)
+{
+ int numItems = (*list)->numItems;
+
+ if (firstItemPosition == numItems + 1)
+ firstItemPosition = LIST_END;
+ else if (firstItemPosition > numItems)
+ return 0;
+
+ if ((*list)->numItems >= (*list)->listSize) {
+ if (!ExpandListSpace (list, -numItemsToInsert))
+ return 0;
+ }
+
+ if (firstItemPosition == LIST_START) {
+ if (numItems == 0) {
+ /* special case for empty list */
+ firstItemPosition = LIST_END;
+ } else {
+ firstItemPosition = 1;
+ }
+ }
+
+ if (firstItemPosition == LIST_END) { /* add at the end of the list */
+ if (ptrToItems)
+ memcpy (ITEMPTR (list, numItems), ptrToItems,
+ (*list)->itemSize * numItemsToInsert);
+ else
+ memset (ITEMPTR (list, numItems), 0,
+ (*list)->itemSize * numItemsToInsert);
+
+ (*list)->numItems += numItemsToInsert;
+ } else { /* move part of list up to make room for new item */
+ memmove (ITEMPTR (list, firstItemPosition - 1 + numItemsToInsert),
+ ITEMPTR (list, firstItemPosition - 1),
+ (numItems + 1 - firstItemPosition) * (*list)->itemSize);
+
+ if (ptrToItems)
+ memmove (ITEMPTR (list, firstItemPosition - 1), ptrToItems,
+ (*list)->itemSize * numItemsToInsert);
+ else
+ memset (ITEMPTR (list, firstItemPosition - 1), 0,
+ (*list)->itemSize * numItemsToInsert);
+
+ (*list)->numItems += numItemsToInsert;
+ }
+
+ return 1;
+}
+
+#ifdef CFG_ALL_LIST_FUNCTIONS
+
+/*******************************/
+
+int ListEqual (list_t list1, list_t list2)
+{
+ if (list1 == list2)
+ return 1;
+
+ if (list1 == NULL || list2 == NULL)
+ return 0;
+
+ if ((*list1)->itemSize == (*list1)->itemSize) {
+ if ((*list1)->numItems == (*list2)->numItems) {
+ return (memcmp (ITEMPTR (list1, 0), ITEMPTR (list2, 0),
+ (*list1)->itemSize * (*list1)->numItems) == 0);
+ }
+ }
+
+ return 0;
+}
+
+/*******************************/
+
+/*
+ * The item pointed to by ptrToItem is copied over the current item
+ * at itemPosition
+ */
+void ListReplaceItem (list_t list, void *ptrToItem, int itemPosition)
+{
+ ListReplaceItems (list, ptrToItem, itemPosition, 1);
+}
+
+/*******************************/
+
+/*
+ * The item pointed to by ptrToItems is copied over the current item
+ * at itemPosition
+ */
+void ListReplaceItems ( list_t list, void *ptrToItems,
+ int firstItemPosition, int numItemsToReplace)
+{
+
+ if (firstItemPosition == LIST_END)
+ firstItemPosition = (*list)->numItems;
+ else if (firstItemPosition == LIST_START)
+ firstItemPosition = 1;
+
+ memmove (ITEMPTR (list, firstItemPosition - 1), ptrToItems,
+ (*list)->itemSize * numItemsToReplace);
+}
+
+/*******************************/
+
+void ListGetItem (list_t list, void *itemDestination, int itemPosition)
+{
+ ListGetItems (list, itemDestination, itemPosition, 1);
+}
+
+#endif /* CFG_ALL_LIST_FUNCTIONS */
+
+/*******************************/
+
+#if defined(CFG_ALL_LIST_FUNCTIONS) || defined(CFG_DEVICE_DEREGISTER)
+
+void ListRemoveItem (list_t list, void *itemDestination, int itemPosition)
+{
+ ListRemoveItems (list, itemDestination, itemPosition, 1);
+}
+
+/*******************************/
+
+void ListRemoveItems (list_t list, void *itemsDestination,
+ int firstItemPosition, int numItemsToRemove)
+{
+ int firstItemAfterChunk, numToMove;
+
+ if (firstItemPosition == LIST_START)
+ firstItemPosition = 1;
+ else if (firstItemPosition == LIST_END)
+ firstItemPosition = (*list)->numItems;
+
+ if (itemsDestination != NULL)
+ memcpy (itemsDestination, ITEMPTR (list, firstItemPosition - 1),
+ (*list)->itemSize * numItemsToRemove);
+
+ firstItemAfterChunk = firstItemPosition + numItemsToRemove;
+ numToMove = (*list)->numItems - (firstItemAfterChunk - 1);
+
+ if (numToMove > 0) {
+ /*
+ * move part of list down to cover hole left by removed item
+ */
+ memmove (ITEMPTR (list, firstItemPosition - 1),
+ ITEMPTR (list, firstItemAfterChunk - 1),
+ (*list)->itemSize * numToMove);
+ }
+
+ (*list)->numItems -= numItemsToRemove;
+}
+#endif /* CFG_ALL_LIST_FUNCTIONS || CFG_DEVICE_DEREGISTER */
+
+/*******************************/
+
+void ListGetItems (list_t list, void *itemsDestination,
+ int firstItemPosition, int numItemsToGet)
+{
+
+ if (firstItemPosition == LIST_START)
+ firstItemPosition = 1;
+ else if (firstItemPosition == LIST_END)
+ firstItemPosition = (*list)->numItems;
+
+ memcpy (itemsDestination,
+ ITEMPTR (list, firstItemPosition - 1),
+ (*list)->itemSize * numItemsToGet);
+}
+
+/*******************************/
+
+/*
+ * Returns a pointer to the item at itemPosition. returns null if an
+ * errors occurred.
+ */
+void *ListGetPtrToItem (list_t list, int itemPosition)
+{
+ if (itemPosition == LIST_START)
+ itemPosition = 1;
+ else if (itemPosition == LIST_END)
+ itemPosition = (*list)->numItems;
+
+ return ITEMPTR (list, itemPosition - 1);
+}
+
+/*******************************/
+
+/*
+ * returns a pointer the lists data (abstraction violation for
+ * optimization)
+ */
+void *ListGetDataPtr (list_t list)
+{
+ return &((*list)->itemList[0]);
+}
+
+/********************************/
+
+#ifdef CFG_ALL_LIST_FUNCTIONS
+
+int ListApplyToEach (list_t list, int ascending,
+ ListApplicationFunc funcToApply,
+ void *callbackData)
+{
+ int result = 0, index;
+
+ if (!list || !funcToApply)
+ goto Error;
+
+ if (ascending) {
+ for (index = 1; index <= ListNumItems (list); index++) {
+ result = funcToApply (index,
+ ListGetPtrToItem (list, index),
+ callbackData);
+ if (result < 0)
+ goto Error;
+ }
+ } else {
+ for (index = ListNumItems (list);
+ index > 0 && index <= ListNumItems (list);
+ index--) {
+ result = funcToApply (index,
+ ListGetPtrToItem (list, index),
+ callbackData);
+ if (result < 0)
+ goto Error;
+ }
+ }
+
+Error:
+ return result;
+}
+
+#endif /* CFG_ALL_LIST_FUNCTIONS */
+
+/********************************/
+
+int ListGetItemSize (list_t list)
+{
+ return (*list)->itemSize;
+}
+
+/********************************/
+
+int ListNumItems (list_t list)
+{
+ return (*list)->numItems;
+}
+
+/*******************************/
+
+#ifdef CFG_ALL_LIST_FUNCTIONS
+
+void ListRemoveDuplicates (list_t list, CompareFunction compareFunction)
+{
+ int numItems, index, startIndexForFind, duplicatesIndex;
+
+ numItems = ListNumItems (list);
+
+ for (index = 1; index < numItems; index++) {
+ startIndexForFind = index + 1;
+ while (startIndexForFind <= numItems) {
+ duplicatesIndex =
+ ListFindItem (list,
+ ListGetPtrToItem (list, index),
+ startIndexForFind,
+ compareFunction);
+ if (duplicatesIndex > 0) {
+ ListRemoveItem (list, NULL, duplicatesIndex);
+ numItems--;
+ startIndexForFind = duplicatesIndex;
+ } else {
+ break;
+ }
+ }
+ }
+}
+
+/*******************************/
+
+
+/*******************************/
+
+int ListFindItem (list_t list, void *ptrToItem, int startingPosition,
+ CompareFunction compareFunction)
+{
+ int numItems, size, index, cmp;
+ void *listItemPtr;
+
+ if ((numItems = (*list)->numItems) == 0)
+ return 0;
+
+ size = (*list)->itemSize;
+
+ if (startingPosition == LIST_START)
+ startingPosition = 1;
+ else if (startingPosition == LIST_END)
+ startingPosition = numItems;
+
+ for (index = startingPosition; index <= numItems; index++) {
+ listItemPtr = ITEMPTR (list, index - 1);
+ cmp = compareFunction
+ ? compareFunction (ptrToItem, listItemPtr)
+ : ListMemBlockCmp (ptrToItem, listItemPtr, size);
+ if (cmp == 0)
+ return index;
+ }
+
+ return 0;
+}
+
+/*******************************/
+
+int ShortCompare (void *a, void *b)
+{
+ if (*(short *) a < *(short *) b)
+ return -1;
+ if (*(short *) a > *(short *) b)
+ return 1;
+ return 0;
+}
+
+/*******************************/
+
+int IntCompare (void *a, void *b)
+{
+ if (*(int *) a < *(int *) b)
+ return -1;
+ if (*(int *) a > *(int *) b)
+ return 1;
+ return 0;
+}
+
+/*******************************/
+
+int CStringCompare (void *a, void *b)
+{
+ return strcmp (*(char **) a, *(char **) b);
+}
+
+/*******************************/
+
+
+int ListBinSearch (list_t list, void *ptrToItem,
+ CompareFunction compareFunction)
+{
+ int index;
+
+ index = BinSearch (ITEMPTR (list, 0),
+ (int) (*list)->numItems,
+ (int) (*list)->itemSize, ptrToItem,
+ compareFunction);
+
+ if (index >= 0)
+ index++; /* lists start from 1 */
+ else
+ index = 0; /* item not found */
+
+ return index;
+}
+
+/**************************************************************************/
+
+/*
+ * Reserves memory for numItems in the list. If it succeeds then
+ * numItems items can be inserted without possibility of an out of
+ * memory error (useful to simplify error recovery in complex
+ * functions). Returns 1 if success, 0 if out of memory.
+ */
+int ListPreAllocate (list_t list, int numItems)
+{
+ if ((*list)->listSize - (*list)->numItems < numItems) {
+ return ExpandListSpace (list,
+ numItems - ((*list)->listSize -
+ (*list)->numItems));
+ } else {
+ return 1; /* enough items are already pre-allocated */
+ }
+}
+
+#endif /* CFG_ALL_LIST_FUNCTIONS */
--- /dev/null
+/*
+ * linux/lib/string.c
+ *
+ * Copyright (C) 1991, 1992 Linus Torvalds
+ */
+
+/*
+ * stupid library routines.. The optimized versions should generally be found
+ * as inline code in <asm-xx/string.h>
+ *
+ * These are buggy as well..
+ *
+ * * Fri Jun 25 1999, Ingo Oeser <ioe@informatik.tu-chemnitz.de>
+ * - Added strsep() which will replace strtok() soon (because strsep() is
+ * reentrant and should be faster). Use only strsep() in new code, please.
+ */
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <malloc.h>
+
+
+#if 0 /* not used - was: #ifndef __HAVE_ARCH_STRNICMP */
+/**
+ * strnicmp - Case insensitive, length-limited string comparison
+ * @s1: One string
+ * @s2: The other string
+ * @len: the maximum number of characters to compare
+ */
+int strnicmp(const char *s1, const char *s2, size_t len)
+{
+ /* Yes, Virginia, it had better be unsigned */
+ unsigned char c1, c2;
+
+ c1 = 0; c2 = 0;
+ if (len) {
+ do {
+ c1 = *s1; c2 = *s2;
+ s1++; s2++;
+ if (!c1)
+ break;
+ if (!c2)
+ break;
+ if (c1 == c2)
+ continue;
+ c1 = tolower(c1);
+ c2 = tolower(c2);
+ if (c1 != c2)
+ break;
+ } while (--len);
+ }
+ return (int)c1 - (int)c2;
+}
+#endif
+
+char * ___strtok;
+
+#ifndef __HAVE_ARCH_STRCPY
+/**
+ * strcpy - Copy a %NUL terminated string
+ * @dest: Where to copy the string to
+ * @src: Where to copy the string from
+ */
+char * strcpy(char * dest,const char *src)
+{
+ char *tmp = dest;
+
+ while ((*dest++ = *src++) != '\0')
+ /* nothing */;
+ return tmp;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRNCPY
+/**
+ * strncpy - Copy a length-limited, %NUL-terminated string
+ * @dest: Where to copy the string to
+ * @src: Where to copy the string from
+ * @count: The maximum number of bytes to copy
+ *
+ * Note that unlike userspace strncpy, this does not %NUL-pad the buffer.
+ * However, the result is not %NUL-terminated if the source exceeds
+ * @count bytes.
+ */
+char * strncpy(char * dest,const char *src,size_t count)
+{
+ char *tmp = dest;
+
+ while (count-- && (*dest++ = *src++) != '\0')
+ /* nothing */;
+
+ return tmp;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRCAT
+/**
+ * strcat - Append one %NUL-terminated string to another
+ * @dest: The string to be appended to
+ * @src: The string to append to it
+ */
+char * strcat(char * dest, const char * src)
+{
+ char *tmp = dest;
+
+ while (*dest)
+ dest++;
+ while ((*dest++ = *src++) != '\0')
+ ;
+
+ return tmp;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRNCAT
+/**
+ * strncat - Append a length-limited, %NUL-terminated string to another
+ * @dest: The string to be appended to
+ * @src: The string to append to it
+ * @count: The maximum numbers of bytes to copy
+ *
+ * Note that in contrast to strncpy, strncat ensures the result is
+ * terminated.
+ */
+char * strncat(char *dest, const char *src, size_t count)
+{
+ char *tmp = dest;
+
+ if (count) {
+ while (*dest)
+ dest++;
+ while ((*dest++ = *src++)) {
+ if (--count == 0) {
+ *dest = '\0';
+ break;
+ }
+ }
+ }
+
+ return tmp;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRCMP
+/**
+ * strcmp - Compare two strings
+ * @cs: One string
+ * @ct: Another string
+ */
+int strcmp(const char * cs,const char * ct)
+{
+ register signed char __res;
+
+ while (1) {
+ if ((__res = *cs - *ct++) != 0 || !*cs++)
+ break;
+ }
+
+ return __res;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRNCMP
+/**
+ * strncmp - Compare two length-limited strings
+ * @cs: One string
+ * @ct: Another string
+ * @count: The maximum number of bytes to compare
+ */
+int strncmp(const char * cs,const char * ct,size_t count)
+{
+ register signed char __res = 0;
+
+ while (count) {
+ if ((__res = *cs - *ct++) != 0 || !*cs++)
+ break;
+ count--;
+ }
+
+ return __res;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRCHR
+/**
+ * strchr - Find the first occurrence of a character in a string
+ * @s: The string to be searched
+ * @c: The character to search for
+ */
+char * strchr(const char * s, int c)
+{
+ for(; *s != (char) c; ++s)
+ if (*s == '\0')
+ return NULL;
+ return (char *) s;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRRCHR
+/**
+ * strrchr - Find the last occurrence of a character in a string
+ * @s: The string to be searched
+ * @c: The character to search for
+ */
+char * strrchr(const char * s, int c)
+{
+ const char *p = s + strlen(s);
+ do {
+ if (*p == (char)c)
+ return (char *)p;
+ } while (--p >= s);
+ return NULL;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRLEN
+/**
+ * strlen - Find the length of a string
+ * @s: The string to be sized
+ */
+size_t strlen(const char * s)
+{
+ const char *sc;
+
+ for (sc = s; *sc != '\0'; ++sc)
+ /* nothing */;
+ return sc - s;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRNLEN
+/**
+ * strnlen - Find the length of a length-limited string
+ * @s: The string to be sized
+ * @count: The maximum number of bytes to search
+ */
+size_t strnlen(const char * s, size_t count)
+{
+ const char *sc;
+
+ for (sc = s; count-- && *sc != '\0'; ++sc)
+ /* nothing */;
+ return sc - s;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRDUP
+char * strdup(const char *s)
+{
+ char *new;
+
+ if ((s == NULL) ||
+ ((new = malloc (strlen(s) + 1)) == NULL) ) {
+ return NULL;
+ }
+
+ strcpy (new, s);
+ return new;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRSPN
+/**
+ * strspn - Calculate the length of the initial substring of @s which only
+ * contain letters in @accept
+ * @s: The string to be searched
+ * @accept: The string to search for
+ */
+size_t strspn(const char *s, const char *accept)
+{
+ const char *p;
+ const char *a;
+ size_t count = 0;
+
+ for (p = s; *p != '\0'; ++p) {
+ for (a = accept; *a != '\0'; ++a) {
+ if (*p == *a)
+ break;
+ }
+ if (*a == '\0')
+ return count;
+ ++count;
+ }
+
+ return count;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRPBRK
+/**
+ * strpbrk - Find the first occurrence of a set of characters
+ * @cs: The string to be searched
+ * @ct: The characters to search for
+ */
+char * strpbrk(const char * cs,const char * ct)
+{
+ const char *sc1,*sc2;
+
+ for( sc1 = cs; *sc1 != '\0'; ++sc1) {
+ for( sc2 = ct; *sc2 != '\0'; ++sc2) {
+ if (*sc1 == *sc2)
+ return (char *) sc1;
+ }
+ }
+ return NULL;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRTOK
+/**
+ * strtok - Split a string into tokens
+ * @s: The string to be searched
+ * @ct: The characters to search for
+ *
+ * WARNING: strtok is deprecated, use strsep instead.
+ */
+char * strtok(char * s,const char * ct)
+{
+ char *sbegin, *send;
+
+ sbegin = s ? s : ___strtok;
+ if (!sbegin) {
+ return NULL;
+ }
+ sbegin += strspn(sbegin,ct);
+ if (*sbegin == '\0') {
+ ___strtok = NULL;
+ return( NULL );
+ }
+ send = strpbrk( sbegin, ct);
+ if (send && *send != '\0')
+ *send++ = '\0';
+ ___strtok = send;
+ return (sbegin);
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRSEP
+/**
+ * strsep - Split a string into tokens
+ * @s: The string to be searched
+ * @ct: The characters to search for
+ *
+ * strsep() updates @s to point after the token, ready for the next call.
+ *
+ * It returns empty tokens, too, behaving exactly like the libc function
+ * of that name. In fact, it was stolen from glibc2 and de-fancy-fied.
+ * Same semantics, slimmer shape. ;)
+ */
+char * strsep(char **s, const char *ct)
+{
+ char *sbegin = *s, *end;
+
+ if (sbegin == NULL)
+ return NULL;
+
+ end = strpbrk(sbegin, ct);
+ if (end)
+ *end++ = '\0';
+ *s = end;
+
+ return sbegin;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRSWAB
+/**
+ * strswab - swap adjacent even and odd bytes in %NUL-terminated string
+ * s: address of the string
+ *
+ * returns the address of the swapped string or NULL on error. If
+ * string length is odd, last byte is untouched.
+ */
+char *strswab(const char *s)
+{
+ char *p, *q;
+
+ if ((NULL == s) || ('\0' == *s)) {
+ return (NULL);
+ }
+
+ for (p=(char *)s, q=p+1; (*p != '\0') && (*q != '\0'); p+=2, q+=2) {
+ char tmp;
+
+ tmp = *p;
+ *p = *q;
+ *q = tmp;
+ }
+
+ return (char *) s;
+}
+#endif
+
+#ifndef __HAVE_ARCH_MEMSET
+/**
+ * memset - Fill a region of memory with the given value
+ * @s: Pointer to the start of the area.
+ * @c: The byte to fill the area with
+ * @count: The size of the area.
+ *
+ * Do not use memset() to access IO space, use memset_io() instead.
+ */
+void * memset(void * s,int c,size_t count)
+{
+ char *xs = (char *) s;
+
+ while (count--)
+ *xs++ = c;
+
+ return s;
+}
+#endif
+
+#ifndef __HAVE_ARCH_BCOPY
+/**
+ * bcopy - Copy one area of memory to another
+ * @src: Where to copy from
+ * @dest: Where to copy to
+ * @count: The size of the area.
+ *
+ * Note that this is the same as memcpy(), with the arguments reversed.
+ * memcpy() is the standard, bcopy() is a legacy BSD function.
+ *
+ * You should not use this function to access IO space, use memcpy_toio()
+ * or memcpy_fromio() instead.
+ */
+char * bcopy(const char * src, char * dest, int count)
+{
+ char *tmp = dest;
+
+ while (count--)
+ *tmp++ = *src++;
+
+ return dest;
+}
+#endif
+
+#ifndef __HAVE_ARCH_MEMCPY
+/**
+ * memcpy - Copy one area of memory to another
+ * @dest: Where to copy to
+ * @src: Where to copy from
+ * @count: The size of the area.
+ *
+ * You should not use this function to access IO space, use memcpy_toio()
+ * or memcpy_fromio() instead.
+ */
+void * memcpy(void * dest,const void *src,size_t count)
+{
+ char *tmp = (char *) dest, *s = (char *) src;
+
+ while (count--)
+ *tmp++ = *s++;
+
+ return dest;
+}
+#endif
+
+#ifndef __HAVE_ARCH_MEMMOVE
+/**
+ * memmove - Copy one area of memory to another
+ * @dest: Where to copy to
+ * @src: Where to copy from
+ * @count: The size of the area.
+ *
+ * Unlike memcpy(), memmove() copes with overlapping areas.
+ */
+void * memmove(void * dest,const void *src,size_t count)
+{
+ char *tmp, *s;
+
+ if (dest <= src) {
+ tmp = (char *) dest;
+ s = (char *) src;
+ while (count--)
+ *tmp++ = *s++;
+ }
+ else {
+ tmp = (char *) dest + count;
+ s = (char *) src + count;
+ while (count--)
+ *--tmp = *--s;
+ }
+
+ return dest;
+}
+#endif
+
+#ifndef __HAVE_ARCH_MEMCMP
+/**
+ * memcmp - Compare two areas of memory
+ * @cs: One area of memory
+ * @ct: Another area of memory
+ * @count: The size of the area.
+ */
+int memcmp(const void * cs,const void * ct,size_t count)
+{
+ const unsigned char *su1, *su2;
+ int res = 0;
+
+ for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
+ if ((res = *su1 - *su2) != 0)
+ break;
+ return res;
+}
+#endif
+
+#ifndef __HAVE_ARCH_MEMSCAN
+/**
+ * memscan - Find a character in an area of memory.
+ * @addr: The memory area
+ * @c: The byte to search for
+ * @size: The size of the area.
+ *
+ * returns the address of the first occurrence of @c, or 1 byte past
+ * the area if @c is not found
+ */
+void * memscan(void * addr, int c, size_t size)
+{
+ unsigned char * p = (unsigned char *) addr;
+
+ while (size) {
+ if (*p == c)
+ return (void *) p;
+ p++;
+ size--;
+ }
+ return (void *) p;
+}
+#endif
+
+#ifndef __HAVE_ARCH_STRSTR
+/**
+ * strstr - Find the first substring in a %NUL terminated string
+ * @s1: The string to be searched
+ * @s2: The string to search for
+ */
+char * strstr(const char * s1,const char * s2)
+{
+ int l1, l2;
+
+ l2 = strlen(s2);
+ if (!l2)
+ return (char *) s1;
+ l1 = strlen(s1);
+ while (l1 >= l2) {
+ l1--;
+ if (!memcmp(s1,s2,l2))
+ return (char *) s1;
+ s1++;
+ }
+ return NULL;
+}
+#endif
+
+#ifndef __HAVE_ARCH_MEMCHR
+/**
+ * memchr - Find a character in an area of memory.
+ * @s: The memory area
+ * @c: The byte to search for
+ * @n: The size of the area.
+ *
+ * returns the address of the first occurrence of @c, or %NULL
+ * if @c is not found
+ */
+void *memchr(const void *s, int c, size_t n)
+{
+ const unsigned char *p = s;
+ while (n-- != 0) {
+ if ((unsigned char)c == *p++) {
+ return (void *)(p-1);
+ }
+ }
+ return NULL;
+}
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+
+static inline void mips_compare_set(u32 v)
+{
+ asm volatile ("mtc0 %0, $11" : : "r" (v));
+}
+
+static inline void mips_count_set(u32 v)
+{
+ asm volatile ("mtc0 %0, $9" : : "r" (v));
+}
+
+
+static inline u32 mips_count_get(void)
+{
+ u32 count;
+
+ asm volatile ("mfc0 %0, $9" : "=r" (count) :);
+ return count;
+}
+
+/*
+ * timer without interrupts
+ */
+
+int timer_init(void)
+{
+ mips_compare_set(0);
+ mips_count_set(0);
+
+ return 0;
+}
+
+void reset_timer(void)
+{
+ mips_count_set(0);
+}
+
+ulong get_timer(ulong base)
+{
+ return mips_count_get() - base;
+}
+
+void set_timer(ulong t)
+{
+ mips_count_set(t);
+}
+
+void udelay (unsigned long usec)
+{
+ ulong tmo;
+ ulong start = get_timer(0);
+
+ tmo = usec * (CFG_HZ / 1000000);
+ while ((ulong)((mips_count_get() - start)) < tmo)
+ /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On MIPS it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return mips_count_get();
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On MIPS it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CFG_HZ;
+}
--- /dev/null
+/*
+ * linux/lib/vsprintf.c
+ *
+ * Copyright (C) 1991, 1992 Linus Torvalds
+ */
+
+/* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */
+/*
+ * Wirzenius wrote this portably, Torvalds fucked it up :-)
+ */
+
+#include <stdarg.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+
+#include <common.h>
+#if !defined (CONFIG_PANIC_HANG)
+#include <command.h>
+/*cmd_boot.c*/
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+#endif
+
+unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base)
+{
+ unsigned long result = 0,value;
+
+ if (*cp == '0') {
+ cp++;
+ if ((*cp == 'x') && isxdigit(cp[1])) {
+ base = 16;
+ cp++;
+ }
+ if (!base) {
+ base = 8;
+ }
+ }
+ if (!base) {
+ base = 10;
+ }
+ while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp)
+ ? toupper(*cp) : *cp)-'A'+10) < base) {
+ result = result*base + value;
+ cp++;
+ }
+ if (endp)
+ *endp = (char *)cp;
+ return result;
+}
+
+long simple_strtol(const char *cp,char **endp,unsigned int base)
+{
+ if(*cp=='-')
+ return -simple_strtoul(cp+1,endp,base);
+ return simple_strtoul(cp,endp,base);
+}
+
+#ifdef CFG_64BIT_STRTOUL
+unsigned long long simple_strtoull (const char *cp, char **endp, unsigned int base)
+{
+ unsigned long long result = 0, value;
+
+ if (*cp == '0') {
+ cp++;
+ if ((*cp == 'x') && isxdigit (cp[1])) {
+ base = 16;
+ cp++;
+ }
+ if (!base) {
+ base = 8;
+ }
+ }
+ if (!base) {
+ base = 10;
+ }
+ while (isxdigit (*cp) && (value = isdigit (*cp)
+ ? *cp - '0'
+ : (islower (*cp) ? toupper (*cp) : *cp) - 'A' + 10) < base) {
+ result = result * base + value;
+ cp++;
+ }
+ if (endp)
+ *endp = (char *) cp;
+ return result;
+}
+#endif /* CFG_64BIT_STRTOUL */
+
+/* we use this so that we can do without the ctype library */
+#define is_digit(c) ((c) >= '0' && (c) <= '9')
+
+static int skip_atoi(const char **s)
+{
+ int i=0;
+
+ while (is_digit(**s))
+ i = i*10 + *((*s)++) - '0';
+ return i;
+}
+
+#define ZEROPAD 1 /* pad with zero */
+#define SIGN 2 /* unsigned/signed long */
+#define PLUS 4 /* show plus */
+#define SPACE 8 /* space if plus */
+#define LEFT 16 /* left justified */
+#define SPECIAL 32 /* 0x */
+#define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */
+
+#define do_div(n,base) ({ \
+ int __res; \
+ __res = ((unsigned long) n) % (unsigned) base; \
+ n = ((unsigned long) n) / (unsigned) base; \
+ __res; \
+})
+
+#ifdef CFG_64BIT_VSPRINTF
+static char * number(char * str, long long num, int base, int size, int precision ,int type)
+#else
+static char * number(char * str, long num, int base, int size, int precision ,int type)
+#endif
+{
+ char c,sign,tmp[66];
+ const char *digits="0123456789abcdefghijklmnopqrstuvwxyz";
+ int i;
+
+ if (type & LARGE)
+ digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ";
+ if (type & LEFT)
+ type &= ~ZEROPAD;
+ if (base < 2 || base > 36)
+ return 0;
+ c = (type & ZEROPAD) ? '0' : ' ';
+ sign = 0;
+ if (type & SIGN) {
+ if (num < 0) {
+ sign = '-';
+ num = -num;
+ size--;
+ } else if (type & PLUS) {
+ sign = '+';
+ size--;
+ } else if (type & SPACE) {
+ sign = ' ';
+ size--;
+ }
+ }
+ if (type & SPECIAL) {
+ if (base == 16)
+ size -= 2;
+ else if (base == 8)
+ size--;
+ }
+ i = 0;
+ if (num == 0)
+ tmp[i++]='0';
+ else while (num != 0)
+ tmp[i++] = digits[do_div(num,base)];
+ if (i > precision)
+ precision = i;
+ size -= precision;
+ if (!(type&(ZEROPAD+LEFT)))
+ while(size-->0)
+ *str++ = ' ';
+ if (sign)
+ *str++ = sign;
+ if (type & SPECIAL) {
+ if (base==8)
+ *str++ = '0';
+ else if (base==16) {
+ *str++ = '0';
+ *str++ = digits[33];
+ }
+ }
+ if (!(type & LEFT))
+ while (size-- > 0)
+ *str++ = c;
+ while (i < precision--)
+ *str++ = '0';
+ while (i-- > 0)
+ *str++ = tmp[i];
+ while (size-- > 0)
+ *str++ = ' ';
+ return str;
+}
+
+/* Forward decl. needed for IP address printing stuff... */
+int sprintf(char * buf, const char *fmt, ...);
+
+int vsprintf(char *buf, const char *fmt, va_list args)
+{
+ int len;
+#ifdef CFG_64BIT_VSPRINTF
+ unsigned long long num;
+#else
+ unsigned long num;
+#endif
+ int i, base;
+ char * str;
+ const char *s;
+
+ int flags; /* flags to number() */
+
+ int field_width; /* width of output field */
+ int precision; /* min. # of digits for integers; max
+ number of chars for from string */
+ int qualifier; /* 'h', 'l', or 'q' for integer fields */
+
+ for (str=buf ; *fmt ; ++fmt) {
+ if (*fmt != '%') {
+ *str++ = *fmt;
+ continue;
+ }
+
+ /* process flags */
+ flags = 0;
+ repeat:
+ ++fmt; /* this also skips first '%' */
+ switch (*fmt) {
+ case '-': flags |= LEFT; goto repeat;
+ case '+': flags |= PLUS; goto repeat;
+ case ' ': flags |= SPACE; goto repeat;
+ case '#': flags |= SPECIAL; goto repeat;
+ case '0': flags |= ZEROPAD; goto repeat;
+ }
+
+ /* get field width */
+ field_width = -1;
+ if (is_digit(*fmt))
+ field_width = skip_atoi(&fmt);
+ else if (*fmt == '*') {
+ ++fmt;
+ /* it's the next argument */
+ field_width = va_arg(args, int);
+ if (field_width < 0) {
+ field_width = -field_width;
+ flags |= LEFT;
+ }
+ }
+
+ /* get the precision */
+ precision = -1;
+ if (*fmt == '.') {
+ ++fmt;
+ if (is_digit(*fmt))
+ precision = skip_atoi(&fmt);
+ else if (*fmt == '*') {
+ ++fmt;
+ /* it's the next argument */
+ precision = va_arg(args, int);
+ }
+ if (precision < 0)
+ precision = 0;
+ }
+
+ /* get the conversion qualifier */
+ qualifier = -1;
+ if (*fmt == 'h' || *fmt == 'l' || *fmt == 'q') {
+ qualifier = *fmt;
+ ++fmt;
+ }
+
+ /* default base */
+ base = 10;
+
+ switch (*fmt) {
+ case 'c':
+ if (!(flags & LEFT))
+ while (--field_width > 0)
+ *str++ = ' ';
+ *str++ = (unsigned char) va_arg(args, int);
+ while (--field_width > 0)
+ *str++ = ' ';
+ continue;
+
+ case 's':
+ s = va_arg(args, char *);
+ if (!s)
+ s = "<NULL>";
+
+ len = strnlen(s, precision);
+
+ if (!(flags & LEFT))
+ while (len < field_width--)
+ *str++ = ' ';
+ for (i = 0; i < len; ++i)
+ *str++ = *s++;
+ while (len < field_width--)
+ *str++ = ' ';
+ continue;
+
+ case 'p':
+ if (field_width == -1) {
+ field_width = 2*sizeof(void *);
+ flags |= ZEROPAD;
+ }
+ str = number(str,
+ (unsigned long) va_arg(args, void *), 16,
+ field_width, precision, flags);
+ continue;
+
+
+ case 'n':
+ if (qualifier == 'l') {
+ long * ip = va_arg(args, long *);
+ *ip = (str - buf);
+ } else {
+ int * ip = va_arg(args, int *);
+ *ip = (str - buf);
+ }
+ continue;
+
+ case '%':
+ *str++ = '%';
+ continue;
+
+ /* integer number formats - set up the flags and "break" */
+ case 'o':
+ base = 8;
+ break;
+
+ case 'X':
+ flags |= LARGE;
+ case 'x':
+ base = 16;
+ break;
+
+ case 'd':
+ case 'i':
+ flags |= SIGN;
+ case 'u':
+ break;
+
+ default:
+ *str++ = '%';
+ if (*fmt)
+ *str++ = *fmt;
+ else
+ --fmt;
+ continue;
+ }
+#ifdef CFG_64BIT_VSPRINTF
+ if (qualifier == 'q') /* "quad" for 64 bit variables */
+ num = va_arg(args, unsigned long long);
+ else
+#endif
+ if (qualifier == 'l')
+ num = va_arg(args, unsigned long);
+ else if (qualifier == 'h') {
+ num = (unsigned short) va_arg(args, int);
+ if (flags & SIGN)
+ num = (short) num;
+ } else if (flags & SIGN)
+ num = va_arg(args, int);
+ else
+ num = va_arg(args, unsigned int);
+ str = number(str, num, base, field_width, precision, flags);
+ }
+ *str = '\0';
+ return str-buf;
+}
+
+int sprintf(char * buf, const char *fmt, ...)
+{
+ va_list args;
+ int i;
+
+ va_start(args, fmt);
+ i=vsprintf(buf,fmt,args);
+ va_end(args);
+ return i;
+}
+
+void panic(const char *fmt, ...)
+{
+ va_list args;
+ va_start(args, fmt);
+ vprintf(fmt, args);
+ putc('\n');
+ va_end(args);
+#if defined (CONFIG_PANIC_HANG)
+ hang();
+#else
+ udelay (100000); /* allow messages to go out */
+ do_reset (NULL, 0, 0, NULL);
+#endif
+}
--- /dev/null
+/*
+ LzmaDecode.c
+ LZMA Decoder (optimized for Speed version)
+
+ LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
+ http://www.7-zip.org/
+
+ LZMA SDK is licensed under two licenses:
+ 1) GNU Lesser General Public License (GNU LGPL)
+ 2) Common Public License (CPL)
+ It means that you can select one of these two licenses and
+ follow rules of that license.
+
+ SPECIAL EXCEPTION:
+ Igor Pavlov, as the author of this Code, expressly permits you to
+ statically or dynamically link your Code (or bind by name) to the
+ interfaces of this file without subjecting your linked Code to the
+ terms of the CPL or GNU LGPL. Any modifications or additions
+ to this file, however, are subject to the LGPL or CPL terms.
+*/
+
+#ifdef CONFIG_LZMA
+
+#include "LzmaDecode.h"
+
+#define kNumTopBits 24
+#define kTopValue ((UInt32)1 << kNumTopBits)
+
+#define kNumBitModelTotalBits 11
+#define kBitModelTotal (1 << kNumBitModelTotalBits)
+#define kNumMoveBits 5
+
+#define RC_READ_BYTE (*Buffer++)
+
+#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \
+ { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}
+
+#ifdef _LZMA_IN_CB
+
+#define RC_TEST { if (Buffer == BufferLim) \
+ { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) { printf("ERROR, %s, %d\n", __FILE__, __LINE__); return result; } \
+ BufferLim = Buffer + size; if (size == 0) { printf("ERROR, %s, %d\n", __FILE__, __LINE__); return LZMA_RESULT_DATA_ERROR; } }}
+
+#define RC_INIT Buffer = BufferLim = 0; RC_INIT2
+
+#else
+
+#define RC_TEST { if (Buffer == BufferLim) { printf("ERROR, %s, %d\n", __FILE__, __LINE__); return LZMA_RESULT_DATA_ERROR; } }
+
+#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2
+
+#endif
+
+#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }
+
+#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)
+#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;
+#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;
+
+#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \
+ { UpdateBit0(p); mi <<= 1; A0; } else \
+ { UpdateBit1(p); mi = (mi + mi) + 1; A1; }
+
+#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)
+
+#define RangeDecoderBitTreeDecode(probs, numLevels, res) \
+ { int i = numLevels; res = 1; \
+ do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \
+ res -= (1 << numLevels); }
+
+
+#define kNumPosBitsMax 4
+#define kNumPosStatesMax (1 << kNumPosBitsMax)
+
+#define kLenNumLowBits 3
+#define kLenNumLowSymbols (1 << kLenNumLowBits)
+#define kLenNumMidBits 3
+#define kLenNumMidSymbols (1 << kLenNumMidBits)
+#define kLenNumHighBits 8
+#define kLenNumHighSymbols (1 << kLenNumHighBits)
+
+#define LenChoice 0
+#define LenChoice2 (LenChoice + 1)
+#define LenLow (LenChoice2 + 1)
+#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))
+#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))
+#define kNumLenProbs (LenHigh + kLenNumHighSymbols)
+
+
+#define kNumStates 12
+#define kNumLitStates 7
+
+#define kStartPosModelIndex 4
+#define kEndPosModelIndex 14
+#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))
+
+#define kNumPosSlotBits 6
+#define kNumLenToPosStates 4
+
+#define kNumAlignBits 4
+#define kAlignTableSize (1 << kNumAlignBits)
+
+#define kMatchMinLen 2
+
+#define IsMatch 0
+#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))
+#define IsRepG0 (IsRep + kNumStates)
+#define IsRepG1 (IsRepG0 + kNumStates)
+#define IsRepG2 (IsRepG1 + kNumStates)
+#define IsRep0Long (IsRepG2 + kNumStates)
+#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))
+#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))
+#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)
+#define LenCoder (Align + kAlignTableSize)
+#define RepLenCoder (LenCoder + kNumLenProbs)
+#define Literal (RepLenCoder + kNumLenProbs)
+
+#if Literal != LZMA_BASE_SIZE
+StopCompilingDueBUG
+#endif
+
+int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)
+{
+ unsigned char prop0;
+ if (size < LZMA_PROPERTIES_SIZE)
+ {
+ printf("ERROR: %s, %d\n", __FILE__, __LINE__);
+ return LZMA_RESULT_DATA_ERROR;
+ }
+ prop0 = propsData[0];
+ if (prop0 >= (9 * 5 * 5))
+ {
+ printf("ERROR: %s, %d\n", __FILE__, __LINE__);
+ return LZMA_RESULT_DATA_ERROR;
+ }
+ {
+ for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));
+ for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);
+ propsRes->lc = prop0;
+ /*
+ unsigned char remainder = (unsigned char)(prop0 / 9);
+ propsRes->lc = prop0 % 9;
+ propsRes->pb = remainder / 5;
+ propsRes->lp = remainder % 5;
+ */
+ }
+
+ #ifdef _LZMA_OUT_READ
+ {
+ int i;
+ propsRes->DictionarySize = 0;
+ for (i = 0; i < 4; i++)
+ propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8);
+ if (propsRes->DictionarySize == 0)
+ propsRes->DictionarySize = 1;
+ }
+ #endif
+ return LZMA_RESULT_OK;
+}
+
+#define kLzmaStreamWasFinishedId (-1)
+
+int LzmaDecode(CLzmaDecoderState *vs,
+ #ifdef _LZMA_IN_CB
+ ILzmaInCallback *InCallback,
+ #else
+ const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
+ #endif
+ unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)
+{
+ CProb *p = vs->Probs;
+ SizeT nowPos = 0;
+ Byte previousByte = 0;
+ UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;
+ UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;
+ int lc = vs->Properties.lc;
+
+ #ifdef _LZMA_OUT_READ
+
+ UInt32 Range = vs->Range;
+ UInt32 Code = vs->Code;
+ #ifdef _LZMA_IN_CB
+ const Byte *Buffer = vs->Buffer;
+ const Byte *BufferLim = vs->BufferLim;
+ #else
+ const Byte *Buffer = inStream;
+ const Byte *BufferLim = inStream + inSize;
+ #endif
+ int state = vs->State;
+ UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];
+ int len = vs->RemainLen;
+ UInt32 globalPos = vs->GlobalPos;
+ UInt32 distanceLimit = vs->DistanceLimit;
+
+ Byte *dictionary = vs->Dictionary;
+ UInt32 dictionarySize = vs->Properties.DictionarySize;
+ UInt32 dictionaryPos = vs->DictionaryPos;
+
+ Byte tempDictionary[4];
+
+ #ifndef _LZMA_IN_CB
+ *inSizeProcessed = 0;
+ #endif
+ *outSizeProcessed = 0;
+ if (len == kLzmaStreamWasFinishedId)
+ return LZMA_RESULT_OK;
+
+ if (dictionarySize == 0)
+ {
+ dictionary = tempDictionary;
+ dictionarySize = 1;
+ tempDictionary[0] = vs->TempDictionary[0];
+ }
+
+ if (len == kLzmaNeedInitId)
+ {
+ {
+ UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
+ UInt32 i;
+ for (i = 0; i < numProbs; i++)
+ p[i] = kBitModelTotal >> 1;
+ rep0 = rep1 = rep2 = rep3 = 1;
+ state = 0;
+ globalPos = 0;
+ distanceLimit = 0;
+ dictionaryPos = 0;
+ dictionary[dictionarySize - 1] = 0;
+ #ifdef _LZMA_IN_CB
+ RC_INIT;
+ #else
+ RC_INIT(inStream, inSize);
+ #endif
+ }
+ len = 0;
+ }
+ while(len != 0 && nowPos < outSize)
+ {
+ UInt32 pos = dictionaryPos - rep0;
+ if (pos >= dictionarySize)
+ pos += dictionarySize;
+ outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];
+ if (++dictionaryPos == dictionarySize)
+ dictionaryPos = 0;
+ len--;
+ }
+ if (dictionaryPos == 0)
+ previousByte = dictionary[dictionarySize - 1];
+ else
+ previousByte = dictionary[dictionaryPos - 1];
+
+ #else /* if !_LZMA_OUT_READ */
+
+ int state = 0;
+ UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;
+ int len = 0;
+ const Byte *Buffer;
+ const Byte *BufferLim;
+ UInt32 Range;
+ UInt32 Code;
+
+ #ifndef _LZMA_IN_CB
+ *inSizeProcessed = 0;
+ #endif
+ *outSizeProcessed = 0;
+
+ {
+ UInt32 i;
+ UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
+ for (i = 0; i < numProbs; i++)
+ p[i] = kBitModelTotal >> 1;
+ }
+
+ #ifdef _LZMA_IN_CB
+ RC_INIT;
+ #else
+ RC_INIT(inStream, inSize);
+ #endif
+
+ #endif /* _LZMA_OUT_READ */
+
+ while(nowPos < outSize)
+ {
+ CProb *prob;
+ UInt32 bound;
+ int posState = (int)(
+ (nowPos
+ #ifdef _LZMA_OUT_READ
+ + globalPos
+ #endif
+ )
+ & posStateMask);
+
+ prob = p + IsMatch + (state << kNumPosBitsMax) + posState;
+ IfBit0(prob)
+ {
+ int symbol = 1;
+ UpdateBit0(prob)
+ prob = p + Literal + (LZMA_LIT_SIZE *
+ (((
+ (nowPos
+ #ifdef _LZMA_OUT_READ
+ + globalPos
+ #endif
+ )
+ & literalPosMask) << lc) + (previousByte >> (8 - lc))));
+
+ if (state >= kNumLitStates)
+ {
+ int matchByte;
+ #ifdef _LZMA_OUT_READ
+ UInt32 pos = dictionaryPos - rep0;
+ if (pos >= dictionarySize)
+ pos += dictionarySize;
+ matchByte = dictionary[pos];
+ #else
+ matchByte = outStream[nowPos - rep0];
+ #endif
+ do
+ {
+ int bit;
+ CProb *probLit;
+ matchByte <<= 1;
+ bit = (matchByte & 0x100);
+ probLit = prob + 0x100 + bit + symbol;
+ RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)
+ }
+ while (symbol < 0x100);
+ }
+ while (symbol < 0x100)
+ {
+ CProb *probLit = prob + symbol;
+ RC_GET_BIT(probLit, symbol)
+ }
+ previousByte = (Byte)symbol;
+
+ outStream[nowPos++] = previousByte;
+ #ifdef _LZMA_OUT_READ
+ if (distanceLimit < dictionarySize)
+ distanceLimit++;
+
+ dictionary[dictionaryPos] = previousByte;
+ if (++dictionaryPos == dictionarySize)
+ dictionaryPos = 0;
+ #endif
+ if (state < 4) state = 0;
+ else if (state < 10) state -= 3;
+ else state -= 6;
+ }
+ else
+ {
+ UpdateBit1(prob);
+ prob = p + IsRep + state;
+ IfBit0(prob)
+ {
+ UpdateBit0(prob);
+ rep3 = rep2;
+ rep2 = rep1;
+ rep1 = rep0;
+ state = state < kNumLitStates ? 0 : 3;
+ prob = p + LenCoder;
+ }
+ else
+ {
+ UpdateBit1(prob);
+ prob = p + IsRepG0 + state;
+ IfBit0(prob)
+ {
+ UpdateBit0(prob);
+ prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;
+ IfBit0(prob)
+ {
+ #ifdef _LZMA_OUT_READ
+ UInt32 pos;
+ #endif
+ UpdateBit0(prob);
+
+ #ifdef _LZMA_OUT_READ
+ if (distanceLimit == 0)
+ #else
+ if (nowPos == 0)
+ #endif
+ {
+ printf("ERROR: %s, %d\n", __FILE__, __LINE__);
+ return LZMA_RESULT_DATA_ERROR;
+ }
+
+ state = state < kNumLitStates ? 9 : 11;
+ #ifdef _LZMA_OUT_READ
+ pos = dictionaryPos - rep0;
+ if (pos >= dictionarySize)
+ pos += dictionarySize;
+ previousByte = dictionary[pos];
+ dictionary[dictionaryPos] = previousByte;
+ if (++dictionaryPos == dictionarySize)
+ dictionaryPos = 0;
+ #else
+ previousByte = outStream[nowPos - rep0];
+ #endif
+ outStream[nowPos++] = previousByte;
+ #ifdef _LZMA_OUT_READ
+ if (distanceLimit < dictionarySize)
+ distanceLimit++;
+ #endif
+
+ continue;
+ }
+ else
+ {
+ UpdateBit1(prob);
+ }
+ }
+ else
+ {
+ UInt32 distance;
+ UpdateBit1(prob);
+ prob = p + IsRepG1 + state;
+ IfBit0(prob)
+ {
+ UpdateBit0(prob);
+ distance = rep1;
+ }
+ else
+ {
+ UpdateBit1(prob);
+ prob = p + IsRepG2 + state;
+ IfBit0(prob)
+ {
+ UpdateBit0(prob);
+ distance = rep2;
+ }
+ else
+ {
+ UpdateBit1(prob);
+ distance = rep3;
+ rep3 = rep2;
+ }
+ rep2 = rep1;
+ }
+ rep1 = rep0;
+ rep0 = distance;
+ }
+ state = state < kNumLitStates ? 8 : 11;
+ prob = p + RepLenCoder;
+ }
+ {
+ int numBits, offset;
+ CProb *probLen = prob + LenChoice;
+ IfBit0(probLen)
+ {
+ UpdateBit0(probLen);
+ probLen = prob + LenLow + (posState << kLenNumLowBits);
+ offset = 0;
+ numBits = kLenNumLowBits;
+ }
+ else
+ {
+ UpdateBit1(probLen);
+ probLen = prob + LenChoice2;
+ IfBit0(probLen)
+ {
+ UpdateBit0(probLen);
+ probLen = prob + LenMid + (posState << kLenNumMidBits);
+ offset = kLenNumLowSymbols;
+ numBits = kLenNumMidBits;
+ }
+ else
+ {
+ UpdateBit1(probLen);
+ probLen = prob + LenHigh;
+ offset = kLenNumLowSymbols + kLenNumMidSymbols;
+ numBits = kLenNumHighBits;
+ }
+ }
+ RangeDecoderBitTreeDecode(probLen, numBits, len);
+ len += offset;
+ }
+
+ if (state < 4)
+ {
+ int posSlot;
+ state += kNumLitStates;
+ prob = p + PosSlot +
+ ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) <<
+ kNumPosSlotBits);
+ RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);
+ if (posSlot >= kStartPosModelIndex)
+ {
+ int numDirectBits = ((posSlot >> 1) - 1);
+ rep0 = (2 | ((UInt32)posSlot & 1));
+ if (posSlot < kEndPosModelIndex)
+ {
+ rep0 <<= numDirectBits;
+ prob = p + SpecPos + rep0 - posSlot - 1;
+ }
+ else
+ {
+ numDirectBits -= kNumAlignBits;
+ do
+ {
+ RC_NORMALIZE
+ Range >>= 1;
+ rep0 <<= 1;
+ if (Code >= Range)
+ {
+ Code -= Range;
+ rep0 |= 1;
+ }
+ }
+ while (--numDirectBits != 0);
+ prob = p + Align;
+ rep0 <<= kNumAlignBits;
+ numDirectBits = kNumAlignBits;
+ }
+ {
+ int i = 1;
+ int mi = 1;
+ do
+ {
+ CProb *prob3 = prob + mi;
+ RC_GET_BIT2(prob3, mi, ; , rep0 |= i);
+ i <<= 1;
+ }
+ while(--numDirectBits != 0);
+ }
+ }
+ else
+ rep0 = posSlot;
+ if (++rep0 == (UInt32)(0))
+ {
+ /* it's for stream version */
+ len = kLzmaStreamWasFinishedId;
+ break;
+ }
+ }
+
+ len += kMatchMinLen;
+ #ifdef _LZMA_OUT_READ
+ if (rep0 > distanceLimit)
+ #else
+ if (rep0 > nowPos)
+ #endif
+ {
+ printf("ERROR: %s, %d\n", __FILE__, __LINE__);
+ return LZMA_RESULT_DATA_ERROR;
+ }
+
+ #ifdef _LZMA_OUT_READ
+ if (dictionarySize - distanceLimit > (UInt32)len)
+ distanceLimit += len;
+ else
+ distanceLimit = dictionarySize;
+ #endif
+
+ do
+ {
+ #ifdef _LZMA_OUT_READ
+ UInt32 pos = dictionaryPos - rep0;
+ if (pos >= dictionarySize)
+ pos += dictionarySize;
+ previousByte = dictionary[pos];
+ dictionary[dictionaryPos] = previousByte;
+ if (++dictionaryPos == dictionarySize)
+ dictionaryPos = 0;
+ #else
+ previousByte = outStream[nowPos - rep0];
+ #endif
+ len--;
+ outStream[nowPos++] = previousByte;
+ }
+ while(len != 0 && nowPos < outSize);
+ }
+ }
+ RC_NORMALIZE;
+
+ #ifdef _LZMA_OUT_READ
+ vs->Range = Range;
+ vs->Code = Code;
+ vs->DictionaryPos = dictionaryPos;
+ vs->GlobalPos = globalPos + (UInt32)nowPos;
+ vs->DistanceLimit = distanceLimit;
+ vs->Reps[0] = rep0;
+ vs->Reps[1] = rep1;
+ vs->Reps[2] = rep2;
+ vs->Reps[3] = rep3;
+ vs->State = state;
+ vs->RemainLen = len;
+ vs->TempDictionary[0] = tempDictionary[0];
+ #endif
+
+ #ifdef _LZMA_IN_CB
+ vs->Buffer = Buffer;
+ vs->BufferLim = BufferLim;
+ #else
+ *inSizeProcessed = (SizeT)(Buffer - inStream);
+ #endif
+ *outSizeProcessed = nowPos;
+ return LZMA_RESULT_OK;
+}
+
+#endif /* CONFIG_LZMA */
--- /dev/null
+/*
+ LzmaDecode.h
+ LZMA Decoder interface
+
+ LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
+ http://www.7-zip.org/
+
+ LZMA SDK is licensed under two licenses:
+ 1) GNU Lesser General Public License (GNU LGPL)
+ 2) Common Public License (CPL)
+ It means that you can select one of these two licenses and
+ follow rules of that license.
+
+ SPECIAL EXCEPTION:
+ Igor Pavlov, as the author of this code, expressly permits you to
+ statically or dynamically link your code (or bind by name) to the
+ interfaces of this file without subjecting your linked code to the
+ terms of the CPL or GNU LGPL. Any modifications or additions
+ to this file, however, are subject to the LGPL or CPL terms.
+*/
+
+#ifndef __LZMADECODE_H
+#define __LZMADECODE_H
+
+#include "LzmaTypes.h"
+
+/* #define _LZMA_IN_CB */
+/* Use callback for input data */
+
+/* #define _LZMA_OUT_READ */
+/* Use read function for output data */
+
+/* #define _LZMA_PROB32 */
+/* It can increase speed on some 32-bit CPUs,
+ but memory usage will be doubled in that case */
+
+/* #define _LZMA_LOC_OPT */
+/* Enable local speed optimizations inside code */
+
+#ifdef _LZMA_PROB32
+#define CProb UInt32
+#else
+#define CProb UInt16
+#endif
+
+#define LZMA_RESULT_OK 0
+#define LZMA_RESULT_DATA_ERROR 1
+
+#ifdef _LZMA_IN_CB
+typedef struct _ILzmaInCallback
+{
+ int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize);
+} ILzmaInCallback;
+#endif
+
+#define LZMA_BASE_SIZE 1846
+#define LZMA_LIT_SIZE 768
+
+#define LZMA_PROPERTIES_SIZE 5
+
+typedef struct _CLzmaProperties
+{
+ int lc;
+ int lp;
+ int pb;
+ #ifdef _LZMA_OUT_READ
+ UInt32 DictionarySize;
+ #endif
+}CLzmaProperties;
+
+int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);
+
+#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))
+
+#define kLzmaNeedInitId (-2)
+
+typedef struct _CLzmaDecoderState
+{
+ CLzmaProperties Properties;
+ CProb *Probs;
+
+ #ifdef _LZMA_IN_CB
+ const unsigned char *Buffer;
+ const unsigned char *BufferLim;
+ #endif
+
+ #ifdef _LZMA_OUT_READ
+ unsigned char *Dictionary;
+ UInt32 Range;
+ UInt32 Code;
+ UInt32 DictionaryPos;
+ UInt32 GlobalPos;
+ UInt32 DistanceLimit;
+ UInt32 Reps[4];
+ int State;
+ int RemainLen;
+ unsigned char TempDictionary[4];
+ #endif
+} CLzmaDecoderState;
+
+#ifdef _LZMA_OUT_READ
+#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; }
+#endif
+
+int LzmaDecode(CLzmaDecoderState *vs,
+ #ifdef _LZMA_IN_CB
+ ILzmaInCallback *inCallback,
+ #else
+ const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
+ #endif
+ unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);
+
+#endif
--- /dev/null
+/*
+LzmaTypes.h
+
+Types for LZMA Decoder
+
+This file written and distributed to public domain by Igor Pavlov.
+This file is part of LZMA SDK 4.40 (2006-05-01)
+*/
+
+#ifndef __LZMATYPES_H
+#define __LZMATYPES_H
+
+#ifndef _7ZIP_BYTE_DEFINED
+#define _7ZIP_BYTE_DEFINED
+typedef unsigned char Byte;
+#endif
+
+#ifndef _7ZIP_UINT16_DEFINED
+#define _7ZIP_UINT16_DEFINED
+typedef unsigned short UInt16;
+#endif
+
+#ifndef _7ZIP_UINT32_DEFINED
+#define _7ZIP_UINT32_DEFINED
+#ifdef _LZMA_UINT32_IS_ULONG
+typedef unsigned long UInt32;
+#else
+typedef unsigned int UInt32;
+#endif
+#endif
+
+/* #define _LZMA_SYSTEM_SIZE_T */
+/* Use system's size_t. You can use it to enable 64-bit sizes supporting */
+
+#ifndef _7ZIP_SIZET_DEFINED
+#define _7ZIP_SIZET_DEFINED
+#ifdef _LZMA_SYSTEM_SIZE_T
+#include <stddef.h>
+typedef size_t SizeT;
+#else
+typedef UInt32 SizeT;
+#endif
+#endif
+
+#endif
--- /dev/null
+/******************************************************************************
+**
+** FILE NAME : LzmaWrapper.c
+** PROJECT : bootloader
+** MODULES : U-boot
+**
+** DATE : 2 Nov 2006
+** AUTHOR : Lin Mars
+** DESCRIPTION : LZMA decoder support for U-boot 1.1.5
+** COPYRIGHT : Copyright (c) 2006
+** Infineon Technologies AG
+** Am Campeon 1-12, 85579 Neubiberg, Germany
+**
+** This program is free software; you can redistribute it and/or modify
+** it under the terms of the GNU General Public License as published by
+** the Free Software Foundation; either version 2 of the License, or
+** (at your option) any later version.
+**
+** HISTORY
+** $Date $Author $Comment
+** 2 Nov 2006 Lin Mars init version which derived from LzmaTest.c from
+** LZMA v4.43 SDK
+*******************************************************************************/
+#define LZMA_NO_STDIO
+#ifndef LZMA_NO_STDIO
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#endif
+
+#include <config.h>
+#include <common.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <malloc.h>
+
+#ifdef CONFIG_LZMA
+
+#include "LzmaDecode.h"
+#include "LzmaWrapper.h"
+
+static const char *kCantReadMessage = "Can not read from source buffer";
+static const char *kCantAllocateMessage = "Not enough buffer for decompression";
+
+static size_t rpos=0, dpos=0;
+
+static int MyReadFileAndCheck(unsigned char *src, void *dest, size_t size)
+{
+ if (size == 0)
+ return 0;
+ memcpy(dest, src + rpos, size);
+ rpos += size;
+ return 1;
+}
+
+int lzma_inflate(unsigned char *source, int s_len, unsigned char *dest, int *d_len)
+{
+ /* We use two 32-bit integers to construct 64-bit integer for file size.
+ You can remove outSizeHigh, if you don't need >= 4GB supporting,
+ or you can use UInt64 outSize, if your compiler supports 64-bit integers*/
+ UInt32 outSize = 0;
+ UInt32 outSizeHigh = 0;
+ SizeT outSizeFull;
+ unsigned char *outStream;
+
+ int waitEOS = 1;
+ /* waitEOS = 1, if there is no uncompressed size in headers,
+ so decoder will wait EOS (End of Stream Marker) in compressed stream */
+
+ SizeT compressedSize;
+ unsigned char *inStream;
+
+ CLzmaDecoderState state; /* it's about 24-80 bytes structure, if int is 32-bit */
+ unsigned char properties[LZMA_PROPERTIES_SIZE];
+
+ int res;
+
+ if (sizeof(UInt32) < 4)
+ {
+ printf("LZMA decoder needs correct UInt32\n");
+ return LZMA_RESULT_DATA_ERROR;
+ }
+
+ {
+ long length=s_len;
+ if ((long)(SizeT)length != length)
+ {
+ printf("Too big compressed stream\n");
+ return LZMA_RESULT_DATA_ERROR;
+ }
+ compressedSize = (SizeT)(length - (LZMA_PROPERTIES_SIZE + 8));
+ }
+
+ /* Read LZMA properties for compressed stream */
+
+ if (!MyReadFileAndCheck(source, properties, sizeof(properties)))
+ {
+ printf("%s\n", kCantReadMessage);
+ return LZMA_RESULT_DATA_ERROR;
+ }
+
+ /* Read uncompressed size */
+ {
+ int i;
+ for (i = 0; i < 8; i++)
+ {
+ unsigned char b;
+ if (!MyReadFileAndCheck(source, &b, 1))
+ {
+ printf("%s\n", kCantReadMessage);
+ return LZMA_RESULT_DATA_ERROR;
+ }
+ if (b != 0xFF)
+ waitEOS = 0;
+ if (i < 4)
+ outSize += (UInt32)(b) << (i * 8);
+ else
+ outSizeHigh += (UInt32)(b) << ((i - 4) * 8);
+ }
+
+ if (waitEOS)
+ {
+ printf("Stream with EOS marker is not supported");
+ return LZMA_RESULT_DATA_ERROR;
+ }
+ outSizeFull = (SizeT)outSize;
+ if (sizeof(SizeT) >= 8)
+ outSizeFull |= (((SizeT)outSizeHigh << 16) << 16);
+ else if (outSizeHigh != 0 || (UInt32)(SizeT)outSize != outSize)
+ {
+ printf("Too big uncompressed stream");
+ return LZMA_RESULT_DATA_ERROR;
+ }
+ }
+
+ /* Decode LZMA properties and allocate memory */
+ if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK)
+ {
+ printf("Incorrect stream properties");
+ return LZMA_RESULT_DATA_ERROR;
+ }
+ state.Probs = (CProb *)malloc(LzmaGetNumProbs(&state.Properties) * sizeof(CProb));
+
+ if (outSizeFull == 0)
+ outStream = 0;
+ else
+ {
+ if (outSizeFull > d_len)
+ outStream = 0;
+ else
+ outStream = dest;
+ }
+
+ if (compressedSize == 0)
+ inStream = 0;
+ else
+ {
+ if ((compressedSize+rpos) > s_len )
+ inStream = 0;
+ else
+ inStream = source + rpos;
+ }
+
+ if (state.Probs == 0
+ || (outStream == 0 && outSizeFull != 0)
+ || (inStream == 0 && compressedSize != 0)
+ )
+ {
+ free(state.Probs);
+ printf("%s\n", kCantAllocateMessage);
+ return LZMA_RESULT_DATA_ERROR;
+ }
+
+ /* Decompress */
+ {
+ SizeT inProcessed;
+ SizeT outProcessed;
+ res = LzmaDecode(&state,
+ inStream, compressedSize, &inProcessed,
+ outStream, outSizeFull, &outProcessed);
+ if (res != 0)
+ {
+ printf("\nDecoding error = %d\n", res);
+ res = 1;
+ }
+ else
+ {
+ *d_len = outProcessed;
+ }
+ }
+
+ free(state.Probs);
+ return res;
+}
+
+#endif /* CONFIG_LZMA */
--- /dev/null
+
+#define IFX_ETH_INITIALIZE_EXTERN extern int danube_switch_initialize(bd_t *);
+#define IFX_ETH_INITIALIZE(bd_t) danube_switch_initialize(bd_t);
+
--- /dev/null
+/*
+ * Copied from Linux Monitor (LiMon) - Networking.
+ *
+ * Copyright 1994 - 2000 Neil Russell.
+ * (See License)
+ * Copyright 2000 Roland Borde
+ * Copyright 2000 Paolo Scaffardi
+ * Copyright 2000-2002 Wolfgang Denk, wd@denx.de
+ */
+
+/*
+ * General Desription:
+ *
+ * The user interface supports commands for BOOTP, RARP, and TFTP.
+ * Also, we support ARP internally. Depending on available data,
+ * these interact as follows:
+ *
+ * BOOTP:
+ *
+ * Prerequisites: - own ethernet address
+ * We want: - own IP address
+ * - TFTP server IP address
+ * - name of bootfile
+ * Next step: ARP
+ *
+ * RARP:
+ *
+ * Prerequisites: - own ethernet address
+ * We want: - own IP address
+ * - TFTP server IP address
+ * Next step: ARP
+ *
+ * ARP:
+ *
+ * Prerequisites: - own ethernet address
+ * - own IP address
+ * - TFTP server IP address
+ * We want: - TFTP server ethernet address
+ * Next step: TFTP
+ *
+ * DHCP:
+ *
+ * Prerequisites: - own ethernet address
+ * We want: - IP, Netmask, ServerIP, Gateway IP
+ * - bootfilename, lease time
+ * Next step: - TFTP
+ *
+ * TFTP:
+ *
+ * Prerequisites: - own ethernet address
+ * - own IP address
+ * - TFTP server IP address
+ * - TFTP server ethernet address
+ * - name of bootfile (if unknown, we use a default name
+ * derived from our own IP address)
+ * We want: - load the boot file
+ * Next step: none
+ *
+ * NFS:
+ *
+ * Prerequisites: - own ethernet address
+ * - own IP address
+ * - name of bootfile (if unknown, we use a default name
+ * derived from our own IP address)
+ * We want: - load the boot file
+ * Next step: none
+ *
+ * SNTP:
+ *
+ * Prerequisites: - own ethernet address
+ * - own IP address
+ * We want: - network time
+ * Next step: none
+ */
+
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <net.h>
+#include "bootp.h"
+#include "tftp.h"
+#include "rarp.h"
+#include "nfs.h"
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#include <miiphy.h>
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_SNTP)
+#include "sntp.h"
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ARP_TIMEOUT 5 /* Seconds before trying ARP again */
+#ifndef CONFIG_NET_RETRY_COUNT
+# define ARP_TIMEOUT_COUNT 5 /* # of timeouts before giving up */
+#else
+# define ARP_TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT)
+#endif
+
+#if 0
+#define ET_DEBUG
+#endif
+
+/** BOOTP EXTENTIONS **/
+
+IPaddr_t NetOurSubnetMask=0; /* Our subnet mask (0=unknown) */
+IPaddr_t NetOurGatewayIP=0; /* Our gateways IP address */
+IPaddr_t NetOurDNSIP=0; /* Our DNS IP address */
+#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2)
+IPaddr_t NetOurDNS2IP=0; /* Our 2nd DNS IP address */
+#endif
+char NetOurNISDomain[32]={0,}; /* Our NIS domain */
+char NetOurHostName[32]={0,}; /* Our hostname */
+char NetOurRootPath[64]={0,}; /* Our bootpath */
+ushort NetBootFileSize=0; /* Our bootfile size in blocks */
+
+/** END OF BOOTP EXTENTIONS **/
+
+ulong NetBootFileXferSize; /* The actual transferred size of the bootfile (in bytes) */
+uchar NetOurEther[6]; /* Our ethernet address */
+uchar NetServerEther[6] = /* Boot server enet address */
+ { 0, 0, 0, 0, 0, 0 };
+IPaddr_t NetOurIP; /* Our IP addr (0 = unknown) */
+IPaddr_t NetServerIP; /* Our IP addr (0 = unknown) */
+volatile uchar *NetRxPkt; /* Current receive packet */
+int NetRxPktLen; /* Current rx packet length */
+unsigned NetIPID; /* IP packet ID */
+uchar NetBcastAddr[6] = /* Ethernet bcast address */
+ { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+uchar NetEtherNullAddr[6] =
+ { 0, 0, 0, 0, 0, 0 };
+#if (CONFIG_COMMANDS & CFG_CMD_CDP)
+uchar NetCDPAddr[6] = /* Ethernet bcast address */
+ { 0x01, 0x00, 0x0c, 0xcc, 0xcc, 0xcc };
+#endif
+int NetState; /* Network loop state */
+#ifdef CONFIG_NET_MULTI
+int NetRestartWrap = 0; /* Tried all network devices */
+static int NetRestarted = 0; /* Network loop restarted */
+static int NetDevExists = 0; /* At least one device configured */
+#endif
+
+/* XXX in both little & big endian machines 0xFFFF == ntohs(-1) */
+ushort NetOurVLAN = 0xFFFF; /* default is without VLAN */
+ushort NetOurNativeVLAN = 0xFFFF; /* ditto */
+
+char BootFile[128]; /* Boot File name */
+
+#if (CONFIG_COMMANDS & CFG_CMD_PING)
+IPaddr_t NetPingIP; /* the ip address to ping */
+
+static void PingStart(void);
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_CDP)
+static void CDPStart(void);
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_SNTP)
+IPaddr_t NetNtpServerIP; /* NTP server IP address */
+int NetTimeOffset=0; /* offset time from UTC */
+#endif
+
+#ifdef CONFIG_NETCONSOLE
+void NcStart(void);
+int nc_input_packet(uchar *pkt, unsigned dest, unsigned src, unsigned len);
+#endif
+
+volatile uchar PktBuf[(PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN];
+
+volatile uchar *NetRxPackets[PKTBUFSRX]; /* Receive packets */
+
+static rxhand_f *packetHandler; /* Current RX packet handler */
+static thand_f *timeHandler; /* Current timeout handler */
+static ulong timeStart; /* Time base value */
+static ulong timeDelta; /* Current timeout value */
+volatile uchar *NetTxPacket = 0; /* THE transmit packet */
+
+static int net_check_prereq (proto_t protocol);
+
+/**********************************************************************/
+
+IPaddr_t NetArpWaitPacketIP;
+IPaddr_t NetArpWaitReplyIP;
+uchar *NetArpWaitPacketMAC; /* MAC address of waiting packet's destination */
+uchar *NetArpWaitTxPacket; /* THE transmit packet */
+int NetArpWaitTxPacketSize;
+uchar NetArpWaitPacketBuf[PKTSIZE_ALIGN + PKTALIGN];
+ulong NetArpWaitTimerStart;
+int NetArpWaitTry;
+
+void ArpRequest (void)
+{
+ int i;
+ volatile uchar *pkt;
+ ARP_t *arp;
+
+#ifdef ET_DEBUG
+ printf ("ARP broadcast %d\n", NetArpWaitTry);
+#endif
+ pkt = NetTxPacket;
+
+ pkt += NetSetEther (pkt, NetBcastAddr, PROT_ARP);
+
+ arp = (ARP_t *) pkt;
+
+ arp->ar_hrd = htons (ARP_ETHER);
+ arp->ar_pro = htons (PROT_IP);
+ arp->ar_hln = 6;
+ arp->ar_pln = 4;
+ arp->ar_op = htons (ARPOP_REQUEST);
+
+ memcpy (&arp->ar_data[0], NetOurEther, 6); /* source ET addr */
+ NetWriteIP ((uchar *) & arp->ar_data[6], NetOurIP); /* source IP addr */
+ for (i = 10; i < 16; ++i) {
+ arp->ar_data[i] = 0; /* dest ET addr = 0 */
+ }
+
+ if ((NetArpWaitPacketIP & NetOurSubnetMask) !=
+ (NetOurIP & NetOurSubnetMask)) {
+ if (NetOurGatewayIP == 0) {
+ puts ("## Warning: gatewayip needed but not set\n");
+ NetArpWaitReplyIP = NetArpWaitPacketIP;
+ } else {
+ NetArpWaitReplyIP = NetOurGatewayIP;
+ }
+ } else {
+ NetArpWaitReplyIP = NetArpWaitPacketIP;
+ }
+
+ NetWriteIP ((uchar *) & arp->ar_data[16], NetArpWaitReplyIP);
+ (void) eth_send (NetTxPacket, (pkt - NetTxPacket) + ARP_HDR_SIZE);
+}
+
+void ArpTimeoutCheck(void)
+{
+ ulong t;
+
+ if (!NetArpWaitPacketIP)
+ return;
+
+ t = get_timer(0);
+
+ /* check for arp timeout */
+ if ((t - NetArpWaitTimerStart) > ARP_TIMEOUT * CFG_HZ) {
+ NetArpWaitTry++;
+
+ if (NetArpWaitTry >= ARP_TIMEOUT_COUNT) {
+ puts ("\nARP Retry count exceeded; starting again\n");
+ NetArpWaitTry = 0;
+ NetStartAgain();
+ } else {
+ NetArpWaitTimerStart = t;
+ ArpRequest();
+ }
+ }
+}
+
+/**********************************************************************/
+/*
+ * Main network processing loop.
+ */
+
+int
+NetLoop(proto_t protocol)
+{
+ bd_t *bd = gd->bd;
+
+#ifdef CONFIG_NET_MULTI
+ NetRestarted = 0;
+ NetDevExists = 0;
+#endif
+
+ /* XXX problem with bss workaround */
+ NetArpWaitPacketMAC = NULL;
+ NetArpWaitTxPacket = NULL;
+ NetArpWaitPacketIP = 0;
+ NetArpWaitReplyIP = 0;
+ NetArpWaitTxPacket = NULL;
+ NetTxPacket = NULL;
+
+ if (!NetTxPacket) {
+ int i;
+ /*
+ * Setup packet buffers, aligned correctly.
+ */
+ NetTxPacket = &PktBuf[0] + (PKTALIGN - 1);
+ NetTxPacket -= (ulong)NetTxPacket % PKTALIGN;
+ for (i = 0; i < PKTBUFSRX; i++) {
+ NetRxPackets[i] = NetTxPacket + (i+1)*PKTSIZE_ALIGN;
+ }
+ }
+
+ if (!NetArpWaitTxPacket) {
+ NetArpWaitTxPacket = &NetArpWaitPacketBuf[0] + (PKTALIGN - 1);
+ NetArpWaitTxPacket -= (ulong)NetArpWaitTxPacket % PKTALIGN;
+ NetArpWaitTxPacketSize = 0;
+ }
+
+ eth_halt();
+#ifdef CONFIG_NET_MULTI
+ eth_set_current();
+#endif
+ if (eth_init(bd) < 0) {
+ eth_halt();
+ return(-1);
+ }
+
+restart:
+#ifdef CONFIG_NET_MULTI
+ memcpy (NetOurEther, eth_get_dev()->enetaddr, 6);
+#else
+ memcpy (NetOurEther, bd->bi_enetaddr, 6);
+#endif
+
+ NetState = NETLOOP_CONTINUE;
+
+ /*
+ * Start the ball rolling with the given start function. From
+ * here on, this code is a state machine driven by received
+ * packets and timer events.
+ */
+
+ switch (protocol) {
+#if (CONFIG_COMMANDS & CFG_CMD_NFS)
+ case NFS:
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_PING)
+ case PING:
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_SNTP)
+ case SNTP:
+#endif
+ case NETCONS:
+ case TFTP:
+ NetCopyIP(&NetOurIP, &bd->bi_ip_addr);
+ NetOurGatewayIP = getenv_IPaddr ("gatewayip");
+ NetOurSubnetMask= getenv_IPaddr ("netmask");
+ NetOurVLAN = getenv_VLAN("vlan");
+ NetOurNativeVLAN = getenv_VLAN("nvlan");
+
+ switch (protocol) {
+#if (CONFIG_COMMANDS & CFG_CMD_NFS)
+ case NFS:
+#endif
+ case NETCONS:
+ case TFTP:
+ NetServerIP = getenv_IPaddr ("serverip");
+ break;
+#if (CONFIG_COMMANDS & CFG_CMD_PING)
+ case PING:
+ /* nothing */
+ break;
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_SNTP)
+ case SNTP:
+ /* nothing */
+ break;
+#endif
+ default:
+ break;
+ }
+
+ break;
+ case BOOTP:
+ case RARP:
+ /*
+ * initialize our IP addr to 0 in order to accept ANY
+ * IP addr assigned to us by the BOOTP / RARP server
+ */
+ NetOurIP = 0;
+ NetServerIP = getenv_IPaddr ("serverip");
+ NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */
+ NetOurNativeVLAN = getenv_VLAN("nvlan");
+ case CDP:
+ NetOurVLAN = getenv_VLAN("vlan"); /* VLANs must be read */
+ NetOurNativeVLAN = getenv_VLAN("nvlan");
+ break;
+ default:
+ break;
+ }
+
+ switch (net_check_prereq (protocol)) {
+ case 1:
+ /* network not configured */
+ eth_halt();
+ return (-1);
+
+#ifdef CONFIG_NET_MULTI
+ case 2:
+ /* network device not configured */
+ break;
+#endif /* CONFIG_NET_MULTI */
+
+ case 0:
+#ifdef CONFIG_NET_MULTI
+ NetDevExists = 1;
+#endif
+ switch (protocol) {
+ case TFTP:
+ /* always use ARP to get server ethernet address */
+ TftpStart();
+ break;
+
+#if (CONFIG_COMMANDS & CFG_CMD_DHCP)
+ case DHCP:
+ /* Start with a clean slate... */
+ BootpTry = 0;
+ NetOurIP = 0;
+ NetServerIP = getenv_IPaddr ("serverip");
+ DhcpRequest(); /* Basically same as BOOTP */
+ break;
+#endif /* CFG_CMD_DHCP */
+
+ case BOOTP:
+ BootpTry = 0;
+ BootpRequest ();
+ break;
+
+ case RARP:
+ RarpTry = 0;
+ RarpRequest ();
+ break;
+#if (CONFIG_COMMANDS & CFG_CMD_PING)
+ case PING:
+ PingStart();
+ break;
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_NFS)
+ case NFS:
+ NfsStart();
+ break;
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_CDP)
+ case CDP:
+ CDPStart();
+ break;
+#endif
+#ifdef CONFIG_NETCONSOLE
+ case NETCONS:
+ NcStart();
+ break;
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_SNTP)
+ case SNTP:
+ SntpStart();
+ break;
+#endif
+ default:
+ break;
+ }
+
+ NetBootFileXferSize = 0;
+ break;
+ }
+
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+#if defined(CFG_FAULT_ECHO_LINK_DOWN) && defined(CONFIG_STATUS_LED) && defined(STATUS_LED_RED)
+ /*
+ * Echo the inverted link state to the fault LED.
+ */
+ if(miiphy_link(eth_get_dev()->name, CFG_FAULT_MII_ADDR)) {
+ status_led_set (STATUS_LED_RED, STATUS_LED_OFF);
+ } else {
+ status_led_set (STATUS_LED_RED, STATUS_LED_ON);
+ }
+#endif /* CFG_FAULT_ECHO_LINK_DOWN, ... */
+#endif /* CONFIG_MII, ... */
+
+ /*
+ * Main packet reception loop. Loop receiving packets until
+ * someone sets `NetState' to a state that terminates.
+ */
+ for (;;) {
+ WATCHDOG_RESET();
+#ifdef CONFIG_SHOW_ACTIVITY
+ {
+ extern void show_activity(int arg);
+ show_activity(1);
+ }
+#endif
+ /*
+ * Check the ethernet for a new packet. The ethernet
+ * receive routine will process it.
+ */
+ eth_rx();
+
+ /*
+ * Abort if ctrl-c was pressed.
+ */
+ if (ctrlc()) {
+ eth_halt();
+ puts ("\nAbort\n");
+ return (-1);
+ }
+
+ ArpTimeoutCheck();
+
+ /*
+ * Check for a timeout, and run the timeout handler
+ * if we have one.
+ */
+ if (timeHandler && ((get_timer(0) - timeStart) > timeDelta)) {
+ thand_f *x;
+
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+# if defined(CFG_FAULT_ECHO_LINK_DOWN) && \
+ defined(CONFIG_STATUS_LED) && \
+ defined(STATUS_LED_RED)
+ /*
+ * Echo the inverted link state to the fault LED.
+ */
+ if(miiphy_link(eth_get_dev()->name, CFG_FAULT_MII_ADDR)) {
+ status_led_set (STATUS_LED_RED, STATUS_LED_OFF);
+ } else {
+ status_led_set (STATUS_LED_RED, STATUS_LED_ON);
+ }
+# endif /* CFG_FAULT_ECHO_LINK_DOWN, ... */
+#endif /* CONFIG_MII, ... */
+ x = timeHandler;
+ timeHandler = (thand_f *)0;
+ (*x)();
+ }
+
+
+ switch (NetState) {
+
+ case NETLOOP_RESTART:
+#ifdef CONFIG_NET_MULTI
+ NetRestarted = 1;
+#endif
+ goto restart;
+
+ case NETLOOP_SUCCESS:
+ if (NetBootFileXferSize > 0) {
+ char buf[10];
+ printf("Bytes transferred = %ld (%lx hex)\n",
+ NetBootFileXferSize,
+ NetBootFileXferSize);
+ sprintf(buf, "%lx", NetBootFileXferSize);
+ setenv("filesize", buf);
+
+ sprintf(buf, "%lX", (unsigned long)load_addr);
+ setenv("fileaddr", buf);
+ }
+ eth_halt();
+ return NetBootFileXferSize;
+
+ case NETLOOP_FAIL:
+ return (-1);
+ }
+ }
+}
+
+/**********************************************************************/
+
+static void
+startAgainTimeout(void)
+{
+ NetState = NETLOOP_RESTART;
+}
+
+static void
+startAgainHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len)
+{
+ /* Totally ignore the packet */
+}
+
+void NetStartAgain (void)
+{
+ char *nretry;
+ int noretry = 0, once = 0;
+
+ if ((nretry = getenv ("netretry")) != NULL) {
+ noretry = (strcmp (nretry, "no") == 0);
+ once = (strcmp (nretry, "once") == 0);
+ }
+ if (noretry) {
+ eth_halt ();
+ NetState = NETLOOP_FAIL;
+ return;
+ }
+#ifndef CONFIG_NET_MULTI
+ NetSetTimeout (10 * CFG_HZ, startAgainTimeout);
+ NetSetHandler (startAgainHandler);
+#else /* !CONFIG_NET_MULTI*/
+ eth_halt ();
+ eth_try_another (!NetRestarted);
+ eth_init (gd->bd);
+ if (NetRestartWrap) {
+ NetRestartWrap = 0;
+ if (NetDevExists && !once) {
+ NetSetTimeout (10 * CFG_HZ, startAgainTimeout);
+ NetSetHandler (startAgainHandler);
+ } else {
+ NetState = NETLOOP_FAIL;
+ }
+ } else {
+ NetState = NETLOOP_RESTART;
+ }
+#endif /* CONFIG_NET_MULTI */
+}
+
+/**********************************************************************/
+/*
+ * Miscelaneous bits.
+ */
+
+void
+NetSetHandler(rxhand_f * f)
+{
+ packetHandler = f;
+}
+
+
+void
+NetSetTimeout(ulong iv, thand_f * f)
+{
+ if (iv == 0) {
+ timeHandler = (thand_f *)0;
+ } else {
+ timeHandler = f;
+ timeStart = get_timer(0);
+ timeDelta = iv;
+ }
+}
+
+
+void
+NetSendPacket(volatile uchar * pkt, int len)
+{
+ (void) eth_send(pkt, len);
+}
+
+int
+NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, int sport, int len)
+{
+ uchar *pkt;
+
+ /* convert to new style broadcast */
+ if (dest == 0)
+ dest = 0xFFFFFFFF;
+
+ /* if broadcast, make the ether address a broadcast and don't do ARP */
+ if (dest == 0xFFFFFFFF)
+ ether = NetBcastAddr;
+
+ /* if MAC address was not discovered yet, save the packet and do an ARP request */
+ if (memcmp(ether, NetEtherNullAddr, 6) == 0) {
+
+#ifdef ET_DEBUG
+ printf("sending ARP for %08lx\n", dest);
+#endif
+ NetArpWaitPacketIP = dest;
+ NetArpWaitPacketMAC = ether;
+
+ pkt = NetArpWaitTxPacket;
+ pkt += NetSetEther (pkt, NetArpWaitPacketMAC, PROT_IP);
+
+ NetSetIP (pkt, dest, dport, sport, len);
+ memcpy(pkt + IP_HDR_SIZE, (uchar *)NetTxPacket + (pkt - (uchar *)NetArpWaitTxPacket) + IP_HDR_SIZE, len);
+
+ /* size of the waiting packet */
+ NetArpWaitTxPacketSize = (pkt - NetArpWaitTxPacket) + IP_HDR_SIZE + len;
+
+ /* and do the ARP request */
+ NetArpWaitTry = 1;
+ NetArpWaitTimerStart = get_timer(0);
+ ArpRequest();
+ return 1; /* waiting */
+ }
+
+#ifdef ET_DEBUG
+ printf("sending UDP to %08lx/%02x:%02x:%02x:%02x:%02x:%02x\n",
+ dest, ether[0], ether[1], ether[2], ether[3], ether[4], ether[5]);
+#endif
+
+ pkt = (uchar *)NetTxPacket;
+ pkt += NetSetEther (pkt, ether, PROT_IP);
+ NetSetIP (pkt, dest, dport, sport, len);
+ (void) eth_send(NetTxPacket, (pkt - NetTxPacket) + IP_HDR_SIZE + len);
+
+ return 0; /* transmitted */
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_PING)
+static ushort PingSeqNo;
+
+int PingSend(void)
+{
+ static uchar mac[6];
+ volatile IP_t *ip;
+ volatile ushort *s;
+ uchar *pkt;
+
+ /* XXX always send arp request */
+
+ memcpy(mac, NetEtherNullAddr, 6);
+
+#ifdef ET_DEBUG
+ printf("sending ARP for %08lx\n", NetPingIP);
+#endif
+
+ NetArpWaitPacketIP = NetPingIP;
+ NetArpWaitPacketMAC = mac;
+
+ pkt = NetArpWaitTxPacket;
+ pkt += NetSetEther(pkt, mac, PROT_IP);
+
+ ip = (volatile IP_t *)pkt;
+
+ /*
+ * Construct an IP and ICMP header. (need to set no fragment bit - XXX)
+ */
+ ip->ip_hl_v = 0x45; /* IP_HDR_SIZE / 4 (not including UDP) */
+ ip->ip_tos = 0;
+ ip->ip_len = htons(IP_HDR_SIZE_NO_UDP + 8);
+ ip->ip_id = htons(NetIPID++);
+ ip->ip_off = htons(0x4000); /* No fragmentation */
+ ip->ip_ttl = 255;
+ ip->ip_p = 0x01; /* ICMP */
+ ip->ip_sum = 0;
+ NetCopyIP((void*)&ip->ip_src, &NetOurIP); /* already in network byte order */
+ NetCopyIP((void*)&ip->ip_dst, &NetPingIP); /* - "" - */
+ ip->ip_sum = ~NetCksum((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2);
+
+ s = &ip->udp_src; /* XXX ICMP starts here */
+ s[0] = htons(0x0800); /* echo-request, code */
+ s[1] = 0; /* checksum */
+ s[2] = 0; /* identifier */
+ s[3] = htons(PingSeqNo++); /* sequence number */
+ s[1] = ~NetCksum((uchar *)s, 8/2);
+
+ /* size of the waiting packet */
+ NetArpWaitTxPacketSize = (pkt - NetArpWaitTxPacket) + IP_HDR_SIZE_NO_UDP + 8;
+
+ /* and do the ARP request */
+ NetArpWaitTry = 1;
+ NetArpWaitTimerStart = get_timer(0);
+ ArpRequest();
+ return 1; /* waiting */
+}
+
+static void
+PingTimeout (void)
+{
+ eth_halt();
+ NetState = NETLOOP_FAIL; /* we did not get the reply */
+}
+
+static void
+PingHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len)
+{
+ IPaddr_t tmp;
+ volatile IP_t *ip = (volatile IP_t *)pkt;
+
+ tmp = NetReadIP((void *)&ip->ip_src);
+ if (tmp != NetPingIP)
+ return;
+
+ NetState = NETLOOP_SUCCESS;
+}
+
+static void PingStart(void)
+{
+#if defined(CONFIG_NET_MULTI)
+ printf ("Using %s device\n", eth_get_name());
+#endif /* CONFIG_NET_MULTI */
+ NetSetTimeout (10 * CFG_HZ, PingTimeout);
+ NetSetHandler (PingHandler);
+
+ PingSend();
+}
+#endif /* CFG_CMD_PING */
+
+#if (CONFIG_COMMANDS & CFG_CMD_CDP)
+
+#define CDP_DEVICE_ID_TLV 0x0001
+#define CDP_ADDRESS_TLV 0x0002
+#define CDP_PORT_ID_TLV 0x0003
+#define CDP_CAPABILITIES_TLV 0x0004
+#define CDP_VERSION_TLV 0x0005
+#define CDP_PLATFORM_TLV 0x0006
+#define CDP_NATIVE_VLAN_TLV 0x000a
+#define CDP_APPLIANCE_VLAN_TLV 0x000e
+#define CDP_TRIGGER_TLV 0x000f
+#define CDP_POWER_CONSUMPTION_TLV 0x0010
+#define CDP_SYSNAME_TLV 0x0014
+#define CDP_SYSOBJECT_TLV 0x0015
+#define CDP_MANAGEMENT_ADDRESS_TLV 0x0016
+
+#define CDP_TIMEOUT (CFG_HZ/4) /* one packet every 250ms */
+
+static int CDPSeq;
+static int CDPOK;
+
+ushort CDPNativeVLAN;
+ushort CDPApplianceVLAN;
+
+static const uchar CDP_SNAP_hdr[8] = { 0xAA, 0xAA, 0x03, 0x00, 0x00, 0x0C, 0x20, 0x00 };
+
+static ushort CDP_compute_csum(const uchar *buff, ushort len)
+{
+ ushort csum;
+ int odd;
+ ulong result = 0;
+ ushort leftover;
+ ushort *p;
+
+ if (len > 0) {
+ odd = 1 & (ulong)buff;
+ if (odd) {
+ result = *buff << 8;
+ len--;
+ buff++;
+ }
+ while (len > 1) {
+ p = (ushort *)buff;
+ result += *p++;
+ buff = (uchar *)p;
+ if (result & 0x80000000)
+ result = (result & 0xFFFF) + (result >> 16);
+ len -= 2;
+ }
+ if (len) {
+ leftover = (signed short)(*(const signed char *)buff);
+ /* CISCO SUCKS big time! (and blows too):
+ * CDP uses the IP checksum algorithm with a twist;
+ * for the last byte it *sign* extends and sums.
+ */
+ result = (result & 0xffff0000) | ((result + leftover) & 0x0000ffff);
+ }
+ while (result >> 16)
+ result = (result & 0xFFFF) + (result >> 16);
+
+ if (odd)
+ result = ((result >> 8) & 0xff) | ((result & 0xff) << 8);
+ }
+
+ /* add up 16-bit and 17-bit words for 17+c bits */
+ result = (result & 0xffff) + (result >> 16);
+ /* add up 16-bit and 2-bit for 16+c bit */
+ result = (result & 0xffff) + (result >> 16);
+ /* add up carry.. */
+ result = (result & 0xffff) + (result >> 16);
+
+ /* negate */
+ csum = ~(ushort)result;
+
+ /* run time endian detection */
+ if (csum != htons(csum)) /* little endian */
+ csum = htons(csum);
+
+ return csum;
+}
+
+int CDPSendTrigger(void)
+{
+ volatile uchar *pkt;
+ volatile ushort *s;
+ volatile ushort *cp;
+ Ethernet_t *et;
+ int len;
+ ushort chksum;
+#if defined(CONFIG_CDP_DEVICE_ID) || defined(CONFIG_CDP_PORT_ID) || \
+ defined(CONFIG_CDP_VERSION) || defined(CONFIG_CDP_PLATFORM)
+ char buf[32];
+#endif
+
+ pkt = NetTxPacket;
+ et = (Ethernet_t *)pkt;
+
+ /* NOTE: trigger sent not on any VLAN */
+
+ /* form ethernet header */
+ memcpy(et->et_dest, NetCDPAddr, 6);
+ memcpy(et->et_src, NetOurEther, 6);
+
+ pkt += ETHER_HDR_SIZE;
+
+ /* SNAP header */
+ memcpy((uchar *)pkt, CDP_SNAP_hdr, sizeof(CDP_SNAP_hdr));
+ pkt += sizeof(CDP_SNAP_hdr);
+
+ /* CDP header */
+ *pkt++ = 0x02; /* CDP version 2 */
+ *pkt++ = 180; /* TTL */
+ s = (volatile ushort *)pkt;
+ cp = s;
+ *s++ = htons(0); /* checksum (0 for later calculation) */
+
+ /* CDP fields */
+#ifdef CONFIG_CDP_DEVICE_ID
+ *s++ = htons(CDP_DEVICE_ID_TLV);
+ *s++ = htons(CONFIG_CDP_DEVICE_ID);
+ memset(buf, 0, sizeof(buf));
+ sprintf(buf, CONFIG_CDP_DEVICE_ID_PREFIX "%02X%02X%02X%02X%02X%02X",
+ NetOurEther[0] & 0xff, NetOurEther[1] & 0xff,
+ NetOurEther[2] & 0xff, NetOurEther[3] & 0xff,
+ NetOurEther[4] & 0xff, NetOurEther[5] & 0xff);
+ memcpy((uchar *)s, buf, 16);
+ s += 16 / 2;
+#endif
+
+#ifdef CONFIG_CDP_PORT_ID
+ *s++ = htons(CDP_PORT_ID_TLV);
+ memset(buf, 0, sizeof(buf));
+ sprintf(buf, CONFIG_CDP_PORT_ID, eth_get_dev_index());
+ len = strlen(buf);
+ if (len & 1) /* make it even */
+ len++;
+ *s++ = htons(len + 4);
+ memcpy((uchar *)s, buf, len);
+ s += len / 2;
+#endif
+
+#ifdef CONFIG_CDP_CAPABILITIES
+ *s++ = htons(CDP_CAPABILITIES_TLV);
+ *s++ = htons(8);
+ *(ulong *)s = htonl(CONFIG_CDP_CAPABILITIES);
+ s += 2;
+#endif
+
+#ifdef CONFIG_CDP_VERSION
+ *s++ = htons(CDP_VERSION_TLV);
+ memset(buf, 0, sizeof(buf));
+ strcpy(buf, CONFIG_CDP_VERSION);
+ len = strlen(buf);
+ if (len & 1) /* make it even */
+ len++;
+ *s++ = htons(len + 4);
+ memcpy((uchar *)s, buf, len);
+ s += len / 2;
+#endif
+
+#ifdef CONFIG_CDP_PLATFORM
+ *s++ = htons(CDP_PLATFORM_TLV);
+ memset(buf, 0, sizeof(buf));
+ strcpy(buf, CONFIG_CDP_PLATFORM);
+ len = strlen(buf);
+ if (len & 1) /* make it even */
+ len++;
+ *s++ = htons(len + 4);
+ memcpy((uchar *)s, buf, len);
+ s += len / 2;
+#endif
+
+#ifdef CONFIG_CDP_TRIGGER
+ *s++ = htons(CDP_TRIGGER_TLV);
+ *s++ = htons(8);
+ *(ulong *)s = htonl(CONFIG_CDP_TRIGGER);
+ s += 2;
+#endif
+
+#ifdef CONFIG_CDP_POWER_CONSUMPTION
+ *s++ = htons(CDP_POWER_CONSUMPTION_TLV);
+ *s++ = htons(6);
+ *s++ = htons(CONFIG_CDP_POWER_CONSUMPTION);
+#endif
+
+ /* length of ethernet packet */
+ len = (uchar *)s - ((uchar *)NetTxPacket + ETHER_HDR_SIZE);
+ et->et_protlen = htons(len);
+
+ len = ETHER_HDR_SIZE + sizeof(CDP_SNAP_hdr);
+ chksum = CDP_compute_csum((uchar *)NetTxPacket + len, (uchar *)s - (NetTxPacket + len));
+ if (chksum == 0)
+ chksum = 0xFFFF;
+ *cp = htons(chksum);
+
+ (void) eth_send(NetTxPacket, (uchar *)s - NetTxPacket);
+ return 0;
+}
+
+static void
+CDPTimeout (void)
+{
+ CDPSeq++;
+
+ if (CDPSeq < 3) {
+ NetSetTimeout (CDP_TIMEOUT, CDPTimeout);
+ CDPSendTrigger();
+ return;
+ }
+
+ /* if not OK try again */
+ if (!CDPOK)
+ NetStartAgain();
+ else
+ NetState = NETLOOP_SUCCESS;
+}
+
+static void
+CDPDummyHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len)
+{
+ /* nothing */
+}
+
+static void
+CDPHandler(const uchar * pkt, unsigned len)
+{
+ const uchar *t;
+ const ushort *ss;
+ ushort type, tlen;
+ uchar applid;
+ ushort vlan, nvlan;
+
+ /* minimum size? */
+ if (len < sizeof(CDP_SNAP_hdr) + 4)
+ goto pkt_short;
+
+ /* check for valid CDP SNAP header */
+ if (memcmp(pkt, CDP_SNAP_hdr, sizeof(CDP_SNAP_hdr)) != 0)
+ return;
+
+ pkt += sizeof(CDP_SNAP_hdr);
+ len -= sizeof(CDP_SNAP_hdr);
+
+ /* Version of CDP protocol must be >= 2 and TTL != 0 */
+ if (pkt[0] < 0x02 || pkt[1] == 0)
+ return;
+
+ /* if version is greater than 0x02 maybe we'll have a problem; output a warning */
+ if (pkt[0] != 0x02)
+ printf("** WARNING: CDP packet received with a protocol version %d > 2\n",
+ pkt[0] & 0xff);
+
+ if (CDP_compute_csum(pkt, len) != 0)
+ return;
+
+ pkt += 4;
+ len -= 4;
+
+ vlan = htons(-1);
+ nvlan = htons(-1);
+ while (len > 0) {
+ if (len < 4)
+ goto pkt_short;
+
+ ss = (const ushort *)pkt;
+ type = ntohs(ss[0]);
+ tlen = ntohs(ss[1]);
+ if (tlen > len) {
+ goto pkt_short;
+ }
+
+ pkt += tlen;
+ len -= tlen;
+
+ ss += 2; /* point ss to the data of the TLV */
+ tlen -= 4;
+
+ switch (type) {
+ case CDP_DEVICE_ID_TLV:
+ break;
+ case CDP_ADDRESS_TLV:
+ break;
+ case CDP_PORT_ID_TLV:
+ break;
+ case CDP_CAPABILITIES_TLV:
+ break;
+ case CDP_VERSION_TLV:
+ break;
+ case CDP_PLATFORM_TLV:
+ break;
+ case CDP_NATIVE_VLAN_TLV:
+ nvlan = *ss;
+ break;
+ case CDP_APPLIANCE_VLAN_TLV:
+ t = (const uchar *)ss;
+ while (tlen > 0) {
+ if (tlen < 3)
+ goto pkt_short;
+
+ applid = t[0];
+ ss = (const ushort *)(t + 1);
+
+#ifdef CONFIG_CDP_APPLIANCE_VLAN_TYPE
+ if (applid == CONFIG_CDP_APPLIANCE_VLAN_TYPE)
+ vlan = *ss;
+#else
+ vlan = ntohs(*ss); /* XXX will this work; dunno */
+#endif
+ t += 3; tlen -= 3;
+ }
+ break;
+ case CDP_TRIGGER_TLV:
+ break;
+ case CDP_POWER_CONSUMPTION_TLV:
+ break;
+ case CDP_SYSNAME_TLV:
+ break;
+ case CDP_SYSOBJECT_TLV:
+ break;
+ case CDP_MANAGEMENT_ADDRESS_TLV:
+ break;
+ }
+ }
+
+ CDPApplianceVLAN = vlan;
+ CDPNativeVLAN = nvlan;
+
+ CDPOK = 1;
+ return;
+
+ pkt_short:
+ printf("** CDP packet is too short\n");
+ return;
+}
+
+static void CDPStart(void)
+{
+#if defined(CONFIG_NET_MULTI)
+ printf ("Using %s device\n", eth_get_name());
+#endif
+ CDPSeq = 0;
+ CDPOK = 0;
+
+ CDPNativeVLAN = htons(-1);
+ CDPApplianceVLAN = htons(-1);
+
+ NetSetTimeout (CDP_TIMEOUT, CDPTimeout);
+ NetSetHandler (CDPDummyHandler);
+
+ CDPSendTrigger();
+}
+#endif /* CFG_CMD_CDP */
+
+
+void
+NetReceive(volatile uchar * inpkt, int len)
+{
+ Ethernet_t *et;
+ IP_t *ip;
+ ARP_t *arp;
+ IPaddr_t tmp;
+ int x;
+ uchar *pkt;
+#if (CONFIG_COMMANDS & CFG_CMD_CDP)
+ int iscdp;
+#endif
+ ushort cti = 0, vlanid = VLAN_NONE, myvlanid, mynvlanid;
+
+#ifdef ET_DEBUG
+ printf("packet received\n");
+#endif
+
+ NetRxPkt = inpkt;
+ NetRxPktLen = len;
+ et = (Ethernet_t *)inpkt;
+
+ /* too small packet? */
+ if (len < ETHER_HDR_SIZE)
+ return;
+
+#if (CONFIG_COMMANDS & CFG_CMD_CDP)
+ /* keep track if packet is CDP */
+ iscdp = memcmp(et->et_dest, NetCDPAddr, 6) == 0;
+#endif
+
+ myvlanid = ntohs(NetOurVLAN);
+ if (myvlanid == (ushort)-1)
+ myvlanid = VLAN_NONE;
+ mynvlanid = ntohs(NetOurNativeVLAN);
+ if (mynvlanid == (ushort)-1)
+ mynvlanid = VLAN_NONE;
+
+ x = ntohs(et->et_protlen);
+
+#ifdef ET_DEBUG
+ printf("packet received\n");
+#endif
+
+ if (x < 1514) {
+ /*
+ * Got a 802 packet. Check the other protocol field.
+ */
+ x = ntohs(et->et_prot);
+
+ ip = (IP_t *)(inpkt + E802_HDR_SIZE);
+ len -= E802_HDR_SIZE;
+
+ } else if (x != PROT_VLAN) { /* normal packet */
+ ip = (IP_t *)(inpkt + ETHER_HDR_SIZE);
+ len -= ETHER_HDR_SIZE;
+
+ } else { /* VLAN packet */
+ VLAN_Ethernet_t *vet = (VLAN_Ethernet_t *)et;
+
+#ifdef ET_DEBUG
+ printf("VLAN packet received\n");
+#endif
+ /* too small packet? */
+ if (len < VLAN_ETHER_HDR_SIZE)
+ return;
+
+ /* if no VLAN active */
+ if ((ntohs(NetOurVLAN) & VLAN_IDMASK) == VLAN_NONE
+#if (CONFIG_COMMANDS & CFG_CMD_CDP)
+ && iscdp == 0
+#endif
+ )
+ return;
+
+ cti = ntohs(vet->vet_tag);
+ vlanid = cti & VLAN_IDMASK;
+ x = ntohs(vet->vet_type);
+
+ ip = (IP_t *)(inpkt + VLAN_ETHER_HDR_SIZE);
+ len -= VLAN_ETHER_HDR_SIZE;
+ }
+
+#ifdef ET_DEBUG
+ printf("Receive from protocol 0x%x\n", x);
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_CDP)
+ if (iscdp) {
+ CDPHandler((uchar *)ip, len);
+ return;
+ }
+#endif
+
+ if ((myvlanid & VLAN_IDMASK) != VLAN_NONE) {
+ if (vlanid == VLAN_NONE)
+ vlanid = (mynvlanid & VLAN_IDMASK);
+ /* not matched? */
+ if (vlanid != (myvlanid & VLAN_IDMASK))
+ return;
+ }
+
+ switch (x) {
+
+ case PROT_ARP:
+ /*
+ * We have to deal with two types of ARP packets:
+ * - REQUEST packets will be answered by sending our
+ * IP address - if we know it.
+ * - REPLY packates are expected only after we asked
+ * for the TFTP server's or the gateway's ethernet
+ * address; so if we receive such a packet, we set
+ * the server ethernet address
+ */
+#ifdef ET_DEBUG
+ puts ("Got ARP\n");
+#endif
+ arp = (ARP_t *)ip;
+ if (len < ARP_HDR_SIZE) {
+ printf("bad length %d < %d\n", len, ARP_HDR_SIZE);
+ return;
+ }
+ if (ntohs(arp->ar_hrd) != ARP_ETHER) {
+ return;
+ }
+ if (ntohs(arp->ar_pro) != PROT_IP) {
+ return;
+ }
+ if (arp->ar_hln != 6) {
+ return;
+ }
+ if (arp->ar_pln != 4) {
+ return;
+ }
+
+ if (NetOurIP == 0) {
+ return;
+ }
+
+ if (NetReadIP(&arp->ar_data[16]) != NetOurIP) {
+ return;
+ }
+
+ switch (ntohs(arp->ar_op)) {
+ case ARPOP_REQUEST: /* reply with our IP address */
+#ifdef ET_DEBUG
+ puts ("Got ARP REQUEST, return our IP\n");
+#endif
+ pkt = (uchar *)et;
+ pkt += NetSetEther(pkt, et->et_src, PROT_ARP);
+ arp->ar_op = htons(ARPOP_REPLY);
+ memcpy (&arp->ar_data[10], &arp->ar_data[0], 6);
+ NetCopyIP(&arp->ar_data[16], &arp->ar_data[6]);
+ memcpy (&arp->ar_data[ 0], NetOurEther, 6);
+ NetCopyIP(&arp->ar_data[ 6], &NetOurIP);
+ (void) eth_send((uchar *)et, (pkt - (uchar *)et) + ARP_HDR_SIZE);
+ return;
+
+ case ARPOP_REPLY: /* arp reply */
+ /* are we waiting for a reply */
+ if (!NetArpWaitPacketIP || !NetArpWaitPacketMAC)
+ break;
+#ifdef ET_DEBUG
+ printf("Got ARP REPLY, set server/gtwy eth addr (%02x:%02x:%02x:%02x:%02x:%02x)\n",
+ arp->ar_data[0], arp->ar_data[1],
+ arp->ar_data[2], arp->ar_data[3],
+ arp->ar_data[4], arp->ar_data[5]);
+#endif
+
+ tmp = NetReadIP(&arp->ar_data[6]);
+
+ /* matched waiting packet's address */
+ if (tmp == NetArpWaitReplyIP) {
+#ifdef ET_DEBUG
+ puts ("Got it\n");
+#endif
+ /* save address for later use */
+ memcpy(NetArpWaitPacketMAC, &arp->ar_data[0], 6);
+
+#ifdef CONFIG_NETCONSOLE
+ (*packetHandler)(0,0,0,0);
+#endif
+ /* modify header, and transmit it */
+ memcpy(((Ethernet_t *)NetArpWaitTxPacket)->et_dest, NetArpWaitPacketMAC, 6);
+ (void) eth_send(NetArpWaitTxPacket, NetArpWaitTxPacketSize);
+
+ /* no arp request pending now */
+ NetArpWaitPacketIP = 0;
+ NetArpWaitTxPacketSize = 0;
+ NetArpWaitPacketMAC = NULL;
+
+ }
+ return;
+ default:
+#ifdef ET_DEBUG
+ printf("Unexpected ARP opcode 0x%x\n", ntohs(arp->ar_op));
+#endif
+ return;
+ }
+ break;
+
+ case PROT_RARP:
+#ifdef ET_DEBUG
+ puts ("Got RARP\n");
+#endif
+ arp = (ARP_t *)ip;
+ if (len < ARP_HDR_SIZE) {
+ printf("bad length %d < %d\n", len, ARP_HDR_SIZE);
+ return;
+ }
+
+ if ((ntohs(arp->ar_op) != RARPOP_REPLY) ||
+ (ntohs(arp->ar_hrd) != ARP_ETHER) ||
+ (ntohs(arp->ar_pro) != PROT_IP) ||
+ (arp->ar_hln != 6) || (arp->ar_pln != 4)) {
+
+ puts ("invalid RARP header\n");
+ } else {
+ NetCopyIP(&NetOurIP, &arp->ar_data[16]);
+ if (NetServerIP == 0)
+ NetCopyIP(&NetServerIP, &arp->ar_data[ 6]);
+ memcpy (NetServerEther, &arp->ar_data[ 0], 6);
+
+ (*packetHandler)(0,0,0,0);
+ }
+ break;
+
+ case PROT_IP:
+#ifdef ET_DEBUG
+ puts ("Got IP\n");
+#endif
+ if (len < IP_HDR_SIZE) {
+ debug ("len bad %d < %d\n", len, IP_HDR_SIZE);
+ return;
+ }
+ if (len < ntohs(ip->ip_len)) {
+ printf("len bad %d < %d\n", len, ntohs(ip->ip_len));
+ return;
+ }
+ len = ntohs(ip->ip_len);
+#ifdef ET_DEBUG
+ printf("len=%d, v=%02x\n", len, ip->ip_hl_v & 0xff);
+#endif
+ if ((ip->ip_hl_v & 0xf0) != 0x40) {
+ return;
+ }
+ if (ip->ip_off & htons(0x1fff)) { /* Can't deal w/ fragments */
+ return;
+ }
+ if (!NetCksumOk((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2)) {
+ puts ("checksum bad\n");
+ return;
+ }
+ tmp = NetReadIP(&ip->ip_dst);
+ if (NetOurIP && tmp != NetOurIP && tmp != 0xFFFFFFFF) {
+ return;
+ }
+ /*
+ * watch for ICMP host redirects
+ *
+ * There is no real handler code (yet). We just watch
+ * for ICMP host redirect messages. In case anybody
+ * sees these messages: please contact me
+ * (wd@denx.de), or - even better - send me the
+ * necessary fixes :-)
+ *
+ * Note: in all cases where I have seen this so far
+ * it was a problem with the router configuration,
+ * for instance when a router was configured in the
+ * BOOTP reply, but the TFTP server was on the same
+ * subnet. So this is probably a warning that your
+ * configuration might be wrong. But I'm not really
+ * sure if there aren't any other situations.
+ */
+ if (ip->ip_p == IPPROTO_ICMP) {
+ ICMP_t *icmph = (ICMP_t *)&(ip->udp_src);
+
+ switch (icmph->type) {
+ case ICMP_REDIRECT:
+ if (icmph->code != ICMP_REDIR_HOST)
+ return;
+ puts (" ICMP Host Redirect to ");
+ print_IPaddr(icmph->un.gateway);
+ putc(' ');
+ return;
+#if (CONFIG_COMMANDS & CFG_CMD_PING)
+ case ICMP_ECHO_REPLY:
+ /*
+ * IP header OK. Pass the packet to the current handler.
+ */
+ /* XXX point to ip packet */
+ (*packetHandler)((uchar *)ip, 0, 0, 0);
+ return;
+#endif
+ default:
+ return;
+ }
+ } else if (ip->ip_p != IPPROTO_UDP) { /* Only UDP packets */
+ return;
+ }
+
+#ifdef CONFIG_UDP_CHECKSUM
+ if (ip->udp_xsum != 0) {
+ ulong xsum;
+ ushort *sumptr;
+ ushort sumlen;
+
+ xsum = ip->ip_p;
+ xsum += (ntohs(ip->udp_len));
+ xsum += (ntohl(ip->ip_src) >> 16) & 0x0000ffff;
+ xsum += (ntohl(ip->ip_src) >> 0) & 0x0000ffff;
+ xsum += (ntohl(ip->ip_dst) >> 16) & 0x0000ffff;
+ xsum += (ntohl(ip->ip_dst) >> 0) & 0x0000ffff;
+
+ sumlen = ntohs(ip->udp_len);
+ sumptr = (ushort *) &(ip->udp_src);
+
+ while (sumlen > 1) {
+ ushort sumdata;
+
+ sumdata = *sumptr++;
+ xsum += ntohs(sumdata);
+ sumlen -= 2;
+ }
+ if (sumlen > 0) {
+ ushort sumdata;
+
+ sumdata = *(unsigned char *) sumptr;
+ sumdata = (sumdata << 8) & 0xff00;
+ xsum += sumdata;
+ }
+ while ((xsum >> 16) != 0) {
+ xsum = (xsum & 0x0000ffff) + ((xsum >> 16) & 0x0000ffff);
+ }
+ if ((xsum != 0x00000000) && (xsum != 0x0000ffff)) {
+ printf(" UDP wrong checksum %08x %08x\n", xsum, ntohs(ip->udp_xsum));
+ return;
+ }
+ }
+#endif
+
+#ifdef CONFIG_NETCONSOLE
+ nc_input_packet((uchar *)ip +IP_HDR_SIZE,
+ ntohs(ip->udp_dst),
+ ntohs(ip->udp_src),
+ ntohs(ip->udp_len) - 8);
+#endif
+ /*
+ * IP header OK. Pass the packet to the current handler.
+ */
+ (*packetHandler)((uchar *)ip +IP_HDR_SIZE,
+ ntohs(ip->udp_dst),
+ ntohs(ip->udp_src),
+ ntohs(ip->udp_len) - 8);
+ break;
+ }
+}
+
+
+/**********************************************************************/
+
+static int net_check_prereq (proto_t protocol)
+{
+ switch (protocol) {
+ /* Fall through */
+#if (CONFIG_COMMANDS & CFG_CMD_PING)
+ case PING:
+ if (NetPingIP == 0) {
+ puts ("*** ERROR: ping address not given\n");
+ return (1);
+ }
+ goto common;
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_SNTP)
+ case SNTP:
+ if (NetNtpServerIP == 0) {
+ puts ("*** ERROR: NTP server address not given\n");
+ return (1);
+ }
+ goto common;
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_NFS)
+ case NFS:
+#endif
+ case NETCONS:
+ case TFTP:
+ if (NetServerIP == 0) {
+ puts ("*** ERROR: `serverip' not set\n");
+ return (1);
+ }
+#if (CONFIG_COMMANDS & (CFG_CMD_PING | CFG_CMD_SNTP))
+ common:
+#endif
+
+ if (NetOurIP == 0) {
+ puts ("*** ERROR: `ipaddr' not set\n");
+ return (1);
+ }
+ /* Fall through */
+
+ case DHCP:
+ case RARP:
+ case BOOTP:
+ case CDP:
+ if (memcmp (NetOurEther, "\0\0\0\0\0\0", 6) == 0) {
+#ifdef CONFIG_NET_MULTI
+ extern int eth_get_dev_index (void);
+ int num = eth_get_dev_index ();
+
+ switch (num) {
+ case -1:
+ puts ("*** ERROR: No ethernet found.\n");
+ return (1);
+ case 0:
+ puts ("*** ERROR: `ethaddr' not set\n");
+ break;
+ default:
+ printf ("*** ERROR: `eth%daddr' not set\n",
+ num);
+ break;
+ }
+
+ NetStartAgain ();
+ return (2);
+#else
+ puts ("*** ERROR: `ethaddr' not set\n");
+ return (1);
+#endif
+ }
+ /* Fall through */
+ default:
+ return (0);
+ }
+ return (0); /* OK */
+}
+/**********************************************************************/
+
+int
+NetCksumOk(uchar * ptr, int len)
+{
+ return !((NetCksum(ptr, len) + 1) & 0xfffe);
+}
+
+
+unsigned
+NetCksum(uchar * ptr, int len)
+{
+ ulong xsum;
+ ushort *p = (ushort *)ptr;
+
+ xsum = 0;
+ while (len-- > 0)
+ xsum += *p++;
+ xsum = (xsum & 0xffff) + (xsum >> 16);
+ xsum = (xsum & 0xffff) + (xsum >> 16);
+ return (xsum & 0xffff);
+}
+
+int
+NetEthHdrSize(void)
+{
+ ushort myvlanid;
+
+ myvlanid = ntohs(NetOurVLAN);
+ if (myvlanid == (ushort)-1)
+ myvlanid = VLAN_NONE;
+
+ return ((myvlanid & VLAN_IDMASK) == VLAN_NONE) ? ETHER_HDR_SIZE : VLAN_ETHER_HDR_SIZE;
+}
+
+int
+NetSetEther(volatile uchar * xet, uchar * addr, uint prot)
+{
+ Ethernet_t *et = (Ethernet_t *)xet;
+ ushort myvlanid;
+
+ myvlanid = ntohs(NetOurVLAN);
+ if (myvlanid == (ushort)-1)
+ myvlanid = VLAN_NONE;
+
+ memcpy (et->et_dest, addr, 6);
+ memcpy (et->et_src, NetOurEther, 6);
+ if ((myvlanid & VLAN_IDMASK) == VLAN_NONE) {
+ et->et_protlen = htons(prot);
+ return ETHER_HDR_SIZE;
+ } else {
+ VLAN_Ethernet_t *vet = (VLAN_Ethernet_t *)xet;
+
+ vet->vet_vlan_type = htons(PROT_VLAN);
+ vet->vet_tag = htons((0 << 5) | (myvlanid & VLAN_IDMASK));
+ vet->vet_type = htons(prot);
+ return VLAN_ETHER_HDR_SIZE;
+ }
+}
+
+void
+NetSetIP(volatile uchar * xip, IPaddr_t dest, int dport, int sport, int len)
+{
+ volatile IP_t *ip = (IP_t *)xip;
+
+ /*
+ * If the data is an odd number of bytes, zero the
+ * byte after the last byte so that the checksum
+ * will work.
+ */
+ if (len & 1)
+ xip[IP_HDR_SIZE + len] = 0;
+
+ /*
+ * Construct an IP and UDP header.
+ * (need to set no fragment bit - XXX)
+ */
+ ip->ip_hl_v = 0x45; /* IP_HDR_SIZE / 4 (not including UDP) */
+ ip->ip_tos = 0;
+ ip->ip_len = htons(IP_HDR_SIZE + len);
+ ip->ip_id = htons(NetIPID++);
+ ip->ip_off = htons(0x4000); /* No fragmentation */
+ ip->ip_ttl = 255;
+ ip->ip_p = 17; /* UDP */
+ ip->ip_sum = 0;
+ NetCopyIP((void*)&ip->ip_src, &NetOurIP); /* already in network byte order */
+ NetCopyIP((void*)&ip->ip_dst, &dest); /* - "" - */
+ ip->udp_src = htons(sport);
+ ip->udp_dst = htons(dport);
+ ip->udp_len = htons(8 + len);
+ ip->udp_xsum = 0;
+ ip->ip_sum = ~NetCksum((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2);
+}
+
+void copy_filename (char *dst, char *src, int size)
+{
+ if (*src && (*src == '"')) {
+ ++src;
+ --size;
+ }
+
+ while ((--size > 0) && *src && (*src != '"')) {
+ *dst++ = *src++;
+ }
+ *dst = '\0';
+}
+
+#endif /* CFG_CMD_NET */
+
+void ip_to_string (IPaddr_t x, char *s)
+{
+ x = ntohl (x);
+ sprintf (s, "%d.%d.%d.%d",
+ (int) ((x >> 24) & 0xff),
+ (int) ((x >> 16) & 0xff),
+ (int) ((x >> 8) & 0xff), (int) ((x >> 0) & 0xff)
+ );
+}
+
+IPaddr_t string_to_ip(char *s)
+{
+ IPaddr_t addr;
+ char *e;
+ int i;
+
+ if (s == NULL)
+ return(0);
+
+ for (addr=0, i=0; i<4; ++i) {
+ ulong val = s ? simple_strtoul(s, &e, 10) : 0;
+ addr <<= 8;
+ addr |= (val & 0xFF);
+ if (s) {
+ s = (*e) ? e+1 : e;
+ }
+ }
+
+ return (htonl(addr));
+}
+
+void VLAN_to_string(ushort x, char *s)
+{
+ x = ntohs(x);
+
+ if (x == (ushort)-1)
+ x = VLAN_NONE;
+
+ if (x == VLAN_NONE)
+ strcpy(s, "none");
+ else
+ sprintf(s, "%d", x & VLAN_IDMASK);
+}
+
+ushort string_to_VLAN(char *s)
+{
+ ushort id;
+
+ if (s == NULL)
+ return htons(VLAN_NONE);
+
+ if (*s < '0' || *s > '9')
+ id = VLAN_NONE;
+ else
+ id = (ushort)simple_strtoul(s, NULL, 10);
+
+ return htons(id);
+}
+
+void print_IPaddr (IPaddr_t x)
+{
+ char tmp[16];
+
+ ip_to_string (x, tmp);
+
+ puts (tmp);
+}
+
+IPaddr_t getenv_IPaddr (char *var)
+{
+ return (string_to_ip(getenv(var)));
+}
+
+ushort getenv_VLAN(char *var)
+{
+ return (string_to_VLAN(getenv(var)));
+}
--- /dev/null
+/*
+ * NFS support driver - based on etherboot and U-BOOT's tftp.c
+ *
+ * Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ */
+
+/* NOTE: the NFS code is heavily inspired by the NetBSD netboot code (read:
+ * large portions are copied verbatim) as distributed in OSKit 0.97. A few
+ * changes were necessary to adapt the code to Etherboot and to fix several
+ * inconsistencies. Also the RPC message preparation is done "by hand" to
+ * avoid adding netsprintf() which I find hard to understand and use. */
+
+/* NOTE 2: Etherboot does not care about things beyond the kernel image, so
+ * it loads the kernel image off the boot server (ARP_SERVER) and does not
+ * access the client root disk (root-path in dhcpd.conf), which would use
+ * ARP_ROOTSERVER. The root disk is something the operating system we are
+ * about to load needs to use. This is different from the OSKit 0.97 logic. */
+
+/* NOTE 3: Symlink handling introduced by Anselm M Hoffmeister, 2003-July-14
+ * If a symlink is encountered, it is followed as far as possible (recursion
+ * possible, maximum 16 steps). There is no clearing of ".."'s inside the
+ * path, so please DON'T DO THAT. thx. */
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <malloc.h>
+#include "nfs.h"
+#include "bootp.h"
+
+/*#define NFS_DEBUG*/
+
+#if ((CONFIG_COMMANDS & CFG_CMD_NET) && (CONFIG_COMMANDS & CFG_CMD_NFS))
+
+#define HASHES_PER_LINE 65 /* Number of "loading" hashes per line */
+#define NFS_TIMEOUT 60
+
+static int fs_mounted = 0;
+static unsigned long rpc_id = 0;
+static int nfs_offset = -1;
+static int nfs_len;
+
+static char dirfh[NFS_FHSIZE]; /* file handle of directory */
+static char filefh[NFS_FHSIZE]; /* file handle of kernel image */
+
+static int NfsDownloadState;
+static IPaddr_t NfsServerIP;
+static int NfsSrvMountPort;
+static int NfsSrvNfsPort;
+static int NfsOurPort;
+static int NfsTimeoutCount;
+static int NfsState;
+#define STATE_PRCLOOKUP_PROG_MOUNT_REQ 1
+#define STATE_PRCLOOKUP_PROG_NFS_REQ 2
+#define STATE_MOUNT_REQ 3
+#define STATE_UMOUNT_REQ 4
+#define STATE_LOOKUP_REQ 5
+#define STATE_READ_REQ 6
+#define STATE_READLINK_REQ 7
+
+static char default_filename[64];
+static char *nfs_filename;
+static char *nfs_path;
+static char nfs_path_buff[2048];
+
+static __inline__ int
+store_block (uchar * src, unsigned offset, unsigned len)
+{
+ ulong newsize = offset + len;
+#ifdef CFG_DIRECT_FLASH_NFS
+ int i, rc = 0;
+
+ for (i=0; i<CFG_MAX_FLASH_BANKS; i++) {
+ /* start address in flash? */
+ if (load_addr + offset >= flash_info[i].start[0]) {
+ rc = 1;
+ break;
+ }
+ }
+
+ if (rc) { /* Flash is destination for this packet */
+ rc = flash_write ((uchar *)src, (ulong)(load_addr+offset), len);
+ if (rc) {
+ flash_perror (rc);
+ return -1;
+ }
+ } else
+#endif /* CFG_DIRECT_FLASH_NFS */
+ {
+ (void)memcpy ((void *)(load_addr + offset), src, len);
+ }
+
+ if (NetBootFileXferSize < (offset+len))
+ NetBootFileXferSize = newsize;
+ return 0;
+}
+
+static char*
+basename (char *path)
+{
+ char *fname;
+
+ fname = path + strlen(path) - 1;
+ while (fname >= path) {
+ if (*fname == '/') {
+ fname++;
+ break;
+ }
+ fname--;
+ }
+ return fname;
+}
+
+static char*
+dirname (char *path)
+{
+ char *fname;
+
+ fname = basename (path);
+ --fname;
+ *fname = '\0';
+ return path;
+}
+
+/**************************************************************************
+RPC_ADD_CREDENTIALS - Add RPC authentication/verifier entries
+**************************************************************************/
+static long *rpc_add_credentials (long *p)
+{
+ int hl;
+ int hostnamelen;
+ char hostname[256];
+
+ strcpy (hostname, "");
+ hostnamelen=strlen (hostname);
+
+ /* Here's the executive summary on authentication requirements of the
+ * various NFS server implementations: Linux accepts both AUTH_NONE
+ * and AUTH_UNIX authentication (also accepts an empty hostname field
+ * in the AUTH_UNIX scheme). *BSD refuses AUTH_NONE, but accepts
+ * AUTH_UNIX (also accepts an empty hostname field in the AUTH_UNIX
+ * scheme). To be safe, use AUTH_UNIX and pass the hostname if we have
+ * it (if the BOOTP/DHCP reply didn't give one, just use an empty
+ * hostname). */
+
+ hl = (hostnamelen + 3) & ~3;
+
+ /* Provide an AUTH_UNIX credential. */
+ *p++ = htonl(1); /* AUTH_UNIX */
+ *p++ = htonl(hl+20); /* auth length */
+ *p++ = htonl(0); /* stamp */
+ *p++ = htonl(hostnamelen); /* hostname string */
+ if (hostnamelen & 3) {
+ *(p + hostnamelen / 4) = 0; /* add zero padding */
+ }
+ memcpy (p, hostname, hostnamelen);
+ p += hl / 4;
+ *p++ = 0; /* uid */
+ *p++ = 0; /* gid */
+ *p++ = 0; /* auxiliary gid list */
+
+ /* Provide an AUTH_NONE verifier. */
+ *p++ = 0; /* AUTH_NONE */
+ *p++ = 0; /* auth length */
+
+ return p;
+}
+
+/**************************************************************************
+RPC_LOOKUP - Lookup RPC Port numbers
+**************************************************************************/
+static void
+rpc_req (int rpc_prog, int rpc_proc, uint32_t *data, int datalen)
+{
+ struct rpc_t pkt;
+ unsigned long id;
+ uint32_t *p;
+ int pktlen;
+ int sport;
+
+ id = ++rpc_id;
+ pkt.u.call.id = htonl(id);
+ pkt.u.call.type = htonl(MSG_CALL);
+ pkt.u.call.rpcvers = htonl(2); /* use RPC version 2 */
+ pkt.u.call.prog = htonl(rpc_prog);
+ pkt.u.call.vers = htonl(2); /* portmapper is version 2 */
+ pkt.u.call.proc = htonl(rpc_proc);
+ p = (uint32_t *)&(pkt.u.call.data);
+
+ if (datalen)
+ memcpy ((char *)p, (char *)data, datalen*sizeof(uint32_t));
+
+ pktlen = (char *)p + datalen*sizeof(uint32_t) - (char *)&pkt;
+
+ memcpy ((char *)NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE, (char *)&pkt, pktlen);
+
+ if (rpc_prog == PROG_PORTMAP)
+ sport = SUNRPC_PORT;
+ else if (rpc_prog == PROG_MOUNT)
+ sport = NfsSrvMountPort;
+ else
+ sport = NfsSrvNfsPort;
+
+ NetSendUDPPacket (NetServerEther, NfsServerIP, sport, NfsOurPort, pktlen);
+}
+
+/**************************************************************************
+RPC_LOOKUP - Lookup RPC Port numbers
+**************************************************************************/
+static void
+rpc_lookup_req (int prog, int ver)
+{
+ uint32_t data[16];
+
+ data[0] = 0; data[1] = 0; /* auth credential */
+ data[2] = 0; data[3] = 0; /* auth verifier */
+ data[4] = htonl(prog);
+ data[5] = htonl(ver);
+ data[6] = htonl(17); /* IP_UDP */
+ data[7] = 0;
+
+ rpc_req (PROG_PORTMAP, PORTMAP_GETPORT, data, 8);
+}
+
+/**************************************************************************
+NFS_MOUNT - Mount an NFS Filesystem
+**************************************************************************/
+static void
+nfs_mount_req (char *path)
+{
+ uint32_t data[1024];
+ uint32_t *p;
+ int len;
+ int pathlen;
+
+ pathlen = strlen (path);
+
+ p = &(data[0]);
+ p = (uint32_t *)rpc_add_credentials((long *)p);
+
+ *p++ = htonl(pathlen);
+ if (pathlen & 3) *(p + pathlen / 4) = 0;
+ memcpy (p, path, pathlen);
+ p += (pathlen + 3) / 4;
+
+ len = (uint32_t *)p - (uint32_t *)&(data[0]);
+
+ rpc_req (PROG_MOUNT, MOUNT_ADDENTRY, data, len);
+}
+
+/**************************************************************************
+NFS_UMOUNTALL - Unmount all our NFS Filesystems on the Server
+**************************************************************************/
+static void
+nfs_umountall_req (void)
+{
+ uint32_t data[1024];
+ uint32_t *p;
+ int len;
+
+ if ((NfsSrvMountPort == -1) || (!fs_mounted)) {
+ /* Nothing mounted, nothing to umount */
+ return;
+ }
+
+ p = &(data[0]);
+ p = (uint32_t *)rpc_add_credentials ((long *)p);
+
+ len = (uint32_t *)p - (uint32_t *)&(data[0]);
+
+ rpc_req (PROG_MOUNT, MOUNT_UMOUNTALL, data, len);
+}
+
+/***************************************************************************
+ * NFS_READLINK (AH 2003-07-14)
+ * This procedure is called when read of the first block fails -
+ * this probably happens when it's a directory or a symlink
+ * In case of successful readlink(), the dirname is manipulated,
+ * so that inside the nfs() function a recursion can be done.
+ **************************************************************************/
+static void
+nfs_readlink_req (void)
+{
+ uint32_t data[1024];
+ uint32_t *p;
+ int len;
+
+ p = &(data[0]);
+ p = (uint32_t *)rpc_add_credentials ((long *)p);
+
+ memcpy (p, filefh, NFS_FHSIZE);
+ p += (NFS_FHSIZE / 4);
+
+ len = (uint32_t *)p - (uint32_t *)&(data[0]);
+
+ rpc_req (PROG_NFS, NFS_READLINK, data, len);
+}
+
+/**************************************************************************
+NFS_LOOKUP - Lookup Pathname
+**************************************************************************/
+static void
+nfs_lookup_req (char *fname)
+{
+ uint32_t data[1024];
+ uint32_t *p;
+ int len;
+ int fnamelen;
+
+ fnamelen = strlen (fname);
+
+ p = &(data[0]);
+ p = (uint32_t *)rpc_add_credentials ((long *)p);
+
+ memcpy (p, dirfh, NFS_FHSIZE);
+ p += (NFS_FHSIZE / 4);
+ *p++ = htonl(fnamelen);
+ if (fnamelen & 3) *(p + fnamelen / 4) = 0;
+ memcpy (p, fname, fnamelen);
+ p += (fnamelen + 3) / 4;
+
+ len = (uint32_t *)p - (uint32_t *)&(data[0]);
+
+ rpc_req (PROG_NFS, NFS_LOOKUP, data, len);
+}
+
+/**************************************************************************
+NFS_READ - Read File on NFS Server
+**************************************************************************/
+static void
+nfs_read_req (int offset, int readlen)
+{
+ uint32_t data[1024];
+ uint32_t *p;
+ int len;
+
+ p = &(data[0]);
+ p = (uint32_t *)rpc_add_credentials ((long *)p);
+
+ memcpy (p, filefh, NFS_FHSIZE);
+ p += (NFS_FHSIZE / 4);
+ *p++ = htonl(offset);
+ *p++ = htonl(readlen);
+ *p++ = 0;
+
+ len = (uint32_t *)p - (uint32_t *)&(data[0]);
+
+ rpc_req (PROG_NFS, NFS_READ, data, len);
+}
+
+/**************************************************************************
+RPC request dispatcher
+**************************************************************************/
+
+static void
+NfsSend (void)
+{
+#ifdef NFS_DEBUG
+ printf ("%s\n", __FUNCTION__);
+#endif
+
+ switch (NfsState) {
+ case STATE_PRCLOOKUP_PROG_MOUNT_REQ:
+ rpc_lookup_req (PROG_MOUNT, 1);
+ break;
+ case STATE_PRCLOOKUP_PROG_NFS_REQ:
+ rpc_lookup_req (PROG_NFS, 2);
+ break;
+ case STATE_MOUNT_REQ:
+ nfs_mount_req (nfs_path);
+ break;
+ case STATE_UMOUNT_REQ:
+ nfs_umountall_req ();
+ break;
+ case STATE_LOOKUP_REQ:
+ nfs_lookup_req (nfs_filename);
+ break;
+ case STATE_READ_REQ:
+ nfs_read_req (nfs_offset, nfs_len);
+ break;
+ case STATE_READLINK_REQ:
+ nfs_readlink_req ();
+ break;
+ }
+}
+
+/**************************************************************************
+Handlers for the reply from server
+**************************************************************************/
+
+static int
+rpc_lookup_reply (int prog, uchar *pkt, unsigned len)
+{
+ struct rpc_t rpc_pkt;
+
+ memcpy ((unsigned char *)&rpc_pkt, pkt, len);
+
+#ifdef NFS_DEBUG
+ printf ("%s\n", __FUNCTION__);
+#endif
+
+ if (ntohl(rpc_pkt.u.reply.id) != rpc_id)
+ return -1;
+
+ if (rpc_pkt.u.reply.rstatus ||
+ rpc_pkt.u.reply.verifier ||
+ rpc_pkt.u.reply.astatus ||
+ rpc_pkt.u.reply.astatus) {
+ return -1;
+ }
+
+ switch (prog) {
+ case PROG_MOUNT:
+ NfsSrvMountPort = ntohl(rpc_pkt.u.reply.data[0]);
+ break;
+ case PROG_NFS:
+ NfsSrvNfsPort = ntohl(rpc_pkt.u.reply.data[0]);
+ break;
+ }
+
+ return 0;
+}
+
+static int
+nfs_mount_reply (uchar *pkt, unsigned len)
+{
+ struct rpc_t rpc_pkt;
+
+#ifdef NFS_DEBUG
+ printf ("%s\n", __FUNCTION__);
+#endif
+
+ memcpy ((unsigned char *)&rpc_pkt, pkt, len);
+
+ if (ntohl(rpc_pkt.u.reply.id) != rpc_id)
+ return -1;
+
+ if (rpc_pkt.u.reply.rstatus ||
+ rpc_pkt.u.reply.verifier ||
+ rpc_pkt.u.reply.astatus ||
+ rpc_pkt.u.reply.data[0]) {
+ return -1;
+ }
+
+ fs_mounted = 1;
+ memcpy (dirfh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE);
+
+ return 0;
+}
+
+static int
+nfs_umountall_reply (uchar *pkt, unsigned len)
+{
+ struct rpc_t rpc_pkt;
+
+#ifdef NFS_DEBUG
+ printf ("%s\n", __FUNCTION__);
+#endif
+
+ memcpy ((unsigned char *)&rpc_pkt, pkt, len);
+
+ if (ntohl(rpc_pkt.u.reply.id) != rpc_id)
+ return -1;
+
+ if (rpc_pkt.u.reply.rstatus ||
+ rpc_pkt.u.reply.verifier ||
+ rpc_pkt.u.reply.astatus) {
+ return -1;
+ }
+
+ fs_mounted = 0;
+ memset (dirfh, 0, sizeof(dirfh));
+
+ return 0;
+}
+
+static int
+nfs_lookup_reply (uchar *pkt, unsigned len)
+{
+ struct rpc_t rpc_pkt;
+
+#ifdef NFS_DEBUG
+ printf ("%s\n", __FUNCTION__);
+#endif
+
+ memcpy ((unsigned char *)&rpc_pkt, pkt, len);
+
+ if (ntohl(rpc_pkt.u.reply.id) != rpc_id)
+ return -1;
+
+ if (rpc_pkt.u.reply.rstatus ||
+ rpc_pkt.u.reply.verifier ||
+ rpc_pkt.u.reply.astatus ||
+ rpc_pkt.u.reply.data[0]) {
+ return -1;
+ }
+
+ memcpy (filefh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE);
+
+ return 0;
+}
+
+static int
+nfs_readlink_reply (uchar *pkt, unsigned len)
+{
+ struct rpc_t rpc_pkt;
+ int rlen;
+
+#ifdef NFS_DEBUG
+ printf ("%s\n", __FUNCTION__);
+#endif
+
+ memcpy ((unsigned char *)&rpc_pkt, pkt, len);
+
+ if (ntohl(rpc_pkt.u.reply.id) != rpc_id)
+ return -1;
+
+ if (rpc_pkt.u.reply.rstatus ||
+ rpc_pkt.u.reply.verifier ||
+ rpc_pkt.u.reply.astatus ||
+ rpc_pkt.u.reply.data[0]) {
+ return -1;
+ }
+
+ rlen = ntohl (rpc_pkt.u.reply.data[1]); /* new path length */
+
+ if (*((char *)&(rpc_pkt.u.reply.data[2])) != '/') {
+ int pathlen;
+ strcat (nfs_path, "/");
+ pathlen = strlen(nfs_path);
+ memcpy (nfs_path+pathlen, (uchar *)&(rpc_pkt.u.reply.data[2]), rlen);
+ nfs_path[pathlen+rlen+1] = 0;
+ } else {
+ memcpy (nfs_path, (uchar *)&(rpc_pkt.u.reply.data[2]), rlen);
+ nfs_path[rlen] = 0;
+ }
+ return 0;
+}
+
+static int
+nfs_read_reply (uchar *pkt, unsigned len)
+{
+ struct rpc_t rpc_pkt;
+ int rlen;
+
+#ifdef NFS_DEBUG_nop
+ printf ("%s\n", __FUNCTION__);
+#endif
+
+ memcpy ((uchar *)&rpc_pkt, pkt, sizeof(rpc_pkt.u.reply));
+
+ if (ntohl(rpc_pkt.u.reply.id) != rpc_id)
+ return -1;
+
+ if (rpc_pkt.u.reply.rstatus ||
+ rpc_pkt.u.reply.verifier ||
+ rpc_pkt.u.reply.astatus ||
+ rpc_pkt.u.reply.data[0]) {
+ if (rpc_pkt.u.reply.rstatus) {
+ return -9999;
+ }
+ if (rpc_pkt.u.reply.astatus) {
+ return -9999;
+ }
+ return -ntohl(rpc_pkt.u.reply.data[0]);;
+ }
+
+ if ((nfs_offset!=0) && !((nfs_offset) % (NFS_READ_SIZE/2*10*HASHES_PER_LINE))) {
+ puts ("\n\t ");
+ }
+ if (!(nfs_offset % ((NFS_READ_SIZE/2)*10))) {
+ putc ('#');
+ }
+
+ rlen = ntohl(rpc_pkt.u.reply.data[18]);
+ if ( store_block ((uchar *)pkt+sizeof(rpc_pkt.u.reply), nfs_offset, rlen) )
+ return -9999;
+
+ return rlen;
+}
+
+/**************************************************************************
+Interfaces of U-BOOT
+**************************************************************************/
+
+static void
+NfsTimeout (void)
+{
+ puts ("Timeout\n");
+ NetState = NETLOOP_FAIL;
+ return;
+}
+
+static void
+NfsHandler (uchar *pkt, unsigned dest, unsigned src, unsigned len)
+{
+ int rlen;
+
+#ifdef NFS_DEBUG
+ printf ("%s\n", __FUNCTION__);
+#endif
+
+ if (dest != NfsOurPort) return;
+
+ switch (NfsState) {
+ case STATE_PRCLOOKUP_PROG_MOUNT_REQ:
+ rpc_lookup_reply (PROG_MOUNT, pkt, len);
+ NfsState = STATE_PRCLOOKUP_PROG_NFS_REQ;
+ NfsSend ();
+ break;
+
+ case STATE_PRCLOOKUP_PROG_NFS_REQ:
+ rpc_lookup_reply (PROG_NFS, pkt, len);
+ NfsState = STATE_MOUNT_REQ;
+ NfsSend ();
+ break;
+
+ case STATE_MOUNT_REQ:
+ if (nfs_mount_reply(pkt, len)) {
+ puts ("*** ERROR: Cannot mount\n");
+ /* just to be sure... */
+ NfsState = STATE_UMOUNT_REQ;
+ NfsSend ();
+ } else {
+ NfsState = STATE_LOOKUP_REQ;
+ NfsSend ();
+ }
+ break;
+
+ case STATE_UMOUNT_REQ:
+ if (nfs_umountall_reply(pkt, len)) {
+ puts ("*** ERROR: Cannot umount\n");
+ NetState = NETLOOP_FAIL;
+ } else {
+ puts ("\ndone\n");
+ NetState = NfsDownloadState;
+ }
+ break;
+
+ case STATE_LOOKUP_REQ:
+ if (nfs_lookup_reply(pkt, len)) {
+ puts ("*** ERROR: File lookup fail\n");
+ NfsState = STATE_UMOUNT_REQ;
+ NfsSend ();
+ } else {
+ NfsState = STATE_READ_REQ;
+ nfs_offset = 0;
+ nfs_len = NFS_READ_SIZE;
+ NfsSend ();
+ }
+ break;
+
+ case STATE_READLINK_REQ:
+ if (nfs_readlink_reply(pkt, len)) {
+ puts ("*** ERROR: Symlink fail\n");
+ NfsState = STATE_UMOUNT_REQ;
+ NfsSend ();
+ } else {
+#ifdef NFS_DEBUG
+ printf ("Symlink --> %s\n", nfs_path);
+#endif
+ nfs_filename = basename (nfs_path);
+ nfs_path = dirname (nfs_path);
+
+ NfsState = STATE_MOUNT_REQ;
+ NfsSend ();
+ }
+ break;
+
+ case STATE_READ_REQ:
+ rlen = nfs_read_reply (pkt, len);
+ NetSetTimeout (NFS_TIMEOUT * CFG_HZ, NfsTimeout);
+ if (rlen > 0) {
+ nfs_offset += rlen;
+ NfsSend ();
+ }
+ else if ((rlen == -NFSERR_ISDIR)||(rlen == -NFSERR_INVAL)) {
+ /* symbolic link */
+ NfsState = STATE_READLINK_REQ;
+ NfsSend ();
+ } else {
+ if ( ! rlen ) NfsDownloadState = NETLOOP_SUCCESS;
+ NfsState = STATE_UMOUNT_REQ;
+ NfsSend ();
+ }
+ break;
+ }
+}
+
+
+void
+NfsStart (void)
+{
+#ifdef NFS_DEBUG
+ printf ("%s\n", __FUNCTION__);
+#endif
+ NfsDownloadState = NETLOOP_FAIL;
+
+ NfsServerIP = NetServerIP;
+ nfs_path = (char *)nfs_path_buff;
+
+ if (nfs_path == NULL) {
+ NetState = NETLOOP_FAIL;
+ puts ("*** ERROR: Fail allocate memory\n");
+ return;
+ }
+
+ if (BootFile[0] == '\0') {
+ sprintf (default_filename, "/nfsroot/%02lX%02lX%02lX%02lX.img",
+ NetOurIP & 0xFF,
+ (NetOurIP >> 8) & 0xFF,
+ (NetOurIP >> 16) & 0xFF,
+ (NetOurIP >> 24) & 0xFF );
+ strcpy (nfs_path, default_filename);
+
+ printf ("*** Warning: no boot file name; using '%s'\n",
+ nfs_path);
+ } else {
+ char *p=BootFile;
+
+ p = strchr (p, ':');
+
+ if (p != NULL) {
+ NfsServerIP = string_to_ip (BootFile);
+ ++p;
+ strcpy (nfs_path, p);
+ } else {
+ strcpy (nfs_path, BootFile);
+ }
+ }
+
+ nfs_filename = basename (nfs_path);
+ nfs_path = dirname (nfs_path);
+
+#if defined(CONFIG_NET_MULTI)
+ printf ("Using %s device\n", eth_get_name());
+#endif
+
+ puts ("File transfer via NFS from server "); print_IPaddr (NfsServerIP);
+ puts ("; our IP address is "); print_IPaddr (NetOurIP);
+
+ /* Check if we need to send across this subnet */
+ if (NetOurGatewayIP && NetOurSubnetMask) {
+ IPaddr_t OurNet = NetOurIP & NetOurSubnetMask;
+ IPaddr_t ServerNet = NetServerIP & NetOurSubnetMask;
+
+ if (OurNet != ServerNet) {
+ puts ("; sending through gateway ");
+ print_IPaddr (NetOurGatewayIP) ;
+ }
+ }
+ printf ("\nFilename '%s/%s'.", nfs_path, nfs_filename);
+
+ if (NetBootFileSize) {
+ printf (" Size is 0x%x Bytes = ", NetBootFileSize<<9);
+ print_size (NetBootFileSize<<9, "");
+ }
+ printf ("\nLoad address: 0x%lx\n"
+ "Loading: *\b", load_addr);
+
+ NetSetTimeout (NFS_TIMEOUT * CFG_HZ, NfsTimeout);
+ NetSetHandler (NfsHandler);
+
+ NfsTimeoutCount = 0;
+ NfsState = STATE_PRCLOOKUP_PROG_MOUNT_REQ;
+
+ /*NfsOurPort = 4096 + (get_ticks() % 3072);*/
+ /*FIX ME !!!*/
+ NfsOurPort = 1000;
+
+ /* zero out server ether in case the server ip has changed */
+ memset (NetServerEther, 0, 6);
+
+ NfsSend ();
+}
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_NFS */
--- /dev/null
+/*
+ * Copyright 1994, 1995, 2000 Neil Russell.
+ * (See License)
+ * Copyright 2000, 2001 DENX Software Engineering, Wolfgang Denk, wd@denx.de
+ */
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include "tftp.h"
+#include "bootp.h"
+
+#undef ET_DEBUG
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+#define WELL_KNOWN_PORT 69 /* Well known TFTP port # */
+#define TIMEOUT 5 /* Seconds to timeout for a lost pkt */
+#ifndef CONFIG_NET_RETRY_COUNT
+# define TIMEOUT_COUNT 10 /* # of timeouts before giving up */
+#else
+# define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT * 2)
+#endif
+ /* (for checking the image size) */
+#define HASHES_PER_LINE 65 /* Number of "loading" hashes per line */
+
+/*
+ * TFTP operations.
+ */
+#define TFTP_RRQ 1
+#define TFTP_WRQ 2
+#define TFTP_DATA 3
+#define TFTP_ACK 4
+#define TFTP_ERROR 5
+#define TFTP_OACK 6
+
+
+static int TftpServerPort; /* The UDP port at their end */
+static int TftpOurPort; /* The UDP port at our end */
+static int TftpTimeoutCount;
+static ulong TftpBlock; /* packet sequence number */
+static ulong TftpLastBlock; /* last packet sequence number received */
+static ulong TftpBlockWrap; /* count of sequence number wraparounds */
+static ulong TftpBlockWrapOffset; /* memory offset due to wrapping */
+static int TftpState;
+
+#define STATE_RRQ 1
+#define STATE_DATA 2
+#define STATE_TOO_LARGE 3
+#define STATE_BAD_MAGIC 4
+#define STATE_OACK 5
+
+#define TFTP_BLOCK_SIZE 512 /* default TFTP block size */
+#define TFTP_SEQUENCE_SIZE ((ulong)(1<<16)) /* sequence number is 16 bit */
+
+#define DEFAULT_NAME_LEN (8 + 4 + 1)
+static char default_filename[DEFAULT_NAME_LEN];
+static char *tftp_filename;
+
+#ifdef CFG_DIRECT_FLASH_TFTP
+extern flash_info_t flash_info[];
+#endif
+
+static __inline__ void
+store_block (unsigned block, uchar * src, unsigned len)
+{
+ ulong offset = block * TFTP_BLOCK_SIZE + TftpBlockWrapOffset;
+ ulong newsize = offset + len;
+#ifdef CFG_DIRECT_FLASH_TFTP
+ int i, rc = 0;
+
+ for (i=0; i<CFG_MAX_FLASH_BANKS; i++) {
+ /* start address in flash? */
+ if (load_addr + offset >= flash_info[i].start[0]) {
+ rc = 1;
+ break;
+ }
+ }
+
+ if (rc) { /* Flash is destination for this packet */
+ rc = flash_write ((char *)src, (ulong)(load_addr+offset), len);
+ if (rc) {
+ flash_perror (rc);
+ NetState = NETLOOP_FAIL;
+ return;
+ }
+ }
+ else
+#endif /* CFG_DIRECT_FLASH_TFTP */
+ {
+ (void)memcpy((void *)(load_addr + offset), src, len);
+ }
+
+ if (NetBootFileXferSize < newsize)
+ NetBootFileXferSize = newsize;
+}
+
+static void TftpSend (void);
+static void TftpTimeout (void);
+
+/**********************************************************************/
+
+static void
+TftpSend (void)
+{
+ volatile uchar * pkt;
+ volatile uchar * xp;
+ int len = 0;
+ volatile ushort *s;
+
+ /*
+ * We will always be sending some sort of packet, so
+ * cobble together the packet headers now.
+ */
+ pkt = NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE;
+
+ switch (TftpState) {
+
+ case STATE_RRQ:
+ xp = pkt;
+ s = (ushort *)pkt;
+ *s++ = htons(TFTP_RRQ);
+ pkt = (uchar *)s;
+ strcpy ((char *)pkt, tftp_filename);
+ pkt += strlen(tftp_filename) + 1;
+ strcpy ((char *)pkt, "octet");
+ pkt += 5 /*strlen("octet")*/ + 1;
+ strcpy ((char *)pkt, "timeout");
+ pkt += 7 /*strlen("timeout")*/ + 1;
+ sprintf((char *)pkt, "%d", TIMEOUT);
+#ifdef ET_DEBUG
+ printf("send option \"timeout %s\"\n", (char *)pkt);
+#endif
+ pkt += strlen((char *)pkt) + 1;
+ len = pkt - xp;
+ break;
+
+ case STATE_DATA:
+ case STATE_OACK:
+ xp = pkt;
+ s = (ushort *)pkt;
+ *s++ = htons(TFTP_ACK);
+ *s++ = htons(TftpBlock);
+ pkt = (uchar *)s;
+ len = pkt - xp;
+ break;
+
+ case STATE_TOO_LARGE:
+ xp = pkt;
+ s = (ushort *)pkt;
+ *s++ = htons(TFTP_ERROR);
+ *s++ = htons(3);
+ pkt = (uchar *)s;
+ strcpy ((char *)pkt, "File too large");
+ pkt += 14 /*strlen("File too large")*/ + 1;
+ len = pkt - xp;
+ break;
+
+ case STATE_BAD_MAGIC:
+ xp = pkt;
+ s = (ushort *)pkt;
+ *s++ = htons(TFTP_ERROR);
+ *s++ = htons(2);
+ pkt = (uchar *)s;
+ strcpy ((char *)pkt, "File has bad magic");
+ pkt += 18 /*strlen("File has bad magic")*/ + 1;
+ len = pkt - xp;
+ break;
+ }
+
+ NetSendUDPPacket(NetServerEther, NetServerIP, TftpServerPort, TftpOurPort, len);
+}
+
+
+static void
+TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len)
+{
+ ushort proto;
+ ushort *s;
+
+ if (dest != TftpOurPort) {
+ return;
+ }
+ if (TftpState != STATE_RRQ && src != TftpServerPort) {
+ return;
+ }
+
+ if (len < 2) {
+ return;
+ }
+ len -= 2;
+ /* warning: don't use increment (++) in ntohs() macros!! */
+ s = (ushort *)pkt;
+ proto = *s++;
+ pkt = (uchar *)s;
+ switch (ntohs(proto)) {
+
+ case TFTP_RRQ:
+ case TFTP_WRQ:
+ case TFTP_ACK:
+ break;
+ default:
+ break;
+
+ case TFTP_OACK:
+#ifdef ET_DEBUG
+ printf("Got OACK: %s %s\n", pkt, pkt+strlen(pkt)+1);
+#endif
+ TftpState = STATE_OACK;
+ TftpServerPort = src;
+ TftpSend (); /* Send ACK */
+ break;
+ case TFTP_DATA:
+ if (len < 2)
+ return;
+ len -= 2;
+ TftpBlock = ntohs(*(ushort *)pkt);
+
+ /*
+ * RFC1350 specifies that the first data packet will
+ * have sequence number 1. If we receive a sequence
+ * number of 0 this means that there was a wrap
+ * around of the (16 bit) counter.
+ */
+ if (TftpBlock == 0) {
+ TftpBlockWrap++;
+ TftpBlockWrapOffset += TFTP_BLOCK_SIZE * TFTP_SEQUENCE_SIZE;
+ printf ("\n\t %lu MB received\n\t ", TftpBlockWrapOffset>>20);
+ } else {
+ if (((TftpBlock - 1) % 10) == 0) {
+ putc ('#');
+ } else if ((TftpBlock % (10 * HASHES_PER_LINE)) == 0) {
+ puts ("\n\t ");
+ }
+ }
+
+#ifdef ET_DEBUG
+ if (TftpState == STATE_RRQ) {
+ puts ("Server did not acknowledge timeout option!\n");
+ }
+#endif
+
+ if (TftpState == STATE_RRQ || TftpState == STATE_OACK) {
+ /* first block received */
+ TftpState = STATE_DATA;
+ TftpServerPort = src;
+ TftpLastBlock = 0;
+ TftpBlockWrap = 0;
+ TftpBlockWrapOffset = 0;
+
+ if (TftpBlock != 1) { /* Assertion */
+ printf ("\nTFTP error: "
+ "First block is not block 1 (%ld)\n"
+ "Starting again\n\n",
+ TftpBlock);
+ NetStartAgain ();
+ break;
+ }
+ }
+
+ if (TftpBlock == TftpLastBlock) {
+ /*
+ * Same block again; ignore it.
+ */
+ break;
+ }
+
+ TftpLastBlock = TftpBlock;
+ NetSetTimeout (TIMEOUT * CFG_HZ, TftpTimeout);
+
+ store_block (TftpBlock - 1, pkt + 2, len);
+
+ /*
+ * Acknoledge the block just received, which will prompt
+ * the server for the next one.
+ */
+ TftpSend ();
+
+ if (len < TFTP_BLOCK_SIZE) {
+ /*
+ * We received the whole thing. Try to
+ * run it.
+ */
+ puts ("\ndone\n");
+ NetState = NETLOOP_SUCCESS;
+ }
+ break;
+
+ case TFTP_ERROR:
+ printf ("\nTFTP error: '%s' (%d)\n",
+ pkt + 2, ntohs(*(ushort *)pkt));
+ puts ("Starting again\n\n");
+ NetStartAgain ();
+ break;
+ }
+}
+
+
+static void
+TftpTimeout (void)
+{
+ if (++TftpTimeoutCount > TIMEOUT_COUNT) {
+ puts ("\nRetry count exceeded; starting again\n");
+ NetStartAgain ();
+ } else {
+ puts ("T ");
+ NetSetTimeout (TIMEOUT * CFG_HZ, TftpTimeout);
+ TftpSend ();
+ }
+}
+
+
+void
+TftpStart (void)
+{
+#ifdef CONFIG_TFTP_PORT
+ char *ep; /* Environment pointer */
+#endif
+
+ if (BootFile[0] == '\0') {
+ sprintf(default_filename, "%02lX%02lX%02lX%02lX.img",
+ NetOurIP & 0xFF,
+ (NetOurIP >> 8) & 0xFF,
+ (NetOurIP >> 16) & 0xFF,
+ (NetOurIP >> 24) & 0xFF );
+ tftp_filename = default_filename;
+
+ printf ("*** Warning: no boot file name; using '%s'\n",
+ tftp_filename);
+ } else {
+ tftp_filename = BootFile;
+ }
+
+#if defined(CONFIG_NET_MULTI)
+ printf ("Using %s device\n", eth_get_name());
+#endif
+ puts ("TFTP from server "); print_IPaddr (NetServerIP);
+ puts ("; our IP address is "); print_IPaddr (NetOurIP);
+
+ /* Check if we need to send across this subnet */
+ if (NetOurGatewayIP && NetOurSubnetMask) {
+ IPaddr_t OurNet = NetOurIP & NetOurSubnetMask;
+ IPaddr_t ServerNet = NetServerIP & NetOurSubnetMask;
+
+ if (OurNet != ServerNet) {
+ puts ("; sending through gateway ");
+ print_IPaddr (NetOurGatewayIP) ;
+ }
+ }
+ putc ('\n');
+
+ printf ("Filename '%s'.", tftp_filename);
+
+ if (NetBootFileSize) {
+ printf (" Size is 0x%x Bytes = ", NetBootFileSize<<9);
+ print_size (NetBootFileSize<<9, "");
+ }
+
+ putc ('\n');
+
+ printf ("Load address: 0x%lx\n", load_addr);
+
+ puts ("Loading: *\b");
+
+ NetSetTimeout (TIMEOUT * CFG_HZ, TftpTimeout);
+ NetSetHandler (TftpHandler);
+
+ TftpServerPort = WELL_KNOWN_PORT;
+ TftpTimeoutCount = 0;
+ TftpState = STATE_RRQ;
+ /* Use a pseudo-random port unless a specific port is set */
+ TftpOurPort = 1024 + (get_timer(0) % 3072);
+#ifdef CONFIG_TFTP_PORT
+ if ((ep = getenv("tftpdstp")) != NULL) {
+ TftpServerPort = simple_strtol(ep, NULL, 10);
+ }
+ if ((ep = getenv("tftpsrcp")) != NULL) {
+ TftpOurPort= simple_strtol(ep, NULL, 10);
+ }
+#endif
+ TftpBlock = 0;
+
+ /* zero out server ether in case the server ip has changed */
+ memset(NetServerEther, 0, 6);
+
+ TftpSend ();
+}
+
+#endif /* CFG_CMD_NET */
--- /dev/null
+/*
+ * This file is derived from crc32.c from the zlib-1.1.3 distribution
+ * by Jean-loup Gailly and Mark Adler.
+ */
+
+/* crc32.c -- compute the CRC-32 of a data stream
+ * Copyright (C) 1995-1998 Mark Adler
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+#ifndef USE_HOSTCC /* Shut down "ANSI does not permit..." warnings */
+#include <common.h> /* to get command definitions like CFG_CMD_JFFS2 */
+#endif
+
+#include "zlib.h"
+
+#define local static
+#define ZEXPORT /* empty */
+unsigned long crc32 (unsigned long, const unsigned char *, unsigned int);
+
+#ifdef DYNAMIC_CRC_TABLE
+
+local int crc_table_empty = 1;
+local uLongf crc_table[256];
+local void make_crc_table OF((void));
+
+/*
+ Generate a table for a byte-wise 32-bit CRC calculation on the polynomial:
+ x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1.
+
+ Polynomials over GF(2) are represented in binary, one bit per coefficient,
+ with the lowest powers in the most significant bit. Then adding polynomials
+ is just exclusive-or, and multiplying a polynomial by x is a right shift by
+ one. If we call the above polynomial p, and represent a byte as the
+ polynomial q, also with the lowest power in the most significant bit (so the
+ byte 0xb1 is the polynomial x^7+x^3+x+1), then the CRC is (q*x^32) mod p,
+ where a mod b means the remainder after dividing a by b.
+
+ This calculation is done using the shift-register method of multiplying and
+ taking the remainder. The register is initialized to zero, and for each
+ incoming bit, x^32 is added mod p to the register if the bit is a one (where
+ x^32 mod p is p+x^32 = x^26+...+1), and the register is multiplied mod p by
+ x (which is shifting right by one and adding x^32 mod p if the bit shifted
+ out is a one). We start with the highest power (least significant bit) of
+ q and repeat for all eight bits of q.
+
+ The table is simply the CRC of all possible eight bit values. This is all
+ the information needed to generate CRC's on data a byte at a time for all
+ combinations of CRC register values and incoming bytes.
+*/
+local void make_crc_table()
+{
+ uLong c;
+ int n, k;
+ uLong poly; /* polynomial exclusive-or pattern */
+ /* terms of polynomial defining this crc (except x^32): */
+ static const Byte p[] = {0,1,2,4,5,7,8,10,11,12,16,22,23,26};
+
+ /* make exclusive-or pattern from polynomial (0xedb88320L) */
+ poly = 0L;
+ for (n = 0; n < sizeof(p)/sizeof(Byte); n++)
+ poly |= 1L << (31 - p[n]);
+
+ for (n = 0; n < 256; n++)
+ {
+ c = (uLong)n;
+ for (k = 0; k < 8; k++)
+ c = c & 1 ? poly ^ (c >> 1) : c >> 1;
+ crc_table[n] = c;
+ }
+ crc_table_empty = 0;
+}
+#else
+/* ========================================================================
+ * Table of CRC-32's of all single-byte values (made by make_crc_table)
+ */
+local const uLongf crc_table[256] = {
+ 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,
+ 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,
+ 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,
+ 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL,
+ 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L,
+ 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L,
+ 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L,
+ 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,
+ 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L,
+ 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL,
+ 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L,
+ 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L,
+ 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L,
+ 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL,
+ 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL,
+ 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,
+ 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL,
+ 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L,
+ 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L,
+ 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L,
+ 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL,
+ 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L,
+ 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L,
+ 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,
+ 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L,
+ 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L,
+ 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L,
+ 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L,
+ 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L,
+ 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL,
+ 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL,
+ 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,
+ 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L,
+ 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL,
+ 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL,
+ 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L,
+ 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL,
+ 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L,
+ 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL,
+ 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,
+ 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL,
+ 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L,
+ 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L,
+ 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL,
+ 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L,
+ 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L,
+ 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L,
+ 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,
+ 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L,
+ 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L,
+ 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL,
+ 0x2d02ef8dL
+};
+#endif
+
+#if 0
+/* =========================================================================
+ * This function can be used by asm versions of crc32()
+ */
+const uLongf * ZEXPORT get_crc_table()
+{
+#ifdef DYNAMIC_CRC_TABLE
+ if (crc_table_empty) make_crc_table();
+#endif
+ return (const uLongf *)crc_table;
+}
+#endif
+
+/* ========================================================================= */
+#define DO1(buf) crc = crc_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8);
+#define DO2(buf) DO1(buf); DO1(buf);
+#define DO4(buf) DO2(buf); DO2(buf);
+#define DO8(buf) DO4(buf); DO4(buf);
+
+/* ========================================================================= */
+uLong ZEXPORT crc32(crc, buf, len)
+ uLong crc;
+ const Bytef *buf;
+ uInt len;
+{
+#ifdef DYNAMIC_CRC_TABLE
+ if (crc_table_empty)
+ make_crc_table();
+#endif
+ crc = crc ^ 0xffffffffL;
+ while (len >= 8)
+ {
+ DO8(buf);
+ len -= 8;
+ }
+ if (len) do {
+ DO1(buf);
+ } while (--len);
+ return crc ^ 0xffffffffL;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) || \
+ ((CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY))
+
+/* No ones complement version. JFFS2 (and other things ?)
+ * don't use ones compliment in their CRC calculations.
+ */
+uLong ZEXPORT crc32_no_comp(uLong crc, const Bytef *buf, uInt len)
+{
+#ifdef DYNAMIC_CRC_TABLE
+ if (crc_table_empty)
+ make_crc_table();
+#endif
+ while (len >= 8)
+ {
+ DO8(buf);
+ len -= 8;
+ }
+ if (len) do {
+ DO1(buf);
+ } while (--len);
+
+ return crc;
+}
+
+#endif /* CFG_CMD_JFFS2 */
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__ /* Dirty trick to get only #defines */
+#endif
+#define __ASM_STUB_PROCESSOR_H__ /* don't include asm/processor. */
+#include <config.h>
+#undef __ASSEMBLY__
+#include <environment.h>
+
+/*
+ * Handle HOSTS that have prepended
+ * crap on symbol names, not TARGETS.
+ */
+#if defined(__APPLE__)
+/* Leading underscore on symbols */
+# define SYM_CHAR "_"
+#else /* No leading character on symbols */
+# define SYM_CHAR
+#endif
+
+/*
+ * Generate embedded environment table
+ * inside U-Boot image, if needed.
+ */
+#if defined(ENV_IS_EMBEDDED)
+/*
+ * Only put the environment in it's own section when we are building
+ * U-Boot proper. The host based program "tools/envcrc" does not need
+ * a seperate section. Note that ENV_CRC is only defined when building
+ * U-Boot itself.
+ */
+#if (defined(CONFIG_CMI) || \
+ defined(CONFIG_FADS) || \
+ defined(CONFIG_HYMOD) || \
+ defined(CONFIG_ICU862) || \
+ defined(CONFIG_R360MPI) || \
+ defined(CONFIG_TQM8xxL) || \
+ defined(CONFIG_RRVISION) || \
+ defined(CONFIG_TRAB) || \
+ defined(CONFIG_PPCHAMELEONEVB) || \
+ defined(CONFIG_M5271EVB) || \
+ defined(CONFIG_NAND_U_BOOT)) && \
+ defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */
+/* XXX - This only works with GNU C */
+# define __PPCENV__ __attribute__ ((section(".ppcenv")))
+# define __PPCTEXT__ __attribute__ ((section(".text")))
+
+#elif defined(USE_HOSTCC) /* Native for 'tools/envcrc' */
+# define __PPCENV__ /*XXX DO_NOT_DEL_THIS_COMMENT*/
+# define __PPCTEXT__ /*XXX DO_NOT_DEL_THIS_COMMENT*/
+
+#else /* Environment is embedded in U-Boot's .text section */
+/* XXX - This only works with GNU C */
+# define __PPCENV__ __attribute__ ((section(".text")))
+# define __PPCTEXT__ __attribute__ ((section(".text")))
+#endif
+
+/*
+ * Macros to generate global absolutes.
+ */
+#define GEN_SYMNAME(str) SYM_CHAR #str
+#define GEN_VALUE(str) #str
+#define GEN_ABS(name, value) \
+ asm (".globl " GEN_SYMNAME(name)); \
+ asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
+
+/*
+ * Macros to transform values
+ * into environment strings.
+ */
+#define XMK_STR(x) #x
+#define MK_STR(x) XMK_STR(x)
+
+/*
+ * Check to see if we are building with a
+ * computed CRC. Otherwise define it as ~0.
+ */
+#if !defined(ENV_CRC)
+# define ENV_CRC ~0
+#endif
+
+env_t environment __PPCENV__ = {
+ ENV_CRC, /* CRC Sum */
+#ifdef CFG_REDUNDAND_ENVIRONMENT
+ 1, /* Flags: valid */
+#endif
+ {
+#if defined(CONFIG_BOOTARGS)
+ "bootargs=" CONFIG_BOOTARGS "\0"
+#endif
+#if defined(CONFIG_BOOTCOMMAND)
+ "bootcmd=" CONFIG_BOOTCOMMAND "\0"
+#endif
+#if defined(CONFIG_RAMBOOTCOMMAND)
+ "ramboot=" CONFIG_RAMBOOTCOMMAND "\0"
+#endif
+#if defined(CONFIG_NFSBOOTCOMMAND)
+ "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0"
+#endif
+#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
+ "bootdelay=" MK_STR(CONFIG_BOOTDELAY) "\0"
+#endif
+#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
+ "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"
+#endif
+#ifdef CONFIG_LOADS_ECHO
+ "loads_echo=" MK_STR(CONFIG_LOADS_ECHO) "\0"
+#endif
+#ifdef CONFIG_ETHADDR
+ "ethaddr=" MK_STR(CONFIG_ETHADDR) "\0"
+#endif
+#ifdef CONFIG_ETH1ADDR
+ "eth1addr=" MK_STR(CONFIG_ETH1ADDR) "\0"
+#endif
+#ifdef CONFIG_ETH2ADDR
+ "eth2addr=" MK_STR(CONFIG_ETH2ADDR) "\0"
+#endif
+#ifdef CONFIG_ETH3ADDR
+ "eth3addr=" MK_STR(CONFIG_ETH3ADDR) "\0"
+#endif
+#ifdef CONFIG_ETHPRIME
+ "ethprime=" CONFIG_ETHPRIME "\0"
+#endif
+#ifdef CONFIG_IPADDR
+ "ipaddr=" MK_STR(CONFIG_IPADDR) "\0"
+#endif
+#ifdef CONFIG_SERVERIP
+ "serverip=" MK_STR(CONFIG_SERVERIP) "\0"
+#endif
+#ifdef CFG_AUTOLOAD
+ "autoload=" CFG_AUTOLOAD "\0"
+#endif
+#ifdef CONFIG_ROOTPATH
+ "rootpath=" MK_STR(CONFIG_ROOTPATH) "\0"
+#endif
+#ifdef CONFIG_GATEWAYIP
+ "gatewayip=" MK_STR(CONFIG_GATEWAYIP) "\0"
+#endif
+#ifdef CONFIG_NETMASK
+ "netmask=" MK_STR(CONFIG_NETMASK) "\0"
+#endif
+#ifdef CONFIG_HOSTNAME
+ "hostname=" MK_STR(CONFIG_HOSTNAME) "\0"
+#endif
+#ifdef CONFIG_BOOTFILE
+ "bootfile=" MK_STR(CONFIG_BOOTFILE) "\0"
+#endif
+#ifdef CONFIG_LOADADDR
+ "loadaddr=" MK_STR(CONFIG_LOADADDR) "\0"
+#endif
+#ifdef CONFIG_PREBOOT
+ "preboot=" CONFIG_PREBOOT "\0"
+#endif
+#ifdef CONFIG_CLOCKS_IN_MHZ
+ "clocks_in_mhz=" "1" "\0"
+#endif
+#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
+ "pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY) "\0"
+#endif
+#ifdef CONFIG_EXTRA_ENV_SETTINGS
+ CONFIG_EXTRA_ENV_SETTINGS
+#endif
+ "\0" /* Term. env_t.data with 2 NULs */
+ }
+};
+#ifdef CFG_ENV_ADDR_REDUND
+env_t redundand_environment __PPCENV__ = {
+ 0, /* CRC Sum: invalid */
+ 0, /* Flags: invalid */
+ {
+ "\0"
+ }
+};
+#endif /* CFG_ENV_ADDR_REDUND */
+
+/*
+ * These will end up in the .text section
+ * if the environment strings are embedded
+ * in the image. When this is used for
+ * tools/envcrc, they are placed in the
+ * .data/.sdata section.
+ *
+ */
+unsigned long env_size __PPCTEXT__ = sizeof(env_t);
+
+/*
+ * Add in absolutes.
+ */
+GEN_ABS(env_offset, CFG_ENV_OFFSET);
+
+#endif /* ENV_IS_EMBEDDED */
--- /dev/null
+diff -urN u-boot-1.1.5.a/Makefile u-boot/Makefile
+--- u-boot-1.1.5.a/Makefile 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/Makefile 2008-05-11 14:14:55.000000000 +0100
+@@ -24,7 +24,7 @@
+ VERSION = 1
+ PATCHLEVEL = 1
+ SUBLEVEL = 5
+-EXTRAVERSION =
++EXTRAVERSION = -IFX-LXDB
+ U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+ VERSION_FILE = $(obj)include/version_autogenerated.h
+
+@@ -44,6 +44,25 @@
+ # Deal with colliding definitions from tcsh etc.
+ VENDOR=
+
++# Default algorithm form compressing u-boot.bin
++ifndef COMPRESS
++COMPRESS=none
++COMPRESS_FILE=$(obj)u-boot.img
++else
++ifeq ($(COMPRESS),lzma)
++COMPRESS_FILE=$(obj)u-boot.limg
++endif
++ifeq ($(COMPRESS),bz2)
++COMPRESS_FILE=$(obj)u-boot.bzimg
++endif
++ifeq ($(COMPRESS),gzip)
++COMPRESS_FILE=$(obj)u-boot.zimg
++endif
++ifeq ($(COMPRESS),none)
++COMPRESS_FILE=$(obj)u-boot.img
++endif
++endif
++
+ #########################################################################
+ #
+ # U-boot build supports producing a object files to the separate external
+@@ -155,6 +174,11 @@
+ endif
+ endif
+
++
++
++
++
++
+ export CROSS_COMPILE
+
+ # load other configuration
+@@ -163,7 +187,9 @@
+ #########################################################################
+ # U-Boot objects....order is important (i.e. start must be first)
+
+-OBJS = cpu/$(CPU)/start.o
++OBJS = cpu/$(CPU)/$(BOARDDIR)/start.o
++OBJS_BOOTSTRAP = cpu/$(CPU)/$(BOARDDIR)/start_bootstrap.o
++
+ ifeq ($(CPU),i386)
+ OBJS += cpu/$(CPU)/start16.o
+ OBJS += cpu/$(CPU)/reset.o
+@@ -186,11 +212,11 @@
+
+ LIBS = lib_generic/libgeneric.a
+ LIBS += board/$(BOARDDIR)/lib$(BOARD).a
+-LIBS += cpu/$(CPU)/lib$(CPU).a
++LIBS += cpu/$(CPU)/$(BOARDDIR)/lib$(CPU).a
+ ifdef SOC
+ LIBS += cpu/$(CPU)/$(SOC)/lib$(SOC).a
+ endif
+-LIBS += lib_$(ARCH)/lib$(ARCH).a
++LIBS += lib_$(ARCH)/$(BOARDIR)/lib$(ARCH).a
+ LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
+ fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a
+ LIBS += net/libnet.a
+@@ -198,27 +224,54 @@
+ LIBS += rtc/librtc.a
+ LIBS += dtt/libdtt.a
+ LIBS += drivers/libdrivers.a
+-LIBS += drivers/nand/libnand.a
+-LIBS += drivers/nand_legacy/libnand_legacy.a
++#LIBS += drivers/nand_$(BOARDDIR)/libnand.a
++#LIBS += drivers/nand_legacy/libnand_legacy.a
+ LIBS += drivers/sk98lin/libsk98lin.a
+ LIBS += post/libpost.a post/cpu/libcpu.a
+ LIBS += common/libcommon.a
+ LIBS += $(BOARDLIBS)
+
+ LIBS := $(addprefix $(obj),$(LIBS))
++
++
++LIBS_BOOTSTRAP = lib_bootstrap/libbootstrap.a
++LIBS_BOOTSTRAP+= board/$(BOARDDIR)/lib$(BOARD).a
++#LIBS_BOOTSTRAP+= board/ifx/libifx.a
++LIBS_BOOTSTRAP+= cpu/$(CPU)/$(BOARDDIR)/lib$(CPU).a
++
++#HEAD_OBJS = cpu/$(CPU)/$(BOARDDIR)/start.o lib_$(ARCH)/board.o
++
++#HEAD_LIBS = board/$(BOARDDIR)/lib$(BOARD).a
++#HEAD_LIBS += cpu/$(CPU)/$(BOARDDIR)/lib$(CPU).a
++#HEAD_LIBS += lib_$(ARCH)/lib$(ARCH).a
++#HEAD_LIBS += lib_generic/libgeneric.a
++#HEAD_LIBS += common/console.o
++#HEAD_LIBS += common/devices.o
++#HEAD_LIBS += common/cmd_bootm.o
++
++#.PHONY : $(LIBS) $(HEAD_LIBS)
+ .PHONY : $(LIBS)
++.PHONY : $(LIBS_BOOTSTRAP)
+
+ # Add GCC lib
+ PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+
+ # The "tools" are needed early, so put this first
+ # Don't include stuff already done in $(LIBS)
++ #examples
+ SUBDIRS = tools \
+- examples \
+ post \
+ post/cpu
+ .PHONY : $(SUBDIRS)
+
++# HEAD_SUBDIRS = tools
++#HEAD_SUBDIRS = lib_generic \
++# cpu/$(CPU) \
++# board/$(BOARDDIR) \
++# common \
++# lib_$(ARCH)
++#.PHONY : $(HEAD_SUBDIRS)
++
+ ifeq ($(CONFIG_NAND_U_BOOT),y)
+ NAND_SPL = nand_spl
+ U_BOOT_NAND = $(obj)u-boot-nand.bin
+@@ -227,13 +280,76 @@
+ __OBJS := $(subst $(obj),,$(OBJS))
+ __LIBS := $(subst $(obj),,$(LIBS))
+
++#__HEAD_OBJS := $(subst $(obj),,$(HEAD_OBJS))
++#__HEAD_LIBS := $(subst $(obj),,$(HEAD_LIBS))
++
+ #########################################################################
+ #########################################################################
+
+ ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
++#IFX_ALL = $(obj)u-boot.ifx $(obj)head.srec $(obj)head.bin $(obj)head $(obj)head.map $(COMPRESS_FILE) $(obj)u-boot.srec
++IFX_ALL = $(obj)u-boot.srec $(obj)u-boot.ifx $(obj)u-boot.lzimg $(obj)System.map $(obj)bootstrap.bin
+
+ all: $(ALL)
+
++ifx_all: $(IFX_ALL)
++
++
++$(obj)u-boot.ifx: $(obj)System.map $(obj)bootstrap.bin $(obj)u-boot.lzimg
++ @cat $(obj)bootstrap.bin > $(obj)u-boot.ifx
++ @cat $(obj)u-boot.lzimg >> $(obj)u-boot.ifx
++
++$(obj)u-boot.lzimg: $(obj)u-boot.bin System.map
++# @lzma -f -z --best -v $(obj)u-boot.bin
++ @lzma e $(obj)u-boot.bin $(obj)u-boot.bin.lzma
++ @./tools/mkimage -A mips -T firmware -C lzma \
++ -a 0x$(shell grep "T _start" $(TOPDIR)/System.map | awk '{ printf "%s", $$1 }') \
++ -e 0x$(shell grep "T _start" $(TOPDIR)/System.map | awk '{ printf "%s", $$1 }') \
++ -n 'u-boot image' -d $(obj)u-boot.bin.lzma $@
++
++$(obj)ld_uboot.img: $(obj)u-boot.ifx $(obj)u-boot.lzimg $(obj)System.map $(obj)bootstrap.bin
++ @ cp -f $(obj)u-boot.ifx $(obj)u-boot.bin
++ @ ./mkbootimg.incaip2 $(obj)ld_uboot.img < ld_uboot.conf
++
++
++
++
++$(obj)u-boot.zimg: $(obj)u-boot.bin $(obj)System.map
++ gzip $(obj)u-boot.bin
++ ./tools/mkimage -A $(ARCH) -T firmware -C gzip \
++ -a 0x$(shell grep "T _start" $(TOPDIR)/System.map | awk '{ printf "%s", $$1 }') \
++ -e 0x$(shell grep "T _start" $(TOPDIR)/System.map | awk '{ printf "%s", $$1 }') \
++ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
++ sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
++ -d u-boot.gz $@
++
++$(obj)u-boot.bzimg: $(obj)u-boot.bin $(obj)System.map
++ bzip $(obj)u-boot.bin
++ ./tools/mkimage -A $(ARCH) -T firmware -C bzip2 \
++ -a 0x$(shell grep "T _start" $(TOPDIR)/System.map | awk '{ printf "%s", $$1 }') \
++ -e 0x$(shell grep "T _start" $(TOPDIR)/System.map | awk '{ printf "%s", $$1 }') \
++ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
++ sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
++ -d u-boot.bz2 $@
++
++$(obj)u-boot.limg: $(obj)u-boot.bin $(obj)System.map
++# @lzma -f -z --best -v $(obj)u-boot.bin
++ @lzma e $(obj)u-boot.bin $(obj)u-boot.bin.lzma
++ ./tools/mkimage -A $(ARCH) -T firmware -C lzma \
++ -a 0x$(shell grep "T _start" $(TOPDIR)/System.map | awk '{ printf "%s", $$1 }') \
++ -e 0x$(shell grep "T _start" $(TOPDIR)/System.map | awk '{ printf "%s", $$1 }') \
++ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
++ sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
++ -d u-boot.bin.lzma $@
++
++$(obj)u-boot.img: $(obj)u-boot.bin $(obj)System.map
++ ./tools/mkimage -A $(ARCH) -T firmware -C none \
++ -a 0x$(shell grep "T _start" $(TOPDIR)/System.map | awk '{ printf "%s", $$1 }') \
++ -e 0x$(shell grep "T _start" $(TOPDIR)/System.map | awk '{ printf "%s", $$1 }') \
++ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
++ sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
++ -d u-boot.bin $@
++
+ $(obj)u-boot.hex: $(obj)u-boot
+ $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
+
+@@ -243,28 +359,36 @@
+ $(obj)u-boot.bin: $(obj)u-boot
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+-$(obj)u-boot.img: $(obj)u-boot.bin
+- ./tools/mkimage -A $(ARCH) -T firmware -C none \
+- -a $(TEXT_BASE) -e 0 \
+- -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
+- sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
+- -d $< $@
+-
+ $(obj)u-boot.dis: $(obj)u-boot
+ $(OBJDUMP) -d $< > $@
+
+-$(obj)u-boot: depend version $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
++$(obj)u-boot: depend version $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
+ UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+ --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
+ -Map u-boot.map -o u-boot
+
++
++
++$(obj)bootstrap.bin: $(obj)bootstrap
++ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
++
++$(obj)bootstrap : depend version $(SUBDIRS) $(OBJS_BOOTSTRAP) $(LIBS_BOOTSTRAP) $(LDSCRIPT_BOOTSTRAP)
++ UNDEF_SYM=`$(OBJDUMP) -x $(LIBS_BOOTSTRAP) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
++ $(LD) $(LDFLAGS_BOOTSTRAP) $$UNDEF_SYM $(OBJS_BOOTSTRAP) \
++ --start-group $(LIBS_BOOTSTRAP) --end-group $(PLATFORM_LIBS) \
++ -Map bootstrap.map -o bootstrap
++
+ $(OBJS):
+- $(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@))
++ $(MAKE) -C cpu/$(CPU)/$(BOARDDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@))
+
+ $(LIBS):
+ $(MAKE) -C $(dir $(subst $(obj),,$@))
+
++
++$(LIBS_BOOTSTRAP):
++ $(MAKE) -C `dirname $@`
++
+ $(SUBDIRS):
+ $(MAKE) -C $@ all
+
+@@ -295,14 +419,14 @@
+
+ tags ctags:
+ ctags -w -o $(OBJTREE)/ctags `find $(SUBDIRS) include \
+- lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \
++ lib_generic board/$(BOARDDIR) cpu/$(CPU)/$(BOARDDIR) lib_$(ARCH) \
+ fs/cramfs fs/fat fs/fdos fs/jffs2 \
+ net disk rtc dtt drivers drivers/sk98lin common \
+ \( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`
+
+ etags:
+ etags -a -o $(OBJTREE)/etags `find $(SUBDIRS) include \
+- lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \
++ lib_generic board/$(BOARDDIR) cpu/$(CPU)/$(BOARDDIR) lib_$(ARCH) \
+ fs/cramfs fs/fat fs/fdos fs/jffs2 \
+ net disk rtc dtt drivers drivers/sk98lin common \
+ \( -name CVS -prune \) -o \( -name '*.[ch]' -print \)`
+@@ -2032,7 +2156,20 @@
+ # MIPS
+ #========================================================================
+ #########################################################################
+-## MIPS32 4Kc
++## Infineon MIPS generic u-boot config
++#########################################################################
++danube_config: unconfig
++ @$(MKCONFIG) $(@:_config=) mips mips danube
++
++amazon_config: unconfig
++ @$(MKCONFIG) $(@:_config=) mips mips amazon
++
++
++incaip2_config: unconfig
++ @$(MKCONFIG) $(@:_config=) mips mips incaip2
++
++#########################################################################
++## MIPS32 4kc
+ #########################################################################
+
+ xtract_incaip = $(subst _100MHz,,$(subst _133MHz,,$(subst _150MHz,,$(subst _config,,$1))))
+@@ -2246,6 +2383,8 @@
+ rm -f $(obj)include/bmp_logo.h
+ find nand_spl -lname "*" -print | xargs rm -f
+ rm -f nand_spl/u-boot-spl nand_spl/u-boot-spl.map
++ rm -f lib_bootstrap/*.o
++ rm -f lib_bootstrap/*.a
+
+ clobber: clean
+ find $(OBJTREE) -type f \( -name .depend \
+@@ -2254,7 +2393,7 @@
+ | xargs -0 rm -f
+ rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS $(obj)include/version_autogenerated.h
+ rm -fr $(obj)*.*~
+- rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
++ rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) $(IFX_ALL)
+ rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c
+ rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
+ rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
+Binary files u-boot-1.1.5.a/bootstrap and u-boot/bootstrap differ
+diff -urN u-boot-1.1.5.a/build_danube.sh u-boot/build_danube.sh
+--- u-boot-1.1.5.a/build_danube.sh 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/build_danube.sh 2008-05-11 14:02:24.000000000 +0100
+@@ -0,0 +1,28 @@
++#!/bin/sh
++IFX_CONFIG_FLASH_SIZE=8
++IFX_CONFIG_MEMORY_SIZE=30
++CONFIG_RAM_TEXT_BASE=0xA0400000
++
++#prepare_headers()
++#{
++# cp -f include/flash_$1.h \
++# include/flash.h
++# cp -f include/net_$1.h \
++# include/net.h
++# cp -f include/asm-mips/cacheops_$1.h \
++# include/asm-mips/cacheops.h
++# cp -f include/asm-mips/mipsregs_$1.h \
++# include/asm-mips/mipsregs.h
++#}
++#prepare_headers "danube"
++UBOOT_COMPRESS=lzma
++UBOOT_CFLAGS="-DCONFIG_IFX_MIPS -DCONFIG_LZMA -DIFX_CONFIG_MEMORY_SIZE=${IFX_CONFIG_MEMORY_SIZE} -DIFX_CONFIG_FLASH_SIZE=${IFX_CONFIG_FLASH_SIZE}"
++
++rm -f .config_ok
++
++make CROSS_COMPILE="mips-linux-uclibc-" CROSS_COMPILE_UCLIBC=1 COMPRESS=${UBOOT_COMPRESS} PLATFORM_CPU=mips32r2 IFX_CFLAGS="${UBOOT_CFLAGS}" UBOOT_RAM_TEXT_BASE=${CONFIG_RAM_TEXT_BASE} CPU_TYPE=${IFX_CONFIG_CPU} danube_config distclean
++
++CROSS_COMPILE="mips-linux-uclibc-" CROSS_COMPILE_UCLIBC=1 COMPRESS=${UBOOT_COMPRESS} PLATFORM_CPU=mips32r2 IFX_CFLAGS="${UBOOT_CFLAGS}" make UBOOT_RAM_TEXT_BASE=${CONFIG_RAM_TEXT_BASE} CPU_TYPE=${IFX_CONFIG_CPU} danube_config
++ echo -n > .config_ok
++
++CROSS_COMPILE="mips-linux-uclibc-" CROSS_COMPILE_UCLIBC=1 COMPRESS=${UBOOT_COMPRESS} PLATFORM_CPU=mips32r2 IFX_CFLAGS="${UBOOT_CFLAGS}" make UBOOT_RAM_TEXT_BASE=${CONFIG_RAM_TEXT_BASE} BOOTSTRAP_PRINTF_STATUS=$2 CPU_TYPE=${IFX_CONFIG_CPU} ifx_all
+diff -urN u-boot-1.1.5.a/common/Makefile u-boot/common/Makefile
+--- u-boot-1.1.5.a/common/Makefile 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/common/Makefile 2008-05-11 14:53:59.000000000 +0100
+@@ -46,7 +46,7 @@
+ env_nand.o env_dataflash.o env_flash.o env_eeprom.o \
+ env_nvram.o env_nowhere.o \
+ exports.o \
+- flash.o fpga.o ft_build.o \
++ flash_$(BOARD).o fpga.o ft_build.o \
+ hush.o kgdb.o lcd.o lists.o lynxkdi.o \
+ memsize.o miiphybb.o miiphyutil.o \
+ s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \
+@@ -60,7 +60,7 @@
+
+ all: $(LIB) $(AOBJS)
+
+-$(LIB): $(obj).depend $(OBJS)
++$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+ $(obj)environment.o: $(src)environment.c $(obj)../tools/envcrc
+diff -urN u-boot-1.1.5.a/common/cmd_bootm.c u-boot/common/cmd_bootm.c
+--- u-boot-1.1.5.a/common/cmd_bootm.c 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/common/cmd_bootm.c 2007-03-09 09:47:46.000000000 +0000
+@@ -31,6 +31,7 @@
+ #include <malloc.h>
+ #include <zlib.h>
+ #include <bzlib.h>
++#include <LzmaWrapper.h>
+ #include <environment.h>
+ #include <asm/byteorder.h>
+
+@@ -79,6 +80,8 @@
+ # define CHUNKSZ (64 * 1024)
+ #endif
+
++#ifndef CFG_HEAD_CODE
++
+ int gunzip (void *, int, unsigned char *, unsigned long *);
+
+ static void *zalloc(void *, unsigned, unsigned);
+@@ -341,6 +344,7 @@
+ #endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */
+ }
+ break;
++#ifndef CONFIG_REMOVE_GZIP
+ case IH_COMP_GZIP:
+ printf (" Uncompressing %s ... ", name);
+ if (gunzip ((void *)ntohl(hdr->ih_load), unc_len,
+@@ -350,6 +354,7 @@
+ do_reset (cmdtp, flag, argc, argv);
+ }
+ break;
++#endif /* CONFIG_REMOVE_GZIP */
+ #ifdef CONFIG_BZIP2
+ case IH_COMP_BZIP2:
+ printf (" Uncompressing %s ... ", name);
+@@ -369,6 +374,18 @@
+ }
+ break;
+ #endif /* CONFIG_BZIP2 */
++#ifdef CONFIG_LZMA
++ case IH_COMP_LZMA:
++ printf (" Uncompressing %s ... ", name);
++ i = lzma_inflate ((unsigned char *)data, len, (unsigned char*)ntohl(hdr->ih_load), &unc_len);
++ if (i != LZMA_RESULT_OK) {
++ printf ("LZMA ERROR %d - must RESET board to recover\n", i);
++ SHOW_BOOT_PROGRESS (-6);
++ udelay(100000);
++ do_reset (cmdtp, flag, argc, argv);
++ }
++ break;
++#endif /* CONFIG_LZMA */
+ default:
+ if (iflag)
+ enable_interrupts();
+@@ -1176,6 +1193,8 @@
+ );
+ #endif /* CFG_CMD_IMLS */
+
++#endif /* ! CFG_HEAD_CODE */
++
+ void
+ print_image_hdr (image_header_t *hdr)
+ {
+@@ -1270,12 +1289,15 @@
+ case IH_COMP_NONE: comp = "uncompressed"; break;
+ case IH_COMP_GZIP: comp = "gzip compressed"; break;
+ case IH_COMP_BZIP2: comp = "bzip2 compressed"; break;
++ case IH_COMP_LZMA: comp = "lzma compressed"; break;
+ default: comp = "unknown compression"; break;
+ }
+
+ printf ("%s %s %s (%s)", arch, os, type, comp);
+ }
+
++#ifndef CFG_HEAD_CODE
++
+ #define ZALLOC_ALIGNMENT 16
+
+ static void *zalloc(void *x, unsigned items, unsigned size)
+@@ -1427,3 +1449,5 @@
+ }
+
+ #endif /* CONFIG_LYNXKDI */
++
++#endif /* ! CFG_HEAD_CODE */
+diff -urN u-boot-1.1.5.a/common/cmd_flash.c u-boot/common/cmd_flash.c
+--- u-boot-1.1.5.a/common/cmd_flash.c 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/common/cmd_flash.c 2007-03-09 09:47:46.000000000 +0000
+@@ -196,9 +196,17 @@
+ }
+
+ static int
+-flash_fill_sect_ranges (ulong addr_first, ulong addr_last,
+- int *s_first, int *s_last,
+- int *s_count )
++flash_fill_sect_ranges(
++ ulong *addr_first_sect_start,
++ ulong addr_first,
++ ulong *addr_last_sect_end,
++ ulong addr_last,
++ int *s_first,
++ int *s_last,
++ int *bPartialStart,
++ int *bPartialEnd,
++ int *s_count,
++ unsigned int bPartialErase)
+ {
+ flash_info_t *info;
+ ulong bank;
+@@ -211,9 +219,7 @@
+ s_last [bank] = -1; /* last sector to erase */
+ }
+
+- for (bank=0,info=&flash_info[0];
+- (bank < CFG_MAX_FLASH_BANKS) && (addr_first <= addr_last);
+- ++bank, ++info) {
++ for (bank=0, info=&flash_info[0]; (bank < CFG_MAX_FLASH_BANKS) && (addr_first <= addr_last); ++bank, ++info) {
+ ulong b_end;
+ int sect;
+ short s_end;
+@@ -225,7 +231,6 @@
+ b_end = info->start[0] + info->size - 1; /* bank end addr */
+ s_end = info->sector_count - 1; /* last sector */
+
+-
+ for (sect=0; sect < info->sector_count; ++sect) {
+ ulong end; /* last address in current sect */
+
+@@ -238,11 +243,21 @@
+
+ if (addr_first == info->start[sect]) {
+ s_first[bank] = sect;
++ } else if (addr_first > info->start[sect] && addr_first <= end && bPartialErase) {
++ *addr_first_sect_start = info->start[sect];
++ s_first[bank] = sect;
++ *bPartialStart = 1;
+ }
++
+ if (addr_last == end) {
+ s_last[bank] = sect;
++ } else if (addr_last >= info->start[sect] && addr_last < end && bPartialErase) {
++ *addr_last_sect_end = end;
++ s_last[bank] = sect;
++ *bPartialEnd = 1;
+ }
+ }
++
+ if (s_first[bank] >= 0) {
+ if (s_last[bank] < 0) {
+ if (addr_last > b_end) {
+@@ -316,6 +331,8 @@
+ struct part_info *part;
+ u8 dev_type, dev_num, pnum;
+ #endif
++ unsigned int bPartialErase = 0;
++
+ int rcode = 0;
+
+ if (argc < 2) {
+@@ -368,8 +385,8 @@
+ }
+ }
+ #endif
+-
+- if (argc != 3) {
++
++ if (argc != 4) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+@@ -397,11 +414,117 @@
+ return 1;
+ }
+
+- rcode = flash_sect_erase(addr_first, addr_last);
++ printf ("Erase Flash from 0x%08lx to 0x%08lx\n", addr_first, addr_last);
++ if(argc == 4) {
++ bPartialErase = simple_strtoul(argv[3], NULL, 10);
++ }
++
++ rcode = flash_sect_erase(addr_first, addr_last, bPartialErase);
+ return rcode;
+ }
+
+-int flash_sect_erase (ulong addr_first, ulong addr_last)
++int flerase_Partial(
++ ulong addr_first_sect_start,
++ ulong addr_first,
++ ulong addr_last_sect_end,
++ ulong addr_last,
++ flash_info_t *info,
++ int first_sect,
++ int last_sect,
++ int bFirstPartial,
++ int bLastPartial) {
++ unsigned int firstMemLen = 0;
++ unsigned int lastMemLen = 0;
++ unsigned int sectMemLen = 0;
++ uchar *pSavedFirstMem = NULL;
++ uchar *pSavedLastMem = NULL;
++ uchar *pSavedSectMem = NULL;
++ int bSectPartial = 0;
++ int rt_code = 0;
++
++ debug("%s ... 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%p, %d, %d, %d, %d\n", __FUNCTION__, addr_first_sect_start, addr_first, addr_last_sect_end, addr_last, info, first_sect, last_sect, bFirstPartial, bLastPartial);
++
++ if (bFirstPartial && bLastPartial && (first_sect == last_sect))
++ {
++ ulong b_end = info->start[0] + info->size - 1;
++ ulong end = (first_sect == (info->sector_count - 1)) ? b_end : info->start[first_sect + 1] - 1;
++ sectMemLen = end - info->start[first_sect] + 1;
++ pSavedSectMem = (uchar *)calloc(sectMemLen, sizeof(char));
++ if (pSavedSectMem == NULL)
++ {
++ debug("calloc %u FAILED\n", sectMemLen);
++ rt_code = 1;
++ goto ret;
++ }
++ memset(pSavedSectMem, 0xff, sectMemLen);
++ bSectPartial = 1;
++ memcpy(pSavedSectMem, (uchar *)addr_first_sect_start, addr_first - addr_first_sect_start);
++ memcpy(pSavedSectMem + (addr_last - info->start[first_sect]) + 1, addr_last + 1, end - addr_last);
++ }
++ else
++ {
++ if (bFirstPartial){
++ firstMemLen = addr_first - addr_first_sect_start + 1;
++ pSavedFirstMem = (uchar *)calloc(firstMemLen,sizeof(char));
++ memcpy(pSavedFirstMem,(uchar *)addr_first_sect_start,firstMemLen - 1);
++ }
++ if (bLastPartial){
++ lastMemLen = addr_last_sect_end - addr_last + 1;
++ pSavedLastMem = (uchar *)calloc(lastMemLen,sizeof(char));
++ memcpy(pSavedLastMem,(uchar *)addr_last + 1,lastMemLen - 1);
++ }
++ }
++
++ if (bFirstPartial){
++ if(flash_erase (info, first_sect, first_sect)) {
++ printf("%s ... Couldn't erase sector %d\n", __FUNCTION__, first_sect);
++ rt_code = 1;
++ goto ret;
++ }
++ debug("%s ... erase sector %d done!\n", __FUNCTION__, first_sect);
++ }
++
++ if (bLastPartial && first_sect != last_sect){
++ if(flash_erase (info, last_sect, last_sect)) {
++ printf("%s ... Couldn't erase sector %d\n", __FUNCTION__, last_sect);
++ rt_code = 1;
++ goto ret;
++ }
++ debug("%s ... erase sector %d done!\n", __FUNCTION__, last_sect);
++ }
++
++ if (bFirstPartial && bLastPartial && (first_sect == last_sect))
++ {
++ flash_write(pSavedSectMem, (uchar *)addr_first_sect_start, sectMemLen);
++ debug("flash_write from 0x%08x with len %u\n", addr_first_sect_start, sectMemLen);
++ }
++ else
++ {
++ if (bFirstPartial){
++ if(flash_write(pSavedFirstMem,(uchar *)addr_first_sect_start,firstMemLen - 1)) {
++ printf("%s ... Couldn't write at 0x%08lx length %d\n", __FUNCTION__, addr_first_sect_start,firstMemLen - 1);
++ rt_code = 1;
++ goto ret;
++ }
++ }
++ if (bLastPartial){
++ if(flash_write(pSavedLastMem,(uchar *)addr_last + 1,lastMemLen - 1)) {
++ printf("%s ... Couldn't write at 0x%08lx length %d\n", __FUNCTION__, addr_last, lastMemLen - 1);
++ rt_code = 1;
++ }
++ }
++ }
++ret:
++ if (bFirstPartial)
++ free(pSavedFirstMem);
++ if (bLastPartial)
++ free(pSavedLastMem);
++ if (bSectPartial)
++ free(pSavedSectMem);
++ return rt_code;
++}
++
++int flash_sect_erase (ulong addr_first, ulong addr_last, unsigned int bPartialErase)
+ {
+ flash_info_t *info;
+ ulong bank;
+@@ -413,27 +536,66 @@
+ int erased = 0;
+ int planned;
+ int rcode = 0;
+-
+- rcode = flash_fill_sect_ranges (addr_first, addr_last,
+- s_first, s_last, &planned );
++ int bPartialStart = 0; // Start sector has to be erased partially
++ int bPartialEnd = 0; // End sector has to be erased partially
++ ulong addr_first_sect_start = 0;// Sector start address of location addr_start
++ ulong addr_last_sect_end = 0; // Sector end address of location addr_last
++
++ rcode = flash_fill_sect_ranges (
++ &addr_first_sect_start,
++ addr_first,
++ &addr_last_sect_end,
++ addr_last,
++ s_first,
++ s_last,
++ &bPartialStart,
++ &bPartialEnd,
++ &planned,
++ bPartialErase );
+
+ if (planned && (rcode == 0)) {
+- for (bank=0,info=&flash_info[0];
+- (bank < CFG_MAX_FLASH_BANKS) && (rcode == 0);
+- ++bank, ++info) {
++ for (bank=0, info=&flash_info[0]; (bank < CFG_MAX_FLASH_BANKS) && (rcode == 0); ++bank, ++info) {
++ ulong b_end = info->start[0] + info->size - 1; /* bank end addr */
+ if (s_first[bank]>=0) {
+- erased += s_last[bank] - s_first[bank] + 1;
+- debug ("Erase Flash from 0x%08lx to 0x%08lx "
+- "in Bank # %ld ",
+- info->start[s_first[bank]],
+- (s_last[bank] == info->sector_count) ?
+- info->start[0] + info->size - 1:
+- info->start[s_last[bank]+1] - 1,
+- bank+1);
+- rcode = flash_erase (info, s_first[bank], s_last[bank]);
++ if(bPartialErase) {
++ rcode = flerase_Partial(
++ addr_first_sect_start,
++ addr_first,
++ addr_last_sect_end,
++ addr_last,
++ info,
++ s_first[bank],
++ s_last[bank],
++ bPartialStart,
++ bPartialEnd);
++ }
++
++ //Erase full sectores
++ if (bPartialStart)
++ s_first[bank] += 1;
++ if (bPartialEnd)
++ s_last[bank] -= 1;
++ if (s_last[bank] >= s_first[bank]) {
++ erased += s_last[bank] - s_first[bank] + 1;
++ debug ("Erase Flash from 0x%08lx to 0x%08lx in Bank # %ld ",
++ info->start[s_first[bank]],
++ (s_last[bank] == info->sector_count) ?
++ info->start[0] + info->size - 1:
++ info->start[s_last[bank]+1] - 1,
++ bank + 1);
++ rcode = flash_erase (info, s_first[bank], s_last[bank]);
++ }
+ }
+ }
+- printf ("Erased %d sectors\n", erased);
++
++ if (erased && !bPartialErase) {
++ printf ("Erased %d sectors\n", erased);
++ } else if (bPartialErase){
++ printf ("Partial erased from 0x%08lx to 0x%08lx\n", addr_first, addr_last);
++ } else {
++ printf ("Error: start and/or end address not on sector boundary\n");
++ rcode = 1;
++ }
+ } else if (rcode == 0) {
+ puts ("Error: start and/or end address"
+ " not on sector boundary\n");
+@@ -629,8 +791,22 @@
+ int protected, i;
+ int planned;
+ int rcode;
+-
+- rcode = flash_fill_sect_ranges( addr_first, addr_last, s_first, s_last, &planned );
++ int bPartialStart = 0; // Start sector has to be erased partially
++ int bPartialEnd = 0; // End sector has to be erased partially
++ ulong addr_first_sect_start = 0;// Sector start address of location addr_start
++ ulong addr_last_sect_end = 0; // Sector end address of location addr_last
++
++ rcode = flash_fill_sect_ranges (
++ &addr_first_sect_start,
++ addr_first,
++ &addr_last_sect_end,
++ addr_last,
++ s_first,
++ s_last,
++ &bPartialStart,
++ &bPartialEnd,
++ &planned,
++ 1 );
+
+ protected = 0;
+
+@@ -690,7 +866,7 @@
+ );
+
+ U_BOOT_CMD(
+- erase, 3, 1, do_flerase,
++ erase, 4, 1, do_flerase,
+ "erase - erase FLASH memory\n",
+ "start end\n"
+ " - erase FLASH from addr 'start' to addr 'end'\n"
+diff -urN u-boot-1.1.5.a/common/cmd_nvedit.c u-boot/common/cmd_nvedit.c
+--- u-boot-1.1.5.a/common/cmd_nvedit.c 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/common/cmd_nvedit.c 2007-03-09 09:47:46.000000000 +0000
+@@ -540,8 +540,19 @@
+ extern char * env_name_spec;
+
+ printf ("Saving Environment to %s...\n", env_name_spec);
+-
++#if 1
++ if(saveenv() == 0) {
++#ifdef UBOOT_ENV_COPY
++ saveenv_copy();
++#else
++ ;
++#endif //UBOOT_ENV_COPY
++ } else
++ return 1;
++ return 0;
++#else
+ return (saveenv() ? 1 : 0);
++#endif
+ }
+
+
+diff -urN u-boot-1.1.5.a/common/console.c u-boot/common/console.c
+--- u-boot-1.1.5.a/common/console.c 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/common/console.c 2007-03-09 09:47:46.000000000 +0000
+@@ -324,7 +324,7 @@
+ #endif
+
+ /** U-Boot INIT FUNCTIONS *************************************************/
+-
++#ifndef CFG_HEAD_CODE
+ int console_assign (int file, char *devname)
+ {
+ int flag, i;
+@@ -357,7 +357,7 @@
+
+ return -1;
+ }
+-
++#endif //CFG_HEAD_CODE
+ /* Called before relocation - use serial functions */
+ int console_init_f (void)
+ {
+@@ -392,6 +392,7 @@
+ }
+ #endif /* CFG_CONSOLE_IS_IN_ENV || CONFIG_SPLASH_SCREEN */
+
++#ifndef CFG_HEAD_CODE
+ #ifdef CFG_CONSOLE_IS_IN_ENV
+ /* Called after the relocation - use desired console functions */
+ int console_init_r (void)
+@@ -570,3 +571,4 @@
+ }
+
+ #endif /* CFG_CONSOLE_IS_IN_ENV */
++#endif //CFG_HEAD_CODE
+diff -urN u-boot-1.1.5.a/common/devices.c u-boot/common/devices.c
+--- u-boot-1.1.5.a/common/devices.c 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/common/devices.c 2007-03-09 09:47:46.000000000 +0000
+@@ -39,6 +39,7 @@
+ list_t devlist = 0;
+ device_t *stdio_devices[] = { NULL, NULL, NULL };
+ char *stdio_names[MAX_FILES] = { "stdin", "stdout", "stderr" };
++#ifndef CFG_HEAD_CODE
+
+ #if defined(CONFIG_SPLASH_SCREEN) && !defined(CFG_DEVICE_NULLDEV)
+ #define CFG_DEVICE_NULLDEV 1
+@@ -214,3 +215,5 @@
+
+ return 0;
+ }
++#endif //CFG_HEAD_CODE
++
+diff -urN u-boot-1.1.5.a/common/env_common.c u-boot/common/env_common.c
+--- u-boot-1.1.5.a/common/env_common.c 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/common/env_common.c 2008-05-11 13:26:45.000000000 +0100
+@@ -219,7 +219,9 @@
+ * We must allocate a buffer for the environment
+ */
+ env_ptr = (env_t *)malloc (CFG_ENV_SIZE);
+- DEBUGF ("%s[%d] malloced ENV at %p\n", __FUNCTION__,__LINE__,env_ptr);
++ if(!env_ptr)
++ DEBUGF ("malloc env_ptr error!!\n");
++ DEBUGF ("%s[%d] malloced ENV at %p\n", __FUNCTION__, __LINE__, env_ptr);
+ #endif
+
+ /*
+@@ -227,6 +229,10 @@
+ */
+ env_get_char = env_get_char_memory;
+
++ //leejack
++ DEBUGF ("%s[%d] gd->env_valid=%d\n", __FUNCTION__, __LINE__, gd->env_valid);
++ DEBUGF ("%s[%d] CFG_ENV_SIZE=%d\n", __FUNCTION__, __LINE__, CFG_ENV_SIZE);
++
+ if (gd->env_valid == 0) {
+ #if defined(CONFIG_GTH) || defined(CFG_ENV_IS_NOWHERE) /* Environment not changable */
+ puts ("Using default environment\n\n");
+@@ -242,18 +248,17 @@
+ }
+
+ memset (env_ptr, 0, sizeof(env_t));
+- memcpy (env_ptr->data,
+- default_environment,
+- sizeof(default_environment));
++ memcpy (env_ptr->data, default_environment, sizeof(default_environment));
++
+ #ifdef CFG_REDUNDAND_ENVIRONMENT
+ env_ptr->flags = 0xFF;
+ #endif
+ env_crc_update ();
+ gd->env_valid = 1;
+- }
+- else {
++ } else {
+ env_relocate_spec ();
+ }
++
+ gd->env_addr = (ulong)&(env_ptr->data);
+
+ #ifdef CONFIG_AMIGAONEG3SE
+diff -urN u-boot-1.1.5.a/common/env_flash.c u-boot/common/env_flash.c
+--- u-boot-1.1.5.a/common/env_flash.c 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/common/env_flash.c 2008-05-11 14:55:45.000000000 +0100
+@@ -66,7 +66,6 @@
+ #endif
+
+ #else /* ! ENV_IS_EMBEDDED */
+-
+ env_t *env_ptr = (env_t *)CFG_ENV_ADDR;
+ #ifdef CMD_SAVEENV
+ static env_t *flash_addr = (env_t *)CFG_ENV_ADDR;
+@@ -201,6 +200,7 @@
+ debug (" %08lX ... %08lX ...",
+ (ulong)&(flash_addr_new->data),
+ sizeof(env_ptr->data)+(ulong)&(flash_addr_new->data));
++
+ if ((rc = flash_write((char *)env_ptr->data,
+ (ulong)&(flash_addr_new->data),
+ sizeof(env_ptr->data))) ||
+@@ -256,7 +256,6 @@
+ #endif /* CMD_SAVEENV */
+
+ #else /* ! CFG_ENV_ADDR_REDUND */
+-
+ int env_init(void)
+ {
+ #ifdef CONFIG_OMAP2420H4
+@@ -280,8 +279,55 @@
+
+ #ifdef CMD_SAVEENV
+
++#ifdef UBOOT_ENV_COPY
++int saveenv_copy(void) {
++ uchar *env_buffer = (char *)env_ptr;
++ char *kernel_addr;
++ char *rootfs_addr;
++ char *rootfs_size;
++ ulong start_addr,end_addr,rootfs_end_addr;
++ ulong flash_start;
++
++ kernel_addr = getenv("f_kernel_addr");
++ end_addr = simple_strtoul(kernel_addr,NULL,16) - 1;
++ start_addr = end_addr - CFG_ENV_SIZE - sizeof(UBOOTCONFIG_COPY_HEADER) + 1;
++
++ rootfs_addr = getenv("f_rootfs_addr");
++ rootfs_size = getenv("f_rootfs_size");
++ rootfs_end_addr = simple_strtoul(rootfs_addr,NULL,16) + simple_strtoul(rootfs_size,NULL,16);
++
++ if(rootfs_end_addr >= start_addr)
++ {
++ printf("Can not copy the environment at 0x%08lx as no space left.\nf_kernel_addr = 0x%08lx while rootfs_end_addr = 0x%08lx\n",start_addr,end_addr,rootfs_end_addr);
++ return 1;
++ }
++
++ debug ("Protect off %08lX ... %08lX\n", (ulong)rootfs_end_addr, end_addr);
++ if (flash_sect_protect (0, rootfs_end_addr, end_addr))
++ return 1;
++
++ //delete the old environment copy, if found
++ flash_start = rootfs_end_addr;
++ while(flash_start + sizeof(UBOOTCONFIG_COPY_HEADER) + ENV_SIZE < end_addr)
++ {
++ if(strncmp((char *)flash_start,UBOOTCONFIG_COPY_HEADER,sizeof(UBOOTCONFIG_COPY_HEADER)) == 0)
++ {
++ flash_sect_erase(flash_start,flash_start + sizeof(UBOOTCONFIG_COPY_HEADER),1);
++ }
++ flash_start += 1;
++ }
++ flash_sect_erase(start_addr,end_addr,1);
++ flash_write(UBOOTCONFIG_COPY_HEADER,start_addr,sizeof(UBOOTCONFIG_COPY_HEADER));
++ flash_write(env_buffer,start_addr + sizeof(UBOOTCONFIG_COPY_HEADER), CFG_ENV_SIZE);
++ flash_sect_protect (1, rootfs_end_addr, end_addr);
++ printf("saved copy of the env at 0x%08lx\n",start_addr);
++ return 0;
++}
++#endif //UBOOT_ENV_COPY
++
+ int saveenv(void)
+ {
++#define debug printf
+ int len, rc;
+ ulong end_addr;
+ ulong flash_sect_addr;
+@@ -331,7 +377,7 @@
+ return 1;
+
+ puts ("Erasing Flash...");
+- if (flash_sect_erase (flash_sect_addr, end_addr))
++ if (flash_sect_erase (flash_sect_addr, end_addr, 1))
+ return 1;
+
+ puts ("Writing to Flash... ");
+diff -urN u-boot-1.1.5.a/common/hush.c u-boot/common/hush.c
+--- u-boot-1.1.5.a/common/hush.c 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/common/hush.c 2008-05-10 18:56:37.000000000 +0100
+@@ -3167,9 +3167,11 @@
+ int code = 0;
+ #endif
+ do {
++ printf("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ ctx.type = flag;
+ initialize_context(&ctx);
+ update_ifs_map();
++ printf("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ if (!(flag & FLAG_PARSE_SEMICOLON) || (flag & FLAG_REPARSING)) mapset((uchar *)";$&|", 0);
+ inp->promptmode=1;
+ rcode = parse_stream(&temp, &ctx, inp, '\n');
+@@ -3180,9 +3182,12 @@
+ syntax();
+ #ifdef __U_BOOT__
+ flag_repeat = 0;
++printf("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ #endif
++ printf("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ }
+ if (rcode != 1 && ctx.old_flag == 0) {
++ printf("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ done_word(&temp, &ctx);
+ done_pipe(&ctx,PIPE_SEQ);
+ #ifndef __U_BOOT__
+@@ -3202,6 +3207,7 @@
+ if (code == -1)
+ flag_repeat = 0;
+ #endif
++ printf("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ } else {
+ if (ctx.old_flag != 0) {
+ free(ctx.stack);
+@@ -3215,6 +3221,7 @@
+ temp.quote = 0;
+ inp->p = NULL;
+ free_pipe_list(ctx.list_head,0);
++ printf("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ }
+ b_free(&temp);
+ } while (rcode != -1 && !(flag & FLAG_EXIT_FROM_LOOP)); /* loop on syntax errors, return on EOF */
+@@ -3235,9 +3242,12 @@
+ #ifdef __U_BOOT__
+ char *p = NULL;
+ int rcode;
++ printf("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ if ( !s || !*s)
+ return 1;
++ printf("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ if (!(p = strchr(s, '\n')) || *++p) {
++ printf("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ p = xmalloc(strlen(s) + 2);
+ strcpy(p, s);
+ strcat(p, "\n");
+@@ -3247,6 +3257,7 @@
+ return rcode;
+ } else {
+ #endif
++ printf("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ setup_string_in_str(&input, s);
+ return parse_stream_outer(&input, flag);
+ #ifdef __U_BOOT__
+diff -urN u-boot-1.1.5.a/config.mk u-boot/config.mk
+--- u-boot-1.1.5.a/config.mk 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/config.mk 2008-05-11 12:23:31.000000000 +0100
+@@ -77,7 +77,7 @@
+ sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules
+ endif
+ ifdef CPU
+-sinclude $(TOPDIR)/cpu/$(CPU)/config.mk # include CPU specific rules
++sinclude $(TOPDIR)/cpu/$(CPU)/$(BOARD)/config.mk # include CPU specific rules
+ endif
+ ifdef SOC
+ sinclude $(TOPDIR)/cpu/$(CPU)/$(SOC)/config.mk # include SoC specific rules
+@@ -130,7 +130,8 @@
+ ARFLAGS = crv
+ RELFLAGS= $(PLATFORM_RELFLAGS)
+ DBGFLAGS= -g # -DDEBUG
+-OPTFLAGS= -Os #-fomit-frame-pointer
++OPTFLAGS= -Os
++#-O2 #-fomit-frame-pointer
+ ifndef LDSCRIPT
+ #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
+ ifeq ($(CONFIG_NAND_U_BOOT),y)
+@@ -139,12 +140,15 @@
+ LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+ endif
+ endif
++
++LDSCRIPT_BOOTSTRAP := $(TOPDIR)/board/$(BOARDDIR)/u-boot-bootstrap.lds
++
+ OBJCFLAGS += --gap-fill=0xff
+
+ gccincdir := $(shell $(CC) -print-file-name=include)
+
+ CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \
+- -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \
++ -D__KERNEL__ -DUBOOT_RAM_TEXT_BASE=$(UBOOT_RAM_TEXT_BASE) \
+
+ ifneq ($(OBJTREE),$(SRCTREE))
+ CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include
+@@ -180,7 +184,10 @@
+
+ AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS)
+
+-LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
++LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(UBOOT_RAM_TEXT_BASE) $(PLATFORM_LDFLAGS)
++LDFLAGS_BOOTSTRAP += -Bstatic -T $(LDSCRIPT_BOOTSTRAP) -Ttext $(BOOTSTRAP_TEXT_BASE) $(PLATFORM_LDFLAGS)
++
++#HEAD_LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(HEAD_FLASH_TEXT_BASE) $(PLATFORM_LDFLAGS)
+
+ # Location of a usable BFD library, where we define "usable" as
+ # "built for ${HOST}, supports ${TARGET}". Sensible values are
+@@ -211,10 +218,17 @@
+
+ #########################################################################
+
++AFLAGS := $(AFLAGS) $(IFX_CFLAGS)
++CFLAGS := $(CFLAGS) $(IFX_CFLAGS)
++CPPFLAGS := $(CPPFLAGS) $(IFX_CFLAGS)
++
++#########################################################################
++
+ export CONFIG_SHELL HPATH HOSTCC HOSTCFLAGS CROSS_COMPILE \
+ AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP \
+ MAKE
+-export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS
++#export UBOOT_RAM_TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS
++export UBOOT_RAM_TEXT_BASE BOOTSTRAP_TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS
+
+ #########################################################################
+
+diff -urN u-boot-1.1.5.a/drivers/Makefile u-boot/drivers/Makefile
+--- u-boot-1.1.5.a/drivers/Makefile 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/drivers/Makefile 2008-05-11 14:54:11.000000000 +0100
+@@ -50,14 +50,14 @@
+ videomodes.o w83c553f.o \
+ ks8695eth.o \
+ pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \
+- rpx_pcmcia.o
++ rpx_pcmcia.o ifx_sw.o
+
+ SRCS := $(COBJS:.o=.c)
+ OBJS := $(addprefix $(obj),$(COBJS))
+
+ all: $(LIB)
+
+-$(LIB): $(obj).depend $(OBJS)
++$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+ #########################################################################
+diff -urN u-boot-1.1.5.a/include/asm-mips/mipsregs.h u-boot/include/asm-mips/mipsregs.h
+--- u-boot-1.1.5.a/include/asm-mips/mipsregs.h 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/include/asm-mips/mipsregs.h 2008-05-11 12:31:57.000000000 +0100
+@@ -48,6 +48,7 @@
+ #define CP0_CAUSE $13
+ #define CP0_EPC $14
+ #define CP0_PRID $15
++#define CP0_EBASE $15,1
+ #define CP0_CONFIG $16
+ #define CP0_LLADDR $17
+ #define CP0_WATCHLO $18
+@@ -330,11 +331,32 @@
+ # define KSU_USER 0x00000010
+ # define KSU_SUPERVISOR 0x00000008
+ # define KSU_KERNEL 0x00000000
++#ifdef CONFIG_DANUBE /* MIPS 24KE */
++/* bits 5 & 6 & 7: reserved */
++/* bits 8~15: IM0~7 */
++/* bits 16: reserved */
++#define ST0_CEE 0x00020000
++/* bits 18: always 0 */
++#define ST0_NMI 0x00080000
++#define ST0_SR 0x00100000
++#define ST0_TS 0x00200000
++#define ST0_BEV 0x00400000
++/* bits 23: reserved */
++#define ST0_MX 0x01000000
++#define ST0_RE 0x02000000
++#define ST0_FR 0x04000000
++#define ST0_RP 0x08000000
++#define ST0_CU0 0x10000000
++#define ST0_CU1 0x20000000
++#define ST0_CU2 0x40000000
++#define ST0_CU3 0x80000000
++#else
+ #define ST0_UX 0x00000020
+ #define ST0_SX 0x00000040
+ #define ST0_KX 0x00000080
+ #define ST0_DE 0x00010000
+ #define ST0_CE 0x00020000
++#endif
+
+ /*
+ * Bitfields in the R[23]000 cp0 status register.
+@@ -471,6 +493,14 @@
+ #define CAUSEF_BD (1 << 31)
+
+ /*
++ * Bits in the coprocessor 0 EBase register
++ */
++#define EBASEB_CPUNUM 0
++#define EBASEF_CPUNUM (0x3ff << EBASEB_CPUNUM)
++#define EBASEB_EXPBASE 12
++#define EBASEF_EXPBASE (0x3ffff << EBASEB_EXPBASE)
++
++/*
+ * Bits in the coprozessor 0 config register.
+ */
+ #define CONF_CM_CACHABLE_NO_WA 0
+@@ -544,4 +574,10 @@
+ #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
+ #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
+
++/*
++ * Bits in ErrCtl register
++ */
++#define ECCB_WST 29
++#define ECCF_WST (0x1 << ECCB_WST)
++
+ #endif /* _ASM_MIPSREGS_H */
+diff -urN u-boot-1.1.5.a/include/cmd_confdefs.h u-boot/include/cmd_confdefs.h
+--- u-boot-1.1.5.a/include/cmd_confdefs.h 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/include/cmd_confdefs.h 2007-03-09 09:47:46.000000000 +0000
+@@ -94,6 +94,7 @@
+ #define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */
+ #define CFG_CMD_SNTP 0x2000000000000000ULL /* SNTP support */
+ #define CFG_CMD_DISPLAY 0x4000000000000000ULL /* Display support */
++#define CFG_CMD_DHRYSTONE 0x8000000000000000ULL /* Dhrystone benchmark support */
+
+ #define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */
+
+@@ -141,6 +142,7 @@
+ CFG_CMD_SPI | \
+ CFG_CMD_UNIVERSE | \
+ CFG_CMD_USB | \
++ CFG_CMD_DHRYSTONE | \
+ CFG_CMD_VFD )
+
+ /* Default configuration
+diff -urN u-boot-1.1.5.a/include/config.h u-boot/include/config.h
+--- u-boot-1.1.5.a/include/config.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/include/config.h 2008-05-11 14:02:25.000000000 +0100
+@@ -0,0 +1,2 @@
++/* Automatically generated - do not edit */
++#include <configs/danube.h>
+diff -urN u-boot-1.1.5.a/include/config.mk u-boot/include/config.mk
+--- u-boot-1.1.5.a/include/config.mk 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/include/config.mk 2008-05-11 14:02:25.000000000 +0100
+@@ -0,0 +1,3 @@
++ARCH = mips
++CPU = mips
++BOARD = danube
+diff -urN u-boot-1.1.5.a/include/flash.h u-boot/include/flash.h
+--- u-boot-1.1.5.a/include/flash.h 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/include/flash.h 2008-05-11 12:31:57.000000000 +0100
+@@ -79,7 +79,7 @@
+ extern unsigned long flash_init (void);
+ extern void flash_print_info (flash_info_t *);
+ extern int flash_erase (flash_info_t *, int, int);
+-extern int flash_sect_erase (ulong addr_first, ulong addr_last);
++extern int flash_sect_erase (ulong addr_first, ulong addr_last, unsigned int bPartialErase);
+ extern int flash_sect_protect (int flag, ulong addr_first, ulong addr_last);
+
+ /* common/flash.c */
+@@ -299,6 +299,10 @@
+ #define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */
+ #define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */
+
++#define MX_ID_29LV320AB 0x22A822A8 /* MXIC MX29LV320AB ID (32 M, bottom ) joelin */
++#define MX_ID_29LV160BB 0x22492249 /* MXIC MX29LV160BB ID (16 M, bottom ) joelin */
++#define MX_ID_29LV640BB 0x22cb22cb /* MXIC MX29LV640BB ID (64 M, bottom ) joelin */
++
+ /*-----------------------------------------------------------------------
+ * Internal FLASH identification codes
+ *
+@@ -422,6 +426,10 @@
+ #define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */
+ #define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */
+
++#define FLASH_29LV320AB 0x00B0 /* MXIC MX29LV320AB( 32M = 4M x 16 ) joelin 10/07/2004*/
++#define FLASH_29LV160BB 0x00B1 /* MXIC MX29LV160BB( 16M = 2M x 16 ) joelin 11/22/2004*/
++#define FLASH_29LV640BB 0x00B2 /* MXIC MX29LV640BB( 64M = 8M x 16 ) liupeng*/
++
+ #define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
+
+
+diff -urN u-boot-1.1.5.a/include/image.h u-boot/include/image.h
+--- u-boot-1.1.5.a/include/image.h 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/include/image.h 2007-03-09 09:47:46.000000000 +0000
+@@ -132,6 +132,7 @@
+ #define IH_COMP_NONE 0 /* No Compression Used */
+ #define IH_COMP_GZIP 1 /* gzip Compression Used */
+ #define IH_COMP_BZIP2 2 /* bzip2 Compression Used */
++#define IH_COMP_LZMA 3 /* lzma Compression Used */
+
+ #define IH_MAGIC 0x27051956 /* Image Magic Number */
+ #define IH_NMLEN 32 /* Image Name Length */
+diff -urN u-boot-1.1.5.a/include/syscall.h u-boot/include/syscall.h
+--- u-boot-1.1.5.a/include/syscall.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/include/syscall.h 2007-03-09 09:47:46.000000000 +0000
+@@ -0,0 +1,42 @@
++#ifndef __MON_SYS_CALL_H__
++#define __MON_SYS_CALL_H__
++
++#ifndef __ASSEMBLY__
++
++#include <common.h>
++
++/* These are declarations of system calls available in C code */
++int mon_getc(void);
++int mon_tstc(void);
++void mon_putc(const char);
++void mon_puts(const char*);
++void mon_printf(const char* fmt, ...);
++void mon_install_hdlr(int, interrupt_handler_t*, void*);
++void mon_free_hdlr(int);
++void *mon_malloc(size_t);
++void mon_free(void*);
++void mon_udelay(unsigned long);
++unsigned long mon_get_timer(unsigned long);
++
++#endif /* ifndef __ASSEMBLY__ */
++
++#define NR_SYSCALLS 11 /* number of syscalls */
++
++
++/*
++ * Make sure these functions are in the same order as they
++ * appear in the "examples/syscall.S" file !!!
++ */
++#define SYSCALL_GETC 0
++#define SYSCALL_TSTC 1
++#define SYSCALL_PUTC 2
++#define SYSCALL_PUTS 3
++#define SYSCALL_PRINTF 4
++#define SYSCALL_INSTALL_HDLR 5
++#define SYSCALL_FREE_HDLR 6
++#define SYSCALL_MALLOC 7
++#define SYSCALL_FREE 8
++#define SYSCALL_UDELAY 9
++#define SYSCALL_GET_TIMER 10
++
++#endif
+diff -urN u-boot-1.1.5.a/include/version_autogenerated.h u-boot/include/version_autogenerated.h
+--- u-boot-1.1.5.a/include/version_autogenerated.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/include/version_autogenerated.h 2008-05-11 14:02:26.000000000 +0100
+@@ -0,0 +1 @@
++#define U_BOOT_VERSION "U-Boot 1.1.5-IFX-LXDB"
+diff -urN u-boot-1.1.5.a/ld_uboot.conf u-boot/ld_uboot.conf
+--- u-boot-1.1.5.a/ld_uboot.conf 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/ld_uboot.conf 2006-11-04 15:03:01.000000000 +0000
+@@ -0,0 +1,8 @@
++TAG_DWNLD()
++{
++ 0xA0B00000 "u-boot.bin" /* Download u-boot image */
++};
++TAG_START()
++{
++ 0xA0B00000
++}; /* Start u-boot image */
+diff -urN u-boot-1.1.5.a/lib_generic/Makefile u-boot/lib_generic/Makefile
+--- u-boot-1.1.5.a/lib_generic/Makefile 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/lib_generic/Makefile 2007-03-09 09:47:46.000000000 +0000
+@@ -28,7 +28,7 @@
+ COBJS = bzlib.o bzlib_crctable.o bzlib_decompress.o \
+ bzlib_randtable.o bzlib_huffman.o \
+ crc32.o ctype.o display_options.o ldiv.o \
+- string.o vsprintf.o zlib.o
++ string.o vsprintf.o zlib.o LzmaDecode.o LzmaWrapper.o
+
+ SRCS := $(COBJS:.o=.c)
+ OBJS := $(addprefix $(obj),$(COBJS))
+diff -urN u-boot-1.1.5.a/lib_mips/board.c u-boot/lib_mips/board.c
+--- u-boot-1.1.5.a/lib_mips/board.c 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/lib_mips/board.c 2008-05-11 13:17:00.000000000 +0100
+@@ -29,6 +29,25 @@
+ #include <net.h>
+ #include <environment.h>
+
++#ifdef CFG_HEAD_CODE
++#undef CONFIG_MICROBZIP2
++
++#ifdef CONFIG_BZIP2
++#include <bzlib.h>
++#endif
++
++#ifdef CONFIG_MICROBZIP2
++#include <micro_bzlib.h>
++#endif
++
++#ifdef CONFIG_LZMA
++#include <LzmaWrapper.h>
++#endif
++
++#include <image.h>
++#include "head.h"
++#endif //CFG_HEAD_CODE
++
+ DECLARE_GLOBAL_DATA_PTR;
+
+ #if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \
+@@ -39,8 +58,6 @@
+ #define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
+ #endif
+
+-#undef DEBUG
+-
+ extern int timer_init(void);
+
+ extern int incaip_set_cpuclk(void);
+@@ -79,6 +96,25 @@
+ mem_malloc_end - mem_malloc_start);
+ }
+
++#ifdef CFG_HEAD_CODE
++void *malloc(unsigned int size) {
++ if(size < (mem_malloc_end - mem_malloc_start)) {
++ mem_malloc_start += size;
++ //printf("malloc : size required = 0x%08lx and pointer = 0x%08lx\n",size,mem_malloc_start - size);
++ return (void *)(mem_malloc_start - size);
++ }
++ return NULL;
++}
++
++void *realloc(void *src,unsigned int size) {
++ return NULL;
++}
++
++void free(void *src) {
++ return;
++}
++#endif //CFG_HEAD_CODE
++
+ void *sbrk (ptrdiff_t increment)
+ {
+ ulong old = mem_malloc_brk;
+@@ -99,7 +135,11 @@
+ #else
+ int board_type = 0; /* use dummy arg */
+ #endif
++#ifdef CONFIG_USE_DDR_RAM
++ puts ("DDR-DRAM: ");
++#else
+ puts ("DRAM: ");
++#endif
+
+ if ((gd->ram_size = initdram (board_type)) > 0) {
+ print_size (gd->ram_size, "\n");
+@@ -116,26 +156,29 @@
+ return (0);
+ }
+
++#ifndef CFG_HEAD_CODE
+ static void display_flash_config(ulong size)
+ {
+ puts ("Flash: ");
+ print_size (size, "\n");
+ }
+-
++#endif
+
+ static int init_baudrate (void)
+ {
++#ifndef CFG_HEAD_CODE
+ char tmp[64]; /* long enough for environment variables */
+ int i = getenv_r ("baudrate", tmp, sizeof (tmp));
+
+ gd->baudrate = (i > 0)
+ ? (int) simple_strtoul (tmp, NULL, 10)
+ : CONFIG_BAUDRATE;
+-
++#else //CFG_HEAD_CODE
++ gd->baudrate = CONFIG_BAUDRATE;
++#endif //CFG_HEAD_CODE
+ return (0);
+ }
+
+-
+ /*
+ * Breath some life into the board...
+ *
+@@ -160,7 +203,9 @@
+
+ init_fnc_t *init_sequence[] = {
+ timer_init,
++#ifndef CFG_HEAD_CODE
+ env_init, /* initialize environment */
++#endif //CFG_HEAD_CODE
+ #ifdef CONFIG_INCA_IP
+ incaip_set_cpuclk, /* set cpu clock according to environment variable */
+ #endif
+@@ -179,7 +224,11 @@
+ gd_t gd_data, *id;
+ bd_t *bd;
+ init_fnc_t **init_fnc_ptr;
++#ifdef CFG_HEAD_CODE
++ ulong addr, addr_sp, len = (ulong)&uboot_end - CFG_HEAD_BASE;
++#else //CFG_HEAD_CODE
+ ulong addr, addr_sp, len = (ulong)&uboot_end - CFG_MONITOR_BASE;
++#endif //CFG_HEAD_CODE
+ ulong *s;
+ #ifdef CONFIG_PURPLE
+ void copy_code (ulong);
+@@ -278,7 +327,8 @@
+ #ifdef CONFIG_PURPLE
+ copy_code(addr);
+ #endif
+-
++
++ puts("\n relocate_code start");
+ relocate_code (addr_sp, id, addr);
+
+ /* NOTREACHED - relocate_code() does not return */
+@@ -292,7 +342,93 @@
+ *
+ ************************************************************************
+ */
++#ifdef CFG_HEAD_CODE
++
++extern void print_image_hdr (image_header_t *hdr);
++extern void jump_unconditional (ulong addr);
++
++void board_init_r (gd_t *id, ulong dest_addr) {
++ int i;
++ ulong addr;
++ ulong data, len, checksum;
++ ulong *len_ptr;
++ image_header_t header;
++ image_header_t *hdr = &header;
++ unsigned int destLen;
+
++ puts("\n relocate code finish.\n");
++
++ /* initialize malloc() area */
++ mem_malloc_init();
++
++ addr = CFG_HEAD_BASE + CFG_UBOOT_OFFSET;
++ memmove (&header, (char *)addr, sizeof(image_header_t));
++
++ if (ntohl(hdr->ih_magic) != IH_MAGIC) {
++ printf ("Bad Magic Number at address 0x%08lx\n",addr);
++ return;
++ }
++
++ data = (ulong)&header;
++ len = sizeof(image_header_t);
++
++ checksum = ntohl(hdr->ih_hcrc);
++ hdr->ih_hcrc = 0;
++ if (crc32 (0, (char *)data, len) != checksum) {
++ printf ("Bad Header Checksum\n");
++ return;
++ }
++
++ print_image_hdr (hdr);
++
++ data = addr + sizeof(image_header_t);
++ len = ntohl(hdr->ih_size);
++ len_ptr = (ulong *)data;
++
++ debug ("Disabling all the interrupts\n");
++ disable_interrupts();
++
++ debug (" Uncompressing UBoot Image ... \n" );
++ /*
++ * If we've got less than 4 MB of malloc() space,
++ * use slower decompression algorithm which requires
++ * at most 2300 KB of memory.
++ */
++ destLen = 0x0;
++
++#ifdef CONFIG_BZIP2
++ i = BZ2_bzBuffToBuffDecompress ((char*)ntohl(hdr->ih_load),
++ 0x400000, (char *)data, len,
++ CFG_MALLOC_LEN < (4096 * 1024), 0);
++ if (i != BZ_OK) {
++ printf ("BUNZIP2 ERROR %d - must RESET board to recover\n", i);
++ return;
++ }
++#elif CONFIG_MICROBZIP2
++ i = micro_bzBuffToBuffDecompress ((char*)ntohl(hdr->ih_load),
++ &destLen, (char *)data, len,
++ CFG_MALLOC_LEN < (4096 * 1024), 0);
++ if (i != RETVAL_OK) {
++ printf ("MICRO_BUNZIP2 ERROR %d - must RESET board to recover\n", i);
++ return;
++ }
++#elif CONFIG_LZMA
++ i = lzma_inflate ((char *)data, len, (char*)ntohl(hdr->ih_load), &destLen);
++ if (i != LZMA_RESULT_OK) {
++ printf ("LZMA ERROR %d - must RESET board to recover\n", i);
++ return;
++ }
++#else
++ printf ("NONE Compressing u-boot body!!\n");
++ memmove ((void *)ntohl(hdr->ih_load), (uchar *)data, len);
++ destLen = len;
++#endif
++ debug (" Uncompression completed successfully with destLen %d.\n ",destLen );
++ debug ("Head: Jumping to u-boot in the ram at 0x%08lx\n", CFG_MONITOR_BASE);
++
++ jump_unconditional(CFG_MONITOR_BASE);
++}
++#else //CFG_HEAD_CODE
+ void board_init_r (gd_t *id, ulong dest_addr)
+ {
+ cmd_tbl_t *cmdtp;
+@@ -305,6 +441,8 @@
+ bd_t *bd;
+ int i;
+
++ puts("\n relocate code finish.\n");
++
+ gd = id;
+ gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
+
+@@ -321,10 +459,10 @@
+ ulong addr;
+
+ addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
+-#if 0
+- printf ("Command \"%s\": 0x%08lx => 0x%08lx\n",
++
++ debug ("Command \"%s\": 0x%08lx => 0x%08lx\n",
+ cmdtp->name, (ulong) (cmdtp->cmd), addr);
+-#endif
++
+ cmdtp->cmd =
+ (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
+
+@@ -424,6 +562,7 @@
+
+ /* NOTREACHED - no way out of command loop except booting */
+ }
++#endif //CFG_HEAD_CODE
+
+ void hang (void)
+ {
+diff -urN u-boot-1.1.5.a/lib_mips/head.h u-boot/lib_mips/head.h
+--- u-boot-1.1.5.a/lib_mips/head.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/lib_mips/head.h 2007-03-09 09:47:46.000000000 +0000
+@@ -0,0 +1,3 @@
++
++//#define CFG_HEAD_LEN 0x00006000
++#define CFG_UBOOT_OFFSET CFG_HEAD_LEN
+diff -urN u-boot-1.1.5.a/lib_mips/time.c u-boot/lib_mips/time.c
+--- u-boot-1.1.5.a/lib_mips/time.c 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/lib_mips/time.c 2007-03-09 09:47:46.000000000 +0000
+@@ -80,6 +80,17 @@
+ /*NOP*/;
+ }
+
++void mdelay (unsigned long msec)
++{
++ int i,j;
++ for(i=0;i<msec;i++)
++ {
++ udelay(1000);
++
++ }
++
++}
++
+ /*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On MIPS it just returns the timer value.
+Binary files u-boot-1.1.5.a/mkbootimg.incaip2 and u-boot/mkbootimg.incaip2 differ
+diff -urN u-boot-1.1.5.a/net/eth.c u-boot/net/eth.c
+--- u-boot-1.1.5.a/net/eth.c 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/net/eth.c 2008-05-11 12:58:45.000000000 +0100
+@@ -25,6 +25,9 @@
+ #include <command.h>
+ #include <net.h>
+ #include <miiphy.h>
++#if defined(CONFIG_IFX_MIPS)
++# include "ifx_eth.c"
++#endif
+
+ #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
+
+@@ -54,6 +57,9 @@
+ extern int skge_initialize(bd_t*);
+ extern int tsec_initialize(bd_t*, int, char *);
+ extern int npe_initialize(bd_t *);
++#if defined(CONFIG_IFX_MIPS)
++ IFX_ETH_INITIALIZE_EXTERN
++#endif
+
+ static struct eth_device *eth_devices, *eth_current;
+
+@@ -235,7 +241,9 @@
+ #if defined(CONFIG_RTL8169)
+ rtl8169_initialize(bis);
+ #endif
+-
++#if defined(CONFIG_IFX_MIPS)
++ IFX_ETH_INITIALIZE(bis)
++#endif
+ if (!eth_devices) {
+ puts ("No ethernet found.\n");
+ } else {
+Binary files u-boot-1.1.5.a/post/cache.o and u-boot/post/cache.o differ
+Binary files u-boot-1.1.5.a/post/cache_8xx.o and u-boot/post/cache_8xx.o differ
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+Binary files u-boot-1.1.5.a/post/cpu/andi.o and u-boot/post/cpu/andi.o differ
+Binary files u-boot-1.1.5.a/post/cpu/asm.o and u-boot/post/cpu/asm.o differ
+Binary files u-boot-1.1.5.a/post/cpu/b.o and u-boot/post/cpu/b.o differ
+Binary files u-boot-1.1.5.a/post/cpu/cmp.o and u-boot/post/cpu/cmp.o differ
+Binary files u-boot-1.1.5.a/post/cpu/cmpi.o and u-boot/post/cpu/cmpi.o differ
+Binary files u-boot-1.1.5.a/post/cpu/complex.o and u-boot/post/cpu/complex.o differ
+Binary files u-boot-1.1.5.a/post/cpu/cr.o and u-boot/post/cpu/cr.o differ
+Binary files u-boot-1.1.5.a/post/cpu/libcpu.a and u-boot/post/cpu/libcpu.a differ
+Binary files u-boot-1.1.5.a/post/cpu/load.o and u-boot/post/cpu/load.o differ
+Binary files u-boot-1.1.5.a/post/cpu/multi.o and u-boot/post/cpu/multi.o differ
+Binary files u-boot-1.1.5.a/post/cpu/rlwimi.o and u-boot/post/cpu/rlwimi.o differ
+Binary files u-boot-1.1.5.a/post/cpu/rlwinm.o and u-boot/post/cpu/rlwinm.o differ
+Binary files u-boot-1.1.5.a/post/cpu/rlwnm.o and u-boot/post/cpu/rlwnm.o differ
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+Binary files u-boot-1.1.5.a/post/cpu.o and u-boot/post/cpu.o differ
+Binary files u-boot-1.1.5.a/post/dsp.o and u-boot/post/dsp.o differ
+Binary files u-boot-1.1.5.a/post/ether.o and u-boot/post/ether.o differ
+Binary files u-boot-1.1.5.a/post/i2c.o and u-boot/post/i2c.o differ
+Binary files u-boot-1.1.5.a/post/libpost.a and u-boot/post/libpost.a differ
+Binary files u-boot-1.1.5.a/post/memory.o and u-boot/post/memory.o differ
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+Binary files u-boot-1.1.5.a/post/rtc.o and u-boot/post/rtc.o differ
+Binary files u-boot-1.1.5.a/post/spr.o and u-boot/post/spr.o differ
+Binary files u-boot-1.1.5.a/post/sysmon.o and u-boot/post/sysmon.o differ
+Binary files u-boot-1.1.5.a/post/tests.o and u-boot/post/tests.o differ
+Binary files u-boot-1.1.5.a/post/uart.o and u-boot/post/uart.o differ
+Binary files u-boot-1.1.5.a/post/usb.o and u-boot/post/usb.o differ
+Binary files u-boot-1.1.5.a/post/watchdog.o and u-boot/post/watchdog.o differ
+diff -urN u-boot-1.1.5.a/tools/Makefile u-boot/tools/Makefile
+--- u-boot-1.1.5.a/tools/Makefile 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/tools/Makefile 2007-03-09 09:47:46.000000000 +0000
+@@ -23,7 +23,7 @@
+
+ BIN_FILES = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX)
+
+-OBJ_LINKS = environment.o crc32.o
++OBJ_LINKS = environment_$(BOARDDIR).o crc32_$(BOARDDIR).o
+ OBJ_FILES = img2srec.o mkimage.o envcrc.o gen_eth_addr.o bmp_logo.o
+
+ ifeq ($(ARCH),mips)
+@@ -117,7 +117,7 @@
+ CPPFLAGS = -idirafter $(SRCTREE)/include \
+ -idirafter $(OBJTREE)/include2 \
+ -idirafter $(OBJTREE)/include \
+- -DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC
++ -DTEXT_BASE=$(TEXT_BASE) -DUSE_HOSTCC $(IFX_CFLAGS)
+ CFLAGS = $(HOST_CFLAGS) $(CPPFLAGS) -O
+ AFLAGS = -D__ASSEMBLY__ $(CPPFLAGS)
+ CC = $(HOSTCC)
+@@ -126,14 +126,14 @@
+
+ all: $(obj).depend $(BINS) $(LOGO_H) subdirs
+
+-$(obj)envcrc$(SFX): $(obj)envcrc.o $(obj)crc32.o $(obj)environment.o
++$(obj)envcrc$(SFX): $(obj)envcrc.o $(obj)crc32_$(BOARDDIR).o $(obj)environment_$(BOARDDIR).o
+ $(CC) $(CFLAGS) -o $@ $^
+
+ $(obj)img2srec$(SFX): $(obj)img2srec.o
+ $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
+ $(STRIP) $@
+
+-$(obj)mkimage$(SFX): $(obj)mkimage.o $(obj)crc32.o
++$(obj)mkimage$(SFX): $(obj)mkimage.o $(obj)crc32_$(BOARDDIR).o
+ $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^
+ $(STRIP) $@
+
+@@ -160,7 +160,7 @@
+ $(obj)envcrc.o: $(src)envcrc.c
+ $(CC) -g $(CFLAGS) -c -o $@ $<
+
+-$(obj)crc32.o: $(obj)crc32.c
++$(obj)crc32_$(BOARDDIR).o: $(obj)crc32_$(BOARDDIR).c
+ $(CC) -g $(CFLAGS) -c -o $@ $<
+
+ $(obj)mkimage.o: $(src)mkimage.c
+@@ -192,16 +192,16 @@
+ done
+ endif
+
+-$(obj)environment.c:
+- @rm -f $(obj)environment.c
+- ln -s $(src)../common/environment.c $(obj)environment.c
++$(obj)environment_$(BOARDDIR).c:
++ @rm -f $(obj)environment_$(BOARDDIR).c
++ ln -s $(src)../common/environment_$(BOARDDIR).c $(obj)environment_$(BOARDDIR).c
+
+-$(obj)environment.o: $(obj)environment.c
++$(obj)environment_$(BOARDDIR).o: $(obj)environment_$(BOARDDIR).c
+ $(CC) -g $(HOST_ENVIRO_CFLAGS) $(CPPFLAGS) -c -o $@ $<
+
+-$(obj)crc32.c:
+- @rm -f $(obj)crc32.c
+- ln -s $(src)../lib_generic/crc32.c $(obj)crc32.c
++$(obj)crc32_$(BOARDDIR).c:
++ @rm -f $(obj)crc32_$(BOARDDIR).c
++ ln -s $(src)../lib_generic/crc32_$(BOARDDIR).c $(obj)crc32_$(BOARDDIR).c
+
+ $(LOGO_H): $(obj)bmp_logo $(LOGO_BMP)
+ $(obj)./bmp_logo $(LOGO_BMP) >$@
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+Binary files u-boot-1.1.5.a/tools/envcrc and u-boot/tools/envcrc differ
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+Binary files u-boot-1.1.5.a/tools/environment_danube.o and u-boot/tools/environment_danube.o differ
+Binary files u-boot-1.1.5.a/tools/gen_eth_addr and u-boot/tools/gen_eth_addr differ
+Binary files u-boot-1.1.5.a/tools/gen_eth_addr.o and u-boot/tools/gen_eth_addr.o differ
+Binary files u-boot-1.1.5.a/tools/img2srec and u-boot/tools/img2srec differ
+Binary files u-boot-1.1.5.a/tools/img2srec.o and u-boot/tools/img2srec.o differ
+Binary files u-boot-1.1.5.a/tools/inca-swap-bytes and u-boot/tools/inca-swap-bytes differ
+Binary files u-boot-1.1.5.a/tools/inca-swap-bytes.o and u-boot/tools/inca-swap-bytes.o differ
+Binary files u-boot-1.1.5.a/tools/mkimage and u-boot/tools/mkimage differ
+diff -urN u-boot-1.1.5.a/tools/mkimage.c u-boot/tools/mkimage.c
+--- u-boot-1.1.5.a/tools/mkimage.c 2006-10-20 16:54:33.000000000 +0100
++++ u-boot/tools/mkimage.c 2007-03-09 09:47:46.000000000 +0000
+@@ -138,6 +138,7 @@
+ { IH_COMP_NONE, "none", "uncompressed", },
+ { IH_COMP_BZIP2, "bzip2", "bzip2 compressed", },
+ { IH_COMP_GZIP, "gzip", "gzip compressed", },
++ { IH_COMP_LZMA, "lzma", "lzma compressed", },
+ { -1, "", "", },
+ };
+
+Binary files u-boot-1.1.5.a/tools/mkimage.o and u-boot/tools/mkimage.o differ
projects / openwrt.git / commitdiff