target/linux/ifxmips/image/u-boot/files/include/configs/danube.h

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * This file contains the configuration parameters for the danube board.
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #include <configs/ifx_cfg.h>
  32
  33 #define  USE_REFERENCE_BOARD
  34 //#define   USE_EVALUATION_BOARD
  35
  36 #define   DANUBE_BOOT_FROM_EBU
  37 #define   DANUBE_USE_DDR_RAM
  38
  39 #ifdef DANUBE_USE_DDR_RAM
  40 //#define  DANUBE_DDR_RAM_111M
  41 #define DANUBE_DDR_RAM_166M
  42 //#define PROMOSDDR400
  43 //#define DDR_SAMSUNG_166M
  44 //#define DDR_PSC_166M
  45 //#define DANUBE_DDR_RAM_133M
  46 #define DANUBE_DDR_RAM_SIZE     32      /* 32M DDR-DRAM for reference board */
  47 #endif
  48 #define CLK_OUT2_25MHZ
  49 #define CONFIG_MIPS32           1       /* MIPS 4Kc CPU core    */
  50 #define CONFIG_DANUBE           1       /* on a danube Board    */
  51 #define RAM_SIZE                0x2000000 /*32M ram*/
  52
  53 #define CPU_CLOCK_RATE          235000000   /* 235 MHz clock for the MIPS core */
  54
  55 #define INFINEON_EBU_BOOTCFG    0x688C688C      /* CMULT = 8 for 150 MHz */
  56
  57 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  58
  59 #define CONFIG_BAUDRATE         115200
  60
  61 #define DEBUG_PARSER            2
  62
  63 /* valid baudrates */
  64 #define CFG_BAUDRATE_TABLE      { 300, 9600, 19200, 38400, 57600, 115200 }
  65
  66 #ifndef CFG_HEAD_CODE
  67 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  68 #endif
  69
  70 #define CONFIG_PREBOOT  "echo;" \
  71         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
  72         "echo"
  73
  74 #undef  CONFIG_BOOTARGS
  75 /* by MarsLin 2005/05/10, to support different hardware configuations */
  76 //#define CONFIG_EXTRA_ENV_SETTINGS     <configs/ifx_extra_env.h>
  77 #define CONFIG_EXTRA_ENV_SETTINGS \
  78         "ethaddr=11:22:33:44:55:66\0" \
  79         "serverip=192.168.45.100\0" \
  80         "ipaddr=192.168.45.108\0"  \
  81         "update_uboot=tftp 0x80500000 u-boot.ifx;era 1:0-10; cp.b 0x80500000 0xb0000000 0x10000\0"
  82
  83 #define CONFIG_BOOTCOMMAND      "run flash_flash"
  84
  85 #define CONFIG_COMMANDS_YES     (CONFIG_CMD_DFL         | \
  86                                  CFG_CMD_ASKENV         | \
  87                                  CFG_CMD_DHRYSTONE      | \
  88                                  CFG_CMD_NET            )
  89
  90 #define CONFIG_COMMANDS_NO      (CFG_CMD_NFS            | \
  91                                  CFG_CMD_FPGA           | \
  92                                  CFG_CMD_IMLS           | \
  93                                  CFG_CMD_ITEST          | \
  94                                  CFG_CMD_XING           | \
  95                                  CFG_CMD_IMI            | \
  96                                  CFG_CMD_BMP            | \
  97                                  CFG_CMD_BOOTD          | \
  98                                  CFG_CMD_CONSOLE        | \
  99                                  CFG_CMD_LOADS          | \
 100                                  CFG_CMD_LOADB          )
 101
 102 #define CONFIG_COMMANDS         (CONFIG_COMMANDS_YES & ~CONFIG_COMMANDS_NO)
 103
 104 #if 0
 105                                  CFG_CMD_DHCP
 106                                  CFG_CMD_ELF
 107                                  CFG_CMD_NAND
 108 #endif
 109
 110 #include <cmd_confdefs.h>
 111
 112 /*
 113  * Miscellaneous configurable options
 114  */
 115 #define CFG_LONGHELP                            /* undef to save memory      */
 116 #define CFG_PROMPT              "DANUBE # "     /* Monitor Command Prompt    */
 117 #define CFG_CBSIZE              256             /* Console I/O Buffer Size   */
 118 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
 119 #define CFG_MAXARGS             16              /* max number of command args*/
 120
 121 #define CFG_MALLOC_LEN          128*1024
 122
 123 #define CFG_BOOTPARAMS_LEN      128*1024
 124
 125 #define CFG_HZ       (CPU_CLOCK_RATE / 2)
 126
 127 #define CFG_LOAD_ADDR           0x80100000      /* default load address */
 128
 129 #define CFG_MEMTEST_START       0x80100000
 130 #define CFG_MEMTEST_END         0x80400000
 131
 132 /*-----------------------------------------------------------------------
 133  * FLASH and environment organization
 134  */
 135 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks */
 136 #define CFG_MAX_FLASH_SECT      (135)   /* max number of sectors on one chip */
 137
 138 #define PHYS_FLASH_1            0xB0000000 /* Flash Bank #1 */
 139 #define PHYS_FLASH_2            0xB4000000 /* Flash Bank #2 */
 140
 141 #define BOOTSTRAP_TEXT_BASE 0xb0000000
 142
 143 /* The following #defines are needed to get flash environment right */
 144 #define CFG_MONITOR_BASE        UBOOT_RAM_TEXT_BASE     /* board/danube/config.mk. = 0xA0800000 */
 145 #define BOOTSTRAP_CFG_MONITOR_BASE      BOOTSTRAP_TEXT_BASE     /* board/danube/config.mk. = 0xA0800000 */
 146 #define CFG_MONITOR_LEN         (256 << 10)
 147
 148 #define CFG_INIT_SP_OFFSET      0x400000
 149
 150 #define CFG_FLASH_BASE          PHYS_FLASH_1
 151
 152 /* timeout values are in ticks */
 153 #define CFG_FLASH_ERASE_TOUT    (20 * CFG_HZ) /* Timeout for Flash Erase */
 154 #define CFG_FLASH_WRITE_TOUT    (20 * CFG_HZ) /* Timeout for Flash Write */
 155
 156 #define CFG_ENV_IS_IN_FLASH     1
 157 //#define CFG_ENV_IS_NOWHERE    1
 158 //#define CFG_ENV_IS_IN_NVRAM   1
 159 /* Address and size of Primary Environment Sector       */
 160 #define CFG_ENV_ADDR            IFX_CFG_FLASH_UBOOT_CFG_START_ADDR
 161 #define CFG_ENV_SIZE            IFX_CFG_FLASH_UBOOT_CFG_SIZE
 162
 163 #define CONFIG_FLASH_16BIT
 164
 165 #define CONFIG_NR_DRAM_BANKS    1
 166
 167 #define CONFIG_DANUBE_SWITCH
 168 #define CONFIG_NET_MULTI
 169 #define CONFIG_ENV_OVERWRITE
 170
 171 #define EXCEPTION_BASE  0x200
 172
 173 /**
 174  *\brief definition for nand
 175  *
 176  */
 177 #define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
 178 #define NAND_ChipID_UNKNOWN     0x00
 179 #define SECTORSIZE 512
 180 #define NAND_MAX_FLOORS 1
 181 #define NAND_MAX_CHIPS 1
 182
 183
 184 #define ADDR_COLUMN 1
 185 #define ADDR_PAGE 2
 186 #define ADDR_COLUMN_PAGE 3
 187
 188
 189 #define AT91_SMART_MEDIA_ALE (1 << 22)  /* our ALE is AD22 */
 190 #define AT91_SMART_MEDIA_CLE (1 << 21)  /* our CLE is AD21 */
 191
 192 #define NAND_DISABLE_CE(nand)
 193 #define NAND_ENABLE_CE(nand)
 194 #define NAND_WAIT_READY(nand)
 195 #define WRITE_NAND_COMMAND(d, adr)
 196 #define WRITE_NAND_ADDRESS(d, adr)
 197 #define WRITE_NAND(d, adr)
 198 #define READ_NAND(adr)
 199 /* the following are NOP's in our implementation */
 200 #define NAND_CTL_CLRALE(nandptr)
 201 #define NAND_CTL_SETALE(nandptr)
 202 #define NAND_CTL_CLRCLE(nandptr)
 203 #define NAND_CTL_SETCLE(nandptr)
 204
 205
 206
 207 #define NAND_BASE_ADDRESS  0xB4000000
 208
 209 #define NAND_WRITE(addr, val)     *((u8*)(NAND_BASE_ADDRESS | (addr))) = val;while((*EBU_NAND_WAIT & 0x08) == 0);
 210 #define NAND_READ(addr, val)      val = *((u8*)(NAND_BASE_ADDRESS | (addr)))
 211 #define NAND_CE_SET
 212 #define NAND_CE_CLEAR
 213 #define NAND_READY       ( ((*EBU_NAND_WAIT)&0x07) == 7)
 214 #define NAND_READY_CLEAR  *EBU_NAND_WAIT = 0;
 215 #define WRITE_CMD    0x18
 216 #define WRITE_ADDR   0x14
 217 #define WRITE_LADDR  0x10
 218 #define WRITE_DATA  0x10
 219 #define READ_DATA    0x10
 220 #define READ_LDATA   0x00
 221 #define ACCESS_WAIT
 222 #define IFX_ATC_NAND 0xc176
 223 #define IFX_BTC_NAND 0xc166
 224 #define ST_512WB2_NAND 0x2076
 225
 226 #define NAND_OK              0x00000000    /* Bootstrap succesful, start address in BOOT_RVEC */
 227 #define NAND_ERR             0x80000000
 228 #define NAND_ACC_TIMEOUT     (NAND_ERR | 0x00000001)
 229 #define NAND_ACC_ERR         (NAND_ERR | 0x00000002)
 230
 231
 232 /*****************************************************************************
 233  * DANUBE
 234  *****************************************************************************/
 235 /* lock cache for C program stack */
 236 /* points to ROM */
 237 /* stack size is 16K */
 238 #define LOCK_DCACHE_ADDR        0x9FC00000
 239 #define LOCK_DCACHE_SIZE        0x1000
 240
 241 /*
 242  * Memory layout
 243  */
 244 #define CFG_SDRAM_BASE          0x80000000
 245 #define CFG_SDRAM_BASE_UNCACHE  0xA0000000
 246 #define CFG_CACHE_LOCK_SIZE  LOCK_DCACHE_SIZE
 247
 248 /*
 249  * Cache settings
 250  */
 251 #define CFG_CACHE_SIZE   16384
 252 #define CFG_CACHE_LINES  32
 253 #define CFG_CACHE_WAYS   4
 254 #define CFG_CACHE_SETS   128
 255
 256 #define CFG_ICACHE_SIZE   CFG_CACHE_SIZE
 257 #define CFG_DCACHE_SIZE   CFG_CACHE_SIZE
 258 #define CFG_CACHELINE_SIZE  CFG_CACHE_LINES
 259
 260 #endif  /* __CONFIG_H */