#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
#define AR91XX_WMAC_SIZE 0x30000
#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
#define AR91XX_WMAC_SIZE 0x30000
+#define AR71XX_MEM_SIZE_MIN 0x0200000
+#define AR71XX_MEM_SIZE_MAX 0x8000000
+
#define AR71XX_CPU_IRQ_BASE 0
#define AR71XX_MISC_IRQ_BASE 8
#define AR71XX_MISC_IRQ_COUNT 8
#define AR71XX_CPU_IRQ_BASE 0
#define AR71XX_MISC_IRQ_BASE 8
#define AR71XX_MISC_IRQ_COUNT 8
+static inline int is_valid_ram_addr(void *addr)
+{
+ if (((u32) addr > KSEG0) &&
+ ((u32) addr < (KSEG0 + AR71XX_MEM_SIZE_MAX)))
+ return 1;
+
+ if (((u32) addr > KSEG1) &&
+ ((u32) addr < (KSEG1 + AR71XX_MEM_SIZE_MAX)))
+ return 1;
+
+ return 0;
+}
+
static __init char *ar71xx_prom_getargv(const char *name)
{
int len = strlen(name);
int i;
static __init char *ar71xx_prom_getargv(const char *name)
{
int len = strlen(name);
int i;
+ if (!is_valid_ram_addr(ar71xx_prom_argv))
return NULL;
for (i = 0; i < ar71xx_prom_argc; i++) {
char *argv = ar71xx_prom_argv[i];
return NULL;
for (i = 0; i < ar71xx_prom_argc; i++) {
char *argv = ar71xx_prom_argv[i];
+ if (!is_valid_ram_addr(argv))
continue;
if (strncmp(name, argv, len) == 0 && (argv)[len] == '=')
continue;
if (strncmp(name, argv, len) == 0 && (argv)[len] == '=')
int len = strlen(envname);
char **env;
int len = strlen(envname);
char **env;
+ if (!is_valid_ram_addr(ar71xx_prom_envp))
- for (env = ar71xx_prom_envp; *env != NULL; env++)
+ for (env = ar71xx_prom_envp; is_valid_ram_addr(*env); env++)
if (strncmp(envname, *env, len) == 0 && (*env)[len] == '=')
return *env + len + 1;
if (strncmp(envname, *env, len) == 0 && (*env)[len] == '=')
return *env + len + 1;
/*
* Atheros AR71xx SoC specific setup
*
/*
* Atheros AR71xx SoC specific setup
*
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Atheros' 2.6.15 BSP
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Atheros' 2.6.15 BSP
#define AR71XX_BASE_FREQ 40000000
#define AR91XX_BASE_FREQ 5000000
#define AR71XX_BASE_FREQ 40000000
#define AR91XX_BASE_FREQ 5000000
-#define AR71XX_MEM_SIZE_MIN 0x0200000
-#define AR71XX_MEM_SIZE_MAX 0x8000000
-
unsigned long ar71xx_mach_type;
u32 ar71xx_cpu_freq;
unsigned long ar71xx_mach_type;
u32 ar71xx_cpu_freq;
#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
#define AR91XX_WMAC_SIZE 0x30000
#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
#define AR91XX_WMAC_SIZE 0x30000
+#define AR71XX_MEM_SIZE_MIN 0x0200000
+#define AR71XX_MEM_SIZE_MAX 0x8000000
+
#define AR71XX_CPU_IRQ_BASE 0
#define AR71XX_MISC_IRQ_BASE 8
#define AR71XX_MISC_IRQ_COUNT 8
#define AR71XX_CPU_IRQ_BASE 0
#define AR71XX_MISC_IRQ_BASE 8
#define AR71XX_MISC_IRQ_COUNT 8